WO2018223569A1 - 一种确定焊线芯片表面焊盘间距的方法 - Google Patents

一种确定焊线芯片表面焊盘间距的方法 Download PDF

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WO2018223569A1
WO2018223569A1 PCT/CN2017/104711 CN2017104711W WO2018223569A1 WO 2018223569 A1 WO2018223569 A1 WO 2018223569A1 CN 2017104711 W CN2017104711 W CN 2017104711W WO 2018223569 A1 WO2018223569 A1 WO 2018223569A1
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file
diameter
wire
chip
capillary
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French (fr)
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吴现伟
龙华
郑瑞
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Lansus Technologies Inc
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Lansus Technologies Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/015—Manufacture or treatment of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H10W72/07141—Means for applying energy, e.g. ovens or lasers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H10W72/9445—Top-view layouts, e.g. mirror arrays

Definitions

  • the present invention relates to the field of soldering, and in particular to a method for determining the pad pitch on a surface of a wire bond chip.
  • PA refers to power amplifier
  • the package operation will touch the completed 3D contour line, that is, 3D caused by the failure to consider the pad pitch in advance during the package operation.
  • the stability of the outline was destroyed.
  • the chip design pad size and position need to consider the larger the pad pitch, the better, but because of the small size of the chip itself, the pitch adjustment is low, so you need to know the arc height in advance.
  • the relationship to the pad pitch is a better way to complete the package.
  • the present invention provides a method of determining the pad pitch on the surface of a bonding wire chip.
  • the method for determining the pad pitch of the surface of the bonding wire chip according to the present invention comprises the following steps:
  • the method further includes the following steps:
  • the pad pitch obtained by the formula is rounded.
  • the angle C of the file tip of the file is 30°.
  • the diameter T of the file tip of the file is 80 um to 100 um.
  • the file diameter H of the file is set to be larger than the wire diameter.
  • the file diameter H of the file is set to be larger than the wire diameter of 3 to 8 um.
  • the method of the invention can more accurately determine the pad pitch on the surface of the bonding wire chip, thereby providing a wider performance debugging space; in addition, it can also reduce the deformation of the package boring tool and the soldered wire, thereby causing line deformation, even with other wires. Short circuits, etc., cause problems such as mutual inductance variation, thereby improving work efficiency and reducing the number of verifications.
  • Figure 1 is a schematic illustration of a method of determining the pad pitch of a wire bond chip surface according to the present invention.
  • the chip design pad size and position should be considered as the pad pitch is as large as possible.
  • the pitch adjustment is low, so it is necessary to know the arc height and solder in advance.
  • the relationship between the disc spacing can better complete the encapsulation.
  • the most commonly used tool is a file, which is used to guide the wire and transfer the wire. Parameters, auxiliary components that are used to bond the solder balls to the pads.
  • the present invention provides a method for determining a pad pitch on a surface of a bonding wire chip, comprising the following steps:
  • Step1 Set the line arc height, defined as K.
  • the line arc refers to the shape of the wire formed by the wire during the running path of the boring tool.
  • the setting of the height of the line arc is artificially set according to the actual work requirements, which is the basis of the follow-up work. If the arc height is changed to higher And the shape of the bonding wire needs to remain unchanged, and the pad pitch on the surface of the bonding wire chip also changes.
  • Step2 Select the file, (1) measure the angle of expansion of the file tip, defined as C; (2) measure the diameter of the file tip, defined as T; (3) measure the hole diameter of the file, defined as H.
  • the angle of the angle of the tip of the file refers to the angle between the shape of the tip and the longitudinal axis.
  • the diameter of the tip of the file refers to the circular diameter of the tip.
  • the diameter of the file refers to the inside of the file. The diameter of the innermost hole of the guide wire at the narrowest point.
  • the diameter of the wire is preferably, when the wire diameter is selected as 25um, the parameter of the file is selected as the angle C of the filed tip of the file is 30°, and the diameter T of the file of the file is 80um ⁇ 100um, the standard for selecting the file is that the file cannot be too large and easy to control, so as to better construct the surface of the wire chip and finally realize the package. It is also required to set the boring tool aperture H of the boring tool to be larger than the wire diameter. Specifically, the boring tool aperture H of the boring tool is set to be larger than the wire diameter of 3 to 8 um, because the welding wire is oscillated in the boring hole. After the welding wire and the pad are stabilized, the wire is formed according to the trajectory of the boring tool. Therefore, a certain gap is required, that is, the wire diameter is usually 25 um, and the boring tool hole diameter is 28 to 33 um.
  • Step3 Determine the pad pitch on the surface of the wire bond chip, defined as P, and the formula is as follows:
  • the method further includes the step of performing a rounding process on the pad pitch obtained by the formula.
  • the P value calculated by the above formula is subjected to the hexadecimal processing to obtain the P value minimum value Pmin, for example.
  • P 100.1um
  • Pmin 101um
  • the wire pad surface pad spacing is at least 101um
  • the wire diameter is known to be 25 um, and the line arc height K is set to 280 um.
  • the angle C of the file tip is 30°; the diameter T of the file tip is 80um; the hole diameter H of the file is 30um.
  • the completed 3D contour line thereby reducing the deformation of the package file and the soldered wire, causing line deformation, and even short-circuiting with other wires, causing problems such as mutual inductance variation, thereby improving work efficiency and reducing the number of verifications.

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  • Wire Bonding (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

提供了一种确定焊线芯片表面焊盘间距的方法。该方法包括以下步骤：设定线弧高度，定义为K；选取劈刀，测量劈刀尖嘴外扩角度，定义为C；测量劈刀尖嘴直径，定义为T；测量劈刀孔径，定义为H；确定焊线芯片表面焊盘间距，定义为P，公式如下：P＝(T+H)/2+[tan(C/2)]*K。该方法可以更准确地确定焊线芯片表面焊盘间距，从而可提供更宽性能调试空间；此外，还可以降低封装劈刀与已焊线触碰导致线变形，甚至与其它线短路等，导致互感变异等问题，从而提高工作效率，并减少验证次数。

Description

一种确定焊线芯片表面焊盘间距的方法 技术领域
本发明涉及焊接领域，具体涉及一种确定焊线芯片表面焊盘间距的方法。
背景技术
PA(PA，指功率放大器)类产品相较其它IC功能产品主要考虑RF(RF，指射频)输出/输入稳定性，且芯片是前期开发材料，大多性能输出和输入已定性，可调空间较小。因此，在封装加工焊线工艺上需要线弧高度(loop height)有较宽的调试空间及3D轮廓的稳定性。
当线弧高度较高且焊盘间距很近时，封装作业会有触碰到已完成的3D轮廓线上，即，在封装作业时，因未能提前考虑到焊盘间距，而导致的3D轮廓线的稳定性遭到破坏。另外，为了让封装有更大可调空间，芯片设计焊盘大小和位置时需要考虑焊盘间距越大越好，但因芯片本身尺寸较小导致间距可调性低，因此需要提前知道线弧高度与焊盘间距的关系，才能更好地完成封装。
发明内容
为解决上述问题，本发明提供一种确定焊线芯片表面焊盘间距的方法。
本发明所述的确定焊线芯片表面焊盘间距的方法，包括以下步骤：
设定线弧高度，定义为K；
选取劈刀，测量劈刀尖嘴外扩角度，定义为C；测量劈刀尖嘴直径，定义为T；测量劈刀孔径，定义为H；
确定焊线芯片表面焊盘间距，定义为P，公式如下：
P＝(T+H)/2+[tan(C/2)]*K。
具体地，该方法还包括以下步骤：
对通过公式得到的焊盘间距进行凑整进制处理。
优选地，当线径为25um时，选取劈刀的劈刀尖嘴外扩角度C为30°。
优选地，当线径为25um时，选取劈刀的劈刀尖嘴直径T为80um～100um。
特别地，将所述劈刀的劈刀孔径H设置为大于线径。
更特别地，将所述劈刀的劈刀孔径H设置为大于线径3～8um。
本发明所述的方法可以更准确地确定焊线芯片表面焊盘间距，从而可提供更宽性能调试空间；此外，还可以降低封装劈刀与已焊线触碰导致线变形，甚至与其它线短路等，导致互感变异等问题，从而提高工作效率，并减少验证次数。
附图说明
图1是本发明所述的确定焊线芯片表面焊盘间距的方法的示意图。
具体实施方式
以下结合附图和实施例，对本发明的具体实施方式进行更加详细的说明，以便能够更好地理解本发明的方案及其各个方面的优点。然而，以下描述的具体实施方式和实施例仅是说明的目的，而不是对本发明的限制。
为了让封装有更大可调空间，芯片设计焊盘大小和位置时时需要考虑焊盘间距越大越好，但因芯片本身尺寸较小导致间距可调性低，因此需要提前知道线弧高度与焊盘间距的关系，才能更好地完成封装。封装过程中，最常使用的工具为劈刀，劈刀是用来引导焊线并传递焊线设备 参数，辅助焊球与焊盘结合的消耗类部件。
如图1所示，本发明提供一种确定焊线芯片表面焊盘间距的方法，包括以下步骤：
Step1：设定线弧高度，定义为K。线弧是指焊线利用劈刀运行轨迹过程中放线形成的焊线形状，线弧高度的设定要根据实际工作需要进行人为设定，是后续工作的基础，如果弧高更改为更高且焊线形状需要保持不变，则焊线芯片表面焊盘间距也要随之发生变化。
Step2：选取劈刀，(1)测量劈刀尖嘴外扩角度，定义为C；(2)测量劈刀尖嘴直径，定义为T；(3)测量劈刀孔径，定义为H。其中，如图1所示，劈刀尖嘴外扩角度是指尖嘴外形与纵轴间角度，劈刀尖嘴直径指的是尖嘴平面圆形直径，劈刀孔径指的是劈刀内引导线的内孔最窄处直径。焊线的直径，简称线径，优选地，当线径选取为25um时，选取劈刀的参数为劈刀尖嘴外扩角度C为30°，劈刀的劈刀尖嘴直径T为80um～100um，选取劈刀的标准在于劈刀不能过大，且易于控制，以便更好地在所述焊线芯片表面施工，最终实现封装。还需要将所述劈刀的劈刀孔径H设置为大于线径，具体地，将所述劈刀的劈刀孔径H设置为大于线径3～8um，因焊线在劈刀孔中是摆动的，焊线与焊盘施工稳定后也为了线根据劈刀轨迹输出形成线弧，因此要留有一定的空隙，即线径通常为25um，则劈刀孔径为28～33um即可。
Step3：确定焊线芯片表面焊盘间距，定义为P，公式如下：
P＝(T+H)/2+[tan(C/2)]*K。
具体地，该方法还包括以下步骤：对通过公式得到的焊盘间距进行凑整进制处理。
特别地，为了不使封装作业会有触碰到已完成的3D轮廓线上以及操作简单，需对上述公式计算得出的P值进行凑整进制处理，得到P值最小值Pmin，举例来说，P＝100.1um，则要近似为Pmin＝101um，也就是说，焊线芯片表面焊盘间距最少为101um，才能不会触碰到已完成的3D轮廓线上，从而降低封装劈刀与已焊线触碰导致线变形，甚至与 其它线短路等，导致互感变异等问题，从而提高工作效率，并减少验证次数。
实施例1
已知线径为25um，此时设定线弧高度K为280um。
选取劈刀，劈刀尖嘴外扩角度C为30°；劈刀尖嘴直径T为80um；劈刀孔径H选取30um。
确定焊线芯片表面焊盘间距，定义为P，公式如下：
P＝(T+H)/2+[tan(C/2)]*K
带入数值可得：
P＝(T+H)/2+[tan(C/2)]*K
P＝1/2(80um+30um)+(tan15°)*280um
＝55um+75.04um
＝130.04um
对P值进行凑整进制处理，即，凑整进制为Pmin＝131um，因此确定焊线芯片表面焊盘间距为至少131um，在此前提下，进行其他操作，则不会触碰到已完成的3D轮廓线上，从而降低封装劈刀与已焊线触碰导致线变形，甚至与其它线短路等，导致互感变异等问题，从而提高工作效率，并减少验证次数。
需要说明的是，以上参照附图所描述的各个实施例仅用以说明本发明而非限制本发明的范围，本领域的普通技术人员应当理解，在不脱离本发明的精神和范围的前提下对本发明进行的修改或者等同替换，均应涵盖在本发明的范围之内。此外，除上下文另有所指外，以单数形式出现的词包括复数形式，反之亦然。另外，除非特别说明，那么任何实施例的全部或一部分可结合任何其它实施例的全部或一部分来使用。

Claims (6)

  1. 一种确定焊线芯片表面焊盘间距的方法，其特征在于，该方法包括以下步骤：
    设定线弧高度，定义为K；
    选取劈刀，测量劈刀尖嘴外扩角度，定义为C；测量劈刀尖嘴直径，定义为T；测量劈刀孔径，定义为H；
    确定焊线芯片表面焊盘间距，定义为P，公式如下：
    P＝(T+H)/2+[tan(C/2)]*K。
  2. 如权利要求1所述的方法，其特征在于，该方法还包括以下步骤：
    对通过公式得到的焊盘间距进行凑整进制处理。
  3. 如权利要求1所述的方法，其特征在于，当线径为25um时，选取劈刀的劈刀尖嘴外扩角度C为30°。
  4. 如权利要求1所述的方法，其特征在于，当线径为25um时，选取劈刀的劈刀尖嘴直径T为80um～100um。
  5. 如权利要求1所述的方法，其特征在于，将所述劈刀的劈刀孔径H设置为大于线径。
  6. 如权利要求5所述的方法，其特征在于，将所述劈刀的劈刀孔径H设置为大于线径3～8um。
PCT/CN2017/104711 2017-06-06 2017-09-30 一种确定焊线芯片表面焊盘间距的方法 Ceased WO2018223569A1 (zh)

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