WO2018219128A1 - 阵列基板及显示装置 - Google Patents

阵列基板及显示装置 Download PDF

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Publication number
WO2018219128A1
WO2018219128A1 PCT/CN2018/086662 CN2018086662W WO2018219128A1 WO 2018219128 A1 WO2018219128 A1 WO 2018219128A1 CN 2018086662 W CN2018086662 W CN 2018086662W WO 2018219128 A1 WO2018219128 A1 WO 2018219128A1
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WIPO (PCT)
Prior art keywords
array substrate
extraction unit
connecting line
connection line
signal connection
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PCT/CN2018/086662
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English (en)
French (fr)
Inventor
张郑欣
徐帅
王智勇
苏海飞
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京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/326,304 priority Critical patent/US10729005B2/en
Publication of WO2018219128A1 publication Critical patent/WO2018219128A1/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0254—High voltage adaptations; Electrical insulation details; Overvoltage or electrostatic discharge protection ; Arrangements for regulating voltages or for using plural voltages
    • H05K1/0257—Overvoltage protection
    • H05K1/0259—Electrostatic discharge [ESD] protection
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/17—Passive-matrix OLED displays
    • H10K59/179—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0277—Bendability or stretchability details
    • H05K1/028—Bending or folding regions of flexible printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09272—Layout details of angles or corners

Definitions

  • the present invention belongs to the field of display technologies, and in particular, to an array substrate and a display device.
  • FIG. 1 illustrates the structure of a peripheral region of an array substrate, which includes a driving chip, a signal connection line, and a first pad for bonding with a flexible circuit board, wherein the driving chip has a plurality of second soldering a first end of the signal connection line covering the position of the first pad, and having a first through hole at a position corresponding to the first pad, and the second end of the signal connection line is covered by the first end
  • the second pad is located above the position and has a second through hole at a position corresponding to the second pad.
  • the second end of the signal connecting line is generally designed to be thinner than the first end, thereby causing the first in the signal connection line.
  • the two ends are prone to ESD (electrostatic discharge), which causes the second end of the signal cable to burn out, resulting in poor array substrate.
  • the present invention aims to at least solve one of the technical problems existing in the prior art, and provides an array substrate and a display device for preventing a second end of an ESD burn-in signal connection line.
  • the technical solution adopted to solve the technical problem of the present invention is an array substrate including a driving chip and a signal connecting line, wherein a first end of the signal connecting line covers a position of a first pad corresponding to a peripheral circuit board Above, and having a first through hole at a position corresponding to the first pad; a second end of the signal connection line covering a position of a second pad corresponding to the driving chip, and A second through hole is disposed at a position corresponding to the second pad; wherein the array substrate further includes an electrostatic take-off unit, and the static electricity extracting unit is connected to the second end of the signal connection line.
  • an end of the electrostatic extraction unit remote from the signal connection line is thinner than a first end of the signal connection line.
  • an end of the electrostatic extraction unit remote from the signal connection line is thinner than a second end of the signal connection line.
  • the electrostatic extraction unit and the signal connection line are integrally formed.
  • the static electricity extracting unit is provided with a plurality of third through holes.
  • the material of the electrostatic extraction unit and the signal connection line is ITO.
  • the peripheral circuit board is a flexible circuit board.
  • the electrostatic extraction unit has a pointed shape.
  • the driving chip is a source driving chip and/or a gate driving chip.
  • a technical solution adopted to solve the technical problem of the present invention is a display device including the above array substrate.
  • the electrostatic extraction unit connected to the second end of the signal connection line is added to the array substrate of the present invention, the charge generated in the production process of the array substrate can be transferred to the electrostatic extraction unit, thereby avoiding the first in the signal connection line.
  • the two ends generate ESD and burn out the signal connection line, causing a problem of defective array substrate.
  • FIG. 1 is a schematic view of a peripheral region of a conventional array substrate
  • Fig. 2 is a schematic view showing a peripheral region of the embodiment 1 of the present invention.
  • the reference numerals are: 1, a signal connection line; 11, a first through hole; 12, a second through hole; 2, a first pad; 3, a driving chip; 31, a second pad; 4, an electrostatic extraction unit .
  • the embodiment provides an array substrate.
  • a driving chip 3 and a signal connecting line 1 are disposed in a peripheral region of the array substrate, wherein the first end of the signal connecting line 1 is covered with a peripheral circuit board.
  • a corresponding first pad 2 is located above the first pad 2 and has a first through hole 11 at a position corresponding to the first pad 2; the second end of the signal connection 1 is covered with the driving chip 3
  • the array substrate in the embodiment is further provided with an electrostatic extraction Unit 4, the static electricity extracting unit 4 is connected to the second end of the signal connection line 1.
  • the second end of the signal connection line 1 in the prior art is thinner than the first end, that is, the end of the signal connection line 1 connected to the driving chip 3 is thinner than the end connected to the first pad 2, thereby causing Most of the electric charge generated in the production process of the array substrate accumulates on the second end of the signal connection line 1, thereby causing ESD (electrostatic discharge) to be easily generated at the second end of the signal connection line 1, thereby causing the signal connection line 1 The second end burned.
  • an electrostatic extraction unit 4 connected to the second end of the signal connection line 1 is added.
  • the second end of the signal connection line 1 and the driving chip are still connected at the communication position of the original pad pad, and the electrostatic extraction unit is connected. 4 is not connected to the driving chip, so the charge generated in the production process of the array substrate can be transferred to the electrostatic extracting unit 4, thereby avoiding ESD at the second end of the signal connecting line 1 and burning the signal connecting line 1, causing the array substrate Bad problem.
  • the electrostatic extraction unit 4 and the signal connection line 1 in the present embodiment are integrally formed, and one end of the electrostatic extraction unit 4 remote from the signal connection line 1 is thinner than the first end of the signal connection line 1.
  • the reason for this is that the signal connection line 1 and the electrostatic extraction unit 4 can be prepared in one patterning process, thereby reducing the cost and increasing the productivity.
  • the shape of the static electricity extraction unit 4 may be a sharp angle, and of course, is not limited to such a shape, as long as the end of the electrostatic extraction unit 4 remote from the signal connection line 1 is thinner than the first end of the signal connection line 1. can.
  • one end of the electrostatic take-off unit 4 remote from the signal connection line 1 is thinner than the second end of the signal connection line 1. Under this configuration, the critical position is protected from damage by transferring the tip.
  • a plurality of third through holes 41 are provided in the static electricity extracting unit 4 .
  • the reason why the third through hole 41 is provided is to make the tip and the film layer of the second end of the signal connection line 1 connected thereto consistent, ensuring that the electrostatic extraction unit 4 can place the second end of the signal connection line 1.
  • the static electricity at the second through hole 12 is completely derived.
  • the driver chip 3 includes a source driver chip 3 and/or a gate driver chip 3 .
  • the signal connection line 1 may connect the source driving chip 3 to the flexible circuit board; or connect the gate driving chip 3 to the flexible circuit board; or connect the gate driving chip 3 to the source driving chip 3, and
  • the source driving chip 3 is connected to the flexible wiring board such that the source driving chip 3 supplies a high-low level signal to the gate driving chip 3.
  • This embodiment provides a display device including the array substrate in Embodiment 1. Since the electrostatic extraction unit 4 connected to the second end of the signal connection line 1 is added to the array substrate in Embodiment 1, the charge generated in the production process of the array substrate can be transferred to the electrostatic extraction unit 4, thereby avoiding the signal. The second end of the connection line 1 generates an ESD to burn out the signal connection line 1, causing a problem that the display device is defective.
  • the display device can be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the display device of the embodiment may further include other conventional structures such as a power supply unit, a display driving unit, and the like.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
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Abstract

本发明提供一种阵列基板及显示装置，属于显示技术领域。本发明的阵列基板，其包括驱动芯片、信号连接线，其中，所述信号连接线的第一端覆盖在与外围电路板对应的第一焊盘所在位置的上方，且在与所述第一焊盘对应的位置具有第一通孔；所述信号连接线的第二端覆盖在与所述驱动芯片对应的第二焊盘所在位置的上方，且在与所述第二焊盘对应的位置具有第二通孔；所述阵列基板上还设置静电引出单元，所述静电引出单元与所述信号连接线的第二端连接。本发明的技术方案可以将阵列基板的生产工艺中所产生的电荷转移到静电引出单元，从而避免在信号连接线的第二端产生 ESD 而烧毁信号连接线，造成阵列基板不良的问题。

Description

阵列基板及显示装置 技术领域
本发明属于显示技术领域，具体涉及一种阵列基板及显示装置。
背景技术
图1示意出现有的阵列基板的周边区域的结构，其包括驱动芯片、信号连接线、用于与柔性线路板绑定的第一焊盘，其中，所述驱动芯片上具有多个第二焊盘，所述信号连接线的第一端覆盖在所述第一焊盘所在位置的上方，且在与第一焊盘对应的位置具有第一通孔，信号连接线的第二端覆盖在第二焊盘所在位置的上方，且在与第二焊盘对应的位置具有第二通孔。
由于驱动芯片上的第二焊盘的面积较小，出于将低阻抗考虑，因此，通常将信号连接线的第二端设计成比第一端细的结构，从而导致在信号连接线的第二端容易产生ESD(静电释放)，进而造成信号连接线的第二端烧毁，造成阵列基板不良。
发明内容
本发明旨在至少解决现有技术中存在的技术问题之一，提供一种防止ESD烧毁信号连接线第二端的阵列基板及显示装置。
解决本发明技术问题所采用的技术方案是一种阵列基板，其包括驱动芯片、信号连接线，其中，所述信号连接线的第一端覆盖在与外围电路板对应的第一焊盘所在位置的上方，且在与所述第一焊盘对应的位置具有第一通孔；所述信号连接线的第二端覆盖在与所述驱动芯片对应的第二焊盘所在位置的上方，且在与所述第二焊盘对应的位置具有第二通孔；其中，所述阵列基板上还设置静电引出单元，所述静电引出单元与所述信号连接线的第二 端连接。
优选的是，所述静电引出单元的远离所述信号连接线的一端比所述信号连接线的第一端细。
优选的是，所述静电引出单元的远离所述信号连接线的一端比所述信号连接线的第二端细。
优选的是，所述静电引出单元与所述信号连接线为一体成型结构。
优选的是，所述静电引出单元上设置有多个第三通孔。
优选的是，所述静电引出单元和所述信号连接线的材料为ITO。
优选的是，所述外围电路板是柔性线路板。
优选的是，所述静电引出单元形状尖角状。
优选的是，所述驱动芯片为源极驱动芯片和/或栅极驱动芯片。
解决本发明技术问题所采用的技术方案是一种显示装置，其包括上述的阵列基板。
本发明具有如下有益效果：
由于在本发明的阵列基板上增加了与信号连接线第二端连接的静电引出单元，因此可以将阵列基板的生产工艺中所产生的电荷转移到静电引出单元，从而避免在信号连接线的第二端产生ESD而烧毁信号连接线，造成阵列基板不良的问题。
附图说明
图1为现有的阵列基板的周边区域的示意图；
图2为本发明的实施例1的周边区域的示意图。
其中附图标记为：1、信号连接线；11、第一通孔；12、第二通孔；2、第一焊盘；3、驱动芯片；31、第二焊盘；4、静电引出单元。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
实施例1：
如图2所示，本实施例提供一种阵列基板，在阵列基板的周边区域设置有驱动芯片3、信号连接线1，其中，所述信号连接线1的第一端覆盖在与外围电路板对应的第一焊盘2所在位置的上方，且在与所述第一焊盘2对应的位置具有第一通孔11；所述信号连接线1的第二端覆盖在与所述驱动芯片3对应的所述第二焊盘31所在位置的上方，且在与所述第二焊盘31对应的位置具有第二通孔12；特别的是，本实施例中的阵列基板上还设置静电引出单元4，所述静电引出单元4与所述信号连接线1的第二端连接。
由于现有技术中信号连接线1的第二端比第一端要细，也即信号连接线1与驱动芯片3连接的一端比与第一焊盘2连接的一端要细，因此，造成在阵列基板的生产工艺中所产生的电荷，大部分积累在信号连接线1的第二端上，从而导致在信号连接线1的第二端容易产生ESD(静电释放)，进而造成信号连接线1的第二端烧毁。而在本实施例的阵列基板上增加了与信号连接线1第二端连接的静电引出单元4，信号连接线1的第二端和驱动芯片依旧在原焊盘pad的连通位置连接，静电引出单元4不和驱动芯片连接，因此可以将阵列基板的生产工艺中所产生的电荷转移到静电引出单元4，从而避免在信号连接线1的第二端产生ESD而烧毁信号连接线1，造成阵列基板不良的问题。
其中，本实施例中的静电引出单元4与信号连接线1为一体成型结构，且静电引出单元4的远离信号连接线1的一端比所述信号连接线1的第一端细。
之所以如此设置是因为，可以将信号连接线1与静电引出单元4在一次构图工艺中制备，从而可以降低成本，同时可以增加产能。
其中，静电引出单元4的形状可以为尖角状，当然也不局限于该种形状，只要保证静电引出单元4的远离信号连接线1的一端比所述信号连接线1的第一端细即可。
其中，在一个优选实现中，静电引出单元4的远离信号连接线1的一端比所述信号连接线1的第二端细。在该结构下，通过将尖端转移保护关键位置免受损伤。
其中，在所述静电引出单元4上设置有多个第三通孔41。
之所以设置第三通孔41的目的是为了使尖端和与其相连的信号连接线1的第二端的膜层保持一致，确保此静电引出单元4能够将信号连接线1的第二端上的第二通孔12处的静电完全导出。
其中，驱动芯片3包括源极驱动芯片3和/或栅极驱动芯片3。此时，信号连接线1可以将源极驱动芯片3与柔性线路板连接；或者将栅极驱动芯片3与柔性线路板连接；亦或者将栅极驱动芯片3与源极驱动芯片3连接，以及将源极驱动芯片3连接柔性线路板，以使得源极驱动芯片3为栅极驱动芯片3提供高低电平信号。
实施例2：
本实施例提供一种显示装置，其包括实施例1中阵列基板。由于实施例1中的阵列基板上增加了与信号连接线1第二端连接的静电引出单元4，因此可以将阵列基板的生产工艺中所产生的电荷转移到静电引出单元4，从而避免在信号连接线1的第二端产生ESD而烧毁信号连接线1，造成显示装置不良的问题。
该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
当然，本实施例的显示装置中还可以包括其他常规结构，如电源单元、显示驱动单元等。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理 而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (10)

  1. 一种阵列基板，其包括驱动芯片、信号连接线，其中，所述信号连接线的第一端覆盖在与外围电路板对应的第一焊盘所在位置的上方，且在与所述第一焊盘对应的位置具有第一通孔；所述信号连接线的第二端覆盖在与所述驱动芯片对应的第二焊盘所在位置的上方，且在与所述第二焊盘对应的位置具有第二通孔；其特征在于，所述阵列基板上还设置静电引出单元，所述静电引出单元与所述信号连接线的第二端连接。
  2. 根据权利要求1所述的阵列基板，其特征在于，所述静电引出单元的远离所述信号连接线的一端比所述信号连接线的第一端细。
  3. 根据权利要求1所述的阵列基板，其特征在于，所述静电引出单元的远离所述信号连接线的一端比所述信号连接线的第二端细。
  4. 根据权利要求2或3所述的阵列基板，其特征在于，所述静电引出单元与所述信号连接线为一体成型结构。
  5. 根据权利要求1所述的阵列基板，其特征在于，所述静电引出单元上设置有多个第三通孔。
  6. 根据权利要求1所述的阵列基板，其特征在于，所述静电引出单元和所述信号连接线的材料为ITO。
  7. 根据权利要求1所述的阵列基板，其特征在于，所述外围电路板为柔性线路板。
  8. 根据权利要求1所述的阵列基板，其特征在于，所述静电引出单元形状为尖角状。
  9. 根据权利要求1所述的阵列基板，其特征在于，所述驱动芯片为源极驱动芯片和/或栅极驱动芯片。
  10. 一种显示装置，其特征在于，包括权利要求1-9中任一项所述的阵列基板。
PCT/CN2018/086662 2017-06-01 2018-05-14 阵列基板及显示装置 WO2018219128A1 (zh)

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101201482A (zh) * 2006-12-15 2008-06-18 胜华科技股份有限公司 具静电防护效果的液晶面板及其制造方法
CN204481026U (zh) * 2015-04-17 2015-07-15 京东方科技集团股份有限公司 一种阵列基板和显示装置
US20150331270A1 (en) * 2014-05-16 2015-11-19 Japan Display Inc. Display device
CN105655326A (zh) * 2014-12-01 2016-06-08 三星显示有限公司 具有改善的静电放电保护的显示装置
CN106094370A (zh) * 2016-08-17 2016-11-09 武汉华星光电技术有限公司 外围电路静电释放防护方法
CN106773414A (zh) * 2017-01-03 2017-05-31 京东方科技集团股份有限公司 接地防护电路及制作方法、阵列基板及制作方法、显示装置
CN106970496A (zh) * 2017-06-01 2017-07-21 京东方科技集团股份有限公司 阵列基板及显示装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW565719B (en) * 1998-03-13 2003-12-11 Toshiba Corp Manufacturing method of array substrate for display device
US6678018B2 (en) * 2000-02-10 2004-01-13 Samsung Electronics Co., Ltd. Thin film transistor array substrate for a liquid crystal display and the method for fabricating the same
WO2014163118A1 (ja) * 2013-04-05 2014-10-09 堺ディスプレイプロダクト株式会社 アクティブマトリクス回路、アクティブマトリクス回路の製造方法、及び画像表示装置
CN103925517B (zh) * 2013-11-27 2018-07-10 上海中航光电子有限公司 一种背光模组以及液晶显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101201482A (zh) * 2006-12-15 2008-06-18 胜华科技股份有限公司 具静电防护效果的液晶面板及其制造方法
US20150331270A1 (en) * 2014-05-16 2015-11-19 Japan Display Inc. Display device
CN105655326A (zh) * 2014-12-01 2016-06-08 三星显示有限公司 具有改善的静电放电保护的显示装置
CN204481026U (zh) * 2015-04-17 2015-07-15 京东方科技集团股份有限公司 一种阵列基板和显示装置
CN106094370A (zh) * 2016-08-17 2016-11-09 武汉华星光电技术有限公司 外围电路静电释放防护方法
CN106773414A (zh) * 2017-01-03 2017-05-31 京东方科技集团股份有限公司 接地防护电路及制作方法、阵列基板及制作方法、显示装置
CN106970496A (zh) * 2017-06-01 2017-07-21 京东方科技集团股份有限公司 阵列基板及显示装置

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