WO2018214743A1

WO2018214743A1 - Code error detection method and device for bit block stream

Info

Publication number: WO2018214743A1
Application number: PCT/CN2018/086326
Authority: WO
Inventors: 张小俊; 钟其文; 黄敬; 查敏
Original assignee: 华为技术有限公司
Priority date: 2017-05-24
Filing date: 2018-05-10
Publication date: 2018-11-29

Abstract

Provided are a code error detection method and device for a bit block stream, for solving the problems of a code error detection method being difficult to realize in an M/N bit block exchange situation and a low loading efficiency. The method comprises: sending a first boundary bit block, wherein the first boundary bit block is used for differentiating N subsequently sent bit blocks; sending an Ith bit block in sequence, wherein I is an integer greater than or equal to 1 and less than or equal to N; determining a first odd-even check result and a second odd-even check result, wherein a check object of the first odd-even check result comprises m consecutive bits of each bit block in the N bit blocks, and a check object of the second odd-even check result comprises n consecutive bits of each bit block in the N bit blocks, with at least one of m and n being greater than or equal to 2; and sending a second boundary bit block, the first odd-even check result and the second odd-even check result, wherein the second boundary bit block is used for differentiating the N bit blocks that have been sent.

Description

Bit block stream error detection method and device

Technical field

The present application relates to the field of communications technologies, and in particular, to a bit block stream error detection method and device.

Background technique

In the prior art, various methods for error detection based on a packet (PACKET) are proposed, for example, Cyclic Redundancy Check (CRC) detection based on PACKET. Each Ethernet packet is judged according to its Frame Check Sequence (FCS) field (CRC-32), and the quality of the user channel can be evaluated by counting the error packet rate over a period of time. However, the above method cannot accurately measure the bit error ratio (BER). When there is no user service data packet, the BER cannot be counted, or when the user service data packet is small, it takes a long time to detect the BER.

For example, according to an Ethernet packet FCS check error, when a Bit error is made, the BER of 1*e-5 is evaluated, and at least 100,000 Ethernet packets need to be continuously sent and received and detected. Assuming that the user service bandwidth is 10 Mbps, full traffic is sent, and the Ethernet packet length is 256 B, the detection time is at least 22.08 seconds. If the user service bandwidth is only 100Kbps and the Ethernet packet length is 256B, the detection time is at least 36.8 minutes (2208 seconds).

As shown in Table 1, the FCS occupies 4 bytes, so the above method still has the problem of occupying more fixed frame bytes, and the bearer efficiency is lower. The CRC-32 check is introduced. When the minimum packet is 64B, the bearer efficiency is reduced by 6.25%. When the maximum packet is 1518B, the bearer efficiency is reduced by 0.263%.

Table 1

In addition, the prior art also proposes a bit error detection method based on bit interleaving parity (BIP) per frame, for example, in Synchronous Digital Hierarchy (SDH), an optical transport network (Optical Transport Network) The frame structure in OTN) sets the overhead bytes of the BIP check. Therefore, this method bears the efficiency rigidity and cannot dynamically define the check algorithm according to user requirements, such as BIP-8 downgrading to BIP-4, or upgrading to BIP. -16.

At present, the fifth-generation communication technology (ie 5G) has been widely studied in the industry. Deterministic low-latency, reliability, and security isolation technologies have become an important issue for 5G to overcome. X-Ethernet (X-E) is a Bit Block switching technology based on the Ethernet physical layer, such as 64/66 Bit Block, which has the technical characteristics of deterministic ultra-low latency. The X-Ethernet is based on the M/N Bit block exchange. The error detection method can be used to perform error detection. For example, the following two methods can be used:

Method 1: Borrowing a method based on PACKET for CRC detection, X-E arranges several Bits to perform CRC check on a block by block, for example, a 66Bit Block, which can set 4 or 8 Bits to perform CRC check on other 60 or 56 Bits.

Method 2: Borrow SDH/OTN mode, arrange one byte or several Bits to implement BIP check by block, such as a 66Bit Block, you can set 2-8 Bits to perform BIP check on other 62-56 Bits.

Although the above two methods can be implemented, regardless of the method, the processing unit in the device needs to operate on a block by block, and thus the implementation is difficult. Moreover, the carrying efficiency of the above two methods is relatively low. For example, each block performs BIP-4/CRC-4 check, the bearer efficiency will decrease by 6.25%, and each block will be BIP-8/CRC-8, and the carrying efficiency will decrease. 12.5%.

Summary of the invention

The embodiment of the present invention provides a bit block stream error detection method and device, which are used to solve the problem that the error detection method in the M/N Bit block exchange scenario is difficult to implement and has low bearer efficiency.

In a first aspect, a bit block stream error detection method includes: transmitting a first boundary bit block, where a first boundary bit block is used to distinguish N pieces of subsequent transmission, N is a positive integer; and transmitting a first bit block in sequence I is an integer greater than or equal to 1 and less than or equal to N; determining a first parity result and a second parity result, the check object of the first parity result including consecutive bits of each of the N bit blocks m bits, the parity object of the second parity result includes consecutive n bits of each of the N bit blocks, at least one of m and n being greater than or equal to 2; transmitting the second boundary bit block, A parity result and a second parity block are used to distinguish N bits that have been transmitted.

Therefore, the method provided by the embodiment of the present application can completely implement the error or error detection of the M/N Bit Block network path, does not affect the user service, and has a bearer efficiency of 100%, and can be inserted or deleted due to the synchronization problem during the transmission process. The bit block, and the detection period (ie, the number of bit blocks between the two boundary bit blocks) and the detection accuracy (ie, the preset algorithm) are dynamically configurable as needed. In addition, the detection method can not only verify that the path of the bit fast stream is an end-to-end path, but also can use the path of the verified bit fast stream as a non-end-to-end path. Therefore, the method provided by the embodiment of the present application can solve the problem that the error detection method in the M/N Bit block exchange scenario is difficult to implement and has low bearer efficiency.

It should be understood that when the path of the verified bit fast stream is from the bit block transmitting end to the bit block receiving end, or when the path of the verified bit fast stream is from the bit block transmitting end to the bit block receiving end When any of the intermediate devices is used, the execution body of the above method may be a bit block transmitting end. When the path of the verified bit fast stream is from the bit block transmitting end to the bit block receiving end, the path of the verified bit fast stream is an end-to-end path. When the path of the verified bit fast stream is any intermediate device from the bit block transmitting end to the bit block receiving end, the path of the verified bit fast stream is a path that is suspended at one end. This application is collectively referred to as a transmitting device. Therefore, the embodiment of the present application can be used not only for error detection of an end-to-end path, but also for error detection of a non-end-to-end path, for example, a planned reserved path, and a protection path of a 1:1 connection protection group. Or have other special purpose paths. When the path of the verified bit fast stream is the second intermediate device from the first intermediate device after the bit block transmitting end to the bit block receiving end, the execution body of the above method may be the first intermediate device. The path of the bit fast stream being verified is a path that is suspended at both ends.

In one possible design, the type of each bit block is an M1/M2 bit block, where M1 represents the number of payload bits in each bit block, and M2 represents the total number of bits per bit block, M2-M1 Represents the number of header sync header bits in each bit block, M1, M2 are positive integers, M2>M1.

In a possible design, the sending the first boundary bit block includes: sending the first boundary bit block to the first device; and sequentially transmitting the first bit block, including: sequentially transmitting the first bit block to the first device; The two boundary bit block, the first parity result, and the second parity result may include two cases: (1) transmitting the second boundary bit block, the first parity result, and the second parity result to the first a device; therefore, in the above implementation, the first parity result and the second parity result are sent to the first device together with the N bit blocks between the two boundary bit blocks and the two boundary bit blocks, when When the path of the verified bit fast stream is from the bit block transmitting end to the bit block receiving end, the first device here may be the bit block receiving end, and when the verified bit fast stream path is the bit block transmitting end When going to any intermediate device before the bit block receiving end, or when the path of the verified bit fast stream is the second intermediate device from the first intermediate device after the bit block transmitting end to the bit block receiving end, here the first A device can also be an intermediate device. (2) transmitting the second boundary bit block to the first device, and transmitting the first parity result and the second parity result to the second device. It should be noted that the second device herein may be an SDN controller or any device having a function of determining a bit stream transmission error. In addition, the two methods can also be used at the same time, that is, the first parity result and the second parity result are sent to both the first device and the second device. Therefore, the embodiments of the present application provide two optional ways to implement error detection, which is more flexible and efficient, and is simple to implement.

In a possible design, the second boundary bit block, the first parity result, and the second parity result are sent, and the following possible implementation manners are: sending the second boundary bit block at the first moment, in the first The first parity result and the second parity result are sent at two moments, wherein the first moment is earlier than the second moment, or the first moment is later than the second moment, and the first moment is equal to the second moment.

In one possible design, the first parity result and the second parity result are stored in a second boundary bit block.

Therefore, assuming that each N bit block in the bit block stream is a group, the i-th boundary bit block stores the first parity result and the second parity result corresponding to the i-th N-bit block, i +1 boundary bit block stores a first parity result and a second parity result corresponding to the i+1th group of N bit blocks, wherein the i+1th group of N bit blocks is the ith boundary bit block A bit block between the i+1th boundary bit block and i is a positive integer.

It should be understood that the boundary bit block mentioned in this application may be a newly inserted bit block, and a new bit block may be deleted, and a first bit block may be deleted to reduce the impact on user bandwidth. The first bit block refers to a bit block in which N bit blocks may be inserted or deleted from N bit blocks during transmission of N bit blocks. For example, for a 64/66 bit block stream, the first block of bits may refer to a free block.

In a possible design, the first parity result and the second parity result are calculated according to a preset check algorithm, and the preset check algorithm is used to increase or decrease the first time in the N bit blocks. The first parity block does not change the first parity result and the second parity result, and the first bit block refers to a bit that may be inserted into or deleted from the N bit blocks during transmission of the N bit blocks. Piece. Therefore, the preset check algorithm provided by the embodiment of the present application can ensure that the first parity result and the second parity result can tolerate insertion or deletion of one or more first bit blocks (such as IDLE Block) during transmission. And when the first bit block has a bit error, it can also be detected.

In a possible design, the preset check algorithm is the xBIP-y algorithm, where x is the number of bits of consecutive bit interleaving, x is determined according to the definition of the pattern of the first bit block, and y is the monitoring area. The number of segments, x, y is a positive integer, y ≥ 2, for example, 8BIP-8 algorithm, 16BIP-4 algorithm. The specific method of determining the first parity result and the second parity result by using the xBIP-y algorithm is: starting from the first payload bit of the N bit blocks, sequentially recording every x consecutive bits of each bit block. Up to the first monitoring section to the yth monitoring section; determining a 1-bit monitoring code by using an odd or even parity for each monitoring section, obtaining a y-bit monitoring code, and the first parity is included in the y-bit monitoring code Verification result and second parity result. Therefore, the xBIP-y algorithm provided by the embodiment of the present application can tolerate insertion or deletion of one or more first bit blocks during transmission, and the method is simple.

In a possible design, the preset verification algorithm is the flexBIP-z algorithm, where z refers to the number of monitoring segments, and the number of consecutive bit interleaving bits corresponding to each monitoring segment is not the same, z monitoring The number of consecutive bit interleaving corresponding to the segments is A1, A2, A 3 ... Az-1, Az, A1, A2, A 3 ... Az-1, Az, z are positive integers, z ≥ 2; The specific method of determining the first parity result and the second parity result by the flexBIP-z algorithm is: starting from the first payload bit of the N bit blocks, recording the A1 consecutive bits in each bit block to the first One monitoring segment records A2 consecutive bits after A1 consecutive bits to the second monitoring segment, and records A3 consecutive bits after A2 consecutive bits to the third monitoring segment until Az- Az consecutive bits after 1 consecutive bits are recorded to the zth monitoring segment; an odd parity or even parity is used for each monitoring segment to determine a 1-bit monitoring code, and a z-bit monitoring code is obtained, and the z-bit monitoring code is obtained. A first parity result and a second parity result are included. Therefore, the flexBIP-z algorithm provided by the embodiment of the present application can more flexibly and succinctly determine the first parity result and the second parity result, and tolerate insertion or deletion of one or more first bit blocks during transmission.

In a possible design, determining the first parity result and the second parity result includes: determining a first verification result set, the first verification result set includes a y-bit monitoring code, or, the first school The result set includes a z-bit monitoring code; transmitting the first parity result and the second parity result, comprising: transmitting the first verification result set. Therefore, the error or error detection of the M/N Bit Block network path can be completely implemented by using the method provided by the embodiment of the present application.

In a second aspect, a bit block stream error detection method includes: receiving a first boundary bit block, where a first boundary bit block is used to distinguish T bits that are subsequently received, T is a positive integer; and receiving a first bit block in sequence I is an integer greater than or equal to 1 and less than or equal to T; receiving a second boundary bit block for distinguishing T bits that have been received; determining a third parity result and a fourth parity result The check object of the third parity result includes consecutive m bits of each of the T bit blocks, and the check object of the second parity result includes consecutive bits of each of the T bit blocks At least one of m bits, m, n is greater than or equal to 2; when receiving the first parity result and the second parity result, according to the first parity result and the third parity result, and Determining, by the second parity result and the fourth parity result, whether there is an error in the T bit blocks, wherein the check object of the first parity result includes consecutive m of each of the N bit blocks Bit, second parity The resulting check object includes consecutive n bits of each of the N bit blocks, and N is the first boundary bit block and the second boundary bit block when determining the first parity result and the second parity result. The number of bit blocks between. Therefore, the method provided by the embodiment of the present application can completely implement the error or error detection of the M/N Bit Block network path, does not affect the user service, and has a bearer efficiency of 100%, and can be inserted or deleted due to the synchronization problem during the transmission process. The bit block, and the detection period (ie, the number of bit blocks between the two boundary bit blocks) and the detection accuracy (ie, the preset algorithm) are dynamically configurable as needed. In addition, the detection method can not only verify that the path of the bit fast stream is an end-to-end path, but also can use the path of the verified bit fast stream as a non-end-to-end path. Therefore, the method provided by the embodiment of the present application can solve the problem that the error detection method in the M/N Bit block exchange scenario is difficult to implement and has low bearer efficiency.

It should be understood that when the path of the verified bit fast stream is from the bit block transmitting end to the bit block receiving end, the execution body of each step in FIG. 13 may be the bit block receiving end, when the checked bit is fast The path of the stream is any intermediate device from the transmitting end of the bit block to the receiving end of the bit block, or the execution body of the above method when the path of the bit stream to be verified is from the transmitting end of the bit block to the receiving end of the bit block Can be an intermediate device. This application is collectively referred to as a receiving device.

It should be noted that the N bit blocks here are the bit blocks between the first boundary bit block and the second boundary bit block when the first parity result and the second parity result are determined by the transmitting device. As an optional embodiment, after the sending device sends the first boundary bit block, sequentially transmitting N bit blocks, and then calculating the first parity result and the second parity result according to the N bit blocks, The two results are stored in a second boundary bit block, and the second boundary bit block is transmitted. However, considering that the path passing from the transmitting device to the receiving device traverses the asynchronous node, the first bit block may be inserted or deleted in the N bit blocks, and the receiving device sequentially receives the first boundary bit block after receiving the first bit block. T bit blocks, where N=T, or N>T (ie, inserting the first bit block in N bit blocks), or N<T (ie, deleting the first bit block in N bit blocks) )three situations.

In a possible design, the method further includes: sending the third parity result and the fourth parity result to the second device when the first parity result and the second parity result are not received, The second device stores the first parity result and the second parity result. It should be noted that the second device herein may be an SDN controller or any device having a function of determining a bit stream transmission error. Further, when the first parity result and the second parity result are received, the third parity result and the fourth parity result may also be transmitted to the second device. Therefore, the second device may receive the first parity result and the second parity result sent by the sending device, and the third parity result and the fourth parity result sent by the receiving device, and the second device according to the two The group result determines if there is a bit error during the transmission of the bit block stream. Therefore, the embodiment of the present application provides error detection by using a third-party device, such as an SDN controller, or any device having a function of determining a bit stream transmission error, which is more flexible and efficient, and is simple to implement.

In a possible design, receiving the second boundary bit block includes: receiving the second boundary bit block at the first time;

Receiving the first parity result and the second parity result, comprising: receiving the first parity result and the second parity result at a second time, wherein the first time is earlier than the second time, or the first The moment is later than the second moment, the first moment being equal to the second moment.

In a possible design, the third parity result and the fourth parity result are calculated according to a preset check algorithm, and the preset check algorithm is used to increase or decrease the first time in the T bit blocks. The third parity result and the fourth parity result are not changed in the bit block, and the first bit block refers to a bit that may be inserted into or deleted from the T bit blocks during transmission of the T bit blocks. Piece. Therefore, the preset check algorithm provided by the embodiment of the present application can ensure that the first parity result and the second parity result can tolerate insertion or deletion of one or more first bit blocks (such as IDLE Block) during transmission. And when the first bit block has a bit error, it can also be detected.

In addition, it should be understood that the receiving device determines a preset algorithm used by the third parity result and the fourth parity result, and a preset algorithm used by the transmitting device to determine the first parity result and the second parity result. The same, the repetition will not be repeated.

In a possible design, the preset check algorithm is the xBIP-y algorithm, where x is the number of bits of consecutive bit interleaving, x is determined according to the definition of the pattern of the first bit block, and y is the monitoring area. The number of segments, x, y is a positive integer, y ≥ 2;

Determining the third parity result and the fourth parity result, comprising: sequentially recording every x consecutive bits of each bit block to the first monitoring area, starting from the first payload bit of the T bit blocks Segment to yth monitoring section; determining a 1-bit monitoring code using odd or even parity for each monitoring section, obtaining a y-bit monitoring code, the y-bit monitoring code including a third parity result and a fourth Parity result. Therefore, the xBIP-y algorithm provided by the embodiment of the present application can tolerate insertion or deletion of one or more first bit blocks during transmission, and the method is simple.

In a possible design, the preset verification algorithm is the flexBIP-z algorithm, where z refers to the number of monitoring segments, and the number of consecutive bit interleaving bits corresponding to each monitoring segment is not the same, z monitoring The number of consecutive bit interleaving corresponding to the segments is A1, A2, A 3 ... Az-1, Az, A1, A2, A 3 ... Az-1, Az, z are positive integers, z ≥ 2;

Determining the third parity result and the fourth parity result, comprising: recording, from the first payload bit of the T bit blocks, A1 consecutive bits of each bit block to the first monitoring segment, Recording A2 consecutive bits after A1 consecutive bits to the second monitoring segment, and recording A3 consecutive bits after A2 consecutive bits to the third monitoring segment until after Az-1 consecutive bits Az consecutive bits are recorded to the zth monitoring section; an odd parity or even parity is used for each monitoring section to determine a 1-bit monitoring code to obtain a z-bit monitoring code, and the z-bit monitoring code includes a third parity The result and the fourth parity result. Therefore, the flexBIP-z algorithm provided by the embodiment of the present application can more flexibly and succinctly determine the first parity result and the second parity result, and tolerate insertion or deletion of one or more first bit blocks during transmission.

In a possible design, determining whether there are bit errors in the T bit blocks according to the first parity result and the third parity result, and the second parity result and the fourth parity result, including: If it is determined that the first parity result and the third parity result are the same, and the second parity result and the fourth parity result are the same, determining that there are no error in the T bit blocks; if the first parity is determined The result of the verification is not the same as the third parity result, and/or the second parity result and the fourth parity result are not the same, and it is determined that there are bit errors in the T bit blocks.

In a possible design, receiving the first parity result and the second parity result, comprising: receiving a first check result set, where the first check result set is calculated according to an xBIP-y algorithm, The first parity result and the second parity result are included in the y-bit monitoring code included in the verification result set; determining the third parity result and the fourth parity result, including: determining the second verification result The second parity result is calculated according to the xBIP-y algorithm, and the y-bit monitoring code included in the second verification result set includes a third parity result and a third parity result;

When receiving the first parity result and the second parity result, determining T according to the first parity result and the third parity result, and the second parity result and the fourth parity result Whether there is an error in the bit block includes: determining whether there is a bit error in the T bit block according to the first check result set and the second check result set. Therefore, the error or error detection of the M/N Bit Block network path can be completely implemented by using the method provided by the embodiment of the present application.

In a possible design, receiving the first parity result and the second parity result, comprising: receiving a first check result set, where the first check result set is calculated according to a flexBIP-z algorithm, a z-bit monitoring code included in a set of verification results includes a first parity result and a second parity result; determining the third parity result and the fourth parity result, comprising: determining a second verification result The set, the second check result set is calculated according to the flexBIP-z algorithm, and the z-bit monitoring code included in the second check result set includes the third parity result and the fourth parity result; when receiving the first a parity result and a second parity result, based on the first parity result and the third parity result, and the second parity result and the fourth parity result, determining whether T bit blocks are The error code includes: determining, according to the first verification result set and the second verification result set, whether the T bit blocks have an error. Therefore, the error or error detection of the M/N Bit Block network path can be completely implemented by using the method provided by the embodiment of the present application.

In a possible design, determining whether the T bit blocks have an error according to the first check result set and the second check result set includes: determining the first check result set and the second check result set If the same, it is determined that there are no error codes in the T bit blocks; if it is determined that the first check result set and the second check result set are not the same, it is determined that the T bit blocks have an error.

A third aspect, a bit block stream error detection method, comprising: determining, by a first device, that a start byte in a start block in a bit block stream and an end byte in an end block corresponding to the start block are detected a segment; the first device calculates a first verification result according to the detected segment. The first device transmits the first check result and the bit block stream. For example, the algorithm used by the first device to calculate the first check result may be CRC-x or BIP-x, and the first check result is recorded as B, and B may be one or more bytes. Therefore, the error or error detection of the M/N Bit Block network path can be completely implemented by using the method provided in the embodiment of the present application, which has little impact on the user service and is close to the SDH/OTN, and is superior to the error detection provided in the prior art. Method, the implementation process is simple and easy to implement.

In one possible design, the bit block stream includes at least one M1/M2 bit block; wherein M1 represents the number of payload bits in each bit block, M2 represents the total number of bits per bit block, and M2-M1 represents The number of header sync header bits in each bit block, M1, M2 are positive integers, M2>M1.

In a possible design, the first device sends the first check result and the bit block stream, including: the first device sends the first check result and the bit block stream to the second device; or the first device sends the first The result of the verification is sent to the third device, and the bit block is sent to the second device. Therefore, the embodiment of the present application provides error detection by using a third-party device, such as an SDN controller, or any device having a function of determining a bit stream transmission error, which is more flexible and efficient, and is simple to implement.

In a possible design, before the first device sends the first verification result and the bit block stream to the second device, the method further includes: the first device storing the first verification result in the end block, and obtaining the updated Ending the block; or, the first device stores the first check result in the check result storage block, and deletes any first bit block in the bit block stream, wherein the check result storage block refers to before the end block A new block, the first block of bits refers to a block of bits that may be inserted into or deleted from the block stream during transmission of the block stream. Therefore, the embodiment of the present application provides two methods for storing the first verification result, and the storage method is more flexible and simple to implement.

In a possible design, the first device stores the first check result in the end block, and obtains the updated end block, including: when the number of bytes occupied by the first check result is greater than or equal to the target number of bytes, The first device stores the first check result before the end byte in the end block, and moves the end byte to a new block after the end block according to the number of bytes occupied by the first check result, and deletes the bit block. Any first block in the stream, the new block where the end byte is moved is used as the updated end block; when the number of bytes occupied by the first check result is less than the target number of bytes, the first device will The first check result is stored before the end byte in the end block, and the end byte is shifted back by the number of bytes occupied by the first check result according to the number of bytes occupied by the first check result, and the end byte is moved. The bit block that is located later is used as the updated end block; wherein the target number of bytes is the number of bytes in the end block after the end byte plus one. Therefore, the method provided by the embodiment of the present application is simple to implement.

A fourth aspect, a bit block stream error detection method, comprising: determining, by the second device, that the start byte in the start block in the bit block stream and the end byte in the end block corresponding to the start block are detected a segment; the second device calculates a second verification result according to the detected segment. When the second device receives the first verification result, the second device determines, according to the first verification result and the second verification result, whether the detected segment has an error. Therefore, the error or error detection of the M/N Bit Block network path can be completely implemented by using the method provided in the embodiment of the present application, which has little impact on the user service and is close to the SDH/OTN, and is superior to the error detection provided in the prior art. Method, the implementation process is simple and easy to implement.

The algorithm used by the second device in calculating the second verification result is the same as the algorithm used when the first device calculates the first verification result.

In a possible design, the second device determines the detected segment according to the start byte in the start block in the bit block stream and the end byte in the end block corresponding to the start block, including three possible Case: (1) When the second device receives the first verification result, and the first verification result is stored in the end block, the second device deletes the second verification result from the end block, and obtains the updated end block. a byte between the start byte in the start block and the end byte in the updated end block as the detected segment; (2) when the second device receives the first check result, and When a check result is stored in the check result storage block, the second device deletes the check result storage block from the bit block stream, and obtains the updated bit block stream, which is to be updated in the start block in the bit block stream. The byte between the start byte and the end byte in the end block is taken as the detected segment, wherein the check result storage block is located before the end block. In the above two cases, the first check result is included in the byte between the start byte in the start block and the end byte in the end block. Therefore, the first check result needs to be deleted first, and the remaining The part is taken as the detected section. In addition, when the second device receives the first check result, and the first check result is stored in the check result storage block, the second device deletes the check result storage block from the bit block stream, and obtains the updated bit. A block stream in which the check result storage block is located before the end block. At the same time, in order to reduce the impact on the user bandwidth, it is necessary to add a first bit block after the end block. (3) When the second device does not receive the first check result, the second device detects the byte between the start byte in the start block and the end byte in the end block in the bit block stream as the detected Section. At this time, the byte between the start byte in the start block and the end byte in the end block does not include the first check result, and can be directly used as the detected segment.

In a possible design, the method further includes: when the second device does not receive the first verification result, the second device sends the second verification result to the third device, where the third device stores the first verification result. . Therefore, the embodiment of the present application provides two methods for storing the first verification result, and the storage method is more flexible and simple to implement.

In a possible design, the second device determines, according to the first verification result and the second verification result, whether the detected segment has an error, including: if the second device determines the first verification result and the second calibration If the test result is the same, it is determined that there is no error in the detected segment; if it is determined that the first verification result is different from the second verification result, it is determined that the detected segment has an error.

In a possible design, the second device deletes the first check result from the end block, and obtains the updated end block, including: when the number of bytes occupied by the first check result is greater than or equal to the target number of bytes The second device moves the end byte to a bit block before the end block according to the number of bytes occupied by the first check result, and adds a first bit block to the bit block stream, where the end byte is moved. The bit block is used as the updated end block; when the number of bytes occupied by the first check result is less than the target number of bytes, the second device moves the end byte to the first school according to the number of bytes occupied by the first check result. The number of bytes occupied by the result is the updated end block after the end byte is moved; wherein the target number of bytes is the number of bytes in the end block before the end byte plus one. Therefore, the method provided by the embodiment of the present application is simple to implement.

A fifth aspect, a bit block stream error detecting apparatus, comprising: a processor, a transceiver, the transceiver is configured to send a bit stream block, and the processor is configured to complete the first aspect according to the bit stream block sent by the transceiver or A method in any of the possible implementations of the first aspect.

In a sixth aspect, a bit block stream error detecting apparatus includes a processor, a transceiver, the transceiver is configured to receive a bit stream block, and the processor is configured to complete the foregoing second aspect according to the bit stream block received by the transceiver or A method in any of the possible implementations of the second aspect.

A seventh aspect, a bit block stream error detecting apparatus, comprising: a processor, a transceiver, the transceiver is configured to send a bit stream block, and the processor is configured to complete the first aspect according to the bit stream block sent by the transceiver or A method in any of the possible implementations of the first aspect.

In an eighth aspect, a bit block stream error detecting apparatus includes a processor, a transceiver, the transceiver is configured to receive a bit stream block, and the processor is configured to complete the second aspect according to the bit stream block received by the transceiver or A method in any of the possible implementations of the second aspect.

The embodiment of the present application proposes a new device for transmitting an M1/M2 bit block stream. A new bit error detection unit is also called a bit error ratio (BER) unit, which is referred to as BER. This unit is used to calculate the check result and error detection. The PE device includes uAdpt, L1.5Switch, nAdpt, and BER. One end is connected to the user equipment, the interface is UNI, the other end is connected to the network device, the interface is NNI, and the P device includes uAdpt, L1.5Switch, nAdpt, and BER. Both ends are connected to the network device, and the interface is NNI, as shown in Figure 23(a) and Figure 23(b).

The embodiment of the present application further provides a packet bearer product, such as an IPRAN and PTN device that plans to load X-E features. Referring to FIG. 24, the present application provides a packet bearer product, where the interface board can be an interface card of a box device or an interface chip of a line card of a box device.

Alternatively, the embodiment of the present application further provides a packet bearer product. Referring to FIG. 25, the present application provides a new type of chip, such as SDxxxx, which is built into the chip, or in an existing interface chip, such as SDyyyy and the host. Between the switch boards, a Field-Programmable Gate Array (FPGA) or Network Processor (NP) is added to implement the BER function through the FPGA or NP.

In a ninth aspect, the present application provides a computer readable storage medium having stored therein instructions that, when run on a computer, cause the computer to perform any of the above aspects or any of the possible aspects of the first aspect Methods.

In a tenth aspect, the present application also provides a computer program product comprising instructions which, when run on a computer, cause the computer to perform the method of any of the first aspect or the first aspect of the first aspect described above.

DRAWINGS

1 is a schematic diagram of a code pattern definition of a 64/66 bit code in an embodiment of the present application;

2 is a schematic diagram of a code pattern definition of a free block in the embodiment of the present application;

FIG. 3(a) is a schematic structural diagram of a PE device in an embodiment of the present application;

FIG. 3(b) is a schematic structural diagram of a P device in an embodiment of the present application;

4 is a schematic diagram of constructing a network by using X-E technology and forwarding in the embodiment of the present application;

FIG. 5 is a schematic diagram of the basic idea of BIP-8 in the embodiment of the present application; FIG.

6 is a method for detecting a bit block stream error in the embodiment of the present application;

FIG. 7 is a schematic diagram of the location and pattern definition of a second boundary bit block in the embodiment of the present application; FIG.

FIG. 8 is a schematic diagram of inserting a first bit block in an embodiment of the present application;

FIG. 9 is a schematic diagram of the basic idea of 8BIP-8 in the embodiment of the present application;

10 is a schematic diagram of the basic idea of 16BIP-4 in the embodiment of the present application;

11(a) is a schematic diagram showing the basic idea of flexBIP-8 in the embodiment of the present application;

11(b) is a schematic diagram showing the basic idea of flexBIP-9 in the embodiment of the present application;

12 is a second method for detecting a bit block stream error in the embodiment of the present application;

FIG. 13 is a third embodiment of a bit block stream error detection method according to an embodiment of the present application;

14 is a schematic diagram of a 64/66 bitstream in an embodiment of the present application;

15 is a schematic diagram of a code pattern definition of a pure data block D in the embodiment of the present application;

16 is a schematic diagram of a code pattern definition of a starting block in an embodiment of the present application;

17 is a schematic diagram of a code pattern definition of an end block in an embodiment of the present application;

FIG. 18 is a schematic diagram of a first device storing a first verification result in an end block according to an embodiment of the present application;

FIG. 19 is a schematic diagram of the first device using the CRC-8 or the BIP-8 to calculate the first check result B insertion end block in the embodiment of the present application;

FIG. 20 is a schematic diagram of a newly added bit block before a first device inserts a first check result B into an end block according to an embodiment of the present application;

21 is a fourth embodiment of a bit block stream error detection method according to an embodiment of the present application;

FIG. 22 is a schematic diagram of a first verification result B in a second device deletion end block according to an embodiment of the present application;

23(a) is a second schematic structural diagram of a PE device in an embodiment of the present application;

23(b) is a second schematic structural diagram of a P device in an embodiment of the present application;

24 is a schematic structural diagram of a packet bearer product in an embodiment of the present application;

25 is a second schematic structural diagram of a packet bearer product in an embodiment of the present application;

26 is a schematic diagram of error detection of an end-to-end path of a bit fast stream to be verified in the embodiment of the present application;

27(a) is a schematic diagram of error detection of a path of a bit fast stream that is verified to be a non-end-to-end path in the embodiment of the present application;

27(b) is a second schematic diagram of error detection of a path of a bit fast stream that is verified to be a non-end-to-end path in the embodiment of the present application;

28 is a schematic structural diagram of a bit block stream error detecting apparatus according to an embodiment of the present application;

FIG. 29 is a second schematic structural diagram of a bit block stream error detecting apparatus according to an embodiment of the present application;

FIG. 30 is a third schematic structural diagram of a bit block stream error detecting apparatus according to an embodiment of the present application;

FIG. 31 is a fourth schematic structural diagram of a bit block stream error detecting apparatus according to an embodiment of the present application.

detailed description

Embodiments of the present application will be described below with reference to the accompanying drawings.

The bit block mentioned in the embodiment of the present application is an M1/M2 bit block, and the M1/M2 bit represents an encoding mode, where M1 represents the number of payload bits in each bit block, and M2 represents each bit. The total number of bits of the bit block, M2-M1 represents the number of header sync header bits in each bit block, M1, M2 are positive integers, M2>M1.

The M1/M2 bit block stream is transmitted on the Ethernet physical layer link. For example, 1G Ethernet uses 8/10Bit encoding, 1GE physical layer link delivers 8/10 Bit Block stream, and 10GE/40GE/100GE adopts 64/. 66 bit code, 10GE/40GE/100GE physical layer link is the 64/66 Bit Block stream. In the future, with the development of Ethernet technology, other coding methods will also appear, such as 128/130 bit encoding and 256/258 bit encoding. For convenience of description, the embodiment of the present application is uniformly represented by an M1/M2 bit block stream.

For the M1/M2 bit block stream exchanged by the L1.5 layer, there are different types of Bit Blocks and are clearly defined in the standard. The following is an example of a 64/66 bit coded pattern definition, as shown in FIG. The first two Bits "10" or "01" of the header are 64/66 Bit Block sync header bits, and the last 64 Bit is used to carry payload data or protocols. Figure 1 includes 16 pattern definitions, each of which represents a pattern definition of a block of bits, where D0-D7 represents the data byte, C0-C7 represents the control byte, S0 represents the start byte, and T0-T7 represents the code. End byte, the second line corresponds to the pattern definition of the IDLE Block, and the free block can be represented by /I/, as shown in Figure 2. Line 7 corresponds to the definition of the pattern of the starting block. The starting block can be represented by /s/, the lines 9-16 correspond to the pattern definition of the 8 ending blocks, and the 8 ending blocks can be represented by /T/.

Further, in the XE technology system, the device shown in FIG. 3(a) and FIG. 3(a) is used to transmit the M1/M2 bit block stream, specifically, as shown in FIG. 3(a) and FIG. 3(b). , including PE equipment and P equipment. The PE device represents an edge device, and one end is connected to the user device. The interface is a user network interface (UNI), the other end is connected to the network device, the interface is NNI, and the P device represents the network device. Both ends are connected to the network. The device is connected. The interface is the network to network interface (NNI) between the networks or devices in the network.

As shown in FIG. 3(a), the client signal adaptation unit (uAdpt) represents a user-side processing unit of the X-E technology system for accessing user service signals and performing code conversion, rate adaptation, and the like. The network signal adaptation unit (nAdpt) represents a network side processing unit of the XE technology system, and is configured to send the service signal in the device to the network side and complete corresponding function processing; or receive the network side service signal and transmit it to other processing units in the device. . The L1.5switch or the X-Ethernet switch, that is, the X-Ethernet Relay (that is, the forwarding of the intermediate node), is embodied as a switching unit.

As shown in FIG. 4, in order to construct a network and forward it by using X-E technology, the path shown in FIG. 4 is an X-E end-to-end forwarding path.

In addition, a brief introduction to the two common verification algorithms used in the embodiments of the present application.

(1) BIP-x: Based on the BIP algorithm, the basic idea of the algorithm is to divide the verified signal into X check blocks. For example, SDH adopts BIP-16, BIP-8, BIP-2, and OTN adopts BIP- 8.

For example, referring to FIG. 5, the 8-bit monitoring code generation process shown by BIP-8 can be briefly described as follows: all the verified parts of the bit stream are grouped into 8 bits, and are divided into a series of 8-bit sequences. Code group. The BIP-8 code is used as the first column, and the first 8-bit sequence is the second column, which is sequentially arranged into a monitoring matrix. Then, the first bit of each 8-bit sequence code group and the first bit of the BIP-8 code form a first monitoring code group (first line of the matrix), and the second bit and BIP of each 8-bit sequence code group The 2nd bit of the -8 code constitutes the 2nd monitoring code group (the second line of the matrix), and so on. Finally, the first bit of the BIP-8 code provides even parity for the first monitoring code group (ie, the number of "1"s in the monitoring code group is even), and the second bit of the BIP-8 code is the first bit. 2 The monitoring code group provides even parity, and so on. It should be noted that odd parity can also be used here.

(2) CRC-x: based on the CRC algorithm, wherein the standardized algorithms include CRC-4, CRC-8, CRC-16, CRC-32, etc., and the X-bit loop check is performed on the verified signal, and the Ethernet frame or The packet uses CRC-32 to store the CRC-32 result in the last FCS field (4 bytes) of the frame or packet.

Referring to FIG. 6, the embodiment of the present application provides a bit block stream error detection method, which solves the problem that the error detection method in the M/N Bit block exchange scenario is difficult to implement and has low bearer efficiency. . The method comprises:

Step 600: Send a first boundary bit block, where the first boundary bit block is used to distinguish N pieces of subsequent transmission, and N is a positive integer.

Step 610: The first bit block is sequentially transmitted, where I is an integer greater than or equal to 1 and less than or equal to N.

Step 620: Determine a first parity result and a second parity result, where the check object of the first parity result includes consecutive m bits of each of the N bit blocks, and the second parity The resulting check object includes consecutive n bits of each of the N bit blocks, at least one of m, n being greater than or equal to two.

Step 630: Send a second boundary bit block, a first parity result, and a second parity result, where the second boundary bit block is used to distinguish N bits that have been transmitted.

It should be understood that when the path of the checked bit block stream is from the bit block transmitting end to the bit block receiving end, or when the path of the checked bit block stream is from the bit block transmitting end to the bit block receiving end When any of the intermediate devices is used, the execution body of each step in FIG. 6 may be a bit block transmitting end. When the path of the checked bit block stream is from the bit block transmitting end to the bit block receiving end, the path of the checked bit block stream is an end-to-end path. When the path of the checked bit block stream is any intermediate device from the bit block transmitting end to the bit block receiving end, the path of the checked bit block stream is a path that is suspended at one end. This application is collectively referred to as a transmitting device.

Therefore, the embodiment of the present application can be used not only for error detection of an end-to-end path, but also for error detection of a non-end-to-end path, for example, a planned reserved path, and a protection path of a 1:1 connection protection group. Or have other special purpose paths.

When the path of the checked bit block stream is the second intermediate device from the first intermediate device after the bit block transmitting end to the bit block receiving end, the execution body of each step in FIG. 6 may be the first intermediate device. The path of the bitstream to be verified is a path that is suspended at both ends.

For the step 600, step 610, step 630, the embodiment of the present application provides the following two possible implementation manners:

The first possible implementation:

Transmitting a first boundary bit block to the first device;

Transmitting the first bit block to the first device in sequence;

Transmitting a second boundary bit block, a first parity result, and a second parity result to the first device;

Therefore, in the above implementation manner, the first parity result and the second parity result are transmitted to the first device together with the N bit blocks between the two boundary bit blocks and the two boundary bit blocks, when being When the path of the bit block stream is from the bit block transmitting end to the bit block receiving end, the first device here may be the bit block receiving end, and the path of the checked bit block stream is from the bit block transmitting end to the bit When the intermediate device before the block receiving end, or when the path of the verified bit block stream is the second intermediate device from the first intermediate device after the bit block transmitting end to the bit block receiving end, the first here A device can also be an intermediate device.

The second possible implementation:

Transmitting a first boundary bit block to the first device;

Transmitting the first bit block to the first device in sequence;

Transmitting the second boundary bit block to the first device, transmitting the first parity result and the second parity result to the second device.

It should be noted that the second device herein may be an SDN controller or any device having a function of determining a bit stream transmission error.

In addition, the two methods can also be used at the same time, that is, the first parity result and the second parity result are sent to both the first device and the second device.

Further, it should be understood that the second boundary bit block is sent at the first moment, and the first parity result and the second parity result are sent at the second moment, where the first moment is earlier than the second moment, or The first moment is later than the second moment, and the first moment is equal to the second moment.

The check object of the first parity result may be consecutive m bits of each of the N bit blocks, and the check object of the second parity result may be each of the N bit blocks a consecutive n bits, in a possible implementation manner, the check object of the first parity result may include the foregoing, in addition to the consecutive m bits of each of the N bit blocks The consecutive m bits of a boundary bit block may also include consecutive m bits of the second boundary bit block; likewise, the check object of the second parity result includes, in addition to each bit block of the N bit blocks. In addition to the consecutive n bits, it may also include consecutive n bits of the first boundary bit block, and may also include consecutive n bits of the second boundary bit block.

In a possible implementation manner, the first parity result and the second parity result may be stored in the second boundary bit block. Therefore, assuming that each N bit block in the bit block stream is a group, the i-th boundary bit block stores the first parity result and the second parity result corresponding to the i-th N-bit block, i +1 boundary bit block stores a first parity result and a second parity result corresponding to the i+1th group of N bit blocks, wherein the i+1th group of N bit blocks is the ith boundary bit block A bit block between the i+1th boundary bit block and i is a positive integer.

It should be understood that the boundary bit block mentioned in this application may be a newly inserted bit block, and a first bit block may be deleted while a boundary bit block is newly inserted, wherein the first bit block refers to N bit blocks or bit blocks deleted from N bit blocks may be inserted during transmission of a bit block. For example, for a 64/66 bit block stream, the first block of bits may refer to a free block.

As an optional embodiment, as shown in FIG. 7, taking a 64/66 bit block stream as an example, after determining the first parity result and the second parity result, the second boundary bit block is in FIG. The bit block pattern definition corresponding to the 8th line, that is, the type of the bit block is 0x4B, the O code of the bit block is 0x06, and the first parity result and the second parity result are stored in the 3 Data fields of the bit block. The unoccupied Data field Bit fills in binary 0. Therefore, the second boundary bit block is inserted after the N bit blocks, and in order to reduce the influence on the user bandwidth, one free block can be deleted.

Considering that the M1/M2 bit block stream traverses the asynchronous node during transmission (that is, the receiving clock is not completely synchronized with the node clock and the transmitting clock), the frequency influence is generally eliminated by inserting or deleting the first bit block. For example, a 64/66 bit block stream is implemented by inserting or deleting an IDLE Block, as shown in FIG. Therefore, when the first parity result and the second parity result are determined in step 620, if the existing BIP-x algorithm is used, the first parity result is affected by inserting or deleting the first bit block during transmission. And the second parity result.

In the embodiment of the present application, the first parity result and the second parity result are calculated according to a preset check algorithm, where the preset check algorithm is used to increase or decrease the first bit in the N bit blocks. The first parity result and the second parity result are not changed at the time of the block.

Specifically, to ensure that the first parity result and the second parity result can tolerate insertion or deletion of one or more first bit blocks (such as IDLE Block) during transmission, and when the first bit block is in error It can also be detected. This application transforms the existing BIP algorithm, which can include but is not limited to the following two algorithms:

Algorithm 1: The preset check algorithm is the xBIP-y algorithm, where x is the number of bits of consecutive bit interleaving, x is determined according to the definition of the pattern of the first bit block, and y is the number of monitored segments, x, y is a positive integer, y ≥ 2.

Starting from the first payload bit of the N bit blocks, every x consecutive bits of each bit block are sequentially recorded to the first monitoring segment to the yth monitoring segment; The parity or even parity determines a 1-bit monitoring code to obtain a y-bit monitoring code, and the y-bit monitoring code includes a first parity result and a second parity result.

It should be understood that the sync bit header in each bit block is not included in the calculation of the first parity result and the second parity result.

As an alternative implementation, as shown in FIG. 9, the existing BIP-x algorithm can be regarded as a special case of the xBIP-y algorithm (ie, a scene of x=1). Figure 8 is a schematic diagram of the 64/66 Bit Block using the 8BIP-8 algorithm. Among them, B0-B7 is 8 monitoring codes (also called check codes) included in the 8BIP-8 algorithm, and each monitoring code corresponds to one monitoring segment, which provides an odd test or even for the bits included in the corresponding monitoring segment. check. Each monitoring segment corresponds to 8 consecutive bits of each bit block, for example, the first monitoring segment corresponds to the first payload bit to the eighth payload bit of each bit block, and the second monitoring segment Corresponding to the ninth payload bit to the 16th payload bit of each bit block, ..., the eighth monitoring segment corresponds to the 57th payload bit to the 64th payload bit of each bit block. Specifically, the inserted IDLE Block has the first byte being 0x1e and the others being 0. The first byte of the IDLE Block enters the 1st monitoring section of 8BIP-8, and the other bytes enter the 2-8th monitoring section. 0x1e has 4 binary 1s, other fields are 0, and there are 0 binary ones. Therefore, no matter how many IDLE blocks are inserted or deleted during transmission, the verification results of B0--B7 are not affected.

As an alternative implementation, such as shown in FIG. 10, FIG. 10 is a schematic diagram of the 64/66 Bit Block using the 16BIP-4 algorithm. Among them, B0-B3 is a four monitoring code (also called a check code) included in the 16BIP-4 algorithm, and each monitoring code corresponds to one monitoring section, providing an odd test or even for the bits included in the corresponding monitoring section. check. Each monitoring section corresponds to 16 consecutive bits of each bit block, for example, the first monitoring section corresponds to the first payload bit of each bit block to the 16th payload bit, and the second monitoring section Corresponding to the 17th payload bit of each bit block to the 32nd payload bit, the third monitoring segment corresponds to the 33rd payload bit of each bit block to the 48th payload bit, the 4th monitoring The segment corresponds to the 49th payload bit to the 64th payload bit of each bit block.

Algorithm 2: The preset check algorithm is a flexBIP-z algorithm, where z refers to the number of monitored segments, and the number of consecutive bit interleaving bits corresponding to each monitoring segment is not the same, and z monitoring segments respectively correspond to The number of bits of consecutive bit interleaving is A1, A2, A 3 ... Az-1, Az, A1, A2, A 3 ... Az-1, Az, z are positive integers, z ≥ 2.

Starting from the first payload bit of the N bit blocks, A1 consecutive bits in each bit block are recorded to the first monitoring segment, and A2 consecutive bits after A1 consecutive bits are recorded to the second Monitoring section, recording A3 consecutive bits after A2 consecutive bits to the third monitoring section until Az consecutive bits after Az-1 consecutive bits are recorded to the zth monitoring section; The monitoring section determines the 1-bit monitoring code by using odd or even parity to obtain a z-bit monitoring code, and the z-bit monitoring code includes a first parity result and a second parity result.

As an alternative implementation, such as shown in Figure 11(a), Figure 11(a) is a schematic diagram of the 64/66 Bit Block using the flexBIP-8 algorithm. Among them, B0-B7 is 8 monitoring codes included in the flexBIP-8 algorithm, and each monitoring code corresponds to one monitoring section, and provides odd or even parity for the bits included in the corresponding monitoring section. The first monitoring segment corresponds to the first payload bit to the eighth payload bit of each bit block, and the second monitoring segment corresponds to the ninth payload bit to the 18th payload bit of each bit block. The third monitoring section corresponds to the 19th payload bit to the 24th payload bit of each bit block, and the 4th monitoring section corresponds to the 25th payload bit to the 33rd payload bit of each bit block, The fifth monitoring segment corresponds to the 34th payload bit to the 40th payload bit of each bit block, and the sixth monitoring segment corresponds to the 41st payload bit to the 48th payload of each bit block. Bit, the seventh monitoring section corresponds to the 49th payload bit of each bit block to the 58th payload bit, and the 8th monitoring section corresponds to the 59th payload bit of each bit block to the 64th Payload bits.

As an alternative implementation, for example, as shown in FIG. 11(b), FIG. 11(b) is a schematic diagram of the 64/6B Bit Block using the flexBIP-9 algorithm. Among them, B0-B8 is 9 monitoring codes included in the flexBIP-9 algorithm, and each monitoring code corresponds to one monitoring section, and provides odd or even parity for the bits included in the corresponding monitoring section. The first monitoring section corresponds to the first payload bit to the eighth payload bit of each bit block, and the second monitoring section corresponds to the ninth payload bit of each bit block to the 15th payload total 7 Bits, the third monitoring segment corresponds to the 16th payload bit of each bit block to the 22nd payload bit, a total of 7 bits, and the 4th monitoring segment corresponds to the 23rd payload bit of each bit block to The 29th payload bit has a total of 7 bits, and the 5th monitoring segment corresponds to the 30th payload bit of each bit block to the 36th payload bit, a total of 7 bits, and the sixth monitoring segment corresponds to each The 37th payload bit of the bit block has a total of 7 bits to the 43rd payload bit, and the 7th monitoring segment corresponds to the 44th payload bit of each bit block to the 50th payload bit of 7 bits. The eighth monitoring section corresponds to the 51st payload bit of each bit block to the 57th payload bit of 7 bits; the ninth monitoring section corresponds to the 58th payload bit of each bit block to The 64th payload bit has a total of 7 bits.

When the first parity result and the second parity result are determined in step 620, the check object of the first parity result includes N bit blocks and the bit block in the first boundary of step 600, each bit block Any one of the consecutive 9 groups of bits enters the check area corresponding to the flexBIP-9 algorithm, and finally forms the first parity result. The check object of the second parity result includes a block of N bits and a bit block in the first boundary of step 600, and consecutive 9 groups of bits of each bit block are selected according to the first parity result. Any one of the other 8 groups outside the group enters the check area corresponding to the flexBIP-9 algorithm, and finally forms a second parity result.

When the first parity result and the second parity result are determined in step 620, the check object of the first parity result includes N bit blocks and the bit block in the second boundary of step 630, each bit block Any one of the consecutive 9 groups of bits enters the check area corresponding to the flexBIP-9 algorithm, and finally forms the first parity result. The check object of the second parity result includes a block of N bits and a block of bits in the second boundary of step 630, and consecutive 9 groups of bits of each block block are selected according to the first parity result. Any one of the other 8 groups outside the group enters the check area corresponding to the flexBIP-9 algorithm, and finally forms a second parity result.

When the third parity result and the fourth parity result are determined in step 1230 below, the check object of the third parity result includes T bit blocks and the bit block in the first boundary described in step 1200, each bit Any one of the consecutive 9 groups of bits of the block enters the check area corresponding to the flexBIP-9 algorithm, and finally forms a third parity result. The check object of the fourth parity result includes a T bit block and a bit block in the first boundary in step 600, and consecutive 9 groups of bits of each bit block are selected according to a third parity result. Any one of the other 8 groups in the group enters the check area corresponding to the flexBIP-9 algorithm, and finally forms a fourth parity result.

When the third parity result and the fourth parity result are determined in step 1230, the check object of the third parity result includes T bit blocks and the bit block in the second boundary of step 1220, each bit block Any one of the consecutive 9 groups of bits enters the check area corresponding to the flexBIP-9 algorithm, and finally forms a third parity result. The check object of the fourth parity result includes T bit blocks and the bit block in the second boundary of step 1220, and the consecutive 9 groups of bits of each bit block are selected according to the third parity result. Any one of the other 8 groups outside the group enters the check area corresponding to the flexBIP-9 algorithm, and finally forms a fourth parity result.

Specifically, the inserted bit block is an IDLE Block, the first byte is 0x1e, and the others are 0. The first byte of the IDLE Block enters the first monitoring section of flexBIP-9, and the other packets are grouped in consecutive 7 bits into the 2-9th monitoring section. 0x1e has 4 binary 1s, other fields are 0, and there are 0 binary ones. Therefore, no matter how many IDLE blocks are inserted or deleted during transmission, the verification results of B0--B8 are not affected.

Specifically, when the inserted bit block is a low power idle block (LPI Block), the first byte is 0x1e, and the others are divided into 8 groups according to 7 bits, and each group is 0x6. The first byte of the LPI enters the first monitoring section of flexBIP-9, and the other packets are grouped in consecutive 7 bits into the 2-9th monitoring section. 0x1e has 4 binary 1s, the other 7bi t fields are 0x6, and there are 2 binary 1s. Therefore, no matter how many LPI blocks are inserted or deleted during transmission, the verification results of B0--B8 are not affected.

Specifically, when the inserted bit block is an ERROR Block, the first byte is 0x1e, and the others are divided into 8 groups according to 7 bits, and each group is 0x1e. The first byte of the LPI enters the first monitoring section of flexBIP-9, and the other packets are grouped in consecutive 7 bits into the 2-9th monitoring section. 0x1e has 4 binary 1s, so the check result of B0--B8 is not affected regardless of how many ERROR blocks are inserted or deleted during transmission.

Therefore, it can be known from the two preset algorithms provided above that the y-bit monitoring code obtained by the algorithm 1 can be used as the first verification result set, or the z-bit monitoring code obtained by the algorithm 2 can be used as the first school. Test results collection. When the first parity result and the second parity result are transmitted, all the obtained verification results, that is, the first verification result set, may be simultaneously transmitted.

As shown in FIG. 12, the embodiment of the present application provides a bit block stream error detection method to solve the problem that the error detection method in the M/N Bit block exchange scenario is difficult to implement and has low bearer efficiency. The method comprises:

Step 1200: Receive a first boundary bit block, where the first boundary bit block is used to distinguish the subsequently received T bit blocks, where T is a positive integer.

Step 1210: Receive the first bit block in sequence, where I is an integer greater than or equal to 1 and less than or equal to T.

Step 1220: Receive a second boundary bit block, where the second boundary bit block is used to distinguish T bits that have been received.

Step 1230: Determine a third parity result and a fourth parity result, where the check object of the third parity result includes consecutive m bits of each of the T bit blocks, and the fourth parity The resulting check object includes consecutive n bits of each of the T bit blocks, at least one of m, n being greater than or equal to two.

Step 1240: When receiving the first parity result and the second parity result, according to the first parity result and the third parity result, and the second parity result and the fourth parity result Determining whether there is an error in the T bit blocks, wherein the check object of the first parity result includes consecutive m bits of each of the N bit blocks, and the check object of the second parity result Included consecutive n bits of each of the N bit blocks, N being a bit block between the first boundary bit block and the second boundary bit block when determining the first parity result and the second parity result Number of.

It should be understood that when the path of the checked bit block stream is from the bit block transmitting end to the bit block receiving end, the execution body of each step in FIG. 12 may be the bit block receiving end, when the checked bit block The path of the stream is any intermediate device from the transmitting end of the bit block to the receiving end of the bit block, or when the path of the bit block stream to be verified is from the transmitting end of the bit block to the receiving end of the bit block, the steps in FIG. 12 The execution body can be an intermediate device. This application is collectively referred to as a receiving device.

It should be noted that the N bit blocks here are the bit blocks between the first boundary bit block and the second boundary bit block when the first parity result and the second parity result are determined by the transmitting device.

As an optional embodiment, after the sending device sends the first boundary bit block, sequentially transmitting N bit blocks, and then calculating the first parity result and the second parity result according to the N bit blocks, The two results are stored in a second boundary bit block, and the second boundary bit block is transmitted. However, considering that the path passing from the transmitting device to the receiving device traverses the asynchronous node, the first bit block may be inserted or deleted in the N bit blocks, and the receiving device sequentially receives the first boundary bit block after receiving the first bit block. T bit blocks, where N=T, or N>T (ie, inserting the first bit block in N bit blocks), or N<T (ie, deleting the first bit block in N bit blocks) )three situations.

In a possible implementation manner, when the first parity result and the second parity result are not received, sending the third parity result and the fourth parity result to the second device, the second device A first parity result and a second parity result are stored. It should be noted that the second device herein may be an SDN controller or any device having a function of determining a bit stream transmission error. Further, when the first parity result and the second parity result are received, the third parity result and the fourth parity result may also be transmitted to the second device. Therefore, the second device may receive the first parity result and the second parity result sent by the sending device, and the third parity result and the fourth parity result sent by the receiving device, and the second device according to the two The group result determines if there is a bit error during the transmission of the bit block stream.

In a possible implementation, the second boundary bit block is received at the first time, and the first parity result and the second parity result are received at the second time, where the first time is earlier than the second time, Or the first moment is later than the second moment, the first moment is equal to the second moment.

The check object of the third parity result may be consecutive m bits of each of the T bit blocks, and the check object of the fourth parity result may be each bit block of the T bit blocks. For consecutive n bits, the check object of the first parity result may be consecutive m bits of each of the N bit blocks, and the check object of the second parity result may be N bit blocks. a consecutive n bits of each bit block, in a possible implementation, the check object of the third parity result includes only m consecutive bits of each bit block in the T bit block In addition, it may further include consecutive m bits of the first boundary bit block, and may also include consecutive m bits of the second boundary bit block; likewise, the check object of the fourth parity result includes T except In addition to successive n bits of each bit block in a block of bits, it may also include consecutive n bits of the first boundary bit block, and may also include consecutive n bits of the second boundary bit block. The check object of the first parity result may include, in addition to consecutive m bits of each of the N bit blocks, consecutive m bits of the first boundary bit block, and may also include The consecutive m bits of the two boundary bit blocks; likewise, the check object of the second parity result may include the first one in addition to the consecutive n bits of each of the N bit blocks The consecutive n bits of the boundary bit block may also include consecutive n bits of the second boundary bit block.

When the check object of the first parity result includes consecutive m bits of the first boundary bit block, the check object of the third parity result also needs to include consecutive m bits of the first boundary bit block; When the check object of the first parity result includes consecutive m bits of the second boundary bit block, the check object of the third parity result also needs to include consecutive m bits of the second boundary bit block; When the check object of the second parity result includes consecutive n bits of the first boundary bit block, the check object of the fourth parity result also needs to include consecutive n bits of the first boundary bit block; When the check object of the second parity result includes consecutive n bits of the second boundary bit block, the check object of the fourth parity result also needs to include consecutive n bits of the second boundary bit block.

In a possible implementation, the first parity result and the second parity result are stored in the second boundary bit block.

In a possible implementation manner, the receiving device determines, according to the first parity result and the third parity result, and the second parity result and the fourth parity result, whether the T bit blocks have an error. The specific method is: if it is determined that the first parity result and the third parity result are the same, and the second parity result is the same as the fourth parity result, determining that there are no error codes in the T bit blocks; It is determined that the first parity result and the third parity result are not the same, and/or the second parity result and the fourth parity result are not the same, and it is determined that the T bit blocks have an error.

In a possible implementation manner, if the receiving device receives the first verification result set, the first verification result set is calculated according to the xBIP-y algorithm, and the first verification result set includes the y-bit monitoring code. A first parity result and a second parity result are included. The receiving device needs to determine a second set of check results, the second parity result is calculated according to the xBIP-y algorithm, and the y-bit monitoring code included in the second check result set includes the third parity result and the first Three parity results. Further, the receiving device determines, according to the first verification result set and the second verification result set, whether the T bit blocks have an error.

In a possible implementation manner, if the receiving device receives the first check result set, the first check result set is calculated according to the flexBIP-z algorithm, and the first check result set includes the z-bit monitoring code. The first parity result and the second parity result are included. The receiving device needs to determine a second verification result set, where the second verification result set is calculated according to the flexBIP-z algorithm, and the z-bit monitoring code included in the second verification result set includes the third parity result and the third Four parity results. Further, the receiving device determines, according to the first verification result set and the second verification result set, whether the T bit blocks have an error.

Specifically, the receiving device determines, according to the first verification result set and the second verification result set, whether the T bit blocks have an error, including the following two possible situations:

(1) if it is determined that the first verification result set and the second verification result set are the same, it is determined that there are no error codes in the T bit blocks;

(2) If it is determined that the first verification result set and the second verification result set are not the same, it is determined that the T bit blocks have an error.

The error or error detection of the M/N Bit Block network path can be completely implemented by using the method provided in the embodiment of the present application, without affecting user services, and the bearer efficiency is 100%, and the bit block inserted or deleted due to the synchronization problem during the transmission process can be tolerated. And the detection period (ie, the number of bit blocks between two boundary bit blocks) and the detection accuracy (ie, the preset algorithm) are dynamically configurable on demand. In addition, the detection method can not only use the path of the bit block stream to be verified as an end-to-end path, but also the path of the bit block stream to be verified as a non-end-to-end path.

As shown in FIG. 13 , the embodiment of the present application provides a bit block stream error detection method to solve the problem that the error detection method in the M/N Bit block exchange scenario is difficult to implement and has low bearer efficiency. The method comprises:

Step 1300: The first device determines the detected segment according to a start byte in the start block in the bit block stream and an end byte in the end block corresponding to the start block.

As shown in FIG. 14, for the 64/66 bit stream, the user service starts with the start block/S/flag, the end block/T/flag ends, and the middle D is a pure data block, as shown in FIG. As shown in Fig. 1, the seventh line corresponds to the pattern definition of the start block, and S0 represents the start byte. Specifically, as shown in Fig. 16, lines 9-16 correspond to the pattern definitions of the eight end blocks, respectively, and T0-T7 represents the end. The byte, as shown in FIG. 17, is exemplified by including T0 in the end block, and the detected segment is a byte from S0 to T0.

Step 1310: The first device calculates a first verification result according to the detected segment.

The algorithm used by the first device in calculating the first check result may be CRC-x or BIP-x, and the result of the first check result is recorded as B, and B may be one or more bytes.

Step 1320: The first device sends the first check result and the bit block stream.

For the step 1320, the sending, by the first device, the first check result and the bit block stream may specifically include the following two possible implementation manners:

The first possible implementation manner: the first device sends the first check result and the bit block stream to the second device.

A second possible implementation manner is: the first device sends the first verification result to the third device, and sends the bit block flow to the second device.

It should be noted that the first device here is a bit block transmitting end, the second device is a bit block receiving end, the third device is an SDN controller, or has any device for determining a bit stream transmission error function.

In a possible implementation manner, before the first device sends the first verification result and the bit block stream to the second device, the first device needs to store the first verification result obtained by the calculation, including the following two types. Possible storage methods:

The first storage mode: the first device stores the first verification result in the end block, and obtains the updated end block.

As shown in FIG. 18, the first device stores the first check result in the end block, and specifically includes the following two scenarios:

Scenario 1: When the number of bytes occupied by the first check result is greater than or equal to the target number of bytes, the first device stores the first check result before the end byte in the end block, and occupies according to the first check result. The number of bytes moves the end byte to a new block after the end block, deletes any first bit block in the bit block stream, and adds the new block where the end byte is moved as the updated end block. The target number of bytes is the number of bytes in the end block after the end byte plus one.

Scenario 2: When the number of bytes occupied by the first check result is less than the target number of bytes, the first device stores the first check result before the end byte in the end block, and is occupied according to the first check result. The number of bytes will end the byte and the number of bytes occupied by the first check result, and the bit block where the end byte is moved is used as the updated end block. The target number of bytes is the number of bytes in the end block after the end byte plus one.

As an optional embodiment, as shown in FIG. 19, when the first device calculates the first calibration result B by using CRC-8 or BIP-8, B occupies only one BYTE.

When the end block is not inserted B, if the end block is D0 D1 D2 D3 D4 D5 D6 T7, the target number of bytes is 1, after inserting B, it is updated to D0 D1 D2 D3 D4 D5 D6 B, and then add a block. The updated end block is T0 C1 C2 C3 C4 C5 C6 C7.

When the end block is not inserted B, if the end block is T0 C1 C2 C3 C4 C5 C6 C7, the target number of bytes is 8, and after inserting B, the updated end block is B T1 C1 C2 C3 C4 C5 C6. Similarly, when the end block is not inserted B, if the end byte included in the end block is T1-T6, after inserting B, the corresponding update is T2-T7.

The second storage mode: the first device stores the first check result in the check result storage block, and deletes any first bit block in the bit block stream, where the check result storage block refers to before the end block A new block, the first bit block refers to a bit block that may be inserted into or deleted from the bit block stream during the transmission of the bit block stream.

For example, before ending the block, next to the end block, a data block is separately allocated for storing the first verification result B calculated by using CRC-x or BIP-x, and the type is D0 D1 D2 D3 D4 D5 D6 D7, corresponding to FIG. 1 The pattern definition corresponding to the first line in the middle. D0-D7 is used to store the calculation result B. At the same time as inserting B, in order to reduce the influence on the user bandwidth, an IDLE Block (/I/identified block) after /T/Block is deleted. As shown in FIG. 20, B occupies one block separately, and the IDLE block after /T/ is deleted one.

Referring to FIG. 21, the embodiment of the present application provides a bit block stream error detection method to solve the problem that the error detection method in the M/N Bit block exchange scenario is difficult to implement and has low bearer efficiency. The method comprises:

Step 2100: The second device determines the detected segment according to the start byte in the start block in the bit block stream and the end byte in the end block corresponding to the start block.

For step 2100, the second device determines, according to the start byte in the start block in the bit block stream and the end byte in the end block corresponding to the start block, that the detected segment includes the following three specific cases:

Case 1: When the second device receives the first verification result, and the first verification result is stored in the end block, the second device deletes the second verification result from the end block, and obtains the updated end block, and The byte between the start byte in the start block and the end byte in the updated end block is taken as the detected segment.

Case 2: When the second device receives the first verification result, and the first verification result is stored in the verification result storage block, the second device deletes the verification result storage block from the bit block stream, and obtains the updated a bit block stream, the byte between the start byte in the start block and the end byte in the end block in the updated bit block stream is used as the detected segment, wherein the check result storage block is located at the end block prior to.

In the above two cases, the first check result is included in the byte between the start byte in the start block and the end byte in the end block. Therefore, the first check result needs to be deleted first, and the remaining The part is taken as the detected section.

Case 3: When the second device does not receive the first check result, the second device detects the byte between the start byte in the start block and the end byte in the end block in the bit block stream as the detected Section.

At this time, the byte between the start byte in the start block and the end byte in the end block does not include the first check result, and can be directly used as the detected segment.

Specifically, in a possible implementation manner, when the second device does not receive the first verification result, the second device sends the second verification result to the third device, where the third device stores the first verification. result. The third device is an SDN controller or any device having a function of determining a bit stream transmission error.

Step 2110: The second device calculates a second verification result according to the detected segment.

Similarly, the algorithm used by the second device in calculating the second verification result is the same as the algorithm used when the first device calculates the first verification result.

Step 2120: When the second device receives the first verification result, the second device determines, according to the first verification result and the second verification result, whether the detected segment has an error.

Specifically, if the second device determines that the first verification result is the same as the second verification result, determining that the detected segment does not have an error, and if it is determined that the first verification result is different from the second verification result, determining that the second verification result is different from the second verification result There is a bit error in the detection section.

Further, the second device deletes the first check result from the end block, and obtains the updated end block, which specifically includes the following two scenarios:

Scenario 1: When the number of bytes occupied by the first check result is greater than or equal to the target number of bytes, the second device moves the end byte to a bit block before the end block according to the number of bytes occupied by the first check result. A first bit block is added to the bit block stream, and the bit block in which the end byte is moved is used as the updated end block. The target number of bytes is the number of bytes in the end block before the end byte plus one.

Scenario 2: When the number of bytes occupied by the first check result is less than the target number of bytes, the first device advances the end byte by the number of bytes occupied by the first check result and advances the byte occupied by the first check result. The number is the bit block in which the end byte is moved as the updated end block. The target number of bytes is the number of bytes in the end block before the end byte plus one.

As shown in FIG. 22, when the first device calculates the first verification result B by using CRC-8 or BIP-8, B occupies only one BYTE.

When the end block is B T1 C1 C2 C3 C4 C5 C6, the target number of bytes is 2, and after B is deleted, the updated end block is T0 C1 C2 C3 C4 C5 C6 C7. Similarly, if the end byte included in the end block is T2-T7, and B is deleted, the corresponding update is T1-T6.

When the end block is T0 C1 C2 C3 C4 C5 C6 C7, the data block immediately before the end block is D0 D1 D2 D3 D4 D5 D6 B, the target number of bytes is 1, and after deleting B, the updated end block is D0 D1 D2 D3 D4 D5 D6 T7.

In addition, when the second device receives the first check result, and the first check result is stored in the check result storage block, the second device deletes the check result storage block from the bit block stream, and obtains the updated bit. A block stream in which the check result storage block is located before the end block. At the same time, in order to reduce the impact on the user bandwidth, it is necessary to add a first bit block after the end block.

The error or error detection of the M/N Bit Block network path can be completely implemented by using the method provided in the embodiment of the present application, which has little impact on the user service, is close to the SDH/OTN, and is superior to the detection mode of the existing packet, and the implementation process is simple. Easy to implement.

The device of the present application proposes a new device for transmitting an M1/M2 bit block stream. A bit error detection unit is also called a bit error ratio (BER) unit, which is referred to as BER. This unit is used to calculate the check result and error detection.

The PE device includes uAdpt, L1.5Switch, nAdpt, and BER. One end is connected to the user equipment, the interface is UNI, and the other end is connected to the network device. The interface is NNI. The P device includes uAdpt, L1.5Switch, nAdpt, and BER. Both are connected to the network device, and the interface is NNI, as shown in Figure 23(a) and Figure 23(b).

The embodiments of the present application are described below with reference to the accompanying drawings.

As an alternative embodiment, referring to Figure 26, the path of the checked bit block stream is an end-to-end path.

Embodiment 1: The user side interface (UNI) is 1GE, the network side interface (NNI) is 100GE, the granularity of the three-end XE equipment XE1, XE2, XE3, L1.5Switch exchange and the network side signal flow is 64/66 Bit Block flow. On the user side of XE1, an 8BIP-8 check result is inserted every 1024 blocks as an example to illustrate the embodiment shown in FIG.

The STEP 1:1GE user signal enters the XE1 device from the UNI side. uAdpt transcodes the 8/10BitBlock to 64/66 Bit Block, which in turn combines the 8GE user signals of the 2Bit sync header into one 64Bit string, and then adds The 2Bit sync header forms a 64/66 Bit block, and in this way, a 64/66 Bit Block stream is finally formed. The BER counts the block in the bit block stream from the uAdpt side, inserts a first boundary bit block before the first bit block, and calculates the first check result set by using the 8BIP-8 algorithm, when the number of blocks reaches After 1024, as the first group of blocks, the first set of check results is stored in a bit block identified by 4B and 06 and inserted after the 1024th bit block as a second boundary bit block. At the same time, an IDLE Block in the bit block stream is deleted. The BER-processed bit block stream enters the L1.5Switch and then enters nAdpt to be sent to the network side.

It should be noted that the BER continues to count the Block, and uses the 8BIP-8 algorithm to calculate the first set of check results of the second set of blocks, which is the same as the processing method of the first set of Blocks, and then the first check result of the second set of Blocks. The set is stored in a bit block identified by 4B and 06 and inserted after the 2048th bit block as a third boundary bit block. The BER repeats the above process until the end of the bit block stream.

STEP 2: The bit block stream sent by X1 is passed to nAdpt of XE2. The receiving clock frequency is slower than the XE1 system clock. The nAdpt of X2 needs to insert one or several IDLE blocks when sending to L1.5Switch to tolerate the clock frequency being out of sync. The resulting transmission speed problem is then passed to the direction of the network side XE3.

STEP 3: The bit block stream sent by X2 is transmitted to XE3, and reaches the BER unit of the UNI side through nAdpt and L1.5Switch; when receiving the first boundary bit block, the BER starts to perform 8BIP-8 on the subsequently received bit block stream. In the parity calculation, when the second boundary bit block inserted by XE1 is received, the BER stops calculating, and the bit block between the first boundary bit block and the second boundary bit block is used as the first group block. The BER compares the second check result set obtained by the current calculation with the first check result set stored in the second boundary bit block, and if there is no difference, there is no error code. If the BER is inconsistent, the number of error codes is counted and stored. At the same time, the second boundary bit block is deleted from the bit block stream and an IDLE Block is inserted. After the BER-processed bit block flows to uAdpt, the two sync headers are removed, and 64 bits are divided into eight 8-bit groups, each of which adds a 2Bit sync header and is sequentially sent to the UNI link.

It should be noted that the BER continues to count the Block, and uses the 8BIP-8 algorithm to calculate a second set of check results for the second set of blocks, and the second set of blocks is a block of bits between the second boundary block and the third boundary block. When the third boundary bit block inserted by XE1 is received, the BER stops calculating. As with the processing method of the first group of blocks, the BER stores the second check result set of the second group of blocks and the third boundary bit block. The first set of check results of the second group of blocks is compared, and if there is no error, the number of errors is counted and stored. The BER repeats the above process until the end of the bit block stream.

Therefore, the user signal enters XE1 and passes through XE2, and flows out of the network from XE3. The xBIP-y error detection is completely implemented on the entire end-to-end path, and the implementation manner is simple. The block carrying the xBIP-y result has no impact on the user service by adding or deleting IDLE Block compensation, and the bearer efficiency is 100%. During the transmission process, the asynchronous node has an IDLE Block insertion or deletion. The xBIP-y algorithm tolerates this scenario and ensures that the verification result is accurate and effective.

In addition, the 8BIP-8 algorithm mentioned above can be calculated and replaced with the flexBIP-z algorithm.

The xBIP-y algorithm, flexBIP-y algorithm is obviously superior to the static rigid mode of ETHERNET, SDH and OTN occupying fixed bytes. It compensates with the first bit block and has no influence on the user signal, but the existing ETHERNET, SDH and OTN errors. Code or error detection occupies a fixed byte and occupies user bandwidth. As an alternative embodiment, referring to Figures 27(a) and 27(b), the path of the checked bit block stream is a non-end-to-end path.

It should be noted that the start end of the path shown in FIG. 27( a ) performs calculation of the first check result set, and the unit inserted into the second boundary bit block is the BER of the nAdpt unit side, and the end of the path performs the calculation second. The check result set deletes the unit of the second boundary bit block as the BER of the nAdpt unit side;

In addition, there is no user signal insertion and extraction in the path shown in FIG. 27(a), that is, uAdpt at both ends is not required to perform related operations.

The start end of the path shown in FIG. 27(b) performs calculation of the first check result set. The unit inserted into the second boundary bit block is the BER of the uAdpt unit side, and the end end of the path performs calculation to delete the second check result set. The unit of the second boundary bit block is the BER of the nAdpt unit side;

Further, the bit block stream in the path shown in FIG. 27(b) does not flow to the L1.5Switch element and the uAdpt unit at the end.

Embodiment 2: The user side interface (UNI) is 1GE, the network side interface (NNI) is 100GE, the granularity of the three-end XE equipment XE1, XE2, XE3, L1.5Switch exchange and the network side signal flow is 64/66 Bit Block flow. In the user side of XE1, a BIP-8 result B1 is inserted into the end block as an example, and the embodiment shown in FIG. 26 is explained.

The STEP 1:1GE user signal enters the XE1 device from the UNI side. uAdpt transcodes the 8/10BitBlock to 64/66 Bit Block, which in turn combines the 8GE user signals of the 2Bit sync header into one 64Bit string, and then adds The 2Bit sync header forms a 64/66 Bit block, and in this way, a 64/66 Bit Block stream is finally formed. The BER identifies the bit block stream from the uAdpt side, starts the BIP-8 calculation from the receipt of the start block /S/identity block, receives the Block stop calculation with the end block /T/identification, and inserts the result B1. Before /T/, the /T/pattern is modified at the same time, and the bit block stream processed by the BER enters the L1.5Switch, and then enters nAdpt and is sent to the network side.

It should be noted that the BER continues to identify the bit block stream from the uAdpt side, repeating the above process until the end of the bit block stream.

STEP 2: The bit block stream sent by X1 is passed to nAdpt of XE2. The receiving clock frequency is higher than the XE1 system clock block. The nAdpt of X2 needs to delete one or several IDLE blocks when sending to L1.5Switch to tolerate the clock frequency being out of sync. The resulting transmission speed problem is then passed to the direction of the network side XE3.

STEP 3: The bit block stream sent by X2 is passed to XE3, and reaches the UNI side BER unit via nAdpt and L1.5Switch; the BER recognizes the bit block stream, and starts BIP- from the start block/S/flag block. 8 Calculate, receive the Block with the end block /T / flag, stop the calculation before ending the result B1 in the block, delete the result B1, and modify the /T / pattern. The BER compares the result B2 obtained by the current calculation with the result B1, and if there is no error, the error is counted and stored. After the BER-processed bit block flows to uAdpt, the two sync headers are removed, and 64 bits are divided into eight 8-bit groups, each of which adds a 2Bit sync header and is sequentially sent to the UNI link.

In addition, the BIP-8 algorithm mentioned above can be calculated and replaced with the CRC-8 algorithm.

Therefore, the user signal enters XE1 and passes through XE2, and flows out of the network from XE3. The CRC or BIP error detection is completely implemented on the entire end-to-end path. The implementation is simple; the bearer efficiency is improved compared with the existing Ethernet, and SDH and OTN are improved. Close, but there is a certain gap with the embodiment 1 shown in FIG. 26;

In addition, in STEP 1, the BER inserts the result B1 into a separate block before /T/Block, while deleting the IDLE Block after /T/Block, and in STEP 3, deleting the independent block, and /T/Block adds IDLE Block to compensate, has no impact on user services, and bears 100% efficiency.

The bit block stream error detection method provided by the embodiment of the present application is a detection mode for the bit block stream transmission path, and is not limited to the telecommunication cable bearer, and can be completely used in a wireless communication, industrial or industrial communication network.

Based on the same concept, the present application further provides a bit block stream error detecting device, which can be used to perform the corresponding method embodiment in FIG. 6 , and thus the bit block stream error detecting device provided by the embodiment of the present application For the implementation manner, reference may be made to the implementation manner of the method, and the repeated description is not repeated.

As shown in FIG. 28, the embodiment of the present application provides a bit block stream error detecting device 2800, including: a transceiver 2801 and a processor 2802;

The transceiver 2801 is configured to send a first boundary bit block, where the first boundary bit block is used to distinguish the N bit blocks that are subsequently sent, and N is a positive integer; the first bit block is sequentially sent, and I is greater than or equal to 1 and less than or equal to An integer of N;

The processor 2802 is configured to determine a first parity result and a second parity result, where the check object of the first parity result includes consecutive m pieces of each of the N bit blocks a bit, the check object of the second parity result includes consecutive n bits of each of the N bit blocks, at least one of m, n being greater than or equal to 2;

The transceiver 2801 is further configured to send a second boundary bit block, the first parity result, and the second parity result, where the second boundary bit block is used to distinguish the that has been sent N bit blocks.

In one possible design, the transceiver 2801 is configured to:

Transmitting a first boundary bit block to the first device;

Transmitting the first bit block to the first device in sequence;

Transmitting a second boundary bit block, the first parity result, and the second parity result to the first device;

Or sending a second boundary bit block to the first device, and sending the first parity result and the second parity result to the second device.

In one possible design, the transceiver 2801 is configured to:

Transmitting a second boundary bit block at a first time, and transmitting a first parity result and a second parity result at a second time, wherein the first time is earlier than the second time, or the first The time is later than the second time, the first time is equal to the second time.

In one possible design, the first parity result and the second parity result are stored in the second boundary bit block.

In a possible design, the first parity result and the second parity result are calculated according to a preset check algorithm, where the preset check algorithm is used when the N The first parity block and the second parity result are not changed when the first bit block is added or decreased in the bit block, and the first bit block refers to the transmission process of the N bit blocks It is possible to insert the N bit blocks or the bit blocks deleted from the N bit blocks.

In a possible design, the preset check algorithm is an xBIP-y algorithm, where x is the number of bits of consecutive bit interleaving, and x is determined according to the definition of the pattern of the first bit block, y Refers to the number of monitored segments, x, y is a positive integer, y ≥ 2;

The processor 2802 is configured to record, from the first payload bit of the N bit blocks, each x consecutive bits of each bit block to the first monitoring segment to the yth monitoring region. segment;

Determining a 1-bit monitoring code by using an odd or even parity for each monitoring section, obtaining a y-bit monitoring code, the y-bit monitoring code including the first parity result and the second parity result.

In a possible design, the preset check algorithm is a flexBIP-z algorithm, where z is the number of monitored segments, and the number of consecutive bit interleaving bits corresponding to each monitoring segment is not the same, z The number of bits of consecutive bit interleaving corresponding to each monitoring section is A1, A2, A 3 ... Az-1, Az, A1, A2, A 3 ... Az-1, Az, z are positive integers, z ≥ 2 ;

The processor 2802 is configured to record, according to the first payload bit of the N bit blocks, the A1 consecutive bits in each bit block to the first monitoring segment, and the A1 consecutive segments A2 consecutive bits after the bit are recorded to the second monitoring segment, and A3 consecutive bits after the A2 consecutive bits are recorded to the third monitoring segment until after the Az-1 consecutive bits are Az consecutive bits are recorded to the zth monitoring section;

Determining a 1-bit monitoring code by using an odd or even parity for each monitoring section, obtaining a z-bit monitoring code, the z-bit monitoring code including the first parity result and the second parity result.

In one possible design, the processor 2802 is configured to:

Determining a first verification result set, the first verification result set includes the y-bit monitoring code, or the first verification result set includes the z-bit monitoring code;

The transceiver 2801 is configured to:

Sending the first set of verification results.

Based on the same concept, the present application further provides a bit block stream error detecting device, which can be used to perform the corresponding method embodiment in FIG. 12, and thus the bit block stream error detecting device provided by the embodiment of the present application is For the implementation manner, reference may be made to the implementation manner of the method, and the repeated description is not repeated.

As shown in FIG. 29, the embodiment of the present application provides a bit block stream error detecting device 2900, including: a transceiver 2901 and a processor 2902;

The transceiver 2901 is configured to receive a first boundary bit block, where the first boundary bit block is used to distinguish the subsequently received T bit blocks, where T is a positive integer; and the first bit block is sequentially received, where I is greater than or equal to 1 and less than or equal to An integer of T; receiving a second boundary bit block, the second boundary bit block being used to distinguish the T bit blocks that have been received;

The processor 2902 is configured to determine a third parity result and a fourth parity result, where the check object of the third parity result includes consecutive m pieces of each of the T bit blocks a bit, the check object of the fourth parity result includes consecutive n bits of each of the T bit blocks, at least one of m, n being greater than or equal to 2; when passing through the transceiver Receiving the first parity result and the second parity result, according to the first parity result and the third parity result, and the second parity result and the fourth a parity result, determining whether the T bit blocks have an error, wherein the check object of the first parity result includes consecutive m bits of each of the N bit blocks, The check object of the second parity result includes consecutive n bits of each of the N bit blocks, where N is the result of determining the first parity result and the second parity result Between the first boundary bit block and the second boundary bit block Patent number blocks.

In one possible design, the transceiver 2901 is also used to:

Transmitting the third parity result and the fourth parity result to a second device when the first parity result and the second parity result are not received, where the second device stores The first parity result and the second parity result are described.

In one possible design, the transceiver 2901 is used to:

Receiving a second boundary bit block at a first time;

Receiving, at a second time, a first parity result and a second parity result, wherein the first time is earlier than the second time, or the first time is later than the second time, The first moment is equal to the second moment.

In a possible design, the third parity result and the fourth parity result are calculated according to a preset check algorithm, where the preset check algorithm is used when the T The third parity result and the fourth parity result are not changed when the first bit block is added or decreased in the bit block, and the first bit block refers to the transmission process of the T bit block It is possible to insert the T bit blocks or the bit blocks deleted from the T bit blocks.

The processor 2902 is configured to record, from the first payload bit of the T bit blocks, each x consecutive bits of each bit block to the first monitoring segment to the yth monitoring region. segment;

Determining a 1-bit monitoring code by using an odd or even parity for each monitoring section, obtaining a y-bit monitoring code, wherein the y-bit monitoring code includes the third parity result and the fourth parity result.

The processor 2902 is configured to record, according to a first payload bit of the T bit blocks, A1 consecutive bits of each bit block to a first monitoring segment, where the A1 consecutive bits are The last A2 consecutive bits are recorded to the second monitoring segment, and the A3 consecutive bits after the A2 consecutive bits are recorded to the third monitoring segment until the Az-1 consecutive bits are followed by Az. Continuous bits are recorded to the zth monitoring section;

Determining a 1-bit monitoring code by using an odd parity or an even parity for each monitoring section, obtaining a z-bit monitoring code including the third parity result and the fourth parity in the z-bit monitoring code result.

In one possible design, the processor 2902 is configured to:

If it is determined that the first parity result and the third parity result are the same, and the second parity result and the fourth parity result are the same, determining that the T bit blocks are not There is a bit error;

Determining the T if it is determined that the first parity result and the third parity result are not the same, and/or the second parity result and the fourth parity result are not the same There are bit errors in the bit blocks.

In one possible design, the transceiver 2901 is configured to:

Receiving a first check result set, where the first check result set is calculated according to an xBIP-y algorithm, where the first check result set includes a y bit monitor code including the first parity result And the second parity result;

The processor 2902 is configured to: determine a second check result set, where the second parity result is calculated according to the xBIP-y algorithm, and the second check result set includes y bit monitoring Included in the code, the third parity result and the third parity result; determining, according to the first verification result set and the second verification result set, whether the T bit blocks have errors code.

In one possible design, the transceiver 2901 is configured to:

Receiving a first check result set, where the first check result set is calculated according to a flexBIP-z algorithm, where the first check result set includes a z-bit monitoring code including the first parity result And the second parity result;

The processor 2902 is configured to: determine a second verification result set, where the second verification result set is calculated according to the flexBIP-z algorithm, and the second verification result set includes z-bit monitoring The code includes the third parity result and the fourth parity result; determining, according to the first verification result set and the second verification result set, whether the T bit block has an error code.

In one possible design, the processor 2902 is configured to:

If it is determined that the first verification result set and the second verification result set are the same, determining that the T bit blocks have no error;

If it is determined that the first verification result set and the second verification result set are different, it is determined that the T bit blocks have an error.

Based on the same concept, the present application further provides a bit block stream error detecting device, which can be used to perform the corresponding method embodiment in FIG. 13 , and therefore, the bit block stream error detecting device provided by the embodiment of the present application is For the implementation manner, reference may be made to the implementation manner of the method, and the repeated description is not repeated.

As shown in FIG. 30, the embodiment of the present application provides a bit block stream error detecting apparatus 3000, including: a transceiver 3001 and a processor 3002;

The processor 3002 is configured to determine, according to a start byte in a start block in a bit block stream and an end byte in an end block corresponding to the start block, a detected segment; and calculate, according to the detected segment First verification result;

The transceiver 3001 is configured to send the first check result and the bit block stream.

In one possible design, the bit block stream includes at least one M1/M2 bit block; wherein M1 represents the number of payload bits in each bit block, and M2 represents the total number of bits per bit block, M2- M1 represents the number of header sync header bits in each bit block, and M1 and M2 are positive integers, and M2>M1.

In one possible design, the transceiver 3001 is configured to:

Transmitting the first verification result and the bit block to the second device;

Or sending the first verification result to the third device, and sending the bit block flow to the second device;

In a possible design, the processor 3002 is further configured to:

Before the transceiver sends the first verification result and the bit block stream to the second device, storing the first verification result in the end block to obtain an updated end block; or Storing the first check result in a check result storage block, and deleting any first bit block in the bit block stream, where the check result storage block refers to being located before the end block A new block, the first bit block being a bit block that may be inserted into or deleted from the bit block stream during transmission of the bit block stream.

In a possible design, the processor 3002 is configured to:

When the number of bytes occupied by the first verification result is greater than or equal to the target number of bytes, storing the first verification result before the end byte in the end block, and according to the first The number of bytes occupied by the verification result moves the end byte to a new block after the end block, deletes any first bit block in the bit block stream, and moves the end byte The new block is located as the updated end block;

When the number of bytes occupied by the first verification result is less than the target number of bytes, storing the first verification result before the end byte in the end block, and according to the The number of bytes occupied by a check result shifts the end byte back by the number of bytes occupied by the first check result, and the bit block where the end byte is moved is used as the updated end block;

The target number of bytes is the number of bytes in the end block after the end byte plus one.

Based on the same concept, the present application further provides a bit block stream error detecting device, which can be used to perform the corresponding method embodiment in FIG. 21, and thus the bit block stream error detecting device provided by the embodiment of the present application is For the implementation manner, reference may be made to the implementation manner of the method, and the repeated description is not repeated.

As shown in FIG. 31, the embodiment of the present application provides a bit block stream error detecting apparatus 3100, including: a transceiver 3101 and a processor 3102;

The processor 3102 is configured to determine a detected segment according to a start byte in a start block in a bit block stream and an end byte in an end block corresponding to the start block, and calculate, according to the detected segment Second verification result;

When the first check result is received by the transceiver 3101, it is determined whether the detected segment has an error according to the first check result and the second check result.

In a possible design, the processor 3102 is configured to:

When the first check result is received by the transceiver, and the first check result is stored in the end block, the second check result is deleted from the end block, and the updated end block is obtained. a byte between the start byte in the start block and the end byte in the updated end block as a detected segment;

When the first verification result is received by the transceiver, and the first verification result is stored in the verification result storage block, the verification result storage block is deleted from the bit block stream, and the updated a bit block stream, the byte between the start byte in the start block and the end byte in the end block in the updated bit block stream is used as a detected segment, wherein a check result storage block is located before the end block;

When the first check result is not received, a byte between the start byte in the start block and the end byte in the end block in the bit block stream is taken as a detected segment;

In one possible design, the transceiver 3101 is further configured to:

When the first verification result is not received, the second verification result is sent to the third device, and the third device stores the first verification result.

In a possible design, the processor 3102 is configured to:

If it is determined that the first verification result is the same as the second verification result, determining that the detected segment does not have an error;

If it is determined that the first check result is different from the second check result, it is determined that the detected segment has an error.

In a possible design, the processor 3102 is configured to:

When the number of bytes occupied by the first check result is greater than or equal to the target number of bytes, moving the end byte to a bit before the end block according to the number of bytes occupied by the first check result Block, adding a first bit block to the bit block stream, and using the bit block in which the end byte is moved as an updated end block;

When the number of bytes occupied by the first check result is less than the target number of bytes, the end byte is forwarded by the first check result according to the number of bytes occupied by the first check result The number of bytes occupied, the bit block in which the end byte is moved is used as the updated end block;

The target number of bytes is the number of bytes in the end block before the end byte plus one.

In summary, the embodiment of the present application provides a bit block stream error detection method, where the method includes: the sending device sends a first boundary bit block, where the first boundary bit block is used to distinguish the N bit blocks that are subsequently sent, N a positive integer; the first bit block is sequentially transmitted, I is an integer greater than or equal to 1 and less than or equal to N; the first parity result and the second parity result are determined, and the check object of the first parity result includes N a continuous m bits of each bit block in the bit block, the check object of the second parity result includes consecutive n bits of each of the N bit blocks, at least one of m and n being greater than or equal to 2: transmitting a second boundary bit block, a first parity result, and a second parity block, wherein the second boundary bit block is used to distinguish N bits that have been transmitted. At the same time, the receiving device receives the first boundary bit block, where the first boundary bit block is used to distinguish the subsequently received T bit blocks, T is a positive integer; the first bit block is sequentially received, and I is an integer greater than or equal to 1 and less than or equal to T; Receiving a second boundary bit block, the second boundary bit block is configured to distinguish the T bit blocks that have been received; determining a third parity result and a fourth parity result, where the check object of the third parity result includes Contiguous m bits of each of the T bit blocks, the check object of the second parity result includes at least one of n consecutive bits, m, n of each of the T bit blocks Greater than or equal to 2; when receiving the first parity result and the second parity result, according to the first parity result and the third parity result, and the second parity result and the fourth parity As a result, it is determined whether there are error codes in the T bit blocks, wherein the check object of the first parity result includes consecutive m bits of each of the N bit blocks, and the check of the second parity result Object includes N bit blocks N consecutive bits of each bit block, the number of bits of the block boundary between a first block and a second boundary bit block of bits N is first determined result and the second parity parity check result. Therefore, the method provided by the embodiment of the present application can completely implement the error or error detection of the M/N Bit Block network path, does not affect the user service, and has a bearer efficiency of 100%, and can be inserted or deleted due to the synchronization problem during the transmission process. The bit block, and the detection period (ie, the number of bit blocks between the two boundary bit blocks) and the detection accuracy (ie, the preset algorithm) are dynamically configurable as needed. In addition, the detection method can not only use the path of the bit block stream to be verified as an end-to-end path, but also the path of the bit block stream to be verified as a non-end-to-end path. Therefore, the method provided by the embodiment of the present application can solve the problem that the error detection method in the M/N Bit block exchange scenario is difficult to implement and has low bearer efficiency.

The embodiment of the present application further provides a bit block stream error detection method, the method comprising: the first device according to a start byte in a start block in a bit block stream and an end word in an end block corresponding to the start block The section determines the detected section; the first device calculates a first verification result according to the detected section. The first device transmits the first check result and the bit block stream. For example, the algorithm used by the first device to calculate the first check result may be CRC-x or BIP-x, and the first check result is recorded as B, and B may be one or more bytes. The second device determines the detected segment according to the start byte in the start block in the bit block stream and the end byte in the end block corresponding to the start block; the second device calculates the second check according to the detected segment result. When the second device receives the first verification result, the second device determines, according to the first verification result and the second verification result, whether the detected segment has an error. Therefore, the error or error detection of the M/N Bit Block network path can be completely implemented by using the method provided in the embodiment of the present application, which has little impact on the user service and is close to the SDH/OTN, and is superior to the error detection provided in the prior art. Method, the implementation process is simple and easy to implement.

Those skilled in the art will appreciate that embodiments of the present application can be provided as a method, system, or computer program product. Therefore, the embodiments of the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Moreover, embodiments of the present application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) including computer usable program code.

Embodiments of the present application are described with reference to flowchart illustrations and/or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present application. It will be understood that each flow and/or block of the flowchart illustrations and/or FIG. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing device to produce a machine for the execution of instructions for execution by a processor of a computer or other programmable data processing device. Means for implementing the functions specified in one or more of the flow or in a block or blocks of the flow chart.

The computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device. The apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.

These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device. The instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

It is apparent that those skilled in the art can make various modifications and variations to the embodiments of the present application without departing from the spirit and scope of the application. Thus, it is intended that the present invention cover the modifications and variations of the embodiments of the present invention.

Claims

A bit block stream error detection method, comprising:

Transmitting a first boundary bit block, where the first boundary bit block is used to distinguish the N bit blocks that are subsequently sent, where N is a positive integer;

Transmitting the first bit block, where I is an integer greater than or equal to 1 and less than or equal to N;

Determining a first parity result and a second parity result, the check object of the first parity result including consecutive m bits of each of the N bit blocks, the second The parity object of the parity result includes consecutive n bits of each of the N bit blocks, at least one of m and n being greater than or equal to 2;

Transmitting a second boundary bit block, the first parity result, and the second parity result, the second boundary bit block being used to distinguish the N bit blocks that have been transmitted.
The method of claim 1 wherein the type of each bit block is an M1/M2 bit block, wherein M1 represents the number of payload bits in each bit block and M2 represents the total bits of each bit block. The number, M2-M1, represents the number of header sync header bits in each bit block, M1, M2 are positive integers, M2>M1.
The method of claim 1 or 2, wherein transmitting the first boundary bit block comprises:

Transmitting a first boundary bit block to the first device;

Sending the first bit block in sequence, including:

Transmitting the first bit block to the first device in sequence;

Transmitting the second boundary bit block, the first parity result, and the second parity result, including:

Transmitting a second boundary bit block, the first parity result, and the second parity result to the first device;

Or sending a second boundary bit block to the first device, and sending the first parity result and the second parity result to the second device.
The method according to claim 1, wherein the check object of the first parity result further comprises consecutive m bits of the first boundary bit block, the second parity result The check object also includes consecutive n bits of the first boundary bit block.
The method according to claim 1 or 4, wherein the check object of the first parity result further comprises consecutive m bits of the second boundary bit block, the second parity The resulting check object also includes consecutive n bits of the second boundary bit block.
The method of any of claims 1-5, wherein transmitting the second boundary bit block, the first parity result, and the second parity result comprises:

Transmitting a second boundary bit block at a first time, and transmitting a first parity result and a second parity result at a second time, wherein the first time is earlier than the second time, or the first The time is later than the second time, the first time is equal to the second time.
The method of any of claims 1-6, wherein the first parity result and the second parity result are stored in the second boundary bit block.
The method according to any one of claims 1 to 7, wherein the first parity result and the second parity result are calculated according to a preset check algorithm, the preset a check algorithm for not changing the first parity result and the second parity result when the first bit block is added or decreased in the N bit blocks, where the first bit block refers to The N bit blocks or bit blocks deleted from the N bit blocks may be inserted during transmission of the N bit blocks.
The method according to claim 8, wherein the preset check algorithm is an xBIP-y algorithm, wherein x is a number of bits of consecutive bit interleaving, and x is a pattern according to the first bit block Defining the definition, y refers to the number of monitoring segments, x, y is a positive integer, y ≥ 2;

Determining the first parity result and the second parity result, including:

Starting from the first payload bit of the N bit blocks, sequentially recording every x consecutive bits of each bit block to the first monitoring segment to the yth monitoring segment;

Determining a 1-bit monitoring code by using an odd or even parity for each monitoring section, obtaining a y-bit monitoring code, the y-bit monitoring code including the first parity result and the second parity result.
The method according to claim 8, wherein the preset check algorithm is a flexBIP-z algorithm, wherein z is the number of monitored segments, and consecutive bit-interleaved bits corresponding to each monitored segment The number of consecutive bit interleaving corresponding to z monitoring sections is A1, A2, A3, ... Az-1, Az, A1, A2, A3, ..., Az-1, Az, z are positive integers. Z≥2;

Determining the first parity result and the second parity result, including:

Starting from the first payload bit of the N bit blocks, record A1 consecutive bits in each bit block to the first monitoring segment, and record A2 consecutive bits after the A1 consecutive bits Up to the second monitoring section, recording A3 consecutive bits after the A2 consecutive bits to the third monitoring section until the Az consecutive bits after the Az-1 consecutive bits are recorded to the zth Monitoring section;

Determining a 1-bit monitoring code by using an odd or even parity for each monitoring section, obtaining a z-bit monitoring code, the z-bit monitoring code including the first parity result and the second parity result.
The method according to claim 9 or 10, wherein determining the first parity result and the second parity result comprises:

Determining a first verification result set, the first verification result set includes the y-bit monitoring code, or the first verification result set includes the z-bit monitoring code;

Transmitting the first parity result and the second parity result, including:

Sending the first set of verification results.
A bit block stream error detection method, comprising:

Receiving a first boundary bit block, where the first boundary bit block is used to distinguish the subsequently received T bit blocks, where T is a positive integer;

Receiving the first bit block in sequence, where I is an integer greater than or equal to 1 and less than or equal to T;

Receiving a second boundary bit block, the second boundary bit block is used to distinguish the T bit blocks that have been received;

Determining a third parity result and a fourth parity result, the check object of the third parity result including consecutive m bits of each of the T bit blocks, the fourth The parity object of the parity result includes consecutive n bits of each of the T bit blocks, at least one of m and n being greater than or equal to 2;

When receiving the first parity result and the second parity result, according to the first parity result and the third parity result, and the second parity result and the first Determining, by the four parity results, whether there is an error in the T bit blocks, wherein the check object of the first parity result includes consecutive m bits of each of the N bit blocks, The check object of the second parity result includes consecutive n bits of each of the N bit blocks, and N is determining the first parity result and the second parity result The number of bit blocks between the first boundary bit block and the second boundary bit block.
The method of claim 12, further comprising:

Transmitting the third parity result and the fourth parity result to a second device when the first parity result and the second parity result are not received, where the second device stores The first parity result and the second parity result are described.
The method according to claim 12, wherein the check object of the third parity result further comprises consecutive m bits of the first boundary bit block, the fourth parity result The check object further includes n bits of the first boundary bit block; the check object of the first parity result further includes consecutive m bits of the first boundary bit block, the second parity The check object of the check result further includes consecutive n bits of the first boundary bit block.
The method according to claim 12 or 14, wherein the check object of the third parity result further comprises consecutive m bits of the second boundary bit block, the fourth parity The resulting check object further includes n bits of the second boundary bit block; the check object of the first parity result further includes consecutive m bits of the second boundary bit block, the first The check object of the second parity result further includes consecutive n bits of the second boundary bit block.
The method according to claims 12-15, characterized in that each type of bit block is an M1/M2 bit block, wherein M1 represents the number of payload bits in each bit block, and M2 represents the block number of each bit block. The total number of bits, M2-M1, represents the number of header sync header bits in each bit block, M1, M2 are positive integers, M2>M1.
The method of any of claims 12-16, wherein receiving the second boundary bit block comprises:

Receiving a second boundary bit block at a first time;

Receiving the first parity result and the second parity result, including:

Receiving, at a second time, a first parity result and a second parity result, wherein the first time is earlier than the second time, or the first time is later than the second time, The first moment is equal to the second moment.
The method of any of claims 12-17, wherein the first parity result and the second parity result are stored in the second boundary bit block.
The method according to any one of claims 12 to 18, wherein the third parity result and the fourth parity result are calculated according to a preset check algorithm, the preset a check algorithm for not changing the third parity result and the fourth parity result when the first bit block is added or decreased in the T bit blocks, where the first bit block refers to The T bit blocks or bit blocks deleted from the T bit blocks may be inserted during transmission of the T bit blocks.
The method according to claim 19, wherein said preset check algorithm is an xBIP-y algorithm, wherein x is a number of bits of consecutive bit interleaving, and x is a pattern according to said first block of bits Defining the definition, y refers to the number of monitoring segments, x, y is a positive integer, y ≥ 2;

Determining the third parity result and the fourth parity result, including:

Starting from the first payload bit of the T bit blocks, every x consecutive bits of each bit block are sequentially recorded to the first monitoring segment to the yth monitoring segment;

Determining a 1-bit monitoring code by using an odd or even parity for each monitoring section, obtaining a y-bit monitoring code, wherein the y-bit monitoring code includes the third parity result and the fourth parity result.
The method according to claim 19, wherein the preset check algorithm is a flexBIP-z algorithm, wherein z is the number of monitored segments, and consecutive bit-interleaved bits corresponding to each monitored segment The number of consecutive bit interleaving corresponding to z monitoring sections is A1, A2, A3, ... Az-1, Az, A1, A2, A3, ... Az-1, Az, z are positive integers. , z≥2;

Determining the third parity result and the fourth parity result, including:

Starting from the first payload bit of the T bit blocks, recording A1 consecutive bits of each bit block to the first monitoring segment, and recording A2 consecutive bits after the A1 consecutive bits to The second monitoring section records A3 consecutive bits after the A2 consecutive bits to the third monitoring section until the Az consecutive bits after the Az-1 consecutive bits are recorded to the zth Monitoring section;

Determining a 1-bit monitoring code by using an odd parity or an even parity for each monitoring section, obtaining a z-bit monitoring code including the third parity result and the fourth parity in the z-bit monitoring code result.
The method according to any one of claims 12 to 20, wherein the first parity result and the third parity result, and the second parity result and the first And determining, by the four parity results, whether the T bit blocks have an error, including:

If it is determined that the first parity result and the third parity result are the same, and the second parity result and the fourth parity result are the same, determining that the T bit blocks are not There is a bit error;

Determining the T if it is determined that the first parity result and the third parity result are not the same, and/or the second parity result and the fourth parity result are not the same There are bit errors in the bit blocks.
The method of claim 19, wherein receiving the first parity result and the second parity result comprises:

Receiving a first check result set, where the first check result set is calculated according to an xBIP-y algorithm, where the first check result set includes a y bit monitor code including the first parity result And the second parity result;

Determining the third parity result and the fourth parity result, including:

Determining a second parity result set, the second parity result being calculated according to the xBIP-y algorithm, where the second parity result set includes a third parity check code included in the y-bit monitoring code And the third parity result;

When receiving the first parity result and the second parity result, according to the first parity result and the third parity result, and the second parity result and the first And determining, by the four parity results, whether the T bit blocks have an error, including:

Determining whether the T bit blocks have an error according to the first check result set and the second check result set.
The method of claim 20, wherein receiving the first parity result and the second parity result comprises:

Receiving a first check result set, where the first check result set is calculated according to a flexBIP-z algorithm, where the first check result set includes a z-bit monitoring code including the first parity result And the second parity result;

Determining the third parity result and the fourth parity result, including:

Determining a second set of check results, the second set of check results being calculated according to the flexBIP-z algorithm, where the z-bit monitoring code included in the second set of check results includes the third parity And the fourth parity result;

When receiving the first parity result and the second parity result, according to the first parity result and the third parity result, and the second parity result and the first And determining, by the four parity results, whether the T bit blocks have an error, including:

Determining whether the T bit blocks have an error according to the first check result set and the second check result set.
The method according to claim 23 or 24, wherein determining whether the T bit blocks have an error according to the first verification result set and the second verification result set comprises:

If it is determined that the first verification result set and the second verification result set are the same, determining that the T bit blocks have no error;

If it is determined that the first verification result set and the second verification result set are different, it is determined that the T bit blocks have an error.
A bit block stream error detection method, comprising:

Determining, by the first device, the detected segment according to a start byte in the start block in the bit block stream and an end byte in the end block corresponding to the start block;

The first device calculates a first verification result according to the detected segment;

The first device sends the first check result and the bit block stream.
The method of claim 26 wherein said bit block stream comprises at least one M1/M2 bit block; wherein M1 represents the number of payload bits in each bit block and M2 represents the total of each bit block The number of bits, M2-M1, represents the number of header sync header bits in each bit block, M1, M2 are positive integers, M2>M1.
The method of claim 26 or 27, wherein the transmitting, by the first device, the first verification result and the bit block stream comprises:

Transmitting, by the first device, the first verification result and the bit block stream to a second device;

Or the first device sends the first check result to the third device, and sends the bit block stream to the second device.
The method according to any one of claims 26 to 28, further comprising: before the first device sends the first verification result and the bit block stream to the second device,

The first device stores the first verification result in the end block, and obtains an updated end block;

Or the first device stores the first check result in a check result storage block, and deletes any first bit block in the bit block stream, where the check result storage block refers to A new block located before the end block, the first bit block being a bit block that may be inserted into or deleted from the bit block stream during transmission of the bit block stream.
The method of claim 29, wherein the first device stores the first verification result in the end block, and obtains an updated end block, including:

When the number of bytes occupied by the first check result is greater than or equal to the target number of bytes, the first device stores the first check result before the end byte in the end block, and And moving the end byte to a new block after the end block according to the number of bytes occupied by the first check result, deleting any first bit block in the bit block stream, The new block where the end byte is moved is used as the updated end block;

When the number of bytes occupied by the first check result is less than the target number of bytes, the first device stores the first check result before the end byte in the end block, And moving the end byte back to the number of bytes occupied by the first check result according to the number of bytes occupied by the first check result, and using the bit block in which the end byte is moved as an update End block

The target number of bytes is the number of bytes in the end block after the end byte plus one.
A bit block stream error detection method, comprising:

The second device determines the detected segment according to a start byte in the start block in the bit block stream and an end byte in the end block corresponding to the start block;

The second device calculates a second verification result according to the detected segment;

When the second device receives the first verification result, the second device determines, according to the first verification result and the second verification result, whether the detected segment has an error.
The method of claim 31 wherein said bit block stream comprises at least one M1/M2 bit block; wherein M1 represents the number of payload bits in each bit block and M2 represents the total of each bit block The number of bits, M2-M1, represents the number of header sync header bits in each bit block, M1, M2 are positive integers, M2>M1.
The method according to claim 31 or 32, wherein the second device determines, according to the start byte in the start block in the bit block stream and the end byte in the end block corresponding to the start block, Detection section, including:

When the second device receives the first verification result, and the first verification result is stored in the end block, the second device deletes the second verification result from the end block Obtaining an updated end block, taking a byte between the start byte in the start block and the end byte in the updated end block as a detected segment;

When the second device receives the first verification result, and the first verification result is stored in the verification result storage block, the second device streams the verification result storage block from the bit block Deleting, obtaining an updated bit block stream, detecting, as the detected byte between the start byte in the start block and the end byte in the end block in the updated bit block stream a segment, wherein the check result storage block is located before the end block;

When the second device does not receive the first check result, the second device sets a start byte in the start block and an end byte in the end block in the bit block stream. Between the bytes as the detected segment.
The method of any of claims 31-33, further comprising:

When the second device does not receive the first verification result, the second device sends the second verification result to the third device, where the third device stores the first verification result.
The method according to any one of claims 31 to 34, wherein the second device determines whether the detected segment has an error according to the first verification result and the second verification result. include:

If the second device determines that the first verification result is the same as the second verification result, determining that the detected segment does not have an error;

If it is determined that the first check result is different from the second check result, it is determined that the detected segment has an error.
The method according to claim 33, wherein the second device deletes the first verification result from the end block to obtain an updated end block, including:

When the number of bytes occupied by the first check result is greater than or equal to the target number of bytes, the second device moves the end byte to the end according to the number of bytes occupied by the first check result. a bit block in front of the block, adding a first bit block to the bit block stream, and using the bit block in which the end byte is moved as an updated end block;

When the number of bytes occupied by the first check result is less than the target number of bytes, the second device advances the end byte according to the number of bytes occupied by the first check result. The number of bytes occupied by the first check result, and the bit block in which the end byte is moved is used as the updated end block;

The target number of bytes is the number of bytes in the end block before the end byte plus one.
A bit block stream error detecting device, comprising:

The transceiver is configured to send a first boundary bit block, where the first boundary bit block is used to distinguish the N bit blocks that are subsequently sent, and N is a positive integer; the first bit block is sequentially sent, and I is greater than or equal to 1 and less than or equal to N. Integer

a processor, configured to determine a first parity result and a second parity result, where the check object of the first parity result includes consecutive m bits of each of the N bit blocks The check object of the second parity result includes consecutive n bits of each of the N bit blocks, at least one of m and n being greater than or equal to 2;

The transceiver is further configured to send a second boundary bit block, the first parity result, and the second parity result, where the second boundary bit block is used to distinguish the N that has been sent Bit blocks.
The device according to claim 37, wherein the check object of the first parity result further comprises consecutive m bits of the first boundary bit block, the second parity result The check object also includes consecutive n bits of the first boundary bit block.
The apparatus according to claim 37 or 38, wherein the check object of the first parity result further comprises consecutive m bits of the second boundary bit block, the second parity The resulting check object also includes consecutive n bits of the second boundary bit block.
The apparatus according to claim 37, wherein each type of the bit block is an M1/M2 bit block, wherein M1 represents the number of payload bits in each bit block, and M2 represents the total bit of each bit block. The number, M2-M1, represents the number of header sync header bits in each bit block, M1, M2 are positive integers, M2>M1.
The device of any of claims 37-40, wherein said transceiver is for:

Transmitting a first boundary bit block to the first device;

Transmitting the first bit block to the first device in sequence;

Transmitting a second boundary bit block, the first parity result, and the second parity result to the first device;

Or sending a second boundary bit block to the first device, and sending the first parity result and the second parity result to the second device.
The device according to any one of claims 37 to 41, wherein the transceiver is configured to:

Transmitting a second boundary bit block at a first time, and transmitting a first parity result and a second parity result at a second time, wherein the first time is earlier than the second time, or the first The time is later than the second time, the first time is equal to the second time.
The apparatus of any of claims 37-41, wherein the first parity result and the second parity result are stored in the second boundary bit block.
The device according to any one of claims 37 to 43, wherein the first parity result and the second parity result are calculated according to a preset check algorithm, the preset a check algorithm for not changing the first parity result and the second parity result when the first bit block is added or decreased in the N bit blocks, where the first bit block refers to The N bit blocks or bit blocks deleted from the N bit blocks may be inserted during transmission of the N bit blocks.
The device according to claim 43, wherein the preset check algorithm is an xBIP-y algorithm, wherein x is a number of bits of consecutive bit interleaving, and x is a pattern according to the first bit block Defining the definition, y refers to the number of monitoring segments, x, y is a positive integer, y ≥ 2;

The processor, for starting from the first payload bit of the N bit blocks, sequentially recording every x consecutive bits of each bit block to the first monitoring segment to the yth monitoring segment ;

Determining a 1-bit monitoring code by using an odd or even parity for each monitoring section, obtaining a y-bit monitoring code, the y-bit monitoring code including the first parity result and the second parity result.
The device according to claim 43, wherein the preset check algorithm is a flexBIP-z algorithm, where z is the number of monitored segments, and consecutive bit interleaved bits corresponding to each monitored segment The number of consecutive bit interleaving corresponding to z monitoring sections is A1, A2, A3, ... Az-1, Az, A1, A2, A3, ..., Az-1, Az, z are positive integers. Z≥2;

The processor, configured to record, according to a first payload bit of the N bit blocks, A1 consecutive bits in each bit block to a first monitoring segment, where the A1 consecutive bits The last A2 consecutive bits are recorded to the second monitoring segment, and the A3 consecutive bits after the A2 consecutive bits are recorded to the third monitoring segment until the Az-1 consecutive bits are followed by Az. Continuous bits are recorded to the zth monitoring section;

Determining a 1-bit monitoring code by using an odd or even parity for each monitoring section, obtaining a z-bit monitoring code, the z-bit monitoring code including the first parity result and the second parity result.
The device according to claim 45 or 46, wherein the processor is configured to:

Determining a first verification result set, the first verification result set includes the y-bit monitoring code, or the first verification result set includes the z-bit monitoring code;

The transceiver is configured to:

Sending the first set of verification results.
A bit block stream error detecting device, comprising:

a transceiver, configured to receive a first boundary bit block, where the first boundary bit block is used to distinguish T bits that are subsequently received, T is a positive integer; and the first bit block is sequentially received, where I is greater than or equal to 1 and less than or equal to T An integer that receives a second boundary bit block, the second boundary bit block being used to distinguish the T bit blocks that have been received;

a processor, configured to determine a third parity result and a fourth parity result, where the check object of the third parity result includes consecutive m bits of each of the T bit blocks The check object of the fourth parity result includes consecutive n bits of each of the T bit blocks, at least one of m, n being greater than or equal to 2; when received by the transceiver And the first parity result and the third parity result, and the second parity result and the fourth parity according to the first parity result and the second parity result a check result, determining whether the T bit block has an error, wherein the check object of the first parity result includes consecutive m bits of each of the N bit blocks, the The check object of the second parity result includes consecutive n bits of each of the N bit blocks, where N is the result of determining the first parity result and the second parity result a bit between the first boundary bit block and the second boundary bit block The number of blocks.
The device of claim 48, wherein the transceiver is further configured to:

Transmitting the third parity result and the fourth parity result to a second device when the first parity result and the second parity result are not received, where the second device stores The first parity result and the second parity result are described.
The device according to claim 48, wherein the check object of the third parity result further comprises consecutive m bits of the first boundary bit block, the fourth parity result The check object further includes n bits of the first boundary bit block; the check object of the first parity result further includes consecutive m bits of the first boundary bit block, the second parity The check object of the check result further includes consecutive n bits of the first boundary bit block.
The apparatus according to claim 48 or 50, wherein the check object of the third parity result further comprises consecutive m bits of the second boundary bit block, the fourth parity The resulting check object further includes n bits of the second boundary bit block; the check object of the first parity result further includes consecutive m bits of the second boundary bit block, the first The check object of the second parity result further includes consecutive n bits of the second boundary bit block.
The apparatus according to claims 48-51, wherein the type of each bit block is an M1/M2 bit block, wherein M1 represents the number of payload bits in each bit block, and M2 represents the block number of each bit block. The total number of bits, M2-M1, represents the number of header sync header bits in each bit block, M1, M2 are positive integers, M2>M1.
The device of any of claims 48-52, wherein the transceiver is for:

Receiving a second boundary bit block at a first time;

Receiving, at a second time, a first parity result and a second parity result, wherein the first time is earlier than the second time, or the first time is later than the second time, The first moment is equal to the second moment.
The apparatus of any of claims 48-53, wherein the first parity result and the second parity result are stored in the second boundary bit block.
The device according to any one of claims 48 to 54, wherein the third parity result and the fourth parity result are calculated according to a preset check algorithm, the preset a check algorithm for not changing the third parity result and the fourth parity result when the first bit block is added or decreased in the T bit blocks, where the first bit block refers to The T bit blocks or bit blocks deleted from the T bit blocks may be inserted during transmission of the T bit blocks.
The device according to claim 55, wherein the preset check algorithm is an xBIP-y algorithm, wherein x is a number of bits of consecutive bit interleaving, and x is a code type definition according to the first bit block Determined, y refers to the number of monitored segments, x, y is a positive integer, y ≥ 2;

The processor, for starting from the first payload bit of the T bit blocks, sequentially recording each x consecutive bits of each bit block to the first monitoring segment to the yth monitoring segment ;

Determining a 1-bit monitoring code by using an odd or even parity for each monitoring section, obtaining a y-bit monitoring code, wherein the y-bit monitoring code includes the third parity result and the fourth parity result.
The device according to claim 55, wherein the preset check algorithm is a flexBIP-z algorithm, wherein z is a number of monitored segments, and consecutive bit-interleaved bits corresponding to each monitored segment The number of consecutive bit interleaving corresponding to z monitoring sections is A1, A2, A3, ... Az-1, Az, A1, A2, A3, ..., Az-1, Az, z are positive integers. Z≥2;

The processor is configured to record, according to a first payload bit of the T bit blocks, A1 consecutive bits of each bit block to a first monitoring segment, and after the A1 consecutive bits A2 consecutive bits are recorded to the second monitoring segment, and A3 consecutive bits after the A2 consecutive bits are recorded to the third monitoring segment until Az-1 consecutive bits are Az Continuous bits are recorded to the zth monitoring section;

Determining a 1-bit monitoring code by using an odd parity or an even parity for each monitoring section, obtaining a z-bit monitoring code including the third parity result and the fourth parity in the z-bit monitoring code result.
The device of any of claims 58-57, wherein the processor is configured to:

If it is determined that the first parity result and the third parity result are the same, and the second parity result and the fourth parity result are the same, determining that the T bit blocks are not There is a bit error;

Determining the T if it is determined that the first parity result and the third parity result are not the same, and/or the second parity result and the fourth parity result are not the same There are bit errors in the bit blocks.
The device of claim 56, wherein said transceiver is for:

Receiving a first check result set, where the first check result set is calculated according to an xBIP-y algorithm, where the first check result set includes a y-bit monitoring code including the first parity result And the second parity result;

The processor is configured to: determine a second verification result set, where the second parity result is calculated according to the xBIP-y algorithm, and the second verification result set includes a y-bit monitoring code Include the third parity result and the third parity result; determining, according to the first verification result set and the second verification result set, whether the T bit block has a bit error .
The device according to claim 57, wherein said transceiver is configured to:

Receiving a first check result set, where the first check result set is calculated according to a flexBIP-z algorithm, where the first check result set includes a z-bit monitoring code including the first parity result And the second parity result;

The processor is configured to: determine a second verification result set, where the second verification result set is calculated according to the flexBIP-z algorithm, and the second verification result set includes a z-bit monitoring code Include the third parity result and the fourth parity result; determining, according to the first verification result set and the second verification result set, whether the T bit block has an error .
The device according to claim 59 or 60, wherein the processor is configured to:

If it is determined that the first verification result set and the second verification result set are the same, determining that the T bit blocks have no error;

If it is determined that the first verification result set and the second verification result set are different, it is determined that the T bit blocks have an error.
A bit block stream error detecting device, comprising:

a processor, configured to determine, according to a start byte in a start block in a bit block stream and an end byte in an end block corresponding to the start block, a detected segment according to the detected segment; a check result;

And a transceiver, configured to send the first verification result and the bit block stream.
The apparatus according to claim 62, wherein said bit block stream comprises at least one M1/M2 bit block; wherein M1 represents the number of payload bits in each bit block, and M2 represents the total of each bit block The number of bits, M2-M1, represents the number of header sync header bits in each bit block, M1, M2 are positive integers, M2>M1.
The device according to claim 62 or 63, wherein the transceiver is configured to:

Transmitting the first verification result and the bit block to the second device;

Or sending the first verification result to the third device, and sending the bit block flow to the second device;
The device according to any one of claims 62 to 64, wherein the processor is further configured to:

Before the transceiver sends the first verification result and the bit block stream to the second device, storing the first verification result in the end block to obtain an updated end block; or Storing the first check result in a check result storage block, and deleting any first bit block in the bit block stream, where the check result storage block refers to being located before the end block A new block, the first bit block being a bit block that may be inserted into or deleted from the bit block stream during transmission of the bit block stream.
The device according to claim 65, wherein said processor is configured to:

When the number of bytes occupied by the first verification result is greater than or equal to the target number of bytes, storing the first verification result before the end byte in the end block, and according to the first The number of bytes occupied by the verification result moves the end byte to a new block after the end block, deletes any first bit block in the bit block stream, and moves the end byte The new block is located as the updated end block;

When the number of bytes occupied by the first verification result is less than the target number of bytes, storing the first verification result before the end byte in the end block, and according to the The number of bytes occupied by a check result shifts the end byte back by the number of bytes occupied by the first check result, and the bit block where the end byte is moved is used as the updated end block;

The target number of bytes is the number of bytes in the end block after the end byte plus one.
A bit block stream error detecting device, comprising:

a processor, configured to determine, according to a start byte in a start block in a bit block stream and an end byte in an end block corresponding to the start block, a detected segment according to the detected segment; Second check result;

When receiving the first verification result by the transceiver, determining, according to the first verification result and the second verification result, whether the detected segment has an error.
The apparatus according to claim 67, wherein said bit block stream comprises at least one M1/M2 bit block; wherein M1 represents the number of payload bits in each bit block, and M2 represents the total of each bit block The number of bits, M2-M1, represents the number of header sync header bits in each bit block, M1, M2 are positive integers, M2>M1.
The device according to claim 67 or 68, wherein said processor is for

When the first check result is received by the transceiver, and the first check result is stored in the end block, the second check result is deleted from the end block, and the updated end block is obtained. a byte between the start byte in the start block and the end byte in the updated end block as a detected segment;

When the first verification result is received by the transceiver, and the first verification result is stored in the verification result storage block, the verification result storage block is deleted from the bit block stream, and the updated a bit block stream, the byte between the start byte in the start block and the end byte in the end block in the updated bit block stream is used as a detected segment, wherein a check result storage block is located before the end block;

When the first check result is not received, a byte between the start byte in the start block and the end byte in the end block in the bit block stream is taken as the detected segment.
The device of any of claims 67-69, wherein the transceiver is further configured to:

When the first verification result is not received, the second verification result is sent to the third device, and the third device stores the first verification result.
The device according to any one of claims 67 to 70, wherein the processor is configured to:

If it is determined that the first verification result is the same as the second verification result, determining that the detected segment does not have an error;

If it is determined that the first check result is different from the second check result, it is determined that the detected segment has an error.
The device according to claim 69, wherein said processor is configured to:

When the number of bytes occupied by the first check result is greater than or equal to the target number of bytes, moving the end byte to a bit before the end block according to the number of bytes occupied by the first check result Block, adding a first bit block to the bit block stream, and using the bit block in which the end byte is moved as an updated end block;

When the number of bytes occupied by the first check result is less than the target number of bytes, the end byte is forwarded by the first check result according to the number of bytes occupied by the first check result The number of bytes occupied, the bit block in which the end byte is moved is used as the updated end block;

The target number of bytes is the number of bytes in the end block before the end byte plus one.