CN113726475A

CN113726475A - Code block processing method and device

Info

Publication number: CN113726475A
Application number: CN202010457843.XA
Authority: CN
Inventors: 徐丽; 钟其文; 孙德胜
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-05-26
Filing date: 2020-05-26
Publication date: 2021-11-30
Also published as: WO2021238791A1

Abstract

The application discloses a code block processing method and equipment, wherein the method comprises the following steps: at least two first code blocks are obtained, the first code block is a P1B/P2B code block, P1 represents the number of payload bits of the first code block, P2 represents the total number of bits of the first code block, and P2-P1 represent the number of sync header bits of the first code block. And obtaining at least one first check-up result according to the at least two first code blocks, wherein the check-up objects of the first check-up result include M bits in each first code block, wherein the M bits are M bits with bit positions between 10 and 65 in the first code block, the starting bit position of the first code block is 0, and bit positions of at least two bits in the M bits in the first code block are not adjacent. The technical scheme provided by the application can avoid inconsistency between the BIP result determined by the receiving end and the BIP result sent by the sending end due to the addition or deletion of the code block.

Description

Code block processing method and device

Technical Field

The present application relates to the field of communications technologies, and in particular, to a code block processing method and device.

Background

Error performance at the physical layer of a communication device is an important factor in determining transmission quality. Since error performance is an important index of network transmission quality, the international telecommunications union (ITU-T) has issued many proposals regarding error parameters and targets, including definition of block error detection principle for inserting Error Detection Code (EDC) into a channel to be detected, and the like.

Bit Interleaved Parity (BIP) is a checking method for monitoring link quality. However, for end-to-end services such as flexible Ethernet (FlexE), an Ethernet physical layer code block switching-based technology system (X-Ethernet, X-E), or a Metro Transport Network (MTN), a situation of adding and deleting code blocks may occur in a process of sending code blocks from a sender to a receiver, as shown in fig. 1.

In the above situation, how to perform the BIP check is to avoid that the BIP result determined by the receiving end is inconsistent with the BIP result sent by the sending end.

Disclosure of Invention

The application provides a code block processing method and device, which can avoid inconsistency between a BIP result (BIP result) determined by a receiving end and a BIP result sent by a sending end due to the addition or deletion of code blocks.

In a first aspect, an embodiment of the present application provides a code block processing method, including: obtaining at least two first code blocks, wherein the first code blocks are P1B/P2B code blocks, P1 represents the number of payload bits of the first code blocks, P2 represents the total number of bits of the first code blocks, and P2-P1 represent the number of bits of a sync header of the first code blocks; obtaining at least one first check-up result according to at least two first code blocks, wherein the check-up objects of the first check-up result comprise M bits in each first code block, wherein the M bits are M bits with bit positions between 10 and 65 in the first code block, the starting bit position of the first code block is 0, and bit positions of at least two bits in the M bits in the first code block are not adjacent.

Illustratively, the first code block is a 64B/66B code block, which has a total number of bits of 66, a number of payload bits of 64, and which includes a 2-bit synchronization header. The first code block may include a data code block and/or a control code block, in accordance with a related protocol or standard, etc. In general, when a first code block is a control code block, 8 bits of the first code block having bit positions between 2 and 9 are a block type field (blocktype field) of the first code block, and 56 bits of the first code block having bit positions between 10 and 65 are a control code (control code) of the first code block.

The M bits are M bits among the 56 bits, and bit positions of at least two bits of the M bits are not adjacent. Therefore, at least one first check result is obtained by checking M bits in each first code block, which can avoid inconsistency between the first check result determined by the receiving end and the fourth check result sent by the sending end due to the need of adding or deleting control code blocks for rate adaptation and the like when the sending end sends at least two first code blocks to the receiving end. For example, the code block processing device may obtain at least one first check result (or at least one seventh check result) of the at least two first code blocks using a parity method. In conjunction with the following, the code block processing apparatus may further obtain at least one second check result (or at least one eighth check result) and at least one third check result (or at least one ninth check result), and the like, of the at least two first code blocks by using a parity check method.

In the embodiment of the present application, the M bits are M bits with bit positions between 10 and 65 in the first code block, which means that the M bits may include one bit with bit position 10 in the first code block, or the M bits may include one bit with bit position 65 in the first code block. Illustratively, the 8 bits with bit positions between 2 and 9 in the first code block are the block type field of the first code block, which means that the block type field of the first code block includes bit position 2, bit position 3, …, bit position 8 and bit position 9. The embodiments of the present application are also applicable to the following description of the similar descriptions of "bit positions between 10 and 65".

It can be understood that the method provided in this embodiment of the present application may be applied not only to the receiving end, but also to the transmitting end, and may also be applied to any intermediate node between the transmitting end and the receiving end, and the like.

In one possible implementation, M is 8, and the bit positions of the M bits in the first code block include at least one of:

10,17,24,31,38,45,52,59；

11,18,25,32,39,46,53,60；

12,19,26,33,40,47,54,61；

13,20,27,34,41,48,55,62；

14,21,28,35,42,49,56,63；

15,22,29,36,43,50,57,64；

16,23,30,37,44,51,58, 65; alternatively, the first and second electrodes may be,

m-7, bit positions of the M bits in the first code block include at least one of:

10,18,26,34,42,50,58；

11,19,27,35,43,51,59；

12,20,28,36,44,52,60；

13,21,29,37,45,53,61；

14,22,30,38,46,54,62；

15,23,31,39,47,55,63；

16,24,32,40,48,56,64；

17,25,33,41,49,57,65。

Illustratively, when the first code block is a Low Power Idle (LPI) code block, the control code of the LPI code block includes 8 7-bit "0 x 06", and the corresponding binary value is "0000110" (saving the upper bit 0). In some implementations, the 7 bits in the first code block with bit positions between 10 and 16 may be 0000110 in order. In other implementations, the 7 bits corresponding to bit positions between 10 and 16 in the first code block are 0110000 in order. Therefore, the embodiment of the present application does not limit the specific bits corresponding to the bit positions.

In this embodiment of the application, the check object of the first check result includes the M bits, and bit positions of the M bits in the first code block are the at least one group, and when the first code block includes an LPI code block, an even check result of the M bits of the LPI code block is 0. Therefore, with the method provided by the embodiment of the present application, when the sending end sends at least two first code blocks to the receiving end, even if the control code block is added or deleted in the at least two first code blocks, at least one first verification result determined by the receiving end is not affected, so that it can be ensured that at least one seventh verification result determined by the sending end is consistent with the at least one first verification result. Or, when the transmitting end transmits the at least two first code blocks to the receiving end, even if the control code blocks are added or deleted in the at least two first code blocks, the at least one seventh check result determined by the receiving end is not affected, so that the at least one first check result determined by the transmitting end is consistent with the at least one seventh check result.

In one possible implementation, obtaining at least one first check result from at least two first code blocks includes: when M is 8, acquiring seven first check results according to the at least two first code blocks; or when M is 7, eight first check results are obtained from the at least two first code blocks.

In one possible implementation, M is 5, and bit positions of the M bits in the first code block include at least one of:

10,34,42,50,58；

27,35,43,51,59；

20,28,36,44,52；

13,21,29,37,45；

14,22,30,38,62；

15,23,31,55,63；

16,24,48,56,64；

17,41,49,57, 65; alternatively, the first and second electrodes may be,

m-2, bit positions of the M bits in the first code block include at least one of:

18,26；

11,19；

12,60；

53,61；

46,54；

39,47；

32,40；

25,33。

for example, the embodiment of the present application is illustrated by exemplifying that 7 bits corresponding to bit positions between 10 and 16 in the first code block are sequentially 0110000.

When the corresponding 7 bits between bit positions 10 and 16 in the first code block are 0000110 in sequence, M is 5 in one possible implementation, and the bit positions of the M bits in the first code block include at least one of the following groups:

10,18,26,34,58；

11,19,27,51,59；

12,20,44,52,60；

13,37,45,53,61；

30,38,46,54,62；

23,31,39,47,55

16,24,32,40,48；

17,25,33,41, 65; alternatively, the first and second electrodes may be,

42,50；

35,43；

28,36；

21,29；

14,22；

15,63；

56,64；

49,57。

in one possible implementation, obtaining at least one first check result from at least two first code blocks includes: sixteen first check results are obtained according to the at least two first code blocks, and the sixteen first check results include eight first check results when M is 5 and eight first check results when M is 2.

10,13,14,15,16；

17,20,21,22,23；

24,27,28,29,30；

31,34,35,36,37；

38,41,42,43,44；

45,48,49,50,51；

52,55,56,57,58；

59,62,63,64,65。

in one possible implementation, the method further includes: obtaining at least one second check-up result according to the at least two first code blocks, wherein a check-up target of the second check-up result comprises N bits in each first code block, where N is 2, and bit positions of the N bits in the first code blocks comprise at least one of the following groups:

11,12；

18,19；

25,26；

32,33；

39,40；

46,47；

53,54；

60,61。

it can be understood that the embodiment of the present application is illustrated by taking 7 bits in the first code block, which correspond to bit positions between 10 and 16, as an example, and sequentially are 0110000.

10,11,12,13,16；

17,18,19,20,23；

24,25,26,27,30；

31,32,33,34,37；

38,39,40,41,44；

45,46,47,48,51；

52,53,54,55,58；

59,60,61,62,65。

in one possible implementation, the bit positions of the N bits in the first code block include at least one of:

14,15；

21,22；

28,29；

35,36；

42,43；

49,50；

56,57；

63,64。

in a possible implementation manner, the first check result and/or the second check result are obtained by a preset check algorithm, where the preset check algorithm is used to ensure that the first check result determined by the receiving end is consistent with the fourth check result determined by the receiving end under the condition that the control code block is added or deleted in the at least two first code blocks; and/or the preset check algorithm is used for ensuring that the second check result determined by the receiving end is consistent with the fifth check result determined by the receiving end under the condition that the control code block is not added or deleted in the at least two first code blocks.

In this embodiment of the application, the first verification result determined by the receiving end and the fourth verification result determined by the receiving end are the same, which means that the verification result when the control code block is added or deleted in the at least two first code blocks is the same as the verification result when the control code block is not added or deleted in the at least two first code blocks.

In one possible implementation, the control code blocks include idle code blocks and/or low power code blocks.

In one possible implementation, the obtaining at least one first check result according to at least two first code blocks includes: the at least one first check result is obtained at a Metro Transport Network (MTN) channel termination layer (MTN path traffic determination) from the at least two first code blocks.

In a possible implementation manner, the method provided in this embodiment of the present application may be applied to a sending end or a PE node, and after obtaining at least two first code blocks, the method further includes: transmitting at least two first code blocks; and after obtaining at least one first check result from at least two first code blocks, the method further comprises: and sending the at least one first check result.

In one possible implementation, before the transmitting the at least two first code blocks, the method further includes: transmitting a first boundary code block; and after the transmitting at least two first code blocks, the method further comprises: and transmitting a second boundary code block, wherein the first boundary code block and the second boundary code block are used for defining the at least two first code blocks.

In one possible implementation, the at least two first code blocks are part or all of T code blocks between the first boundary code block and the second boundary code block, and T is greater than or equal to 2.

Here, the T code blocks between the first boundary code block and the second boundary code block may be understood as: the T code blocks do not include a first boundary code block and a second boundary code block; alternatively, the T code blocks include a first boundary code block and/or a second boundary code block. In other words, the check-object of the first check-result may include part or all of the T code blocks between the first border code block and the second border code block; alternatively, the check object of the first check result may further include the first border code block and/or the second border code block.

In one possible implementation, the at least one first check result is included in a first boundary code block; or, the at least one first check result is included in the second border code block; or, the at least one first check result is included in the third boundary code block; or, the at least one first check result is contained in a jth first code block after the second boundary code block (or the first boundary code block, the third boundary code block), where j is greater than or equal to 1; alternatively, the at least one first check result is included in a jth first code block before the second boundary code block (or the first boundary code block, the third boundary code block), where j is greater than or equal to 1.

In this embodiment, the sending end may determine at least one first check result in the MTN channel termination layer. The receiving end may determine at least one seventh check result, etc. at the MTN channel termination layer.

In a possible implementation manner, the method provided in this embodiment of the present application may also be applied to a receiving end or a PE node, and the method further includes: receiving at least one seventh check-out result of the at least two first code blocks, a check-out object of the seventh check-out result comprising M bits of each of the at least two first code blocks; and comparing the at least one first check result with the at least one seventh check result to obtain the error conditions of the at least two first code blocks.

In this embodiment of the application, the at least one seventh verification result may be understood as a result sent by the sending end to the receiving end, and the at least one first verification result is a result determined by the receiving end. In this case, the receiving end may compare the seventh check result with the first check result, so as to obtain the error conditions of the at least two first code blocks. For example, if the first check result and the seventh check result obtained by the receiving end are identical, it indicates that there is no error in at least two first code blocks. For another example, if the first check result and the seventh check result obtained by the receiving end are not consistent, it indicates that there is an error in at least two first code blocks.

It is to be understood that, when the at least one first verification result is determined by the receiving end and the at least one seventh verification result is sent by the sending end to the receiving end, or when the at least one first verification result is determined by the sending end and the at least one seventh verification result is determined by the receiving end, the number of the first code blocks included in the verification object of the seventh verification result and the verification object of the first verification result may be different.

In one possible implementation, before acquiring at least two first code blocks, the method further includes: receiving a first boundary code block; and after acquiring the at least two first code blocks, the method further comprises: a second border code block is received, the first border code block and the second border code block to delimit at least two first code blocks.

Here, the T code blocks between the first boundary code block and the second boundary code block may be understood as: the T code blocks do not include a first boundary code block and a second boundary code block; alternatively, the T code blocks include a first boundary code block and/or a second boundary code block. In other words, the check object of the first check result may include part or all of the T code blocks; alternatively, the check object of the first check result may further include the first border code block and/or the second border code block. For example, the T code blocks may include 16k first code blocks.

In one possible implementation, the at least one seventh check result is included in the first boundary code block; or, the at least one seventh check result is included in the second border code block; or, the at least one seventh check result is included in the third boundary code block; or, the at least one seventh check result is included in a jth first code block after the second boundary code block (or the first boundary code block, the third boundary code block), where j is greater than or equal to 1; alternatively, the at least one first check result is included in a jth first code block before the second boundary code block (or the first boundary code block, the third boundary code block), where j is greater than or equal to 1.

In this embodiment, the sending end may determine at least one seventh check result in the MTN channel termination layer. The receiving end may determine at least one first check result, etc. at the MTN channel termination layer.

In a second aspect, an embodiment of the present application provides a code block processing apparatus configured to perform the method in the first aspect or any possible implementation manner of the first aspect. The code block processing device comprises corresponding means to perform the method of the first aspect or any possible implementation of the first aspect.

For example, the code block processing device may include a transceiver unit and a processing unit.

In a third aspect, an embodiment of the present application provides a code block processing apparatus, which includes a processor configured to execute a program stored in a memory, and when executed, cause the code block processing apparatus to perform a method as set forth in the first aspect or any possible implementation manner of the first aspect.

In one possible implementation, the memory is located outside of the code block processing device described above.

In one possible implementation, the memory is located within the code block processing device described above.

In one possible implementation, the code block processing device further includes a transceiver to receive signals or transmit signals. Illustratively, the transceiver may be configured to transmit at least two first code blocks or to transmit at least one first check result, etc. As another example, the transceiver may be configured to receive at least two first code blocks or to receive at least one first check result, and/or the like.

In a fourth aspect, an embodiment of the present application provides a code block processing apparatus, which includes a processing circuit and an interface circuit, the processing circuit being configured to obtain at least two first code blocks, where the first code block is a P1B/P2B code block, P1 represents the number of bits of a payload of the first code block, P2 represents the total number of bits of the first code block, and P2-P1 represent the number of bits of a sync header of the first code block; and obtaining at least one first check result according to the at least two first code blocks, wherein the check objects of the first check result include M bits in each first code block, the M bits are M bits with bit positions between 10 and 65 in the first code block, the starting bit position of the first code block is 0, and bit positions of at least two bits in the M bits in the first code block are not adjacent.

It is understood that reference may also be made to the following for specific implementations of the processing circuit and the interface circuit, which will not be described in detail herein.

In a fifth aspect, embodiments of the present application provide a computer-readable storage medium for storing a computer program, which when run on a computer causes the method shown in the first aspect or any possible implementation manner of the first aspect to be performed.

Alternatively, the computer readable storage medium is used to store a computer program which, when executed, causes the method illustrated in the first aspect or any possible implementation of the first aspect described above to be performed.

In a sixth aspect, embodiments of the present application provide a computer program product comprising a computer program or computer code which, when run on a computer, causes the method illustrated in the first aspect or any possible implementation manner of the first aspect to be performed.

Alternatively, the computer program product comprises a computer program or computer code which, when run, causes the method illustrated in the first aspect or any possible implementation of the first aspect described above to be performed.

In a seventh aspect, an embodiment of the present application provides a computer program, which when running on a computer, performs the method shown in the first aspect or any possible implementation manner of the first aspect.

Alternatively, the computer program may be executed to perform a method as illustrated in the first aspect or any possible implementation manner of the first aspect.

In an eighth aspect, an embodiment of the present application provides a code block processing system, where the code block processing system includes a sending end and a receiving end, where the sending end may be configured to perform the correlation method shown in the first aspect, and the receiving end may also be configured to perform the correlation method shown in the first aspect.

It is understood that reference may also be made to the following for specific implementations of the transmitting end and the receiving end, which will not be described in detail herein.

Drawings

Fig. 1 is a schematic diagram of a network architecture provided in an embodiment of the present application;

fig. 2a is a schematic diagram illustrating a pattern definition of a 64B/66B code block according to an embodiment of the present application;

fig. 2B is a schematic diagram illustrating a pattern definition of a 64B/66B code block according to an embodiment of the present application;

fig. 2c is a schematic diagram of code pattern definition of an idle code block according to an embodiment of the present application;

fig. 2d is a schematic diagram illustrating a pattern definition of an LPI code block according to an embodiment of the present application;

Fig. 3a is a schematic diagram of an MTN network architecture according to an embodiment of the present application;

fig. 3b is a forwarding schematic diagram of an MTN network according to an embodiment of the present application;

fig. 3c is a schematic diagram of a change in the number of code blocks according to an embodiment of the present application;

fig. 4a is a schematic diagram illustrating an influence of an idle code block and an LPI code block on a check result according to an embodiment of the present application;

fig. 4b is a schematic diagram illustrating an influence of an idle code block on a check result according to an embodiment of the present application;

fig. 5a is a schematic diagram of a network architecture according to an embodiment of the present application;

FIG. 5b is a schematic diagram of another network architecture provided by the embodiments of the present application;

fig. 6 is a flowchart illustrating a code block processing method according to an embodiment of the present application;

FIG. 7a is a schematic diagram of a zonal verification provided in an embodiment of the present application;

FIG. 7b is a schematic diagram of another partition checking provided in the embodiments of the present application;

fig. 8a is a schematic diagram of a check method of an LPI code block according to an embodiment of the present application;

FIG. 8b is a schematic diagram of a verification method provided in the embodiments of the present application;

fig. 8c is a schematic diagram illustrating a checking method of an idle code block according to an embodiment of the present application;

fig. 8d is a schematic diagram of a check method of an LPI code block according to an embodiment of the present application;

Fig. 9a is a schematic diagram of a check method of an LPI code block according to an embodiment of the present application;

FIG. 9b is a schematic diagram of a verification method provided in the embodiments of the present application;

fig. 10a is a schematic diagram of a check method of an LPI code block according to an embodiment of the present application;

fig. 10b is a schematic diagram of a check method of an LPI code block according to an embodiment of the present application;

fig. 11a is a schematic diagram of a verification method of an LPI code block according to an embodiment of the present application;

fig. 11b is a schematic diagram of a check method of an LPI code block according to an embodiment of the present application;

fig. 12a is a schematic flowchart of a code block processing method provided in an embodiment of the present application;

fig. 12b is a schematic diagram of a relationship between a BIP result and a boundary code block according to an embodiment of the present application;

fig. 12c is a schematic diagram of a relationship between a BIP result and a boundary code block according to an embodiment of the present application;

fig. 12d is a schematic diagram of another BIP result and a boundary code block according to an embodiment of the present application;

fig. 12e is a schematic diagram illustrating a relationship between a BIP result and a boundary code block according to an embodiment of the present application;

fig. 12f is a schematic flowchart of another code block processing method provided in this embodiment of the present application;

fig. 13 is a schematic structural diagram of a code block processing apparatus provided in an embodiment of the present application;

Fig. 14 is a schematic structural diagram of a code block processing apparatus provided in an embodiment of the present application;

fig. 15 is a schematic structural diagram of a code block processing apparatus provided in an embodiment of the present application;

fig. 16 is a schematic diagram of a code block processing system provided in an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more clear, the present application will be further described with reference to the accompanying drawings.

The terms "first" and "second," and the like in the description, claims, and drawings of the present application are used solely to distinguish between different objects and not to describe a particular order. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions. Such as a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those skilled in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

In this application, "at least one" means one or more, "a plurality" means two or more, "at least two" means two or three and three or more, "and/or" for describing an association relationship of associated objects, which means that there may be three relationships, for example, "a and/or B" may mean: only A, only B and both A and B are present, wherein A and B may be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one item(s) below" or similar expressions refer to any combination of these items. For example, at least one (one) of a, b, or c, may represent: a, b, c, "a and b," a and c, "" b and c, "or" a and b and c.

The terms referred to in the present application are described in detail below.

P1B/P2B bit block (bit block): one encoding scheme may be referred to as a P1B/P2B code block (block), or a P1B/P2B block, or a P1B/P2B code block, or a P1B/P2B bit stream, or a P1/P2 (or P1B/P2B) bit block, or the like. Where P1 represents the number of payload bits in a block (or block) of bits; p2 represents the total number of bits of the bit block, P2-P1 represent the number of sync header bits in the bit block, P1, P2 are positive integers, and P2 is greater than P1.

Illustratively, what is carried on an ethernet (ethernet) physical layer link is such a block of P1B/P2B bits. For example, 1G Ethernet (1gigabit Ethernet, 1GE) adopts 8B/10B bit block coding mode, and 1GE physical layer link transfers 8B/10B bit block; the 10GE/40GE/100GE adopts a 64B/66B bit block coding mode, and the 10GE/40GE/100GE physical layer link transfers 64B/66B bit blocks. It is understood that, in the future, with the development of ethernet technology, other encoding modes may also occur, such as 128B/130B (also referred to as 128B/130B) bit block, 256B/258B (also referred to as 256B/258B) bit block, and the present application does not limit the specific values of the above-mentioned P1 and P2.

Exemplarily, the above-mentioned P1 ═ 64 and P2 ═ 66, that is, the method provided by the present application will be illustrated below by using a 64B/66B code block as an example. It is understood that the 64B/66B code blocks shown below may also be replaced by 64B/66B bit blocks, or 64/66 code blocks, or 64/66 bit blocks, or 64B/66B code blocks, or 64B/66B bit blocks, or 64B/66B bit block streams, or 64B/66B code blocks, etc.

As an example, fig. 2a and 2B show different pattern definitions for a 64B/66B code block. As shown in fig. 2a or fig. 2b, 2 bits "10" or "01" of the header are synchronization header bits, and the last 64 bits are payload bits, which can be used to carry payload data and the like. Fig. 2a shows 12 pattern definitions, fig. 2b shows 16 pattern definitions, and each row in fig. 2a and fig. 2b represents a pattern definition, where D0-D7 represent data bytes, C0-C7 represent control bytes, S0 represents a start byte of a Media Access Control (MAC) frame, and T0-T7 represent an end byte of the MAC frame. It is understood that fig. 2a is the code pattern definition at the port 40G or 100G, fig. 2B is the code pattern definition at the port 10G, and in a specific implementation, the code pattern definition of the 64B/66B code block may be more, and the present application does not limit this.

Control code block: the control pattern defined in the above-mentioned P1B/P2B code block. Illustratively, the sync header of the control code block may be "10", and the control code block may further include a block type field (block type field) and a control code (control code). Illustratively, the block type field (block type field) of the control code blocks defined in 64B/66B may be 0x 1E. For example, fig. 2c shows an idle (idle) code block, where the sync header bit of the idle code block is "10", the first control block byte is 0x1E, and the 0x1E may represent a block type field (block type field) of the idle code block, and its corresponding 8 bits are "00011110"; the remaining 8 bits are 0x00, and the 0x00 may represent a control code (control code) of the idle code block, and its corresponding 7 bits are "0000000" (upper bit 0 is omitted). For another example, fig. 2d shows a Low Power Idle (LPI) code block, which has a sync header bit of "10" and a first control byte of 0x 1E; the remaining 8 bits are all 0x06, and the corresponding 7 bits are "0000110" (with the upper bit 0 omitted). Optionally, the control code block may further include an error (error) code block or the like, which is not shown in the drawing. It is to be understood that the idle code blocks shown in this application may also be referred to as idle control code blocks, etc., and the LPI code blocks may also be referred to as LPI control code blocks, etc., which are not limited in this application.

Bit position (Bit position): as shown in fig. 2a or fig. 2b, the 8 bits with bit positions between 2 and 9 in the first code block may be 0x1E, but the application is not limited to the specific bit positions of its corresponding 8 bits "00011110". For example, 8 bits with bit positions between 2 and 9 in the first code block may be 00011110 in order. As another example, the 8 bits with bit positions between 2 and 9 in the first code block may also be 01111000 in order. For an LPI code block, 7 bits of the LPI code block having bit positions between 10 and 16 may be 0x06, and the corresponding 7 bits are "0000110". For example, 7 bits of the LPI code block having bit positions between 10 and 16 may be 0000110 in sequence. For another example, the 7 bits with bit positions between 10 and 16 in the LPI code block may also be 0110000 in sequence. In other words, when the code block processing device transmits the first code block, the transmission order of the bits included in the first code block may be the order of the bits included by one byte from the upper bits to the lower bits; alternatively, the code block may include bits in the order of transmission from the lower order to the upper order of the bits included in one byte.

It is understood that in the present application, the transmission order of bits is differentiated with one byte as granularity. However, in a specific implementation, the transmission order of the bits may also be differentiated by taking other units as granularity, such as a half byte (i.e. 4 bits), and the like, which is not limited in this application. It is understood that the bit positions between 2 and 9 in the first code block shown above can be understood as: the bit positions in the first code block are 8 bits between 2, 3, 4, 5, 6, 7, 8 and 9, i.e. between

bit positions

2 and 9 in the first code block comprise bit position 2 and bit position 9. Likewise, bit positions 10 and 16 in the first code block may also be included between bit positions 10 and 16. The application applies equally to similar explanations for "between bit positions 10 to 65" below.

BIP-x: based on the BIP algorithm, the basic idea of the BIP algorithm is to divide the signal to be checked (e.g. the at least two first code blocks) into x check blocks (which may also be referred to as x monitoring codes, x check regions, etc.). For example, the Synchronous Digital Hierarchy (SDH) employs BIP-16, BIP-8, or BIP-2, etc. An Optical Transport Network (OTN) employs BIP-8.

It is understood that the BIP-x provided by the present application may further include BIP- (1+7), BIP- (1+8), BIP- (1+16) or BIP- (2+7), BIP- (2+8), BIP- (2+16), and the like.

The first check result: the check-object of the first check-result includes M bits in each of the at least two first code blocks. The first check result may also be referred to as a check block (or a monitoring code) in x check blocks (or x monitoring codes, x check areas, etc.).

And the second check result: the check-object of the second check-up result includes N bits in each of the at least two first code blocks. The check result may also be referred to as a check block (or a monitoring code) in x check blocks (or x monitoring codes, x check regions, etc.).

And a third checking result: the check-object of the third check-result includes 8 bits with bit positions between 2 and 9 in each of the at least two first code blocks. The third verification result may also be referred to as a verification code (or a monitoring code) in x verification codes (or x monitoring codes, x verification areas, etc.).

In some implementations, the x monitoring codes included in the BIP-x in the embodiment of the present application may include at least one first check result and at least one third check result. In other implementations, the x monitoring codes included in the BIP-x in the embodiment of the present application may include at least one first check result, at least one second check result, and at least one third check result.

It is understood that for convenience of description, the check code will be collectively referred to as a monitoring code hereinafter. It is understood that the x monitor codes shown in the present application can also be understood as BIP results (BIP results). In other words, the BIP result can also be understood as x monitoring codes obtained according to the BIP-x algorithm.

And (3) BIPs: the sending end determines the BIP results of at least two code blocks (e.g., at least two first code blocks), and the sending end needs to send the BIP results of the at least two code blocks to the receiving end.

BIPd: and the receiving end determines the BIP results of at least two code blocks. Generally, the number of the at least two first code blocks transmitted by the transmitting end is different from the number of the at least two first code blocks received by the receiving end.

Error rate: a ratio of a number of erroneous bits in the at least two code blocks to a total number of bits of the at least two code blocks. If the bit error rate can satisfy the following conditions:

wherein, the BER is a Bit error rate (Bit error rate, BER); the number of error bits indicates the number of bits of errors occurring in the received code block. Illustratively, 66 bits may be included in one 64B/66B code block.

As shown in fig. 1, a transmitting end transmits at least two code blocks to a receiving end, the code blocks including 64B/66B code blocks. However, the rate at which the code blocks are transmitted by the transmitting end and the rate at which the code blocks are received by the receiving end may not be the same, in which case the transmitting end needs to perform rate adaptation.

For example, as shown in fig. 3a, a data stream and the like acquired by a transmitting end are adapted by an MTN path adaptation layer (MTN path adaptation)301 to form a 64B/66B code block stream. After the 64B/66B code block stream passes through an MTN path termination layer (MTN path termination)302, OAM (operation, administration, and main) information including a BIP result is inserted into the 64B/66B code block stream. In this embodiment, the sender may determine (or calculate) the BIP result at the MTN channel termination layer. In combination with the following, that is, the sender may determine at least one first check result (or may further include at least one second check result or at least one third check result) at the MTN channel termination layer; or at least one seventh verification result (or may also include at least one eighth verification result and at least one ninth verification result), and so on.

Then, the sending end may perform 1.5-layer forwarding through an MTN path connection layer (MTN path connection)303, that is, determine a corresponding relationship of the ingress port at the MTN path connection layer, thereby determining the port. An MTN section adaptation layer (MTN section adaptation)304 is a function of adapting from a channel layer to a section layer, and each MAC data stream (for example, in the form of a 64B/66B code block) in the MTN section adaptation layer is interleaved to form a 64B/66B code block stream. Then, the one 64B/66B code block stream passes through an MTN section layer termination layer (MTN section termination)305 to be inserted with overhead information such as section layer OAM. The 64B/66B code block stream then passes through an adaptation layer (adaptation)306 into the physical layer for transmission, etc.

Fig. 3b presents a forwarding diagram for MTN networking. The top layer client service at the sending end becomes 64B/66B code block flow after being adapted by the MTN channel adaptation layer. After the 64B/66B code block stream of each service enters the MTN channel termination layer, BIP calculation is performed, and a BIP result is placed into an OAM code block (i.e., the OAM code block includes OAM information including a BIP result) and sent together with the 64B/66B code block stream. The 64B/66B code block stream added with the OAM information is interleaved with 64B/66B code block streams of other services at the same outlet through an MTN channel connection layer and an MTN section layer adaptation layer to become a path of 64B/66B code block stream. And then the path of 64B/66B code block flow is inserted into segment overhead information through an MTN segment layer terminating layer, and then is sent to a link through an Ethernet bottom layer.

The intermediate node (MTN node 2) only processes the traffic 64B/66B code block stream and does not sense the traffic data stream and OAM information in the traffic code block stream, i.e., the OAM information is end-to-end and the intermediate node does not sense.

After a host node (MTN node 3) receives a service code block stream, the service code block stream will first pass through an MTN segment layer terminating layer to take out segment layer overhead information (such as segment layer OAM information), and then pass through an MTN segment layer adaptation layer, to de-interleave one path of interleaved service code stream, and pass through an MTN channel connection layer switching network, and then upward by an MTN channel terminating layer, to extract channel layer OAM information in the service code block stream, where the channel layer OAM information includes a BIP result. In this embodiment, the sink node may determine the local BIP result at the MTN channel termination layer. In conjunction with the following, in the case that the sender may determine at least one first check result (or may further include at least one second check result or at least one third check result) at its MTN channel termination layer, the sink node may determine at least one seventh check result (or may further include at least one eighth check result and at least one ninth check result) at its MTN channel termination layer. In case the sender determines at least one seventh check result (or may further include at least one eighth check result and at least one ninth check result) at its MTN channel termination layer, the sink node may determine at least one first check result (or may further include at least one second check result or at least one third check result) at its MTN channel termination layer. Then, the sink node compares the local BIP result with the received BIP result, and counts the number of wrong bits.

In other words, at the transmitting end, when the channel layer traffic is transmitted to the segment layer, rate adaptation (or may also be referred to as clock synchronization) may be required because of the deviation of the channel layer and segment layer rates, and the BIP result is already placed in the OAM code block and transmitted. At the intermediate node, rate adaptation is also required because there may be a rate deviation in the clock frequency between the ingress port and the egress port. At the sink node, rate adaptation may also be required when the customer traffic code block stream is sent from the segment layer to the channel layer. Therefore, the at least two code blocks received by the receiving end may not coincide with the at least two code blocks sent by the sending end. In this embodiment, the sending end, the intermediate node, the destination node, and the like may be collectively referred to as code block processing equipment.

As shown in fig. 3c, the code block processing device may add or delete one or more control code blocks in at least two code blocks, thereby achieving rate adaptation. The control code blocks may for example comprise idle code blocks, LPI code blocks or sequence code blocks (O code blocks), etc.

As can be seen from fig. 3a and 3b, when the sending end performs rate adaptation, the BIP result calculated by the sending end is already carried in the OAM information. In other words, the BIP result sent by the sending end to the receiving end is the BIP result when the sending end has not added or deleted the control code block. Further, when the sending end performs rate adaptation, the BIP result is already carried in the OAM information. Therefore, whether the granularity of rate adaptation is the granularity of code blocks or the granularity of bits, etc., the BIP result calculated by the sending end is not affected.

Fig. 4a and 4b are schematic diagrams illustrating the effect on the BIP result when a code block processing device adds a control code block, as shown in fig. 4a and 4 b. Illustratively, the code block processing device needs to add a control code block such as an LPI code block or an idle code block due to rate adaptation, as shown in fig. 4a, the BIP result of the data code block transmitted by the transmitting end is "10000000", whereas the BIP result of a single control code block is "01111000". In this case, as shown in fig. 4b, if one control code block, for example, an idle code block, is added to the code block transmitted from the transmitting side, the final BIP result determined by the receiving side is "11111000". In other words, when the control code block is added or deleted due to rate adaptation, the BIP result of the data code block transmitted by the transmitting end may not be consistent with the BIP result determined by the receiving end by 4 bits.

In this case, the receiving end may compare the calculated BIPd with the received BIPs to evaluate the error condition of the link. However, since the rate adaptation needs to increase the number of control code blocks, it is easy for the receiving end to misjudge the error condition of the link. For example, adding control code blocks may result in an accumulation of the number of error bits in the link error rate statistics, thereby resulting in an increase in the error rate when the receiver calculates the error rate. Alternatively, the error-free data currently received by the receiving end is regarded as the error-free data and is discarded by the receiving end, further resulting in the waste of bandwidth.

In view of this, the present application provides a code block processing method and device, which can effectively avoid the situation that a BIP result determined by a receiving end is inconsistent with a BIP result determined by a sending end due to rate adaptation performed when an asynchronous node is traversed (a receiving clock, a node clock, or a sending clock is not necessarily completely synchronous) and a control code block is added or deleted.

The method provided by the application can be applied to any network needing error code detection or link quality evaluation, such as MTN, Flexe, SDH/OTN or industrial Ethernet. As shown in fig. 5a and/or fig. 5b, the method provided by the present application may be applied to the transmitting end and/or the receiving end shown in fig. 5a and/or fig. 5 b. Meanwhile, the method provided by the application can also be applied to scenes in which the BIP check needs to be performed hop by hop, such as P nodes or PE nodes. It can be understood that in fig. 5a, the sender includes a standard ethernet interface, and the P node includes an MTN/FlexE interface, so that a communication function needs to be implemented between the sender and the P node through a Provider Edge (PE) node, for example, the communication function may include forwarding a 64B/66B code block. In fig. 5b, the sender can directly communicate with the P node because the sender includes an MTN/FlexE interface. For convenience of illustration, in fig. 5a and/or fig. 5b, only one line is shown between the sending end and the PE node, between the PE node and the P node, between the P node and the receiving end, or between the sending end and the P node, but it does not mean that there is only one line. And the number of interfaces in fig. 5a and/or fig. 5b are merely examples, and the number of interfaces and the types of interfaces included in the code block processing device are not limited in the embodiment of the present application.

Illustratively, the sending end may include a wired device, a wireless device (including a wireless terminal device or a wireless user device, etc.), a switch, a router, a network card, or the like. Meanwhile, the sending end may further include a device with an ethernet port, or a device with an MTN/FlexE interface, and the like. Meanwhile, the receiving end may also include a switch, a router, a network card, or the like. In other words, the methods provided herein may be applied to code block processing devices, which may include wired devices, wireless devices, switches, routers, or network cards, among others. Alternatively, the method provided by the present application may also be applied to devices and the like having similar functions, which are not limited in the present application.

Referring to fig. 6, fig. 6 is a flowchart illustrating a code block processing method provided in an embodiment of the present application, which may be applied to the network architecture shown in fig. 5a and/or fig. 5 b. As shown in fig. 6, the method includes:

601. the code block processing apparatus acquires at least two first code blocks, which are P1B/P2B code blocks, P1 represents the number of payload bits in the first code block, P2 represents the total number of bits of the first code block, and P2-P1 represent the number of sync header bits in the first code block.

In the embodiment of the application, P1 is 64, P2 is 66; alternatively, P1 ═ 128, P2 ═ 130, and the like, and reference may be made to the above for specific descriptions of P1 and P2, and details thereof are not described here.

It is to be understood that the at least two first code blocks may include two first code blocks; alternatively, three or more first code blocks and the like may be included.

602. The code block processing device obtains at least one first check-up result from at least two first code blocks, a check-up object of the first check-up result including M bits in each first code block, where the M bits are M bits having Bit positions (Bit positions) of between 10 and 65 in the first code block, a starting Bit position of the first code block is 0, and Bit positions of at least two bits of the M bits in the first code block are not adjacent.

The above M bits can also be understood as: m bits between 11 th bit to 66 th bit in the first code block whose starting bit is the 1 st bit. Illustratively, the 1 st bit and the 2 nd bit of the first code block are the synchronization header of the first code block, i.e., the two bits with

bit positions

0 and 1 in the first code block are the synchronization header of the first code block.

For example, when the first code block is a 64B/66B code block, the bit positions of the 2-bit synchronization header in the first code block are 0 and 1, or the 2-bit synchronization header is the 1 st bit and the 2 nd bit of the first code block. When the first code block includes the control code block defined in 64B/66B, the 3 rd bit to the 10 th bit are the block type field of the first code block, such as 0x1E in fig. 2a or fig. 2B. In other words, the bit positions of the block type field of the first code block are 2 to 9. Meanwhile, the 11 th bit to the 66 th bit in the first code block are 8 control codes of 7 bits in fig. 2a or fig. 2 b. In other words, the bit positions of the control code of the first code block are 10 to 65.

The starting bit position of the first code block shown above is 0, and in a specific implementation, the starting bit position of the first code block may also be 1, 2, or 3, etc. As in the case of the starting bit position of 1, the M bits are M bits between bit positions 11 to 66 in the first code block. As another example, in the case where the starting bit position is 2, the M bits are M bits having bit positions between 12 and 67 in the first code block. Therefore, the starting bit position shown in the embodiment of the present application should not be construed as a limitation to the embodiment of the present application. It is understood that other embodiments shown in this application are equally applicable to the description of the starting bit position.

Exemplarily, when the first code block includes an LPI code block, as shown in fig. 7a, the 3 rd bit to the 10 th bit are sequentially "01111000"; the 11 th bit to the 66 th bit are 8 "0110000".

Exemplarily, when the first code block includes an LPI code block, as shown in fig. 7b, the 3 rd bit to the 10 th bit are "00011110" in order; the 11 th bit to the 66 th bit are 8 "0000110".

It can be understood that, in the embodiment of the present application, the value of X in fig. 7a and/or fig. 7b is not limited, and the value of Y may refer to the following, which is not detailed here first.

In the embodiment of the present application, the bit positions of at least two bits of the M bits in the first code block are not adjacent, which can be understood as: at least two bits of the M bits are not adjacent to each other in the bit position of the first code block, or it can be understood that: at least two bits of the M bits are not consecutive in bit position in the first code block. Illustratively, the M bits are 7 bits with bit positions between 10 and 16 in the first code block, then bit position 10 and bit position 11 in the 7 bits are adjacent (or continuous), but bit position 10 and bit position 12 (or bit position 13, etc.) are not adjacent (or discontinuous).

In this embodiment of the application, the first verification result may be obtained by a preset verification algorithm, where the preset verification algorithm is used to ensure that the first verification result determined by the receiving end is consistent with the fourth verification result determined by the receiving end without adding or deleting the control code block in the at least two first code blocks.

Considering that one or more control code blocks are added or deleted when the at least two first code blocks traverse the asynchronous node, the number of the at least two first code blocks received by the receiving end and the number of the at least two first code blocks transmitted by the transmitting end may not be the same. Exemplarily, if the control code blocks are added, the number of the first code blocks received by the receiving end is greater than the number of the first code blocks sent by the sending end; if the control code blocks are deleted, the number of the first code blocks received by the receiving end is smaller than the number of the first code blocks sent by the sending end. For example, the transmitting end sends 16k first code blocks (e.g., 16384 first code blocks may be included, etc.) to the receiving end, and the transmitting end or the receiving end may add or delete one or more control code blocks when the 16k first code blocks traverse the asynchronous node. Therefore, the receiving end may receive 16k + n first code blocks, where n may be a positive integer, 0, or a negative integer. In this case, the check object of the first check result may be M bits of each of the 16k + n first code blocks. And the check object of the fourth check result is M bits of each of the 16k first code blocks. It can be understood that the first verification result and the fourth verification result use the same predetermined verification algorithm.

By implementing the embodiment of the application, at least one first check result is obtained by checking M bits in each first code block, and it can be avoided that the first check result determined by the receiving end is inconsistent with the fourth check result sent by the sending end due to the addition or deletion of the control code blocks when the sending end sends at least two first code blocks to the receiving end.

The control code blocks in the embodiments of the present application may be the patterns defined in the P1B/P2B code blocks, for example, the control code blocks may include idle code blocks and LPI code blocks. Alternatively, the control code block in the embodiment of the present application may also be another type of code block, such as a local error (LF) code block, a remote error (RF) code block, or an error (error) code block, and the specific type of the control code block is not limited in the embodiment of the present application. It is understood that, for convenience of description, the method provided by the embodiment of the present application will be described below by taking the control code block as an LPI code block as an example.

The M bits in the embodiment of the present application are described in detail below.

The first method,

M-8, bit positions of the M bits in the first code block include at least one of:

10,17,24,31,38,45,52,59；

11,18,25,32,39,46,53,60；

12,19,26,33,40,47,54,61；

13,20,27,34,41,48,55,62；

14,21,28,35,42,49,56,63；

15,22,29,36,43,50,57,64；

16,23,30,37,44,51,58,65。

alternatively, the above M bits may also be understood to include at least one of the following groups:

11 th bit, 18 th bit, 25 th bit, 32 th bit, 39 th bit, 46 th bit, 53 th bit, 60 th bit;

12 th bit, 19 th bit, 26 th bit, 33 th bit, 40 th bit, 47 th bit, 54 th bit, 61 th bit;

13 th bit, 20 th bit, 27 th bit, 34 th bit, 41 th bit, 48 th bit, 55 th bit, 62 th bit;

14 th bit, 21 st bit, 28 th bit, 35 th bit, 42 th bit, 49 th bit, 56 th bit, 63 th bit;

15 th bit, 22 nd bit, 29 th bit, 36 th bit, 43 th bit, 50 th bit, 57 th bit, 64 th bit;

16 th bit, 23 th bit, 30 th bit, 37 th bit, 44 th bit, 51 th bit, 58 th bit, 65 th bit;

the 17 th bit, the 24 th bit, the 31 th bit, the 38 th bit, the 45 th bit, the 52 th bit, the 59 th bit, and the 66 th bit.

As shown in fig. 8a, the LPI code block includes 1 block type field of 8 bits and 8 control codes of 7 bits. The 8 7-bit control code "0000110" of the LPI code block is transformed into 7 8 bits, such as 58 bits of "00000000" and 28 bits of "11111111". It is to be understood that fig. 8a and 8b are illustrated with the order of the bit positions in the first code block from small to large being 01111000, 0110000. In other words, in fig. 8a and 8b, the 8 bits between the bit positions 2 and 9 in the first code block are 01111000 in turn, the 7 bits between the bit positions 10 and 16 in the first code block are 0110000 in turn, the 7 bits between the bit positions 17 and 23 in the first code block are 0110000 in turn, and so on, the bits (or bit values) corresponding to the 64 bit positions in the first code block in turn can be obtained.

Illustratively, the code block processing apparatus checks the second row (i.e., the bit positions are 10,17,24,31,38,45,52,59) of each first code block to obtain the first check result, checks the third row (i.e., the bit positions are 11,18,25,32,39,46,53,60) of each first code block to obtain the first check result, and so on, the code block processing apparatus may obtain seven first check results. In other words, the code block processing apparatus obtaining at least one first check result from at least two first code blocks includes: the code block processing apparatus records M bits in each of at least two first code blocks to at least one first monitored section (monitored block), and determines a monitored code (monitored block) of the at least one first monitored section according to a parity method. The first monitoring section may be understood as any one or more of the threads 2 to 8 shown in fig. 8a, and the monitoring code may be understood as the first check result. I.e. 8 bits with

bit positions

10,17,24,31,38,45,52,59 in each first code block enter a first monitoring section, 8 bits with

bit positions

11,18,25,32,39,46,53,60 in each first code block may enter another first monitoring section, and so on, the code block processing apparatus may obtain seven monitoring codes (e.g. b1 to b7 in fig. 8 b) of seven monitoring sections, one monitoring section corresponding to one monitoring code.

Further, the code block processing device may further obtain at least one third check result from the at least two first code blocks, and the check object of the at least one third check result includes 8 bits with bit positions between 2 and 9 in each first code block. I.e. 8 bits with bit positions between 2 and 9 in each first code block, may enter the third surveillance zone so that the code block processing device may obtain the surveillance codes of this third surveillance zone (e.g. b0 in fig. 8 b). For example, the 8-bit monitoring code (BIP-8) shown in fig. 8b, such as b0, b1 to b7, may each be a one-bit monitoring code. It can be understood that the embodiment of the present application is not limited to how many bits the monitoring code is specific.

As shown in fig. 8c, when the control code block includes an IDLE code block (or called IDLE code block), the code block processing device may also obtain at least one third check result and seven first check results. For a specific implementation of the code block processing device to obtain at least one third check result and seven first check results, reference may be made to fig. 8a, which is not described in detail here. It can be understood that, for a specific implementation when the control code block includes an idle code block, details are not described below, and the code block processing method provided in the embodiment of the present application will be illustrated below by taking the control code block including an LPI code block as an example.

Alternatively, taking the example that the control code block includes an LPI code block, as shown in fig. 8d, fig. 8d illustrates the order of the bit positions in the LPI code block from small to large as 00011110, 0000110, and …. In other words, in fig. 8d, when an LPI code block is included in the at least two first code blocks, 8 bits between

bit positions

2 and 9 in the LPI code block are 00011110 in order, 7 bits between bit positions 10 and 16 in the LPI code block are 0000110 in order, 7 bits between bit positions 17 and 23 in the LPI code block are 0000110 in order, and so on, bits corresponding to 64 bit positions in the LPI code block in order can be obtained. It is understood that other types of control code blocks are equally applicable to this description, and the embodiments of the present application are not described in detail.

In the embodiment of the present application, although 8 bits corresponding to 0x1E and 7 bits corresponding to 0x06 are arranged differently in the first code block in fig. 8a and 8d, the bit positions of the M bits in the first code block obtained according to the above-described method (the above-described 7 groups of M bits are shown) are the same. It can be understood that, for the correspondence between each thread and the bit position in fig. 8a to 8d, the embodiment of the present application is not limited.

Thus, the code block processing apparatus can obtain 8 monitoring codes (b0 to b7), i.e., 7 first check results and 1 third check result, of at least two first code blocks. It can be understood that the 8 monitoring codes may also be referred to as a verification result of BIP-8, or may also be referred to as a BIP result, and the like, which is not limited in this embodiment of the present application. It is understood that in the method shown in fig. 8a to 8d, the predetermined checking algorithm may be referred to as a BIP-8 checking algorithm.

In the embodiment of the present application, when the first code block includes an LPI code block, as shown in fig. 8a and 8d, since an even number of "1" (for example, 8 1 s) is included in the check object of the first check result, the first check result of the LPI code block is 0 according to the parity check method. That is, it can be obtained by the parity check method that the seven first check results of the LPI code block are 0 respectively, and the third check result is 0. When the first code block includes an idle code block, as shown in fig. 8c, it can be obtained by the parity method that seven first check results of the idle code block are 0, respectively, and the third check result is 0. Therefore, when the transmitting end transmits at least two first code blocks to the receiving end, even if the control code block is added or deleted in the at least two first code blocks, the BIP results of the at least two first code blocks after the control code block is added or deleted are not affected. It is understood that other embodiments shown in the present application are also applicable to this description, for example, the method shown in fig. 9a and 9b, the method shown in fig. 10a and 10b, and the method shown in fig. 11a and 11b are all applicable, and the details are not repeated.

In other words, the preset check algorithm may be used to ensure that the first check result determined by the receiving end in the case where the control code block is added or deleted in the at least two first code blocks is identical to the fourth check result determined by the receiving end in the case where the control code block is not added or deleted in the at least two first code blocks. Meanwhile, the preset check algorithm may be further configured to ensure that a third check result determined by the receiving end is consistent with a sixth check result determined by the receiving end under the condition that the control code block is not added or deleted in the at least two first code blocks.

Alternatively, fig. 8a to 8d illustrate an example in which when M is 8, the code block processing apparatus obtains seven first check results. In one possible implementation, M may also be equal to 16, 24, 32, 40, 48, or 56, etc. Where M is 16, the bit positions of the 16 bits in the first code block may include two groups of seven groups of bit positions shown in method one; when M is 24, the bit positions of the 24 bits in the first code block may include three groups of seven groups of bit positions shown in method one; when M is 32, the bit positions of the 32 bits in the first code block may include four of the seven sets of bit positions shown in method one; when M is 40, the bit positions of 40 bits in the first code block may include five groups of seven groups of bit positions shown in method one; when M is 48, the bit positions of 48 bits in the first code block may include six groups of seven groups of bit positions shown in method one; when M is 56, the bit positions of 56 bits in the first code block may include seven groups of the seven groups of bit positions shown in method one.

For example, the code block processing device may obtain three first check results when M is 16, and one first check result when M is 8. In this case, the code block processing apparatus can obtain four first check results. For another example, the code block processing device may obtain two first check results when M is 24, and one first check result when M is 8. In this case, the code block processing apparatus can obtain three first check results. For another example, the code block processing apparatus may acquire one first check result when M is 32, one first check result when M is 24, and the like.

It is understood that for the specific implementation when M is equal to 16, 24, 32, 40, 48 or 56, reference may be made to the description when M is equal to 8, and detailed description is omitted here.

It can be understood that fig. 8a to 8d illustrate the code block processing method provided in the embodiment of the present application by taking a control code block as an example, but the code block processing method provided in the embodiment of the present application can also be applied to a data code block. In other words, the code block processing method provided by the embodiment of the present application may be applied to at least two first code blocks including data code blocks and/or control code blocks.

The second method,

10,18,26,34,42,50,58；

11,19,27,35,43,51,59；

12,20,28,36,44,52,60；

13,21,29,37,45,53,61；

14,22,30,38,46,54,62；

15,23,31,39,47,55,63；

16,24,32,40,48,56,64；

17,25,33,41,49,57,65。

11 th bit, 19 th bit, 27 th bit, 35 th bit, 43 th bit, 51 th bit, 59 th bit;

12 th bit, 20 th bit, 28 th bit, 36 th bit, 44 th bit, 52 th bit, 60 th bit;

13 th bit, 21 st bit, 29 th bit, 37 th bit, 45 th bit, 53 th bit, 61 th bit;

14 th bit, 22 nd bit, 30 th bit, 38 th bit, 46 th bit, 54 th bit, 62 th bit;

15 th bit, 23 th bit, 31 th bit, 39 th bit, 47 th bit, 55 th bit, 63 th bit;

16 th bit, 24 th bit, 32 th bit, 40 th bit, 48 th bit, 56 th bit, 64 th bit;

17 th bit, 25 th bit, 33 th bit, 41 th bit, 49 th bit, 57 th bit, 65 th bit;

18 th bit, 26 th bit, 34 th bit, 42 th bit, 50 th bit, 58 th bit, and 66 th bit.

It is understood that, in the first method and the second method, regarding the relationship between the bit position and the several bits, the third method and the fourth method are also applicable, and the details are not described below to avoid redundancy.

As shown in fig. 9a, 8 7-bit control codes "0000110" of LPI code blocks are transformed into 7 8 bits, and 7 bits can be obtained by padding the 7 bits of each row into 8 bits. The 7 8 bits are "01100000", "11000001", "10000011", "00000110", "00001100", "00011000", "00110000", respectively. It is understood that fig. 9a illustrates the bit positions 01111000, 0110000, … in order from small to large. In other words, in fig. 9a, when an LPI code block is included in the at least two first code blocks, 8 bits between

bit positions

2 and 9 in the LPI code block are 01111000 in order, 7 bits between bit positions 10 and 16 in the LPI code block are 0110000 in order, 7 bits between bit positions 17 and 23 in the LPI code block are 0110000 in order, and so on, bits corresponding to 64 bit positions in the LPI code block in order can be obtained. It is understood that fig. 10a and 11a are equally applicable to this description, and will not be described in detail below to avoid repetition.

Illustratively, the code block processing device checks the first column (i.e., bit positions 10,18,26,34,42,50,58) of each first code block to obtain a first check result; the second column (i.e. bit positions 11,19,27,35,43,51,59) of each first code block is checked to obtain a first check result, and so on, the code block processing device may obtain eight first check results. In other words, 7 bits with

bit positions

10,18,26,34,42,50,58 in each first code block may enter one monitoring section, 7 bits with

bit positions

11,19,27,35,43,51,59 in each first code block may enter another monitoring section, and so on, the code block processing apparatus may obtain eight monitoring codes for eight monitoring sections, one monitoring section corresponding to one monitoring code.

Further, the code block processing device may further obtain at least one third check result from the at least two first code blocks, and the check object of the at least one third check result includes 8 bits with bit positions between 2 and 9 in each first code block. I.e. 8 bits with bit positions between 2 and 9 per first code block, may enter the third surveillance zone so that the code block processing device may obtain the surveillance codes of this third surveillance zone.

Alternatively, taking the example that the control code block includes an LPI code block, as shown in fig. 9b, fig. 9b illustrates that the bit positions in the LPI code block are 00011110, 0000110, and … in order from small to large. In other words, in fig. 9b, when an LPI code block is included in the at least two first code blocks, 8 bits between

bit positions

2 and 9 in the LPI code block are 00011110 in order, 7 bits between bit positions 10 and 16 in the LPI code block are 0000110 in order, 7 bits between bit positions 17 and 23 in the LPI code block are 0000110 in order, and so on, 64 bits sequentially corresponding to bit positions in the LPI code block can be obtained. It is understood that fig. 10b and 11b are equally applicable to this description, and will not be described in detail below to avoid repetition.

Accordingly, when the control code block is an idle code block, the code block processing device may also obtain at least one third check result and eight first check results.

In the embodiment of the present application, although 8 bits corresponding to 0x1E and 7 bits corresponding to 0x06 are arranged differently in the first code block in fig. 9a and 9b, the bit positions of the M bits in the first code block obtained according to the above-described method (the 8 groups of M bits shown above) are the same. It is understood that, the corresponding relationship between each thread and the bit position in fig. 9a and 9b is not limited in the embodiments of the present application.

Thereby, the code block processing apparatus may obtain the 9 monitoring codes of the at least two first code blocks, i.e. the 8 first check results and the 1 third check result. It is understood that in the method shown in fig. 9a and 9b, the predetermined checking algorithm may be referred to as a BIP-9 checking algorithm. For the specific description of the preset checking algorithm, reference may be made to the descriptions in fig. 8a to 8d, and details thereof are not described here.

In one possible implementation, M may also be equal to 14, 21, 28, 35, 42, 49, or 56, etc. Where M is 14, the bit positions of the 14 bits in the first code block may include two groups of the eight groups of bit positions shown in method two; when M is 21, the bit positions of the 21 bits in the first code block may include three groups of eight groups of bit positions shown in method two; when M is 28, the bit positions of the 28 bits in the first code block may include four groups of the eight groups of bit positions shown in method two; when M is 35, the bit positions of 35 bits in the first code block may include five groups of the eight groups of bit positions shown in method two; when M is 42, the bit positions of 42 bits in the first code block may include six groups of eight groups of bit positions shown in method two; when M is 49, the bit positions of 49 bits in the first code block may include seven groups of the eight groups of bit positions shown in method two; when M is 56, the bit positions of 56 bits in the first code block may include eight groups of the eight groups of bit positions shown in method two.

For example, the code block processing device may obtain four first check results when M is 14, for example. For another example, the code block processing apparatus may further acquire two first check results when M is 21, and two first check results when M is 7. For another example, the code block processing apparatus may further acquire two first check results when M is 21, and one first check result when M is 14. For another example, the code block processing apparatus may also acquire two first check results when M is 28, and the like.

It is understood that for the specific implementation when M is equal to 14, 21, 28, 35, 42, 49 or 56, reference may be made to the description when M is equal to 7, and detailed description is omitted here. It is understood that the description of the values of M in the first and second methods are equally applicable to the third and fourth methods.

The third method,

In some implementations, M-5, bit positions of the M bits in the first code block include at least one of:

10,34,42,50,58；

27,35,43,51,59；

20,28,36,44,52；

13,21,29,37,45；

14,22,30,38,62；

15,23,31,55,63；

16,24,48,56,64；

17,41,49,57,65。

as shown in fig. 10a, the code block processing apparatus may check a part of bits (e.g., bit positions 10,34,42,50,58) in the first column of each first code block to obtain a first check result; partial bits (e.g. bit positions 27,35,43,51,59) in the second column of each first code block are checked to obtain first check results, and so on, the code block processing apparatus may obtain eight first check results.

Optionally, the check object of the first check result may further include 2n bits of the remaining 16 bits (bit positions are 18,26,11,19,12,60,53,61,46,54,39,47,32,40,25,33), where n is greater than or equal to 1, and n is less than or equal to 8. For example, the code block processing device checks the remaining 16 bits, obtaining a first check result. That is, the remaining 16 bits can enter a monitoring section to obtain a monitoring code. In this case, the code block processing apparatus may obtain 10 monitored codes of the at least two first code blocks, that is, the first check result when 8M is 5, the first check result when 1M is 16, and the at least one third check result. For another example, the code block processing device performs check on 8 bits of the remaining 16 bits to obtain a first check result. In this case, the code block processing apparatus may obtain 11 monitoring codes of the at least two first code blocks, that is, the first check result when 8M is 5, the first check result when 2M is 8, and the at least one third check result.

For another example, the code block processing device may further check 2 bits of the remaining 16 bits to obtain 8 first check results, that is, the check object of the first check result may further include 2 bits of the remaining 16 bits. Illustratively, M is 2, and the bit positions of the 2 bits in the remaining 16 bits in the first code block may include at least one of the following groups:

18,26；

11,19；

12,60；

53,61；

46,54；

39,47；

32,40；

25,33。

In this case, as shown in fig. 10a, the code block processing apparatus may obtain 17 monitored codes of at least two first code blocks, i.e., 16 first check results and 1 third check result, where the 16 first check results may be understood to include 8 first check results when M is 5 and 8 first check results when M is 2.

Alternatively, M may be equal to not only 5 but also 10, 15, 20, 25, 30, 35 or 40. Where, when M is 10, the bit positions of the 10 bits in the first code block may include two groups of eight groups of bit positions shown in method three (eight groups of bit positions shown when M is 5); when M is 15, the bit positions of the 15 bits in the first code block may include three groups of eight groups of bit positions shown in method three; when M is 20, the bit positions of the 20 bits in the first code block may include four groups of eight groups of bit positions shown in method three; when M is 25, the bit positions of 25 bits in the first code block may include five groups of the eight groups of bit positions shown in method three; when M is 30, the bit positions of the 30 bits in the first code block may include six groups of eight groups of bit positions shown in method three; when M is 35, the bit positions of the 35 bits in the first code block may include seven groups of the eight groups of bit positions shown in method three; when M is 40, the bit positions of 40 bits in the first code block may include eight groups of the eight groups of bit positions shown in method three.

Alternatively, M may be equal to not only 2 but also 4, 6, 8, 10, 12, 14 or 16. When M is 4, the bit positions of the 4 bits in the first code block may include two groups of eight groups of bit positions shown by method three (eight groups of bit positions shown when M is 2); when M is 6, the bit positions of the 6 bits in the first code block may include three groups of eight groups of bit positions shown in method three; when M is 8, the bit positions of the 8 bits in the first code block may include four groups of eight groups of bit positions shown in method three; when M is 10, the bit positions of the 10 bits in the first code block may include five groups of the eight groups of bit positions shown in method three; when M is 12, the bit positions of the 12 bits in the first code block may include six groups of eight groups of bit positions shown in method three; when M is 14, the bit positions of the 14 bits in the first code block may include seven groups of the eight groups of bit positions shown in method three; when M is 16, the bit positions of the 16 bits in the first code block may include eight groups of the eight groups of bit positions shown in method three.

In other implementations, M is 2, and the bit positions of the M bits in the first code block include at least one of:

18,26；

11,19；

12,60；

53,61；

46,54；

39,47；

32,40；

25,33。

In this case, the code block processing apparatus can obtain 8 first check results. For how the code block processing device obtains the 8 first check results, reference may be made to the above-described embodiments, which are not described in detail here.

Optionally, the check object of the first check result may further include one or more bits of the remaining 40 bits. For example, the check object of the first check result may further include one bit of the remaining 40 bits, in which case the code block processing device may obtain 8+ 40-48 first check results and at least one third check result. For another example, the check object of the first check result may further include the remaining 40 bits, in which case the code block processing device may obtain 9 first check results and at least one third check result.

For example, the check object of the first check result may further include 5 bits of the remaining 40 bits, for example, M ═ 5, and bit positions of the 5 bits of the remaining 40 bits in the first code block may include at least one of the following groups:

10,34,42,50,58；

27,35,43,51,59；

20,28,36,44,52；

13,21,29,37,45；

14,22,30,38,62；

15,23,31,55,63；

16,24,48,56,64；

17,41,49,57,65。

in this case, the code block processing device may obtain 16 first check results and at least one third check result. It is to be understood that for a detailed description of embodiments herein, reference may be made to other embodiments without departing from the spirit or scope of the present disclosure.

It is understood that fig. 10a is illustrated by way of example that 7 bits between bit positions 10 and 16 in an LPI code block are 0110000 in sequence. In still other implementations, as shown in fig. 10b, when an LPI code block is included in the at least two first code blocks, where the 7 bits with bit positions between 10 and 16 are 0000110 in sequence, M is 5, and the bit positions of the M bits in the first code block include at least one of the following groups:

10,18,26,34,58；

11,19,27,51,59；

12,20,44,52,60；

13,37,45,53,61；

30,38,46,54,62；

23,31,39,47,55

16,24,32,40,48；

17,25,33,41, 65; alternatively, the first and second electrodes may be,

42,50；

35,43；

28,36；

21,29；

14,22；

15,63；

56,64；

49,57。

it is understood that for the specific description of fig. 10b, reference may be made to fig. 10a, fig. 8d, fig. 9b, etc., and detailed description thereof is omitted here.

It is understood that in the method shown in fig. 10a and 10b, the predetermined verification algorithm may be referred to as a BIP-17 verification algorithm.

The fourth method,

10,13,14,15,16；

17,20,21,22,23；

24,27,28,29,30；

31,34,35,36,37；

38,41,42,43,44；

45,48,49,50,51；

52,55,56,57,58；

59,62,63,64,65。

as shown in fig. 11a, the 8 7-bit control code "0000110" of the LPI code block is transformed into 7 8 bits, such as 5 8 bits of "00000000" and 2 8 bits of "11111111".

The code block processing device checks partial bits (for example, bit positions of 10,13,14,15,16) in the first column of each first code block to obtain a first check result; by analogy, the code block processing device may obtain 8 first check results.

Optionally, the check object of the first check result may further include at least three bits of the remaining 16 bits (11, 12; 18, 19; 25, 26; 32, 33; 39, 40; 46, 47; 53, 54; 60, 61). It is understood that for such implementation, reference may be made to other embodiments, such as may be found in the detailed description of fig. 10a, etc., and will not be described in detail herein.

Optionally, the code block processing apparatus may further obtain at least one second check-up result according to the at least two first code blocks, where check-up objects of the second check-up result include N bits of each first code block; wherein N is 2, and bit positions of the N bits in the first code block include at least one of:

11,12；

18,19；

25,26；

32,33；

39,40；

46,47；

53,54；

60,61。

it is understood that fig. 11a illustrates that 7 bits between bit positions 10 and 16 in an LPI code block are 0110000 in sequence. In further implementations, as shown in fig. 11b, when an LPI code block is included in the at least two first code blocks, where 7 bits between 10 and 16 in bit position are 0000110 in sequence, M is 5, and bit positions of the M bits in the first code block include at least one of the following groups:

10,11,12,13,16；

17,18,19,20,23；

24,25,26,27,30；

31,32,33,34,37；

38,39,40,41,44；

45,46,47,48,51；

52,53,54,55,58；

59,60,61,62,65。

14,15；

21,22；

28,29；

35,36；

42,43；

49,50；

56,57；

63,64。

As shown in fig. 11a and 11b, the code block processing device may obtain 8 first check results when M is 5, 8 second check results when N is 2, and at least one third check result. In this case, the preset check algorithm may also be referred to as a BIP-17 check algorithm.

It is understood that the value of M in method four can be referred to the description of method three, and is not described in detail here.

For the fourth method, the first verification result and the second verification result may be obtained by a preset verification algorithm, where the preset verification algorithm may be used to ensure that the first verification result determined by the receiving end is consistent with the fourth verification result determined by the receiving end under the condition that the control code block is added or deleted in the at least two first code blocks; and/or the preset check algorithm is used for ensuring that the second check result determined by the receiving end is consistent with the fifth check result determined by the receiving end under the condition that the control code block is not added or deleted in the at least two first code blocks.

In this embodiment of the application, the third verification result may also be obtained by a preset verification algorithm, and the preset verification algorithm may be further configured to ensure that the third verification result determined by the receiving end is consistent with the sixth verification result determined by the receiving end under the condition that the control code block is not added or deleted in the at least two first code blocks. For the specific description of the fifth verification result and the sixth verification result, reference may be made to the description of the fourth verification result above, and details thereof are not described here.

It is understood that the check-up objects of the at least one third check-up result shown above are 8 bits with bit positions between 2 and 9 in each first code block. However, in a specific implementation, the check object of the third check result may also be any one or more bits with bit positions between 2 and 9 in each first code block. For example, the check object of the third check result may be one bit with a bit position between 2 and 9 in each first code block. In this case, the code block processing apparatus can obtain 8 third check results. For another example, the check object of the third check result may also be two bits with bit positions between 2 and 9 in each first code block. In this case, the code block processing apparatus can obtain 4 third check results. It can be understood that even if the check object of the third check result is two bits with bit positions between 2 and 9 in each first code block, there may be more methods how the bit positions of the two bits are distributed, and therefore, the embodiment of the present application does not limit the specific bit positions of the two bits.

For another example, the check object of the third check result may also be 4 bits with bit positions between 2 and 9 in each first code block. It can be understood that, for whether the number of bits included in the check object of each third check result is the same, the embodiment of the present application is not limited.

For example, the verification object of the third verification result may include at least one of the following groups:

2,4,6,8；3,5,7,9。

alternatively, the verification object of the third verification result may include at least one of the following groups:

2；3,4,5,6,7,8,9。

2,3,4,5,6；7,8,9。

2,3,4,9；5,6,7,8。

2,3,4；5,6,7,8,9。

it is to be understood that the above are exemplary only and are not to be construed as limiting the embodiments of the present application.

In order to more vividly understand the method provided by the present application, the method provided by the present application will be exemplified by a transmitting end and a receiving end.

Fig. 12a is a schematic flowchart of a code block processing method provided in an embodiment of the present application, and as shown in fig. 12a, the method includes:

1201. the transmitting end obtains 16k first code blocks, and determines at least one seventh check result according to the 16k first code blocks.

The check object of the seventh check result includes M bits in each of the 16k first code blocks.

It can be understood that, in the embodiment of the present application, how the transmitting end obtains the 16k first code blocks is not limited. Illustratively, the transmitting end may generate the 16k first code blocks; alternatively, the transmitting end may also obtain the 16k first code blocks and the like from other nodes.

1202. The transmitting end transmits a first boundary code block to the receiving end, wherein the first boundary code block is used for distinguishing 16k first code blocks transmitted subsequently.

1203. The transmitting end transmits 16k first code blocks to the receiving end.

For example, the seventh check result determined by the sending end may be understood as: in fig. 3a, the sender inserts a seventh verification result in the BIP results included in the OAM information inserted in the MTN tunnel termination layer. The 16k first code blocks sent by the sending end to the receiving end can be understood as follows: when the sending end carries out the BIP check, the sending end obtains the checking object of the BIP result.

It can be understood that, since the sending end needs to perform rate adaptation between the MTN tunnel connection layer and the MTN segment layer adaptation layer, the number of the first code blocks actually sent by the sending end to the receiving end may be greater than 16k, less than 16k, or equal to 16 k. But the check object of the at least one seventh check result transmitted by the transmitting end to the receiving end includes M bits in each of the 16k first code blocks.

1204. And the sending end sends a second boundary code block to the receiving end, wherein the second boundary code block comprises at least one seventh check result and is used for distinguishing the sent 16k first code blocks.

In this embodiment, the boundary code blocks (including the first boundary code block or the second boundary code block, etc.) may include a termination code block (T code block), a start code block (S code block), a sequence code block (sequential set, O code block), or a custom code block, which is not limited in this embodiment. In the embodiment of the present application, the first boundary code block and the second boundary code block may be used to define the 16k first code blocks. The 16k first code blocks may not include the first boundary code block and the second boundary code block, or the 16k first code blocks may further include the first boundary code block and/or the second boundary code block, and the relationship between the 16k first code blocks and the first boundary code block and the second boundary code block is not limited in the embodiment of the present application. For example, when the 16k first code blocks include a first boundary code block and/or a second boundary code block, the check object of the at least one seventh check result may further include M bits with bit positions between 10 and 65 in the first boundary code block and/or the second boundary code block. Therefore, the embodiment of the present application does not limit whether the check object of the BIP result includes the first boundary code block and/or the second boundary code block.

The second boundary code block may further include an OAM code block, where the OAM code block includes the at least one seventh check result, or may be understood as the OAM code block carries the at least one seventh check result.

For example, in fig. 3c, the transmitting end needs to determine a BIP result, and a check object of the BIP result may include 16k first code blocks sent by the transmitting end. I.e. the check object of the BIP result comprises e.g. 16k first code blocks comprised in the check-up interval in fig. 3 c. Therefore, to distinguish the i-th group of 16k first code blocks from the i + 1-th group of 16k first code blocks transmitted by the transmitting end, the transmitting end may transmit at least two boundary code blocks (e.g., may include a first boundary code block and a second boundary code block) to the receiving end. The receiving end can know the check object of the BIP result determined by the sending end through the at least two boundary code blocks, and further, the receiving end can determine whether the control code block is added or deleted in the 16k first code blocks according to the at least two boundary code blocks.

Illustratively, the step 1204 is illustrated as including at least one seventh verification result in the second bordered code block, in other words, including the BIP result (e.g., including at least one seventh verification result and at least one ninth verification result, etc.) in the second bordered code block. Optionally, as shown in fig. 12b, the check-up interval between the first boundary code block and the second boundary code block may include 16k first code blocks, and the second boundary code block includes a BIP result, and the check-up object of the BIP result includes the 16k first code blocks. Further, the receiving end receives 16k + n first code blocks, as shown in fig. 12c, and the receiving end may learn the check objects of the BIP result, such as 16k +2 first code blocks, according to the first boundary code block and the second boundary code block. It is understood that, in fig. 12b, the third time when the transmitting end transmits the second boundary code block may be equal to the fourth time when the transmitting end transmits the BIP result. Similarly, in fig. 12c, the fifth time when the receiving end receives the second boundary code block is equal to the sixth time when the receiving end receives the BIP result.

Alternatively, the BIP results of the 16k first code blocks included in the check interval shown in fig. 12b may also be included in the third boundary code block, and so on. In this case, the third time when the transmitting end transmits the second boundary code block is earlier than the fourth time when the transmitting end transmits the BIP result. Meanwhile, the fifth time when the receiving end receives the second boundary code block is earlier than the sixth time when the receiving end receives the BIP result. That is, the BIP result may also be included in a third boundary code block, which is a boundary code block following the second boundary code block, the second boundary code block and the third boundary code block being used to define another set of 16k first code blocks following the 16k first code blocks.

Alternatively, the BIP result may be included in the first boundary code block.

Alternatively, as shown in fig. 12d, the BIP result may be included in a jth first code block after the first boundary code block or the second boundary code block, for example, the jth first code block may include the first code block or the second first code block. Similarly, the BIP result may be included in the jth first code block following the third boundary code block. When the BIP result is included in the jth first code block after the first boundary code block, the third time when the transmitting end transmits the second boundary code block is later than the fourth time when the transmitting end transmits the BIP result. When the BIP result is included in the second boundary code block or the jth first code block after the third boundary code block, the third time when the transmitting end transmits the second boundary code block is earlier than the fourth time when the transmitting end transmits the BIP result. Similarly, the fifth time when the receiving end receives the second boundary code block is earlier than the sixth time when the receiving end receives the BIP result.

Alternatively, as shown in fig. 12e, the BIP result may be included in a jth first code block before the first boundary code block or the second boundary code block, and the jth first code block may include the first code block or the second first code block, and so on. In this case, the third time at which the transmitting end transmits the second boundary code block is later than the fourth time at which the transmitting end transmits the BIP result. Similarly, the fifth time when the receiving end receives the second boundary code block is later than the sixth time when the receiving end receives the BIP result. Similarly, the BIP result may also be included in the jth first code block before the third boundary code block or the fourth boundary code block, and the like, which is not limited in this embodiment of the present application.

Optionally, the BIP result may also be included in the jth first code block before the third boundary code block.

It is understood that the above description of the BIP result and the boundary code block is equally applicable to fig. 12f, and is not repeated herein.

1205. The receiving end receives a first boundary code block.

1206. The receiving end receives the 16k + n first code blocks, and determines at least one first check result according to the 16k + n first code blocks, wherein n is a positive integer, 0 or a negative integer.

It can be understood that, in the process of sending the first code block to the receiving end, other intermediate nodes may also be passed through; meanwhile, the sending end, the intermediate node or the receiving end may perform rate adaptation, so the specific value of n is not limited in the embodiment of the present application.

It is understood that the specific implementation manner of the receiving end obtaining the first verification result can refer to the above, and is not described in detail here.

1207. And the receiving end receives the second boundary code block and obtains at least one seventh check result included in the second boundary code block.

For example, during the process of receiving 16k first code blocks, the receiving end may check the received first code blocks at the same time. Then, in case the receiving end receives the second border code block, the check results, e.g., at least one first check result, for the 16k first code blocks may be obtained.

1208. And the receiving end compares the at least one seventh check result with the at least one first check result to obtain the error code conditions of the 16k + n first code blocks.

For example, if the first check result and the seventh check result obtained by the receiving end are identical, it indicates that there is no error in at least two first code blocks. For another example, if the first check result and the seventh check result obtained by the receiving end are not consistent, it indicates that there is an error in at least two first code blocks.

It is understood that, in the above description of the verification results of the boundary code block and the 16k first code blocks, the boundary code block and the BIP result are taken as examples, but the embodiment of the present application does not limit the verification results included in the BIP result. For example, the BIP result may include at least one seventh verification result and at least one ninth verification result. For another example, the BIP result may include at least one seventh verification result, at least one eighth verification result, and at least one ninth verification result. For example, the second border code block may further include at least one eighth check result, and the check object of the eighth check result includes N bits in each of the 16k first code blocks. In this case, the receiving end may further obtain at least one second check result from the 16k + n first code blocks. For example, the second border code block may further include at least one ninth check result, and the check object of the ninth check result includes 8 bits between bit positions 2 to 9 in each of the 16k first code blocks. In this case, the receiving end may further obtain at least one third check result according to the 16k + n first code blocks.

In other words, the receiving end may further compare the at least one eighth check result with the at least one second check result, and/or compare the at least one ninth check result with the at least one third check result, to obtain error conditions of the 16k + n first code blocks. It is understood that fig. 12f is equally applicable to this description, and is not detailed in fig. 12f to avoid redundancy.

Fig. 12f is a schematic flowchart of a code block processing method provided in an embodiment of the present application, and as shown in fig. 12f, the method includes:

1211. the transmitting end obtains 16k first code blocks, and determines at least one first check result according to the 16k first code blocks.

The check-object of the first check-result includes M bits of each of the 16k first code blocks.

1212. The transmitting end transmits a first boundary code block to the receiving end, wherein the first boundary code block is used for distinguishing 16k first code blocks transmitted subsequently.

1213. The transmitting end transmits 16k first code blocks to the receiving end.

1214. The sending end sends a second boundary code block to the receiving end, and the second boundary code block comprises at least one first check result.

1215. The receiving end receives a first boundary code block.

1216. The receiving end receives the 16k + n first code blocks, and determines at least one seventh check result according to the 16k + n first code blocks.

1217. And the receiving end receives the second boundary code block and obtains at least one first check result included in the second boundary code block.

1218. And the receiving end compares the at least one seventh check result with the at least one first check result to obtain the error code conditions of the 16k + n first code blocks.

It is understood that for the specific description of the first boundary code block and the second boundary code block, reference may be made to fig. 12a, and a detailed description thereof is omitted here. For example, the transmitting end may also transmit the second boundary code block at the first time and transmit the 16k first code blocks at the second time. Accordingly, the receiving end receives the second boundary code block at the seventh time and 16k + n first code blocks at the eighth time. For example, as in fig. 12b or 12c, the first time may be equal to the second time. For another example, as shown in fig. 12d, the first time may be earlier than the second time. For another example, as shown in fig. 12e, the first time may be later than the second time. It is understood that for the specific description of the first time and the second time, reference may be made to the third time and the fourth time, which will not be described in detail herein.

It is understood that for the other description of fig. 12f, reference may be made to fig. 12a to 12e, which are not described in detail here.

In various embodiments shown in the present application, the at least two first code blocks or the 16k first code blocks may include a control code block in addition to the data code block, and the control code block may include the LPI code block or the idle code block, etc. described above.

In some implementations, the at least two first code blocks or the 16k first code blocks may be understood as all of the T code blocks between the first boundary code block and the second boundary code block, T being greater than or equal to 2. For example, the check-object of the first check-up result may include M bits in each of the at least two first code blocks or the 16k first code blocks. In other words, the code block processing device may obtain at least one first check result according to at least two first code blocks or 16k first code blocks, and the code processing device may include a transmitting end, a receiving end, a PE node, or the like. For example, the check object of the first check result in fig. 12a and/or fig. 12b may include 16k first code blocks between the first boundary code block and the second boundary code block. In the embodiment of the present application, the 16k first code blocks between the first boundary code block and the second boundary code block may be understood as: the 16k first code blocks do not include a first boundary code block and a second boundary code block; alternatively, the 16k first code blocks include a first boundary code block and/or a second boundary code block.

In other implementations, the at least two first code blocks or the 16k first code blocks may also be understood as a portion of T code blocks between the first boundary code block and the second boundary code block, T being greater than or equal to 2. If there are 16k + n1 code blocks between the first border code block and the second border code block, the code block processing device may obtain at least one first check-up result from a portion of the 16k + n1 code blocks, e.g., the 16k first code blocks, with n1 being greater than or equal to 1. For example, the check-object of the first check-up result may not include a special code block (or may also be referred to as a second code block) among the T code blocks between the first border code block and the second border code block. In this case, for example, when the transmitting end determines the BIP result, a special code block of the T code blocks between the first boundary code block and the second boundary code block may be excluded, and at least one first check result may be obtained from the remaining first code block. Meanwhile, when determining the BIP result, the receiving end also needs to exclude a special code block from the T code blocks between the first boundary code block and the second boundary code block. In other words, when the sender and the receiver may agree in advance to determine the BIP result, the check object of the BIP result may not include the special code block. Illustratively, the special code block may include, for example, an idle code block, an LPI code block, an error code block, a local error code block, a remote error code block, or the like, and the specific code pattern of the special code block is not limited in the embodiments of the present application.

It can be understood that the above-illustrated embodiments have respective emphasis, and the implementation manner not described in detail in one embodiment may refer to other embodiments, which are not described in detail here. Furthermore, the various embodiments described herein may be implemented as stand-alone solutions or combined in accordance with inherent logic and are intended to fall within the scope of the present application.

The code block processing apparatus provided by the embodiment of the present application is described below.

Fig. 13 is a schematic structural diagram of a code block processing apparatus provided in an embodiment of the present application, which may be used to perform the operations shown in fig. 6; alternatively, the code block processing device may also be configured to perform the operations performed by the transmitting end or the receiving end in fig. 12a and 12 f. Illustratively, the code block processing device may include not only a transmitting end, a receiving end, but also a PE node and the like.

As shown in fig. 13, the code block processing apparatus includes a processing unit 1301 and a transceiving unit 1302. Wherein the content of the first and second substances,

a processing unit 1301, configured to obtain at least two first code blocks, where the first code block is a P1B/P2B code block, P1 represents the number of payload bits of the first code block, P2 represents the total number of bits of the first code block, and P2-P1 represent the number of bits of a sync header of the first code block;

The processing unit 1301 is further configured to obtain at least one first check result according to the at least two first code blocks, where a check object of the first check result includes M bits in each first code block; wherein the M bits are M bits with bit positions between 10 and 65 in the first code block, and the starting bit position of the first code block is 0; and at least two bits of the M bits are not adjacent in bit position in the first code block.

In this embodiment of the application, the processing unit 1301 may further obtain at least two first code blocks through the transceiver unit 1302.

In one possible implementation, the processing unit 1301 is specifically configured to, when M is 8, obtain seven first check results according to at least two first code blocks; or when M is 7, eight first check results are obtained from the at least two first code blocks.

In a possible implementation manner, the processing unit 1301 is specifically configured to obtain sixteen first check results according to the at least two first code blocks, where the sixteen first check results include eight first check results when M is 5 and eight first check results when M is 2.

In a possible implementation manner, the processing unit 1301 is further configured to obtain at least one second check-up result according to at least two first code blocks, and a check-up object of the second check-up result includes N bits in each first code block.

In a possible implementation manner, the first check result and/or the second check result are obtained by a preset check algorithm, where the preset check algorithm is used to ensure that the first check result determined by the code block processing device is consistent with the fourth check result determined by the code block processing device under the condition that the control code block is added or deleted in the at least two first code blocks; and/or the preset check-up algorithm is used for ensuring that the second check-up result determined by the code block processing device is consistent with the fifth check-up result determined by the code block processing device under the condition that the control code block is not added or deleted in the at least two first code blocks.

In one possible implementation, P1-64 and P2-66.

In a possible implementation, the transceiver 1302 is configured to transmit at least two first code blocks; and sending at least one first check result.

In a possible implementation manner, the transceiver 1302 is configured to receive at least one seventh check result of the at least two first code blocks, where a check object of the seventh check result includes M bits of each of the at least two first code blocks;

The processing unit 1301 is further configured to compare the at least one first check result with the at least one seventh check result to obtain error conditions of the at least two first code blocks.

It is understood that specific descriptions of the M bits and the N bits, and specific descriptions of the first check result, the second check result, and the third check result may refer to the detailed descriptions of fig. 7a to 11b, and detailed descriptions thereof are omitted here.

It is to be understood that when the code block processing device shown in fig. 13 is a code block processing device or a component of a code block processing device implementing the above functions, the processing unit 1301 can be one or more processors, the transceiver unit 1302 can be a transceiver, or the transceiver unit 1302 can also be a transmitting unit and a receiving unit, the transmitting unit can be a transmitter, the receiving unit can be a receiver, and the transmitting unit and the receiving unit are integrated into one device, such as a transceiver.

When the code block processing device is a circuit system such as a chip or an integrated circuit, the processing unit 1301 can be one or more processors, and the transceiving unit 1302 can be an input/output interface, also referred to as a communication interface, or an interface circuit, or an interface, and the like. Or the transceiving unit 1302 may also be a transmitting unit and a receiving unit, the transmitting unit may be an output interface, the receiving unit may be an input interface, and the transmitting unit and the receiving unit are integrated into one unit, such as an input-output interface.

In some implementations, the code block processing apparatus shown in fig. 13 may be the code block processing apparatus or a component of the code block processing apparatus in the various method embodiments described above that implements the above-described functionality. In this case, the transceiver 1302 may be implemented by a transceiver, and the processing unit 1301 may be implemented by a processor. As shown in fig. 14, the code block processing device 140 includes one or more processors 1420 and a transceiver 1410. The processor and transceiver may be configured to perform the functions or operations performed by the code block processing device described above, and so on. Alternatively, the processor and the transceiver may be further configured to perform functions or operations performed by the transmitting end or the receiving end.

In this case, the functions or operations performed by the transceiver 1410 and/or the processor 1420, etc. may be referred to fig. 13, and will not be described in detail here.

In various implementations of the code block processing device shown in fig. 14, a transceiver may include a receiver to perform a function (or operation) of receiving and a transmitter to perform a function (or operation) of transmitting. And transceivers for communicating with other devices/apparatuses over a transmission medium. Processor 1420 receives and transmits data and/or signaling using transceiver 1410 and is configured to implement the corresponding method described in fig. 6, fig. 12a, or fig. 12f in the above-described method embodiments.

Optionally, the code block processing apparatus 140 may also include one or more memories 1430 for storing program instructions and/or data. A memory 1430 is coupled to the processor 1420. The coupling in the embodiments of the present application is an indirect coupling or a communication connection between devices, units or modules, and may be an electrical, mechanical or other form for information interaction between the devices, units or modules. The processor 1420 may operate in conjunction with the memory 1430. Processor 1420 may execute program instructions stored in memory 1430. Optionally, at least one of the one or more memories may be included in the processor.

The specific connection medium between the transceiver 1410, the processor 1420 and the memory 1430 is not limited in this embodiment. In fig. 14, the memory 1430, the processor 1420 and the transceiver 1410 are connected by a bus 1440, the bus is shown by a thick line in fig. 14, and the connection manner between other components is only for illustrative purposes and is not limited thereto. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown in FIG. 14, but this is not intended to represent only one bus or type of bus.

In the embodiments of the present application, the processor may be a general-purpose processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, or the like, which may implement or execute the methods, steps, and logic blocks disclosed in the embodiments of the present application. A general purpose processor may be a microprocessor or any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present application may be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules in a processor.

It is understood that the code block processing apparatus shown in the embodiment of the present application may further have more components and the like than those shown in fig. 14, and the embodiment of the present application does not limit this.

It will be appreciated that the methods performed by the processor and transceiver shown above are merely examples, and reference may be made to the methods described above for the steps specifically performed by the processor and transceiver.

In other implementations, the code block processing apparatus shown in fig. 13 can be circuitry. In this case, the processing unit 1301 may be implemented by a processing circuit, and the transmitting/receiving unit 1302 may be implemented by an interface circuit. As shown in fig. 15, the circuitry may include processing circuitry 1501 and interface circuitry 1502. The processing circuit 1501 may be a chip, a logic circuit, an integrated circuit or a system on chip (SoC) chip, and the like, and the interface circuit 1502 may be a communication interface, an input/output interface, and the like.

For example, the processing circuit 1501 is configured to obtain at least two first code blocks, where the first code block is a P1B/P2B code block, P1 represents the number of payload bits of the first code block, P2 represents the total number of bits of the first code block, and P2-P1 represent the number of bits of a sync header of the first code block;

the processing circuit 1501 is further configured to obtain at least one first check result from the at least two first code blocks, where a check object of the first check result includes M bits in each first code block; wherein the M bits are M bits with bit positions between 10 and 65 in the first code block, and the starting bit position of the first code block is 0; and at least two bits of the M bits are not adjacent in bit position in the first code block.

In this embodiment, the processing circuit 1501 may further obtain at least two first code blocks through the interface circuit 1502.

In one possible implementation, the processing circuit 1501 is specifically configured to obtain seven first check results from at least two first code blocks when M is 8; or when M is 7, eight first check results are obtained from the at least two first code blocks.

In one possible implementation, the processing circuit 1501 is specifically configured to obtain sixteen first check results from at least two first code blocks, where the sixteen first check results include eight first check results when M is 5 and eight first check results when M is 2.

In a possible implementation, the processing circuit 1501 is further configured to obtain at least one second check-up result according to at least two first code blocks, and a check-up object of the second check-up result includes N bits in each first code block.

In one possible implementation, P1-64 and P2-66.

In one possible implementation, the interface circuit 1502 is configured to output at least two first code blocks; and outputting at least one first check result.

In a possible implementation manner, the interface circuit 1502 is configured to obtain at least one seventh check result of the at least two first code blocks, where a check object of the seventh check result includes M bits of each of the at least two first code blocks;

the processing circuit 1501 is further configured to compare the at least one first check result with the at least one seventh check result to obtain error conditions of the at least two first code blocks.

In the embodiments of the present application, the processing circuit may be a general-purpose processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, or the like, and may implement or execute the methods, steps, and logic blocks disclosed in the embodiments of the present application.

It will be appreciated that the methods performed by the interface circuit and the processing circuit shown above are merely examples, and reference may be made to the methods described above for the steps specifically performed by the interface circuit and the processing circuit.

Fig. 16 is a code block processing system provided in an embodiment of the present application, and as shown in fig. 16, the code block processing system may include a transmitting end and a receiving end. The transmitting end may be configured to perform the method performed by the code block processing device in fig. 6, and the receiving end may also be configured to perform the method performed by the code block processing device in fig. 6. Alternatively, the transmitting end may be further configured to execute the method performed by the transmitting end in fig. 12a and/or fig. 12f, and the receiving end may be further configured to execute the method performed by the receiving end in fig. 12a and/or fig. 12 f.

Optionally, the code block processing system may further include an intermediate node, which may include a PE node or a P node, etc. Illustratively, the PE node may be configured to perform the method performed by the code block processing device of fig. 6.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implementing, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may also be an electric, mechanical or other form of connection.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the technical effects of the solutions provided by the embodiments of the present application.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may essentially or partially contribute to the prior art, or all or part of the technical solution may be embodied in the form of a software product stored in a readable storage medium, and including several instructions for causing a computer device (which may be a personal computer, a server, or a code block processing device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned readable storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a read-only memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

In addition, the present application also provides a computer program for implementing the operations and/or processes performed by the code block processing device in the method for configuring routing domain identification provided by the present application.

Embodiments of the present application also provide a computer-readable storage medium having stored therein computer code, which, when executed on a computer, causes the computer to perform the operations and/or processes performed by the code block processing device in the method for configuring routing domain identities provided by the present application.

Embodiments of the present application also provide a computer program product, which includes computer code or a computer program that, when run on a computer, causes operations and/or processes performed by a code block processing device in a method of configuring routing domain identification provided by the present application to be performed.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A code block processing method, the method comprising:

obtaining at least two first code blocks, wherein the first code blocks are P1B/P2B code blocks, the P1 represents the number of payload bits of the first code blocks, the P2 represents the total number of bits of the first code blocks, and the P2-P1 represent the number of sync header bits of the first code blocks;

obtaining at least one first check-up result according to the at least two first code blocks, where a check-up object of the first check-up result includes M bits in each of the first code blocks, the M bits are M bits with bit positions between 10 and 65 in the first code block, a starting bit position of the first code block is 0, and bit positions of at least two bits in the M bits in the first code block are not adjacent.

2. The method of claim 1, wherein M-8, and wherein bit positions of the M bits in the first code block comprise at least one of:

10,17,24,31,38,45,52,59；

11,18,25,32,39,46,53,60；

12,19,26,33,40,47,54,61；

13,20,27,34,41,48,55,62；

14,21,28,35,42,49,56,63；

15,22,29,36,43,50,57,64；

the bit positions of the M bits in the first code block include at least one of:

10,18,26,34,42,50,58；

11,19,27,35,43,51,59；

12,20,28,36,44,52,60；

13,21,29,37,45,53,61；

14,22,30,38,46,54,62；

15,23,31,39,47,55,63；

16,24,32,40,48,56,64；

17,25,33,41,49,57,65。

3. the method of claim 2, wherein the obtaining at least one first check-up result from the at least two first code blocks comprises:

When M is 8, acquiring seven first check results according to the at least two first code blocks; alternatively, the first and second electrodes may be,

when M is 7, eight first check results are obtained according to the at least two first code blocks.

4. The method of claim 1, wherein M-5, and wherein bit positions of the M bits in the first code block comprise at least one of:

10,34,42,50,58；

27,35,43,51,59；

20,28,36,44,52；

13,21,29,37,45；

14,22,30,38,62；

15,23,31,55,63；

16,24,48,56,64；

17,41,49,57, 65; alternatively, the first and second electrodes may be,

m-2, bit positions of the M bits in the first code block including at least one of:

18,26；

11,19；

12,60；

53,61；

46,54；

39,47；

32,40；

25,33。

5. the method of claim 4, wherein the obtaining at least one first check-up result from the at least two first code blocks comprises:

and acquiring sixteen first check results according to the at least two first code blocks, where the sixteen first check results include eight first check results when M is 5 and eight first check results when M is 2.

6. The method of claim 1, wherein M-5, and wherein bit positions of the M bits in the first code block comprise at least one of:

10,13,14,15,16；

17,20,21,22,23；

24,27,28,29,30；

31,34,35,36,37；

38,41,42,43,44；

45,48,49,50,51；

52,55,56,57,58；

59,62,63,64,65。

7. the method of claim 6, further comprising:

obtaining at least one second check-up result according to the at least two first code blocks, wherein a check-up target of the second check-up result includes N bits in each of the first code blocks, where N is 2, and bit positions of the N bits in the first code blocks include at least one of:

11,12；

18,19；

25,26；

32,33；

39,40；

46,47；

53,54；

60,61。

8. The method according to any of claims 1-7, wherein the first check result and/or the second check result are obtained by a pre-arranged check algorithm, which is configured to ensure that the first check result determined by a receiving end in case of adding or deleting a control code block in the at least two first code blocks is identical to a fourth check result determined by the receiving end in case of not adding or deleting the control code block in the at least two first code blocks; and/or the preset check algorithm is configured to ensure that the second check result determined by the receiving end is consistent with a fifth check result determined by the receiving end without adding or deleting the control code block in the at least two first code blocks.

9. The method of claim 8, wherein the control code blocks comprise idle code blocks and/or low power code blocks.

10. The method according to any one of claims 1-9, wherein P1-64 and P2-66.

11. The method according to any of claims 1-10, wherein after the obtaining at least two first code blocks, the method further comprises:

Transmitting the at least two first code blocks;

after obtaining at least one first check result according to the at least two first code blocks, the method further includes:

and sending the at least one first check result.

12. The method according to any one of claims 1-10, further comprising:

receiving at least one seventh check-out result of at least two first code blocks, a check-out object of the seventh check-out result comprising M bits of each of the at least two first code blocks;

and comparing the at least one first check result with the at least one seventh check result to obtain the error conditions of the at least two first code blocks.

13. A code block processing apparatus, characterized in that the apparatus comprises:

a processor configured to obtain at least two first code blocks, where the first code block is a P1B/P2B code block, the P1 represents the number of payload bits of the first code block, the P2 represents the total number of bits of the first code block, and the P2-P1 represent the number of bits of a sync header of the first code block;

the processor is further configured to obtain at least one first check result according to the at least two first code blocks, where a check object of the first check result includes M bits in each of the first code blocks, the M bits are M bits with bit positions between 10 and 65 in the first code block, a starting bit position of the first code block is 0, and bit positions of at least two bits of the M bits in the first code block are not adjacent to each other.

14. The apparatus of claim 13, wherein M-8, bit positions of the M bits in the first code block comprise at least one of:

10,17,24,31,38,45,52,59；

11,18,25,32,39,46,53,60；

12,19,26,33,40,47,54,61；

13,20,27,34,41,48,55,62；

14,21,28,35,42,49,56,63；

15,22,29,36,43,50,57,64；

10,18,26,34,42,50,58；

11,19,27,35,43,51,59；

12,20,28,36,44,52,60；

13,21,29,37,45,53,61；

14,22,30,38,46,54,62；

15,23,31,39,47,55,63；

16,24,32,40,48,56,64；

17,25,33,41,49,57,65。

15. the apparatus of claim 14,

the processor is specifically configured to, when M is equal to 8, obtain seven first check results according to the at least two first code blocks; or, specifically, when M is 7, eight first check results are obtained according to the at least two first code blocks.

16. The apparatus of claim 13, wherein M-5, bit positions of the M bits in the first code block comprise at least one of:

10,34,42,50,58；

27,35,43,51,59；

20,28,36,44,52；

13,21,29,37,45；

14,22,30,38,62；

15,23,31,55,63；

16,24,48,56,64；

17,41,49,57, 65; alternatively, the first and second electrodes may be,

18,26；

11,19；

12,60；

53,61；

46,54；

39,47；

32,40；

25,33。

17. the apparatus of claim 16,

the processor is specifically configured to obtain sixteen first check results according to the at least two first code blocks, where the sixteen first check results include eight first check results when M is 5 and eight first check results when M is 2.

18. The apparatus of claim 13, wherein M-5, bit positions of the M bits in the first code block comprise at least one of:

10,13,14,15,16；

17,20,21,22,23；

24,27,28,29,30；

31,34,35,36,37；

38,41,42,43,44；

45,48,49,50,51；

52,55,56,57,58；

59,62,63,64,65。

19. the apparatus of claim 18,

the processor is further configured to obtain at least one second check-up result according to the at least two first code blocks, where a check-up target of the second check-up result includes N bits in each of the first code blocks, where N is 2, and bit positions of the N bits in the first code blocks include at least one of:

11,12；

18,19；

25,26；

32,33；

39,40；

46,47；

53,54；

60,61。

20. the apparatus according to any of claims 13-19, wherein the first and/or second check-up results are derived by a pre-set check-up algorithm for ensuring that in case of an addition or deletion of a control code block in the at least two first code blocks, the first check-up results determined by the code block handling apparatus coincide with fourth check-up results determined by the code block handling apparatus in case of no addition or deletion of the control code block in the at least two first code blocks; and/or the preset check-up algorithm is configured to ensure that, in a case where a control code block is added or deleted from the at least two first code blocks, the second check-up result determined by the code block processing device is consistent with a fifth check-up result determined by the code block processing device in a case where the control code block is not added or deleted from the at least two first code blocks.

21. The apparatus of claim 20, wherein the control code blocks comprise idle code blocks and/or low power code blocks.

22. The apparatus as claimed in any one of claims 13-21, wherein P1-64 and P2-66.

23. The apparatus according to any one of claims 13-22, further comprising:

a transceiver for transmitting the at least two first code blocks; and sending the at least one first check result.

24. The apparatus according to any one of claims 13-22, further comprising:

a transceiver configured to receive at least one seventh check-out result of at least two first code blocks, a check-out object of the seventh check-out result comprising M bits of each of the at least two first code blocks;

the processor is further configured to compare the at least one first check result with the at least one seventh check result to obtain error conditions of the at least two first code blocks.

25. A computer-readable storage medium, comprising a computer program which, when run on a computer, performs the method of any of claims 1-12.

26. A computer program product enabling the method according to any of claims 1-12 to be performed when the computer program product runs on a computer.