JPS62159933A - Frame synchronizing detection circuit - Google Patents

Abstract

PURPOSE:To improve the overhead of a signal quantity of a frame pattern with respect to a transmission data quantity and a mean asynchronizing duration time characteristic by dividing the frame constitution on a transmission line into the unit of sub frames, inserting the frame pattern to a head bit of each sub frame scatteringly so as to apply synchronization detection. CONSTITUTION:One frame is divided into N-set of sub frames, each sub frame is constituted in the unit of M-bit to attain the constitution of one frame (NXM) bits and the frame bit is inserted to the head bit of each sub frame. The frame pattern inserted to the head bit of each sub frame is a cyclic code comprising 1 word N-bit generated by an optional generation polynomial. Thus, the quotient between the code polynomial using 1 word N-bit extracted from one series of the signal separated by using the property of the cyclic code as the coefficient and the generation polynomial is calculated to detect the frame pattern thereby ensuring the sub frame synchronization. Simultaneously, the 1 word N-bit being the coefficient of the code polynomial is retrieved to detect the head of the sub frame thereby ensuring the frame synchronization quickly.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to an llTl period detection circuit used in digital transmissions such as backbone transmission systems, public networks, and subscriber systems.

(Prior art) There has been remarkable progress in transmission technology using optical fibers as transmission media, and the amount of transmitted information is several hundred Mbps.
It is becoming possible to transmit data at speeds of several Gbps per second.In order to effectively use the large-capacity digital transmission system, a 1-hour segmentation method can be considered, but since high-speed processing is required, Make the frame configuration as simple as possible 1
We are trying to downsize and simplify the circuit. One such method is a bit-based time division multiplexing method, and FIG. 3 is a frame configuration diagram of a general bit multiplexing method.

In the figure, l frame consists of bits, l
The frame is divided into channels in units of bits, and one channel is assigned to the frame channel, and P'
are frame channels, #1 to sK-+, which are 11 channels in bit units. In this method 1,
When bit multiplexing, the unique frame pattern is inserted one bit at a time into the frame pattern in units of several frames, and in synchronization detection, after separating takes in units of channels, the signal string separated from any channel is Synchronization is detected by detecting a frame channel based on whether it matches the inserted unique frame pattern.

Another method is to divide the frame into subframes and distribute the frame pattern to each subframe. FIG. 4 shows a general example of the frame structure. In Fig. 1, one frame is divided into L subframes, and each subframe is in bit units, and consists of l frame (IXL) bits, and the first bit of each subframe is One frame pattern is inserted one by one in sequence. Fj (i=1.2...,
L) indicates frame bits inserted in the first bit of each subframe + 7), indicating a subframe in units of bits #1 to #L.

In this method, (PIF2F3...pL-
1pt,) is the frame pattern, and from the signal sequence separated by 1 in synchronization detection (PIF2F3
......, F"L-IF'L)'! 67 L'
- Synchronization detection is performed by detecting the system pattern. The frame pattern is the frame bit Fl~
It is not necessary to insert it into all of Ft, even if H, frame pattern is frame bit PIF"3F5...
・Remaining frame picks if inserted in F
It is also possible to transmit information such as a transmission path monitor and a service monitor using 2F4Fg.

(Problems to be Solved by the Invention) In the bit multiplexing system as shown in FIG.
Bits are used. In order to downsize and simplify the circuit, it is impossible to increase the length of K that constitutes one frame, so the signal amount of the frame pattern in the amount of transmitted data becomes as large as J/K. ing. This overhead increases transmission capacity and speed.
Therefore, it is expected that the network will become thicker, and considering the reliability and serviceability of the system, channels for transmitting information such as transmission path monitors and service monitors will also be required, and this tendency will increase significantly. It turns out.

Also, the frame can be sub-7L' as shown in FIG.
- It is a unique frame pattern in the method of dividing Li into 2nd place and dispersing it into frame pattern f=%tt-bu frame (PIF'2P3...pt, -I
Synchronization detection is performed by detecting a signal sequence that matches the signal sequence (FL) from the separated signal sequence, thereby ensuring frame synchronization and subframe synchronization. By inserting and transmitting information such as a transmission path monitor or service monitor in frame bits F1 to FL, or by increasing the number of subframes in a frame and the number of subframe constituent bits I, It becomes possible to transmit information with less overhead relative to the amount of transmitted data without increasing complexity.

However, once the synchronization is lost, the frame pattern (PIF2F3...pt, -1p
In order to detect a signal string that matches t, ) from a separated signal string, hunting for one frame is required in the worst case, so the worst synchronization time required to recover synchronization is Lx] 'x 1 frame (SBC), and if the number of subframes and the number of subframe constituent bits 1 become large, the frame pattern (F
IP2F3...1 to detect F"L-IPL)
The average time taken to complete the test was increasing.

The present invention solves these problems by reducing the overhead of the amount of frame pattern signals relative to the amount of transmitted data without increasing the circuit size or complexity. It is an object of the present invention to provide a synchronization detection circuit suitable for a high-speed, large-capacity transmission system capable of reducing the average time.

(Means for Solving the Problem) In the present invention, in a frame which is divided into UN subframes and each subframe has a configuration of uM bits, one bit of the M pits is used for frame synchronization, and the frame is divided into UN subframes. 19 generated from the generator polynomial as a synchronization pattern
- an expansion circuit for extracting a received signal every M bits using a cyclic code consisting of N bits; Calculate the remainder with the generator polynomial.

This method performs synchronization detection using a means to perform synchronization.

(Function) When performing synchronization detection, it is desirable to downsize and simplify the circuit.The frame structure on the transmission path is divided into subframes, and the frame pattern is divided by the starting pitch of each subframe. and insert in sync detection,
Frame pattern detection, that is, synchronization detection, is possible by extracting the frame bits dispersed and inserted into the first bits of each subframe, so the operating speed required for the synchronization detection circuit is reduced and the circuit is small. It is possible to configure a synchronization detection circuit suitable for high-speed, large-capacity transmission systems by simplifying and simplifying the transmission. It is expected to realize a transmission system in which the overhead of the signal amount of the frame pattern corresponding to Cheetah t+ is reduced. In addition, since the frame pattern in which the first 11 bits of each sub-frame (7 harems are inserted) is a cyclic code consisting of 1 word and N bits generated from an arbitrary generator polynomial, the property of a 1-cycle code is used in synchronization detection. By calculating the remainder of the generator polynomial and the code polynomial whose coefficients are bits for l words extracted from one series of signals separated by At the same time, the coefficient 1 of the code polynomial
By searching bits into words, it is possible to detect where the beginning of a subframe is, so frame synchronization can be quickly secured, and the average time it takes to return to a synchronized state after going out of synchronization is shortened. is expected to be shortened. At this time, it is not necessarily necessary to search for hits in all N pits of 1 word, and it is possible to detect information of 1 word by searching for a shorter bit length, which increases the size and complexity of the synchronization detection circuit. It is also possible to further reduce the Furthermore, by arbitrarily selecting the generator polynomial and code length N, it is possible to increase the minimum Hamming distance dl-1 between generated cyclic codes. It becomes possible to realize a synchronization detection circuit that is resistant to errors.

(Example) The synchronization detection circuit of the present invention will be explained below.

FIG. 1 is a diagram showing a frame structure in the present invention. In the figure, one frame is divided into seven subframes, each subframe is composed of HM bits, and 1
The frame has a structure of (7XM) bits, and the first 1 bit of each subframe is sequentially inserted into the frame pattern in a distributed manner. Pi (i=1, 2.
...7) is a frame bit inserted into the first bit of each subframe, and #1 to #7 indicate a boop frame in units of M bits. For example, (PIF2F3F41i”5F6F?)=(110
0010)...I), and generally speaking, when the code word is (a6aHa2...aゎ-,), a(
1-¥-n-1 order, Ell to n-2 order, am-1
The code polynomial F(xi is 1Qxl
= am-1+aII-2x + a, -3X2+-・
+ alX"-"+aox"-' (21
It can be expressed as Here, it is assumed that the code length is n, and in terms of time, a high-order term a□ appears first, progresses sequentially to low-order terms, and finally t-al-1 is raised.

As can be seen from equation (2), when the code word is made up of a 7-bit string, the code polynomial F (xi can be a polynomial of degree 6, and equation (1) is) 1xl =
XlX 10X6 (expressed as 31, generating polynomial Qx)
If C1xl = 1+X+X3 (41), then 4 illusions = Q[xlQx]
(If there exists a polynomial Qi
is a cyclic formula.

From the above, it can be seen that the frame pattern 11100010) is a code generated from the generating polynomial of equation (4). Furthermore, the publication ``One Code Logic'' (Hiroshi Miyayo).

Yoshihiro Iwadare, Hideki Imai, Shokodo P, 194-+97) As shown in X
When dividing 11 +1 (generated from 3(x), n
The codewords form a cyclic code. Therefore, the generating polynomial of Equation 1 (4) is (X +1)/G[xl = (X'+1)/(X
+X+1 )=x4+x2+x+1
171, X+1 is divided by X+X+X+1, so the codeword of code length 7 generated from the generator polynomial in Equation 1 (4) becomes a cyclic code. That is, each row component of the matrix F in equation (8) generates a cyclic code with a code length of 7, and W+=(1100(130) (9−
1) W2=(1000101) (9
-2) W3=(0(101011)
(9-3)W4=(0010110)
(9-4) W5=((month 01100)
(9-5) W6; (eye 100 (1)
(Q-6)W7=(0310001)
(9-7), Wl, W2. ...
..., when W7 is used as a coefficient, the code polynomial is evenly divisible by the generator polynomial of equation (4). Furthermore, from the method of selecting the generator polynomial and code length, the minimum mink distance d of the cyclic code is uniquely determined.71 When the equation (j) is the generator polynomial, the minimum mink distance is d a = 3 ( 1(1) (The relationship between the Hamming length, the generator polynomial, and the $i length is described in the aforementioned Nako literature P249-251.

FIG. 2 shows an example of the synchronization detection circuit of the present invention (see 12), which detects synchronization from the frame shown in FIG. 1. 202 is the iM column, parallel converter (S-P), 2031 is the clock line, 21
132 clock control signal lines, 2041 to 204M parallel-converted M information lines and information output terminals, 205 clock control circuits (CLK, CTT), 206 to hexadecimal counter, 207 to control gates, 2081 to 2082 niM
(I D 2) Adder, 2 (191 to 2093 are 1
This is a subframe length delay element. In the same figure, the first
Information input terminal (20
1), becomes the input signal of the serial/parallel converter (202), and connects M information lines (2041 to 2 (14M
) is parallel-converted, and a clock control circuit (
205) and the input signal of the MOD2 adder (2081). On the other hand, the MOD2 adder (208t to 2082
) and one subframe length delay element (20!H~209
3) The generator polynomial ()(x) = I +X of equation (4)
+X l constitutes a divider.

In addition, a clock signal of f o /7 (Hz) is serially generated by a heptad counter (206 N), where f o is the transmission line.

It is sent from the parallel converter (202), and using this output, the delay elements (2091 to 209
a) The contents of the above are cleared. As a result, the divider 2 sequentially connects the information line (2041) f every frame period.
This is a divider that divides the polynomial that uses the generated 7 bits as a code word of 1 word to be transmitted by the generating polynomial of equation (4), and the remainder is applied to the delay elements (2091 to 2093). This is because the generator polynomial of equation (4) is successively divided by the code polynomial whose code word is a bit string extracted from each of the seven subframes.

The remainder of the division, that is, the delay element (2091 to 2
If the values of 093) are all zero, then the information line (2041)
This is a frame pattern that is distributed and assigned to the first bit of each subframe in the signal sent from the information line (2041>). This means that the incoming signal is not a frame pattern.In this way, frame patterns can be easily detected.In some cases, when the division remainder is zero, it is possible to Incoming l word 7 bit frame pattern ID formula (Q-1)
There are seven types (9-2)...(9-7), and subframe synchronization is ensured when the division remainder is zero.

If the division remainder is not zero, synchronization detection cannot be performed. Until synchronization is ensured, at worst the subframe length M
Only hunting is a ward (,.

In the worst case synchronization recovery time, Mx + frame [SEC
), the information line (20
It is a good idea to search for the 7-bit summer word sent from 41) during one frame and ensure frame synchronization. For this search, it is not necessary to search all of the 7 bits in one word, and the formula (9-1) (9-21,..., (9
-7), if you search for at least 3 bits, you can confirm that they are mutually exclusive, and you can immediately detect which frame pattern has ensured subframe synchronization. This information can be used to easily and immediately ensure subframe synchronization. Control j gate (2 (17)
The input is the output of the delay elements (2091 to 21193) and is a gate that detects whether the remainder of the division is zero or non-zero, and the output is the power of the clock control circuit (205). Historically, the clock control circuit (205) is powered by the information line (204), ? There is an output of a forward counter (206), and in this tarock control circuit, at least 3
The memory of the bit is shouldered and the data is sent for one frame.
The first 3 bits of the 7-bit word frame pattern are held, and this information and the output of the control game (207) are used to confirm that subframe synchronization is secured and to ensure frame synchronization. control information is sent to the serial/parallel converter (2032) using the clock control signal line (2032).
2) J is transmitted and frame synchronization is ensured.

Above, the number of subframes in one frame is 7, the generator polynomial is l-1-X+X, and the cyclic code is (110001
Although the case (1) has been described as an example, the present invention is not limited to these combinations, and various combinations can be considered. Also, it is not necessary to use the 9th frame
Frame slam on all 1 bits of c head) 7! :
There is no need to insert each bit in correspondence;
It is also possible to correspond to one bit of the frame pattern in every subframe and use the rest for information transmission such as a transmission line monitoring monitor or a transmission monitor.

(Effects of the Invention) In this way, the synchronization detection circuit according to the present invention is used because of the amount of transmitted data, the overhead threat of the frame pattern signal frequency, the ease of synchronization detection, and the average asynchronous duration characteristics compared to conventional methods. It can be seen that this is a significant improvement compared to the synchronization detection circuit with the configuration shown in FIG.

This invention is a synchronization detection circuit suitable for such high-speed, large-capacity transmission systems, and is expected to find use in transmission systems that will become even faster and larger in the future.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the frame structure of the present invention, FIG. 2 is a diagram showing an example of the configuration of the synchronization detection circuit of the present invention, and FIGS. 3 and 4 are diagrams showing the conventional frame structure. be. -201H input information and information input terminal in the figure. Parallel converter at 202, clock line at 2031.

Claims (1)

[Claims] In a frame that is divided into N subframes and each subframe has an M bit configuration, one bit of the M bits is used for frame synchronization, and a frame synchronization pattern is generated from a generator polynomial. an expansion circuit that uses a cyclic code consisting of one word and N bits and extracts a received signal every M bits, and is connected to the output of the expansion circuit,
A frame synchronization detection circuit comprising means for calculating a remainder between a code polynomial whose coefficients are N bits extracted from the data string and the generator polynomial.