WO2018214732A1 - 阵列基板及其制备方法、显示装置 - Google Patents

阵列基板及其制备方法、显示装置 Download PDF

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Publication number
WO2018214732A1
WO2018214732A1 PCT/CN2018/086187 CN2018086187W WO2018214732A1 WO 2018214732 A1 WO2018214732 A1 WO 2018214732A1 CN 2018086187 W CN2018086187 W CN 2018086187W WO 2018214732 A1 WO2018214732 A1 WO 2018214732A1
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Prior art keywords
substrate
shielding layer
electrostatic shielding
orthographic projection
pattern
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English (en)
French (fr)
Inventor
王培�
金贤镇
张凯
史大为
王文涛
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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Priority to US16/344,742 priority Critical patent/US10978495B2/en
Publication of WO2018214732A1 publication Critical patent/WO2018214732A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0251—Manufacture or treatment of multiple TFTs characterised by increasing the uniformity of device parameters
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/60—Arrangements for protection of devices protecting against electrostatic charges or discharges, e.g. Faraday shields

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate, a method for fabricating the same, and a display device.
  • An array substrate that is, a TFT substrate including a Thin Film Transistor, is one of important components of a display product.
  • the array substrate includes a base substrate, and the thin film transistor is disposed on the base substrate.
  • an array substrate including:
  • An electrostatic shielding layer disposed on the base substrate
  • An orthographic projection of the pattern of the electrostatic shielding layer on the substrate substrate covers an orthographic projection of a pattern of at least one of the gate line, the data line, and the thin film transistor on the substrate.
  • the pattern of the electrostatic shielding layer includes a plurality of lateral portions and a plurality of longitudinal portions, the plurality of lateral portions and the plurality of longitudinal portions intersecting each other to form a grid-like pattern,
  • An orthographic projection of the lateral portion on the substrate substrate covers an orthographic projection of the gate line on the substrate substrate, and an orthographic projection of the longitudinal portion on the substrate substrate covers the data line at the Orthographic projection on a substrate.
  • the lateral portion further includes a plurality of protrusions formed on the same side and connected to the longitudinal portion, the protrusions, a portion of the lateral portion that is connected to the protrusions, and An orthographic projection of the combination of the portions of the longitudinal portion that are connected to the protrusions on the base substrate covers an orthographic projection of the thin film transistor on the substrate.
  • a width of the lateral portion perpendicular to a direction in which the gate line extends is greater than a line width of the gate line
  • the width of the longitudinal portion perpendicular to the extending direction of the data line is greater than the line width of the data line;
  • An area of a region where the protrusion portion, a portion of the lateral portion connected to the protrusion portion, and a portion of the vertical portion connected to the protrusion portion are larger than an area of a region where the thin film transistor is located .
  • the electrostatic shielding layer comprises polysilicon having dopant ions.
  • the electrostatic shielding layer is located in at least one of a display area of the array substrate or a gate driving area of the array substrate.
  • Some embodiments of the present disclosure provide a method for fabricating an array substrate, including:
  • An orthographic projection of the pattern of the electrostatic shielding layer on the substrate substrate covers an orthographic projection of a pattern of at least one of the gate line, the data line, and the thin film transistor on the substrate.
  • the forming the electrostatic shielding layer comprises:
  • the polysilicon pattern layer is subjected to an ion doping treatment to form an electrostatic shielding layer, wherein the electrostatic shielding layer has a predetermined resistance.
  • the preparation method further includes:
  • the electrostatic shielding layer is subjected to a heat activation treatment to increase the order of the doping ions in the electrostatic shielding layer.
  • the forming the electrostatic shielding layer comprises:
  • the nitrogen-doped polysilicon film is subjected to a patterning process to form an electrostatic shielding layer.
  • the pattern of the electrostatic shielding layer formed includes:
  • An orthographic projection of the lateral portion on the base substrate covers an orthographic projection of the gate line on the base substrate, and an orthographic projection of the longitudinal portion on the base substrate covers the data line An orthographic projection on the substrate substrate.
  • the lateral portion further includes a plurality of protrusions formed on the same side and connected to the longitudinal portion, the protrusions, a portion of the lateral portion that is connected to the protrusions, An orthographic projection of a combination of portions of the longitudinal portion connected to the protrusions on the base substrate covers an orthographic projection of the thin film transistor on the substrate.
  • a width of the lateral portion in a direction perpendicular to the extending direction of the gate line is greater than a line width of the gate line
  • a width of the vertical portion in a direction perpendicular to a direction perpendicular to the data line is greater than the data line.
  • Some embodiments of the present disclosure provide a display device including the above array substrate.
  • FIG. 1 is a flow chart of a method for fabricating an array substrate according to some embodiments of the present disclosure
  • FIG. 2 is a schematic partial structural view of an array substrate according to some embodiments of the present disclosure.
  • Figure 3 is a cross-sectional view taken along line AA' of Figure 2;
  • FIG. 4 is a schematic diagram showing a step-by-step structure of preparation of an array substrate according to some embodiments of the present disclosure
  • FIG. 5 is a schematic diagram showing a step-by-step structure of further preparation of an array substrate according to some embodiments of the present disclosure
  • FIG. 6 is a schematic diagram showing a step-by-step structure of further preparation of an array substrate according to some embodiments of the present disclosure
  • FIG. 7 is a schematic diagram showing a step-by-step structure of further preparation of an array substrate according to some embodiments of the present disclosure.
  • FIG. 8 is a schematic diagram showing a step-by-step structure of further preparation of an array substrate according to some embodiments of the present disclosure.
  • FIG. 9 is a partial schematic structural diagram of an array substrate according to some embodiments of the present disclosure.
  • FIG. 10 is a schematic diagram of a display device according to some embodiments of the present disclosure.
  • the terms “first”, “second” and similar terms used in the description and the claims are not intended to mean any order, quantity or importance, and are merely used to distinguish different components.
  • the word “comprising” or “comprises” or the like means that the element or item preceding the word is intended to encompass the element or the item and its equivalents.
  • the terminology or positional relationship of the indications such as “transverse”, “longitudinal” and the like is based on the orientation or positional relationship shown in the drawings, and is merely for convenience of explanation of the technical description of the present disclosure, and is not intended to indicate or imply The device or component must have a particular orientation, is constructed and operated in a particular orientation, and thus is not to be construed as limiting the disclosure.
  • the number of processes performed on the substrate (usually a glass substrate) is large, and thus the glass substrate usually comes into contact with the machine several times.
  • the static accumulation of the machine during the contact of the surface of the glass substrate adjacent to the machine table, such as the glass substrate during contact with the roller for transport or the support pin for support (Pin) will generate static electricity.
  • the re-contact of the glass substrate with the roller or the support pin causes an ESD (Electro-Static discharge). Since the thickness of the base substrate is thin, the charge released during the electrostatic discharge is transmitted to the TFT on the glass substrate, which causes the performance of the TFT element to fail, thereby causing defects such as bright spots and black spots in the display product.
  • some embodiments of the present disclosure provide a method for fabricating an array substrate, including but not limited to step 02 (S02), that is, forming gate lines and data lines over a substrate. And thin film transistors.
  • the preparation method further includes a step 01 (S01) of sequentially forming an electrostatic shielding layer and an isolation layer covering the electrostatic shielding layer on the base substrate.
  • the orthographic projection of the pattern of the electrostatic shielding layer on the substrate substrate covers the orthographic projection of the pattern of at least one of the gate line, the data line, and the thin film transistor on the substrate.
  • step 02 is performed after the step 01, so the gate lines, the data lines and the thin film transistors are formed on the isolation layer covering the electrostatic shielding layer.
  • the isolation layer is made of an insulating material for isolating the electrostatic shielding layer from subsequently formed signal lines (gate lines and data lines) and thin film transistors (TFTs).
  • the manufacturing process of the gate lines, the data lines, and the thin film transistors, and the structure of the TFTs can be used in the related art, and the embodiment of the present disclosure does not limit this.
  • the material of the electrostatic shielding layer is a metal material, a semiconductor material or an ion-doped semiconductor material having a certain debugging resistance, and as long as it has conductivity, the static electricity induced on the surface of the substrate substrate away from the electrostatic shielding layer can be shielded. Just fine.
  • an electrostatic shielding layer is disposed between the gate line, the data line, and the TFT and the substrate, and the orthographic projection of the pattern of the electrostatic shielding layer on the substrate is covered.
  • the electrostatic shielding layer is disposed under the gate line, the data line, and the TFT region, that is, the pattern of the electrostatic shielding layer on the substrate substrate is overlaid on the substrate substrate, and the pattern of the data line and the thin film transistor is on the substrate. Orthographic projection on.
  • the pattern of the electrostatic shielding layer 2 includes a plurality of lateral portions 2a and a plurality of longitudinal portions 2b, and the plurality of lateral portions 2a and the plurality of longitudinal portions 2b intersect each other to form a grid-like pattern.
  • the orthographic projection of the lateral portion 2a on the base substrate 1 covers the orthographic projection of the gate line 3 on the base substrate 1, and the orthographic projection of the longitudinal portion 2b on the base substrate 1 covers the positive of the data line 4 on the base substrate 1. projection.
  • lateral and “longitudinal” are merely illustrative of the portions of the electrostatic shielding layer 2 that respectively shield the gate lines 3 and the data lines 4, and are not limited to the direction of the gate lines and the data lines.
  • the above array substrate also includes a gate insulating layer, a data line, and a gate insulating layer, an interlayer insulating layer, and the like for isolating each layer of metal during the process of the TFT, since the gate insulating layer, the interlayer insulating layer, and the previously formed isolation layer are both It is a transparent insulating layer, so it is not shown in FIG. 2 above.
  • the lateral portion 2a further includes a plurality of protrusions 2c formed on the same side and connected to the longitudinal portion 2b.
  • the orthographic projection of the protrusion 2c, the portion of the lateral portion 2a connected to the protrusion 2c, and the portion of the longitudinal portion 2b connected to the protrusion 2c on the base substrate 1 covers the thin film transistor to be formed (in the figure
  • the abbreviation "TFT" indicates an orthographic projection on the substrate substrate 1.
  • "formed on the same side” means a side formed on a portion of the lateral portion 2a extending in the lateral direction.
  • the area of the electrostatic shielding layer 2 is larger than the area of each of the above structures.
  • the width of the lateral portion 2a perpendicular to the extending direction of the gate line 3 is larger than the line width of the gate line 3
  • the width of the longitudinal portion 2b perpendicular to the extending direction of the data line 4 is larger than the line width of the data line 4.
  • the area of the portion where the projection portion 2c and the portion of the lateral portion 2a which are connected to the projection portion 2c and the portion of the longitudinal portion 2b which is connected to the projection portion 2c are combined is larger than the area of the region where the TFT is located.
  • the gate line 3 it has a "length" dimension from left to right in FIG. 2 and a “width” dimension perpendicular to the length in the illustrated plane, and therefore, the above-described lateral portion 2a extends perpendicular to the gate line 3.
  • the width of the direction is its corresponding dimension perpendicular to the length in Figure 2.
  • the data line 4 it has a "width” dimension from left to right in FIG. 2 and a "length” dimension perpendicular to the width, and therefore, the width of the above-mentioned longitudinal portion 2b is perpendicular to the extending direction of the data line 4. That is, it is in the corresponding size in the left-to-right direction in FIG.
  • the orthographic projection of the combination of the protrusion 2c, the portion of the lateral portion 2a that is connected to the protrusion 2c, and the portion of the longitudinal portion 2b that is connected to the protrusion 2c covers the TFT on the base substrate 1.
  • the orthographic projection on the base substrate 1 so that the area of the combined region is larger than the area of the region where the TFT is located, that is, the length of the region in which the combination is located from the left to the right and the width along the direction perpendicular to the length. Both are larger than the corresponding length and width of the area where the TFT is located.
  • the material of the electrostatic shielding layer is a metallic material, such as deposited elemental molybdenum (Mo).
  • the material of the electrostatic shielding layer is a semiconductor material.
  • the electrostatic shielding layer composed of the metal material is easily bonded to the gate metal layer (including the gate lines and the TFTs).
  • the gate in the middle commonly referred to as the Gate layer
  • the source and drain metal layers including the data lines, the source and drain in the TFT, commonly referred to as the SD layer
  • the active layer in the TFT generate parasitic capacitance. Therefore, it may increase the energy consumption of the product.
  • the conductivity of the semiconductor material is between the conductor metal and the insulator, the resistance of the semiconductor material is large and the shielding effect is limited.
  • an ion-doped semiconductor material having a certain debugging resistance is used as a material of the electrostatic shielding layer.
  • the step of forming the electrostatic shielding layer includes steps 11-13 (S11-S13).
  • step 11 (S11) a polysilicon film covering the base substrate is formed.
  • step 12 (S12) the polysilicon film is subjected to a patterning process to form a polysilicon pattern layer, for example, forming a pattern composed of the lateral portion, the longitudinal portion, and the protrusion.
  • step 13 (S13) the polysilicon pattern layer is subjected to an ion doping treatment to form an electrostatic shielding layer.
  • the formed electrostatic shielding layer has a predetermined resistance.
  • the electrostatic shielding layer has a predetermined resistance by controlling the doping concentration and/or the doped ion species.
  • the preset resistance is such that the electrostatic shielding layer is less likely to generate parasitic capacitance with at least one of the gate metal layer, the source/drain metal layer, and the active layer in the TFT, and the shielding effect is optimal.
  • the step of forming a polysilicon film covering the base substrate includes forming an amorphous silicon (a-Si) film covering the substrate, and crystallizing the amorphous silicon film to make amorphous silicon The film is converted into a polysilicon (P-Si) film.
  • a-Si amorphous silicon
  • P-Si polysilicon
  • the crystallization process includes a solid phase process and an Excimer laser anneal crystallization (ELA) process.
  • ELA Excimer laser anneal crystallization
  • the amorphous silicon film is subjected to dehydrogenation treatment before the ELA process in order to avoid flash explosion of hydrogen contained in the preparation of the amorphous silicon.
  • the process of the dehydrogenation process can be used in the prior art, and the details of the embodiments of the present disclosure will not be described again.
  • the debugging effect of the resistance after the ion doping is poor, so the polysilicon film formed in the embodiment of the present disclosure is ion-doped to obtain a suitable debugging resistor. .
  • the patterning process described above may be any process in which a film layer (a layer of or a plurality of films, an embodiment of the present disclosure, which is a monolithic polysilicon film deposited on a substrate), is processed to form a specific pattern.
  • the patterning process is to apply a mask, expose the photoresist, develop, and etch the film layer (specifically, the polysilicon film is dry etched, Dry Etch), and remove (specifically, Stripping process, Strip) photoresist process.
  • the electrostatic shielding layer disposed under the TFT can also function as a light shielding layer (Light Shielding, abbreviated as LS).
  • the above preparation method further includes the following steps. That is, the electrostatic shielding layer is subjected to a heat activation treatment to increase the order of the doping ions in the electrostatic shielding layer.
  • the thermal motion of the doped ions is increased to increase the uniformity of diffusion in the polycrystalline silicon main body, so that the order of the doping ions is increased, and the shielding effect of the electrostatic shielding layer can be further enhanced.
  • the step of thermally activating the electrostatic shielding layer is performed after the step of forming the electrostatic shielding layer described above, and before the subsequent structures such as gate lines, data lines, and TFTs have not been formed.
  • the step of thermally activating the electrostatic shielding layer is performed after the step of forming the electrostatic shielding layer described above, and before the subsequent structures such as gate lines, data lines, and TFTs have not been formed.
  • the entire substrate is subjected to a heat treatment while activating the electrostatic shield layer and the remaining film layers.
  • the specific steps may be flexibly adjusted according to the process of the above array substrate, which is not limited by the embodiment of the present disclosure.
  • the electrostatic shield layer described above comprises a nitrogen doped polysilicon (N+a-Si) material.
  • the preparation step of the electrostatic shielding layer includes, for example, directly forming a nitrogen-doped polysilicon film covering the substrate by using a deposition method (Deposition), and performing a patterning process on the nitrogen-doped polysilicon film. An electrostatic shielding layer is formed.
  • the above “direct” means that the nitrogen element (N) in the formed N+a-Si is directly formed in the deposition raw material at the time of deposition, and is not formed again by the subsequent ion implantation plasma doping process. This setting makes the process simple and has less impact on productivity.
  • the method for preparing the array substrate provided by the embodiment of the present disclosure is exemplified below.
  • the preparation method comprises the steps a-e.
  • Step a As shown in FIG. 4, an a-Si film is deposited on a base substrate (not shown in FIG. 4) by a deposition method, and a-Si is crystallized into P-Si by a dehydrogenation treatment and an ELA process.
  • the pattern of P-Si is then defined using a mask, by exposure photoresist, dry etching (Dry Etch), and strip photoresist. This pattern needs to block the subsequently formed gate lines, data lines, and TFT regions to completely shield the ground substrate from the static electricity induced by the machine surface away from the pattern. Doping the pattern of P-Si to modulate a certain preset resistance for P-Si.
  • the pattern of the electrostatic shielding layer (LS Layer) 2 after completion of the ion doping process is as shown in FIG. 5, that is, the lateral portion 2a including the laterally intersecting cross section, the longitudinal portion 2b, and the longitudinal portion 2b extending from the lateral portion 2a and the longitudinal portion 2b Connected protrusions 2c.
  • an isolation layer covering the electrostatic shield layer 2 is formed on the base substrate.
  • Step b as shown in FIG. 6, a polysilicon active layer (Poly Layer, indicated by P in the figure) is formed on the isolation layer.
  • the process can be followed by existing conventional processes. Since the polysilicon active layer is a structure applied to the LTPS TFT and has a pattern similar to the inverted character " ⁇ ", the pattern of the polysilicon active layer is formed by the protrusion 2c, the lateral portion 2a, and the protrusion formed as described above. The portion where the 2c is connected and the portion of the longitudinal portion 2b that is connected to the projection 2c are blocked.
  • opposite ends of the polysilicon active layer " ⁇ " pattern are formed with oppositely disposed source contact regions and drain contact regions formed by ion doping to improve subsequent contact with the source and drain electrodes. Performance improves TFT device performance.
  • a gate insulating layer covering the active layer of polysilicon is formed on the isolation layer thereafter.
  • Step c as shown in FIG. 7, a pattern of the gate lines 3 is formed on the gate insulating layer, and the process can be carried out by a conventional conventional process.
  • the pattern of the gate lines 3 is entirely blocked by the lower lateral portion 2a.
  • the region where the pattern of the gate line 3 overlaps with the polysilicon active layer having the inverted character " ⁇ " pattern is a gate.
  • Step d forming an interlayer insulating layer (Interlayer Dielectric, ILD for short) covering the gate line 3, wherein the interlayer insulating layer is formed with a via hole penetrating the interlayer insulating layer and the underlying gate insulating layer to expose the polysilicon A source contact region and a drain contact region on the source layer.
  • ILD Interlayer Dielectric
  • the substrate is subjected to a heat activation treatment.
  • the arrangement is such that the order of the doping ions in the electrostatic shielding layer 2 is increased, so that the ions implanted in the source contact region and the drain contact region of the polysilicon active layer are arranged in an orderly manner, thereby simplifying The number of processes.
  • Step e as shown in FIG. 8, a data line 4 and a drain (labeled as d in the figure) are formed on the interlayer insulating layer.
  • the portion of the data line 4 that is connected to the source contact region through the via is directly used as the source of the TFT (labeled as s in the figure), and the drain is connected to the drain contact region through the via.
  • the data line 4 is blocked by the lower longitudinal portion 2b, and the drain is blocked by the lower projection 2c.
  • PLN Planarization Layer, organic film layer as a flat layer
  • P-ITO Layer Panel ITO
  • PVX Passivation Layer
  • C-ITO Common ITO
  • the array substrate includes a gate line 3, a data line 4, and a thin film transistor disposed above the base substrate 1. And an electrostatic shielding layer 2 disposed on the base substrate 1, and an isolation layer 5 covering the electrostatic shielding layer 2.
  • the gate line 3, the data line 4, and the thin film transistor are disposed on the isolation layer 5.
  • the orthographic projection of the pattern of the electrostatic shielding layer 2 on the base substrate 1 covers the orthographic projection of the pattern of at least one of the gate line 3, the data line 4, and the thin film transistor on the base substrate 1.
  • the shielding can be used to avoid the static electricity accumulated by the machine during the ESD being transferred to the TFT through the gate line or the data line, or directly transmitted to the TFT element, thereby avoiding the appearance of the display product due to ESD. Highlights, dark spots and other defects, improve product yield.
  • the electrostatic shielding layer is disposed in the display area to shield the gate lines, the data lines, and the TFTs in the display area from electrostatic shielding. In some embodiments, the electrostatic shielding layer is disposed in a Gate Driver on Array (GOA) region of the array substrate to electrostatically shield the structure in the GOA region. In some embodiments, the electrostatic shielding layer described above is disposed within the display area and the GOA area. In some embodiments, as shown in FIG. 9, the GOA regions 10 are disposed on both sides of the display region 20. In other embodiments, the GOA area is disposed on one side of the display area.
  • GOA Gate Driver on Array
  • the electrostatic shielding layer comprises ion doped polysilicon, and the doped polysilicon has a predetermined resistance. Thereby, the electrostatic shielding layer is less likely to generate parasitic capacitance with at least one of the gate metal layer, the source/drain metal layer, and the active layer in the TFT, thereby achieving an optimum shielding effect.
  • some embodiments of the present disclosure provide a display device 100 including the above array substrate.
  • the display device 100 is, for example, a product or a component having any display function such as a liquid crystal display, a liquid crystal television, an organic electroluminescence display, an organic electroluminescence television, a digital photo frame, a mobile phone, a tablet computer, a digital photo frame, or a navigator.

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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)

Abstract

一种阵列基板包括，设置在衬底基板（1）上的静电屏蔽层（2），覆盖静电屏蔽层（2）的隔离层（5），以及设置在隔离层（5）上的栅线（3）、数据线（4）和薄膜晶体管。静电屏蔽层（2）的图案在衬底基板（1）上的正投影覆盖所述栅线（3）、数据线（4）和薄膜晶体管中至少一者的图案在衬底基板（1）上的正投影。

Description

阵列基板及其制备方法、显示装置
本申请要求于2017年5月23日提交中国专利局、申请号为201710370614.2、发明名称为“一种阵列基板及其制备方法、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板及其制备方法、显示装置。
背景技术
阵列基板，即包括薄膜晶体管(Thin Film Transistor)的TFT基板是显示产品的重要组成构件之一。阵列基板包括衬底基板，薄膜晶体管设置在衬底基板上。
发明内容
本公开的一些实施例提供了一种阵列基板，包括：
设置在衬底基板上的静电屏蔽层；
覆盖所述静电屏蔽层的隔离层；以及
设置在所述隔离层上的栅线、数据线和薄膜晶体管，其中
所述静电屏蔽层的图案在所述衬底基板上的正投影覆盖所述栅线、所述数据线和所述薄膜晶体管中至少一者的图案在所述衬底基板上的正投影。
在一些实施例中，所述静电屏蔽层的图案包括多条横向部和多条纵向部，所述多条横向部与所述多条纵向部相互交叉形成网格状的图案，
横向部在所述衬底基板上的正投影覆盖所述栅线在所述衬底基板上的正投影，所述纵向部在所述衬底基板上的正投影覆盖所述数据线在所述衬底基板上的正投影。
在一些实施例中，所述横向部还包括形成在同一侧的多个与所述纵向部连接的突起部，所述突起部、所述横向部的与所述突起部相连接的部分、及所述纵向部的与所述突起部相连接的部分的组合在所 述衬底基板上的正投影覆盖所述薄膜晶体管在所述衬底基板上的正投影。
在一些实施例中，所述横向部垂直于所述栅线延伸方向的宽度大于所述栅线的线宽；
所述纵向部垂直于所述数据线延伸方向的宽度大于所述数据线的线宽；以及
所述突起部、所述横向部的与所述突起部相连接的部分、以及所述纵向部的与所述突起部相连接的部分的组合所在区域的面积大于所述薄膜晶体管所在区域的面积。
在一些实施例中，所述静电屏蔽层包括具有掺杂离子的多晶硅。
在一些实施例中，所述静电屏蔽层位于所述阵列基板的显示区域或所述阵列基板的栅极驱动区域中的至少一个中。
本公开一些实施例提供了一种阵列基板的制备方法，包括：
在衬底基板上依次形成静电屏蔽层、覆盖所述静电屏蔽层的隔离层；以及
在所述隔离层上形成栅线、数据线和薄膜晶体管，其中，
所述静电屏蔽层的图案在所述衬底基板上的正投影覆盖所述栅线、所述数据线和所述薄膜晶体管中至少一者的图案在所述衬底基板上的正投影。
在一些实施例中，所述形成静电屏蔽层包括：
形成覆盖衬底基板的多晶硅薄膜；
对所述多晶硅薄膜进行构图工艺处理，以形成多晶硅图案层；以及，
对所述多晶硅图案层进行离子掺杂处理，以形成静电屏蔽层，其中所述静电屏蔽层具有预设电阻。
在一些实施例中，在形成所述静电屏蔽层之后，所述制备方法还包括：
对所述静电屏蔽层进行加热活化处理，以提高所述静电屏蔽层中掺杂离子的排列有序程度。
在一些实施例中，所述形成静电屏蔽层包括：
直接形成覆盖衬底基板的氮掺杂多晶硅薄膜；以及
对所述氮掺杂多晶硅薄膜进行构图工艺处理，以形成静电屏蔽层。
在一些实施例中，形成的所述静电屏蔽层的图案，包括：
多条横向部和多条纵向部，所述多条横向部与所述多条纵向部相互交叉形成网格状的图案，其中，
所述横向部在所述衬底基板上的正投影覆盖所述栅线在所述衬底基板上的正投影，所述纵向部在所述衬底基板上的正投影覆盖所述数据线在所述衬底基板上的正投影。
在一些实施例中，所述横向部还包括形成在同一侧的多个与所述纵向部连接的突起部，所述突起部、所述横向部的与所述突起部相连接的部分、所述纵向部的与所述突起部相连接的部分的组合在所述衬底基板上的正投影覆盖所述薄膜晶体管在所述衬底基板上的正投影。
在一些实施例中，所述横向部沿垂直于所述栅线延伸方向的宽度大于所述栅线的线宽，所述纵向部沿垂直于所述数据线延伸方向的宽度大于所述数据线的线宽，所述突起部、所述横向部的与所述突起部相连接的部分、所述纵向部的与所述突起部相连接的部分的组合所在区域的面积大于所述薄膜晶体管所在区域的面积。
本公开一些实施例提供了一种显示装置，包括上述的阵列基板。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需使用的附图作简单地介绍。显而易见地，下面描述的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一些实施例提供的一种阵列基板的制备方法的流程图；
图2为本公开一些实施例提供的一种阵列基板的局部结构示意 图；
图3为图2中沿线AA’的剖面图；
图4为本公开一些实施例提供的阵列基板的制备分步结构示意图；
图5为本公开一些实施例提供的阵列基板的进一步制备分步结构示意图；
图6为本公开一些实施例提供的阵列基板的进一步制备分步结构示意图；
图7为本公开一些实施例提供的阵列基板的进一步制备分步结构示意图；
图8为本公开一些实施例提供的阵列基板的进一步制备分步结构示意；
图9为本公开一些实施例提供的一种阵列基板的局部结构示意图；以及
图10为本公开一些实施例提供的显示装置的示意图。
具体实施方式
下面将结合附图，对本公开的实施例进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
需要指出的是，除非另有定义，本公开实施例中所使用的所有术语(包括技术和科学术语)具有与本公开所属领域的普通技术人员共同理解的相同含义。还应当理解，诸如在通常字典里定义的那些术语应当被解释为具有与它们在相关技术的上下文中的含义相一致的含义，而不应用理想化或极度形式化的意义来解释，除非这里明确地这样定义。
例如，本公开说明书以及权利要求书中所使用的术语“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，仅是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指 出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“横向”、“纵向”等指示的方位或位置关系的术语为基于附图所示的方位或位置关系，仅是为了便于说明本公开的技术方案的简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
此外，由于本公开实施例所涉及的各信号线及TFT元件等结构实际尺寸非常微小，为了清楚起见，本公开实施例附图中的各结构尺寸均被放大，除非另有说明，均不代表实际尺寸比例。
相关技术中，在阵列基板的制备过程中，衬底基板(通常为玻璃基板)上进行的工艺制程较多，因此玻璃基板通常会与机台发生多次接触。在玻璃基板邻近机台的表面与机台相接触的过程中会使机台累积静电，比如玻璃基板在与用于运输的滚轴(Roller)或用于支撑的支撑针(Pin)的接触期间会使这些部件产生静电。而玻璃基板与滚轴或支撑针的再次接触会引起ESD(Electro-Static discharge，静电放电)。由于衬底基板的厚度较薄，因此，静电放电过程中释放的电荷传输到玻璃基板上的TFT而导致TFT元件性能失效，从而造成显示产品出现亮点、黑斑等不良。
针对上述问题，如图1所示，本公开一些实施例提供了一种阵列基板的制备方法，该制备方法包括但不限于步骤02(S02)，即在衬底基板上方形成栅线、数据线和薄膜晶体管。在前述S02之前，该制备方法还包括步骤01(S01)，即在衬底基板上依次形成静电屏蔽层、和覆盖静电屏蔽层的隔离层。静电屏蔽层的图案在衬底基板上的正投影覆盖栅线、数据线和薄膜晶体管中至少一者的图案在衬底基板上的正投影。
需要说明的是，上述步骤02是在步骤01之后进行的，因此栅线、数据线和薄膜晶体管形成于覆盖静电屏蔽层的隔离层之上。隔离层由绝缘材料构成，用于隔离静电屏蔽层与后续形成的信号线(栅线和数据线)及薄膜晶体管(TFT)。栅线、数据线和薄膜晶体管的制 备工艺以及TFT的结构(如顶栅型或底栅型)均可沿用现有技术的相关设计，本公开实施例对此不作限定。
在一些实施例中，静电屏蔽层的材料为金属材料、半导体材料或经过离子掺杂的具有一定调试电阻的半导体材料，只要具有导电性，可屏蔽衬底基板远离静电屏蔽层的表面感应的静电即可。
基于此，通过本公开的实施例提供的上述制备方法，在栅线、数据线和TFT与衬底基板之间设置静电屏蔽层，且静电屏蔽层的图案在衬底基板上的正投影覆盖栅线、数据线和薄膜晶体管中至少一者的图案在衬底基板上的正投影，从而可采用屏蔽的方式来避免机台积累的静电在ESD时释放的电荷通过栅线或数据线传输到TFT上，或直接传输到TFT元件上，从而可避免由于ESD导致的显示产品出现亮点、黑斑等多种不良，提高了产品良率。
在上述基础上，由于阵列基板的衬底基板的远离静电屏蔽层的表面的ESD可能在衬底基板上的任意区域内发生，因此，为了进一步提高静电屏蔽层的屏蔽效果，在一些实施例中，将静电屏蔽层设置在栅线、数据线和TFT区域的下方，即静电屏蔽层的图案在衬底基板上的正投影覆盖栅线、数据线和薄膜晶体管这三者的图案在衬底基板上的正投影。
在一些实施例中，如图2所示，静电屏蔽层2的图案包括多条横向部2a和多条纵向部2b，多条横向部2a与多条纵向部2b相互交叉形成网格状的图案。横向部2a在衬底基板1上的正投影覆盖栅线3在衬底基板1上的正投影，纵向部2b在衬底基板1上的正投影覆盖数据线4在衬底基板1上的正投影。
需要说明的是，为清楚示出静电屏蔽层2的图案，上述图2中已将后续形成的栅线3、数据线4以及TFT结构示出。并且，栅线3、数据线4以及TFT结构的具体数量仅为示意。
上述的“横向”、“纵向”仅为说明静电屏蔽层2中分别屏蔽栅线3和数据线4的部分是相对设置的，并非为对栅线与数据线方向的限定。
上述的阵列基板当然还包括形成栅线、数据线以及TFT过程中隔离各层金属的栅绝缘层、层间绝缘层等结构，由于栅绝缘层、层间绝缘层以及在先形成的隔离层均为透明绝缘层，故上述图2中未示出。
在一些实施例中，如图2所示，上述横向部2a还包括形成在同一侧的多个与纵向部2b连接的突起部2c。突起部2c、横向部2a的与突起部2c相连接的部分、纵向部2b的与突起部2c相连接的部分的组合在衬底基板1上的正投影覆盖待形成的薄膜晶体管(图中以缩写“TFT”示意出)在衬底基板1上的正投影。如图2所示，“形成在同一侧”是指形成在横向部2a的沿横向延伸的部分的一侧。
在一些实施例中，为了全面屏蔽ESD释放的电荷，静电屏蔽层2的区域大于上述各结构的区域。例如，如图2所示，上述横向部2a垂直于栅线3延伸方向的宽度大于栅线3的线宽，上述纵向部2b垂直于数据线4延伸方向的宽度大于数据线4的线宽，且突起部2c、横向部2a的与突起部2c相连接的部分、纵向部2b的与突起部2c相连接的部分的组合所在区域的面积大于TFT所在区域的面积。
这里，针对栅线3而言，其具有图2中自左至右的“长度”尺寸和图示平面中垂直于该长度的“宽度”尺寸，因此，上述横向部2a垂直于栅线3延伸方向的宽度即为其在图2中垂直于长度的相应尺寸。针对数据线4而言，其具有在图2中自左至右的“宽度”尺寸和垂直于该宽度的“长度”尺寸，因此，上述纵向部2b沿垂直于数据线4的延伸方向的宽度即为其在图2中沿自左至右方向上的相应尺寸。针对TFT而言，由于上述突起部2c、横向部2a的与突起部2c相连接的部分、及纵向部2b的与突起部2c相连接的部分的组合在衬底基板1上的正投影覆盖TFT在衬底基板1上的正投影，故该组合所在区域的面积大于TFT所在区域的面积，即该组合所在区域的沿从左至右的方向的长度和沿垂直于长度的方向的宽度的尺寸均大于TFT所在区域的相应长度和宽度的尺寸。
由前述描述可知，在一些实施例中，静电屏蔽层的材料为金属材料，例如沉积的单质钼(Mo)。在另一些实施例中，静电屏蔽层的 材料为半导体材料。
然而，由于金属材料的电阻较小，而静电屏蔽层与后续形成的栅线、数据线以及TFT结构有重叠区域，导致金属材料构成的静电屏蔽层易于与栅金属层(包括有栅线、TFT中的栅极，通常称之为Gate层)、源漏金属层(包括有数据线、TFT中的源极和漏极，通常称之为SD层)以及TFT中的有源层产生寄生电容，因此可能会增加产品能耗。并且，由于半导体材料的导电性介于导体金属与绝缘体之间，因此半导体材料的电阻较大，屏蔽效果有限。针对上述问题，本公开一些实施例中，采用经过离子掺杂的具有一定调试电阻的半导体材料作为静电屏蔽层的材料。
在以上情况下，在一些实施例中，形成静电屏蔽层的步骤包括步骤11-13(S11-S13)。
步骤11(S11)，形成覆盖衬底基板的多晶硅薄膜。
步骤12(S12)，对多晶硅薄膜进行构图工艺处理，以形成多晶硅图案层，例如形成上述的由横向部、纵向部以及突起部构成的图案。
步骤13(S13)，对多晶硅图案层进行离子掺杂(Doping)处理，以形成静电屏蔽层。形成的静电屏蔽层具有预设电阻。
需要说明的是，在一些实施例中，通过控制掺杂浓度和/或掺杂的离子种类，使得静电屏蔽层具有预设电阻。该预设电阻为使得静电屏蔽层不易与栅金属层、源漏金属层以及TFT中的有源层中的至少一者产生寄生电容的同时，屏蔽效果最优的阻值。
在一些实施例中，形成覆盖衬底基板的多晶硅薄膜的步骤包括，形成覆盖衬底基板的非晶硅(a-Si)薄膜，以及对非晶硅薄膜进行晶化处理，以使非晶硅薄膜转化为多晶硅(P-Si)薄膜。
在一些实施例中，晶化过程包括固相法以及准分子激光退火(Excimer laser anneal crystallization，简称为ELA)工艺。在一些实施例中，当采用ELA工艺晶化非晶硅薄膜时，为避免非晶硅制备时含有的氢发生闪爆，在进行ELA工艺前对非晶硅薄膜进行去氢处 理。去氢化处理的过程可沿用现有技术，本公开实施例对此不再赘述。
这里，考虑到非晶硅的结构中缺点较多，对其进行离子掺杂后电阻的调试效果较差，故本公开实施例中对形成的多晶硅薄膜进行离子掺杂，以获得适宜的调试电阻。
上述的构图工艺可以是对膜层(由一层或多层薄膜，本公开实施例即为沉积在衬底基板上的整层铺设的多晶硅薄膜)进行处理以形成具有特定图案的任意工艺。在一些实施例中，构图工艺是应用一次掩模板(Mask)，对光刻胶曝光、显影、刻蚀膜层(具体到多晶硅薄膜则为干法刻蚀，Dry Etch)、去除(具体可以为剥离工艺，Strip)光刻胶的工艺。
当后续形成的TFT中的有源层为LTPS(Low Temperature Poly Silicon，低温多晶硅)时，由于LTPS受光照影响容易产生漏电流问题，而多晶硅经离子掺杂后的光透过率会有所降低，故设置在TFT下方的静电屏蔽层还可起到遮光层(Light Shielding，简称为LS)的遮光的效果。
在一些实施例中，对于上述静电屏蔽层包括经过离子掺杂的具有一定调试电阻的多晶硅的情况，在形成上述静电屏蔽层的步骤之后，上述制备方法还包括以下步骤。即，对静电屏蔽层进行加热活化处理，以提高静电屏蔽层中掺杂离子的排列有序程度。
通过对静电屏蔽层进行加热，利用掺杂离子受热后的热运动提高其在多晶硅主体中的扩散均匀程度，使得掺杂离子的排列有序程度提高，可进一步增强静电屏蔽层的屏蔽效果。
在一些实施例中，对静电屏蔽层进行加热活化处理的步骤是在形成上述静电屏蔽层的步骤之后、且还未形成后续的栅线、数据线以及TFT等结构之前。可选地，当后续形成的栅线、数据线以及TFT等结构也需要加热活化处理时，对整个基板进行一次加热处理，同时活化静电屏蔽层以及其余膜层。具体步骤可根据上述阵列基板的工艺灵活调整，本公开实施例对此不作限定。
在一些实施例中，上述的静电屏蔽层包括氮掺杂多晶硅 (N+a-Si)材料。在此情况下，静电屏蔽层的制备步骤例如包括，采用沉积法(Deposition，简称为Dep)直接形成覆盖衬底基板的氮掺杂多晶硅薄膜，以及对氮掺杂多晶硅薄膜进行构图工艺处理，以形成静电屏蔽层。
这里，上述的“直接”是指形成的N+a-Si中的氮元素(N)是沉积时在沉积原材料中直接形成的，而不是后续经离子注入等离子掺杂工艺再次形成的。如此设置，可使工艺简单，对产能影响较小。
下面对本公开实施例提供的阵列基板的制备方法进行举例说明。该制备方法包括步骤a-e。
步骤a、如图4所示，采用沉积法在衬底基板(图4中未示出)上沉积a-Si薄膜，经过去氢处理及ELA工艺将a-Si晶化转换为P-Si。然后应用掩膜板(Mask)、通过曝光光刻胶、干法刻蚀(Dry Etch)及剥离(Strip)光刻胶定义P-Si的图案(Pattern)。此图案需遮挡后续形成的栅线、数据线、TFT区域，以便全面地屏蔽衬底基板(Glass)远离该图案的表面通过机台感应的静电。对P-Si的图案进行离子掺杂(Doping)，以给P-Si调试一定的预设电阻。电阻太大屏蔽效果变差，电阻太小则会与后续遮挡的结构形成一定的寄生电容。离子掺杂工艺完成后的静电屏蔽层(LS Layer)2的图案如图5所示，即包括横纵交叉的横向部2a、纵向部2b以及从横向部2a上延伸出的并与纵向部2b相连的突起部2c。
在此之后在衬底基板上形成覆盖静电屏蔽层2的隔离层。
步骤b、如图6所示，在隔离层上形成多晶硅有源层(Poly Layer，图中以P标识出)。其工艺可沿用现有常规工艺。由于该多晶硅有源层为应用于LTPS TFT中的结构，具有类似于倒立的字符“Π”的图案，故该多晶硅有源层的图案被前述形成的突起部2c、横向部2a的与突起部2c相连接的部分、及纵向部2b的与突起部2c相连接的部分的组合所遮挡。
在一些示例中，多晶硅有源层“Π”图案的两端处还形成有经离子掺杂形成的相对设置的源极接触区与漏极接触区，以提高后续与 源极、漏极相接触的性能，提高TFT的器件性能。
在此之后在隔离层上形成覆盖多晶硅有源层的栅绝缘层。
步骤c、如图7所示，在栅绝缘层上形成栅线3的图案，其工艺可沿用现有常规工艺。栅线3的图案被下方的横向部2a全部遮挡住。其中，栅线3的图案与具有倒立的字符“Π”图案的多晶硅有源层重叠的区域为栅极。
步骤d、形成覆盖栅线3的层间绝缘层(Inter layer Dielectric，简称为ILD)，该层间绝缘层上形成有贯穿层间绝缘层与下方的栅绝缘层的过孔，以露出多晶硅有源层上的源极接触区与漏极接触区。
在此之后，对基板进行加热活化处理。如此设置，可在提高静电屏蔽层2中掺杂离子的排列有序程度的同时，使得多晶硅有源层中源极接触区与漏极接触区中植入的离子得到有序的排列，从而简化工艺次数。
步骤e、如图8所示，在层间绝缘层上形成数据线4与漏极(图中标记为d)。数据线4通过过孔与源极接触区相连的部分则直接作为TFT的源极(图中标记为s)，漏极则通过过孔与漏极接触区相连。数据线4被下方的纵向部2b所遮挡，漏极被下方的突起部2c所遮挡。
在此之后，形成PLN(Planarization Layer，作为平坦层的有机膜层)、P-ITO Layer(Pixel ITO，像素电极)、PVX(Passivation Layer，保护层)以及C-ITO(Common ITO，公共电极)等结构，其过程可沿用现有技术，本公开实施例对此不作限定。
本公开一些实施例提供了一种采用上述制备方法获得的阵列基板，如图2和图3所示，该阵列基板包括，设置在衬底基板1上方的栅线3、数据线4和薄膜晶体管，以及，设置在衬底基板1上的静电屏蔽层2、覆盖静电屏蔽层2的隔离层5。栅线3、数据线4和薄膜晶体管设置在隔离层5上。静电屏蔽层2的图案在衬底基板1上的正投影覆盖栅线3、数据线4和薄膜晶体管中至少一者的图案在衬底基板1上的正投影。
据此，可采用屏蔽的方式来避免机台积累的静电在ESD时释放的电荷通过栅线或数据线传输到TFT上，或直接传输到TFT元件上，从而可避免由于ESD导致的显示产品出现亮点、黑斑等多种不良，提高了产品良率。
在一些实施例中，上述静电屏蔽层设置在显示区域内，即可对显示区域内的栅线、数据线和TFT进行静电屏蔽的防护。在一些实施例中，上述静电屏蔽层设置在阵列基板的栅极驱动(Gate Driver on Array，简称为GOA)区域，从而对GOA区域内的结构进行静电屏蔽。在一些实施例中，上述静电屏蔽层设置在显示区域和GOA区域内。在一些实施例中，如图9所示，GOA区域10设置在显示区域20的两侧。在另一些实施例中，GOA区域设置在显示区域的一侧。
在一些实施例中，静电屏蔽层包括经离子掺杂处理的多晶硅，且掺杂后的多晶硅具有预设电阻。从而可使得静电屏蔽层不易与栅金属层、源漏金属层以及TFT中的有源层中的至少一者产生寄生电容的同时，达到最优的屏蔽效果。
如图10所示，本公开一些实施例提供了一种显示装置100，包括上述的阵列基板。上述显示装置100例如是液晶显示器、液晶电视、有机电致发光显示器、有机电致发光电视、数码相框、手机、平板电脑、数码相框或导航仪等具有任何显示功能的产品或者部件。
本公开实施例的所有附图是上述阵列基板的简略的示意图，只为清楚描述本方案体现了与发明点相关的结构，对于其他的与发明点无关的结构是现有结构，在附图中并未体现或只体现部分。
以上所述，仅为本公开的一些实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (14)

  1. 一种阵列基板，包括：
    设置在衬底基板上的静电屏蔽层；
    覆盖所述静电屏蔽层的隔离层；以及
    设置在所述隔离层上的栅线、数据线和薄膜晶体管，其中
    所述静电屏蔽层的图案在所述衬底基板上的正投影覆盖所述栅线、所述数据线和所述薄膜晶体管中至少一者的图案在所述衬底基板上的正投影。
  2. 根据权利要求1所述的阵列基板，其中，所述静电屏蔽层的图案包括多条横向部和多条纵向部，所述多条横向部与所述多条纵向部相互交叉形成网格状的图案，
    横向部在所述衬底基板上的正投影覆盖所述栅线在所述衬底基板上的正投影，所述纵向部在所述衬底基板上的正投影覆盖所述数据线在所述衬底基板上的正投影。
  3. 根据权利要求2所述的阵列基板，其中，所述横向部还包括形成在同一侧的多个与所述纵向部连接的突起部，所述突起部、所述横向部的与所述突起部相连接的部分、及所述纵向部的与所述突起部相连接的部分的组合在所述衬底基板上的正投影覆盖所述薄膜晶体管在所述衬底基板上的正投影。
  4. 根据权利要求3所述的阵列基板，其中，
    所述横向部垂直于所述栅线延伸方向的宽度大于所述栅线的线宽；
    所述纵向部垂直于所述数据线延伸方向的宽度大于所述数据线的线宽；以及
    所述突起部、所述横向部的与所述突起部相连接的部分、以及所述纵向部的与所述突起部相连接的部分的组合所在区域的面积大于所述薄膜晶体管所在区域的面积。
  5. 根据权利要求1所述的阵列基板，其中，所述静电屏蔽层包括 具有掺杂离子的多晶硅。
  6. 根据权利要求1所述的阵列基板，其中，所述静电屏蔽层位于所述阵列基板的显示区域或所述阵列基板的栅极驱动区域中的至少一个中。
  7. 一种如权利要求1所述的阵列基板的制备方法，包括：
    在衬底基板上依次形成静电屏蔽层、覆盖所述静电屏蔽层的隔离层；以及
    在所述隔离层上形成栅线、数据线和薄膜晶体管，其中，
    所述静电屏蔽层的图案在所述衬底基板上的正投影覆盖所述栅线、所述数据线和所述薄膜晶体管中至少一者的图案在所述衬底基板上的正投影。
  8. 根据权利要求7所述的制备方法，其中，所述形成静电屏蔽层包括：
    形成覆盖衬底基板的多晶硅薄膜；
    对所述多晶硅薄膜进行构图工艺处理，以形成多晶硅图案层；以及
    对所述多晶硅图案层进行离子掺杂处理，以形成静电屏蔽层，其中，所述静电屏蔽层具有预设电阻。
  9. 根据权利要求8所述的制备方法，其中，在形成所述静电屏蔽层之后，所述制备方法还包括：
    对所述静电屏蔽层进行加热活化处理，以提高所述静电屏蔽层中掺杂离子的排列有序程度。
  10. 根据权利要求7所述的制备方法，其中，所述形成静电屏蔽层包括：
    直接形成覆盖衬底基板的氮掺杂多晶硅薄膜；以及
    对所述氮掺杂多晶硅薄膜进行构图工艺处理，以形成静电屏蔽层。
  11. 根据权利要求7至10任一项所述的制备方法，其中，形成的所述静电屏蔽层的图案，包括，
    多条横向部和多条纵向部，所述多条横向部与所述多条纵向部相 互交叉形成网格状的图案，
    且其中，横向部在所述衬底基板上的正投影覆盖所述栅线在所述衬底基板上的正投影，所述纵向部在所述衬底基板上的正投影覆盖所述数据线在所述衬底基板上的正投影。
  12. 根据权利要求11所述的制备方法，其中，所述横向部还包括形成在同一侧的多个与所述纵向部连接的突起部，所述突起部、所述横向部的与所述突起部相连接的部分、以及所述纵向部的与所述突起部相连接的部分的组合在所述衬底基板上的正投影覆盖所述薄膜晶体管在所述衬底基板上的正投影。
  13. 根据权利要求12所述的制备方法，其中，
    所述横向部垂直于所述栅线延伸方向的宽度大于所述栅线的线宽；
    所述纵向部垂直于所述数据线延伸方向的宽度大于所述数据线的线宽；
    所述突起部、所述横向部的与所述突起部相连接的部分、以及所述纵向部的与所述突起部相连接的部分的组合所在区域的面积大于所述薄膜晶体管所在区域的面积。
  14. 一种显示装置，包括如权利要求1-6任一项所述的阵列基板。
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