WO2018205671A1 - 阵列基板和包括其的嵌入式触摸显示面板 - Google Patents

阵列基板和包括其的嵌入式触摸显示面板 Download PDF

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Publication number
WO2018205671A1
WO2018205671A1 PCT/CN2018/072083 CN2018072083W WO2018205671A1 WO 2018205671 A1 WO2018205671 A1 WO 2018205671A1 CN 2018072083 W CN2018072083 W CN 2018072083W WO 2018205671 A1 WO2018205671 A1 WO 2018205671A1
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Prior art keywords
layer
conductive pattern
shield ring
array substrate
pattern layer
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PCT/CN2018/072083
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English (en)
French (fr)
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杨盛际
董学
陈小川
玄明花
卢鹏程
王磊
肖丽
于静
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京东方科技集团股份有限公司
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Publication of WO2018205671A1 publication Critical patent/WO2018205671A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/40—OLEDs integrated with touch screens

Definitions

  • the present disclosure relates to the field of display technology and, more particularly, to an array substrate and an embedded touch display panel including the array substrate.
  • OLED Organic Light Emitting Device
  • TFE Thin Film Encapsulation
  • the touch sensitivity may be affected due to interference of external noise on the internal signals of the panel.
  • an array substrate includes: a plurality of conductive pattern layers stacked on each other; and a first shield ring. Further, in the above array substrate, the first shielding ring is disposed in the same layer as the first conductive pattern layer of the plurality of conductive pattern layers and is located around the first conductive pattern layer.
  • the plurality of conductive pattern layers include a gate pattern layer, a source-drain electrode layer, and a cathode layer and an anode layer of the light emitting device.
  • the first conductive pattern layer is one of a cathode layer, an anode layer, a source-drain electrode layer, and a gate pattern layer.
  • the array substrate further includes a second shielding ring.
  • the second shielding ring is disposed in the same layer as the second conductive pattern layer of the plurality of conductive pattern layers and is located around the second conductive pattern layer.
  • the first conductive pattern layer and the second conductive pattern layer are two selected from the cathode layer, the anode layer, the source-drain electrode layer, and the gate pattern layer.
  • the first conductive pattern layer and the second conductive pattern layer are a cathode layer and an anode layer, respectively.
  • the first conductive pattern layer is a cathode layer and the second conductive pattern layer is an anode layer, or vice versa.
  • the shield ring eg, the first shield ring located at the periphery of the cathode layer and the shield ring (eg, the second shield ring) located at the periphery of the anode layer pass through the first formed in the pixel defining layer of the array substrate
  • the through holes are electrically connected to each other.
  • the array substrate further includes a third shielding ring, wherein the third shielding ring is disposed in the same layer as the third conductive pattern layer of the plurality of conductive pattern layers and is located in the third conductive pattern layer Surroundings.
  • the first conductive pattern layer, the second conductive pattern layer, and the third conductive pattern layer are a cathode layer, an anode layer, and a source-drain electrode layer, respectively.
  • the first conductive pattern layer is a cathode layer
  • the second conductive pattern layer is an anode layer
  • the third conductive pattern layer is a source-drain electrode layer.
  • a shield ring located at the periphery of the anode layer and a shield ring (eg, the first shield ring) located at the periphery of the cathode layer pass through the first formed in the pixel defining layer of the array substrate
  • the via holes are electrically connected to each other, and a shield ring (eg, a second shield ring) located at a periphery of the anode layer and a shield ring (eg, a third shield ring) located at a periphery of the source-drain electrode layer pass through a portion formed in the planarization layer
  • the two through holes are electrically connected to each other.
  • the array substrate further includes a fourth shielding ring, wherein the fourth shielding ring is disposed in the same layer as the fourth conductive pattern layer of the plurality of conductive pattern layers and is located around the fourth conductive pattern layer.
  • the first conductive pattern layer, the second conductive pattern layer, the third conductive pattern layer, and the fourth conductive pattern layer are a cathode layer, an anode layer, and a source-drain electrode, respectively Layer and gate pattern layer.
  • the first conductive pattern layer is a cathode layer
  • the second conductive pattern layer is an anode layer
  • the third conductive pattern layer is a source-drain electrode layer
  • the fourth conductive pattern layer is a gate pattern layer.
  • a shield ring eg, a second shield ring
  • a shield ring located at the periphery of the anode layer
  • a shield ring eg, the first shield ring located at the periphery of the cathode layer pass through the first formed in the pixel defining layer of the array substrate
  • the via holes are electrically connected to each other, and a shield ring (for example, a second shield ring) located at a periphery of the anode layer and a shield ring (eg, a third shield ring) located at a periphery of the source-drain electrode layer are formed in the planarization layer of the array substrate.
  • the second via holes are electrically connected to each other, and a shield ring (for example, a third shield ring) located at a periphery of the source-drain electrode layer and a shield ring (eg, a fourth shield ring) located at a periphery of the gate pattern layer are formed in the array
  • a shield ring for example, a third shield ring located at a periphery of the source-drain electrode layer and a shield ring (eg, a fourth shield ring) located at a periphery of the gate pattern layer are formed in the array
  • the third via holes in the gate insulating layer of the substrate are electrically connected to each other.
  • the array substrate further includes a second shielding ring, wherein the second shielding ring is disposed in the same layer as the second conductive pattern layer of the plurality of conductive pattern layers and is located in the second conductive pattern layer Surroundings.
  • the first shield ring located at the periphery of the first conductive pattern layer and the second shield ring located at the periphery of the second conductive pattern layer are electrically connected to each other.
  • the first shield ring is electrically insulated from the first conductive pattern layer by a bridging manner.
  • an embedded touch display panel is also provided.
  • the embedded touch display panel includes the array substrate described in any of the above embodiments.
  • FIG. 1 is a plan view showing a first shield ring in an array substrate according to an embodiment of the present disclosure
  • FIG. 2 is a schematic cross-sectional view showing an array substrate including a first shield ring, in accordance with an embodiment of the present disclosure
  • FIG. 3 is a schematic cross-sectional view showing an array substrate including a second shield ring, in accordance with an embodiment of the present disclosure
  • FIG. 4 is a schematic cross-sectional view showing an array substrate including a third shield ring, in accordance with an embodiment of the present disclosure
  • FIG. 5 is a schematic cross-sectional view showing an array substrate including a first shield ring, a second shield ring, and a third shield ring, according to an embodiment of the present disclosure
  • FIG. 6 is a schematic cross-sectional view showing an array substrate including a first shield ring, a second shield ring, a third shield ring, and a fourth shield ring, according to an embodiment of the present disclosure
  • FIG. 7 is a partial plan view showing electrical isolation of different shield rings from respective conductive pattern layers by way of a jumper, in accordance with an embodiment of the present disclosure.
  • spatially relative terms such as “lower”, “above”, “upper”, “below”, etc., may be used herein to describe one element or feature as shown in the figures. The relationship of other components or features. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation.
  • an array substrate includes: a plurality of conductive pattern layers stacked on each other and a first shield ring, wherein the first shield ring and the first conductive pattern layer of the plurality of conductive pattern layers The same layer is disposed and located at the periphery of the first conductive pattern layer.
  • the first shield ring may also be disposed in a peripheral region of the array substrate.
  • the plurality of conductive pattern layers may include a gate pattern layer, a source-drain electrode layer, and a cathode layer and an anode layer of the light emitting device, and the first conductive pattern layer is a cathode layer, an anode layer, One of the source-drain electrode layer and the gate pattern layer.
  • the array substrate further includes a second shielding ring, wherein the second shielding ring is disposed in the same layer as the second conductive pattern layer of the plurality of conductive pattern layers and is located around the second conductive pattern layer .
  • the first shield ring needs to be electrically insulated from the first conductive pattern layer by a jumper.
  • the shield ring 200 is disposed in a peripheral region of the array substrate, that is, in a non-display region (ie, a peripheral region) of the array substrate.
  • the array substrate further includes a light emitting device, and such a light emitting device includes a cathode 109 serving as a touch electrode.
  • the first shielding ring 200 is disposed around the touch electrode 109 to effectively shield the interference of external noise on the internal signal of the substrate, thereby improving the touch sensitivity.
  • the first shield ring 200 can be electrically coupled to an integrated circuit chip (IC chip), and the IC chip can provide a ground signal to the first shield ring 200.
  • IC chip integrated circuit chip
  • the cathode 109 of the light emitting device can be connected to an external gate lead.
  • the plurality of conductive pattern layers described herein may include a gate pattern layer, a source-drain electrode layer, and a cathode layer and an anode layer of the light emitting device, and the first conductive pattern layer described herein is a cathode layer, an anode layer, and a source-drainage One of the pole layer and the gate pattern layer.
  • the array substrate further includes a second shielding ring disposed in the same layer as the second conductive pattern layer of the plurality of conductive pattern layers and located at a periphery of the second conductive pattern layer, wherein the first conductive pattern layer and the first The two conductive pattern layers are two selected from the cathode layer, the anode layer, the source-drain electrode layer, and the gate pattern layer.
  • the first conductive pattern layer is a cathode layer and the second conductive pattern layer is an anode layer.
  • the second shield ring located at the periphery of the anode layer and the first shield ring located at the periphery of the cathode layer are electrically connected to each other through the first through holes formed in the pixel defining layer of the array substrate.
  • the array substrate further includes a third shield ring disposed in the same layer as the third conductive pattern layer of the plurality of conductive pattern layers and located at a periphery of the third conductive pattern layer.
  • the first conductive pattern layer, the second conductive pattern layer, and the third conductive pattern layer are a cathode layer, an anode layer, and a source-drain electrode layer, respectively.
  • the first conductive pattern layer is a cathode layer
  • the second conductive pattern layer is an anode layer
  • the third conductive pattern layer is a source-drain electrode layer.
  • the second shield ring located at the periphery of the anode layer and the first shield ring located at the periphery of the cathode layer are electrically connected to each other through the first through holes formed in the pixel defining layer of the array substrate, and are located at the periphery of the anode layer
  • the second shield ring and the third shield ring located at the periphery of the source-drain electrode layer are electrically connected to each other through a second through hole formed in the planarization layer.
  • the array substrate further includes a third shield ring disposed in the same layer as the fourth conductive pattern layer of the plurality of conductive pattern layers and located at a periphery of the fourth conductive pattern layer.
  • the first conductive pattern layer, the second conductive pattern layer, the third conductive pattern layer, and the fourth conductive pattern layer are a cathode layer, an anode layer, a source-drain electrode layer, and a gate pattern layer, respectively.
  • the first conductive pattern layer is a cathode layer
  • the second conductive pattern layer is an anode layer
  • the third conductive pattern layer is a source-drain electrode layer
  • the fourth conductive pattern layer is a gate pattern layer.
  • the second shield ring located at the periphery of the anode layer and the first shield ring located at the periphery of the cathode layer are electrically connected to each other through the first through holes formed in the pixel defining layer of the array substrate, and the second portion located around the anode layer
  • the shield ring and the third shield ring located at the periphery of the source-drain electrode layer are electrically connected to each other through a second via formed in the planarization layer of the array substrate, and the third shield ring located at the periphery of the source-drain electrode layer and the gate are located
  • the fourth shield ring around the pole pattern layer is electrically connected to each other through a third through hole formed in the gate insulating layer of the array substrate.
  • the array substrate further includes a second shield ring disposed in the same layer as the second one of the plurality of conductive pattern layers and located at a periphery of the second conductive pattern layer.
  • the first shield ring located at the periphery of the first conductive pattern layer and the second shield ring located at the periphery of the second conductive pattern layer are electrically connected to each other.
  • the first shield ring may be electrically insulated from the first conductive pattern layer by a bridging manner as needed.
  • FIG. 2 is a schematic cross-sectional view showing an array substrate including a first shield ring, in accordance with an embodiment of the present disclosure.
  • the array substrate 100 mainly includes: a substrate substrate 101; a gate pattern layer 102 sequentially formed on the substrate substrate 101, a gate insulating layer 103 covering the gate pattern layer 102, An active pattern layer 104 formed on the gate insulating layer 103, a source electrode layer 105S and a drain electrode layer 105D respectively contacting the active pattern layer 104 and partially covering the gate insulating layer 103 (ie, a source-drain electrode layer) 105S-105D); and a planarization layer 106.
  • the array substrate 100 further includes a light emitting device formed on the planarization layer 106 and an encapsulation layer 110, wherein the light emitting device includes a cathode layer 109 serving as a touch electrode, an anode layer 107, and disposed between the cathode layer 109 and the anode layer 107.
  • the pixel defining layer PDL is disposed between the cathode layer 109 and the anode layer 107.
  • the first shield ring 200 is disposed in a peripheral region of the array substrate 100 and formed around the cathode 109. In the cross-sectional view of FIG. 2, only the first shield ring 200 disposed in the left side region of the array substrate 100 is shown. However, in practice, the first shield ring 200 may be formed in any peripheral region of the array substrate 100, as specifically shown in FIG.
  • the first shield ring 200 is formed in the same layer as the cathode layer 109 and is electrically insulated from the cathode layer 109.
  • the first shield ring 200 and the cathode layer 109 electrically insulated from each other may be formed by depositing an electrode material layer on the pixel defining layer PDL and the organic light emitting layer 108, and then performing, for example, a patterning process on the electrode material layer.
  • the first shield ring 200 can pass over the external leads of the cathode layer 109 by bridging. That is, the first shield ring 200 may be traversed by other conductive patterns on different layers (eg, a gate metal pattern on the gate insulating layer 103, or an anode metal pattern on the planarization layer 106, etc.) Pick up. Therefore, the first shield ring 200 can be electrically insulated from the cathode layer 109.
  • FIG. 3 is a schematic cross-sectional view showing an array substrate including a second shield ring, according to an embodiment of the present disclosure.
  • the array substrate 100-1 according to the present embodiment is different from the arrangement manner of the first shield ring 200 in the previous embodiment except that the second shield ring 200-1 is disposed differently than the first shield ring 200 in the previous embodiment.
  • the second shield ring 200-1 is not formed in the same layer as the cathode layer 109, but is formed in the same layer as the anode layer 107, and is electrically insulated from the anode layer 107.
  • the second shield ring 200-1 is formed around the anode layer 107 in the peripheral region of the array substrate 100-1.
  • the second shield ring 200-1 and the anode layer 107 that are electrically insulated from each other can be formed by depositing an electrode material layer on the planarization layer 106 and then performing, for example, a patterning process on the electrode material layer.
  • the second shield ring 200-1 can also be electrically insulated from the anode layer 107 by a similar bridging method as necessary.
  • the array substrate may include a first shield ring 200 formed in the same layer as the cathode layer 109 and electrically insulated from the cathode layer 109, and a second shield ring 200 formed in the same layer as the anode layer 107 and electrically insulated from the anode layer 107. 1 both.
  • the first shield ring 200 may be electrically connected to the second shield ring 200-1 through a first via formed in the pixel defining layer PDL. Therefore, the interference of the clock signal and the spurious signal on the touch signal can be better shielded.
  • FIG. 4 is a schematic cross-sectional view showing an array substrate including a third shield ring, in accordance with an embodiment of the present disclosure.
  • the array substrate 100-2 according to the present embodiment is different from the arrangement manner of the first shield ring 200 in the previous embodiment except that the arrangement manner of the third shield ring 200-2 is different from that of the first embodiment.
  • the third shield ring 200-2 is not formed in the same layer as the cathode layer 109, but is formed in the same layer as the source electrode 105S and the drain electrode 105D, and is electrically insulated from the source electrode 105S and the drain electrode 105D.
  • the third shield ring 200-2 is formed around the source electrode 105S and the drain electrode 105D in the peripheral region of the array substrate 100-2.
  • the third shield ring 200-2 and the source electrode 105S which are electrically insulated from each other can be formed by depositing a metal material layer on the gate insulating layer 103 and then performing a patterning process on the metal material layer, for example. And drain electrode 105D.
  • the third shield ring 200-2 may also be electrically insulated from the source electrode 105S and the drain electrode 105D by a similar bridging method as necessary.
  • FIG. 5 is a schematic cross-sectional view showing an array substrate including a first shield ring, a second shield ring, and a third shield ring, according to an embodiment of the present disclosure.
  • the array substrate 100-3 according to the present embodiment has a configuration similar to that of the array substrate 100 of the previous embodiment except for the second and third shield rings, and the differences between the two will be mainly described below. .
  • the array substrate includes a first shielding ring, a second shielding ring, and a third shielding ring.
  • the first shield ring 200 is formed in the same layer as the cathode layer 109 and is electrically insulated from the cathode layer 109;
  • the second shield ring 200-1 is formed in the same layer as the anode layer 107, and is electrically insulated from the anode layer 107;
  • the third shield ring 200-2 is formed in the same layer as the source electrode 105S and the drain electrode 105D, and is electrically insulated from the source electrode 105S and the drain electrode 105D.
  • the first shield ring 200 may be electrically connected to the second shield ring 200-1 through a first via hole H1 formed in the pixel defining layer PDL, and the second shield ring 200-1 may be formed by flat
  • the second via hole H2 in the layer 106 is electrically connected to the third shield ring 200-2. Therefore, the first shield ring 200, the second shield ring 200-1, and the third shield ring 200-2 are electrically connected to each other.
  • first shield ring 200 the second shield ring 200-1, and the third shield ring 200-2 may be similar to those described in the above embodiments, respectively.
  • first shielding ring 200, the second shielding ring 200-1, and the third shielding ring 200-2 may not be electrically connected to each other.
  • two of the first shield ring 200, the second shield ring 200-1, and the third shield ring 200-2 are electrically connected to each other.
  • the first shielding ring 200 and the second shielding ring 200-1 are electrically connected to each other, or the second shielding ring 200-1 and the third shielding ring 200-2 are electrically connected to each other.
  • FIG. 6 is a schematic cross-sectional view showing an array substrate including a first shield ring, a second shield ring, a third shield ring, and a fourth shield ring, according to an embodiment of the present disclosure.
  • the array substrate 100-4 according to the present embodiment has a configuration similar to that of the array substrate 100 of the previous embodiment except for the second shield ring, the third shield ring, and the fourth shield ring, and will mainly be described below. the difference.
  • the array substrate includes a first shielding ring, a second shielding ring, a third shielding ring, and a fourth shielding ring.
  • the first shield ring 200 is formed in the same layer as the cathode layer 109 and is electrically insulated from the cathode layer 109;
  • the second shield ring 200-1 is formed in the same layer as the anode layer 107, and is electrically insulated from the anode layer 107;
  • the triple shield ring 200-2 is formed in the same layer as the source electrode 105S and the drain electrode 105D, and is electrically insulated from the source electrode 105S and the drain electrode 105D;
  • the fourth shield ring 200-3 is formed in the same layer as the gate pattern layer 102, And electrically insulated from the gate pattern layer 102.
  • the first shield ring 200 may be electrically connected to the second shield ring 200-1 through a first via hole H1 formed in the pixel defining layer PDL, and the second shield ring 200-1 may be formed by planarization.
  • the second via hole H2 in the layer 106 is electrically connected to the third shield ring 200-2, and the third shield ring 200-2 may pass through the third via hole H3 and the fourth shield ring 200 formed in the gate insulating layer 103. -3 electrical connection.
  • the first shield ring 200, the second shield ring 200-1, the third shield ring 200-2, and the fourth shield ring 200-3 can be electrically connected to each other.
  • first shield ring 200, the second shield ring 200-1, the third shield ring 200-2, and the fourth shield ring 200-3 may not be electrically connected to each other.
  • two of the first shielding ring 200, the second shielding ring 200-1, the third shielding ring 200-2, and the fourth shielding ring 200-3 may be electrically connected to each other.
  • FIGS. 2-6 An array substrate including different shield rings in accordance with some embodiments of the present disclosure is illustrated in FIGS. 2-6. However, according to the present disclosure, the array substrate of the present disclosure is not limited only to the examples shown in FIGS. 2 to 6.
  • FIG. 7 is a partial plan view showing that different shield rings are crossed across a gate wiring electrically connected to a touch electrode in a bridging manner to be electrically insulated from a gate wiring, in accordance with an embodiment of the present disclosure.
  • the cathode layer 109 of the light emitting device is connected downward through the hollow region T1 in the pixel defining layer PDL to be electrically connected to the underlying lateral anode metal layer (for example, an ITO/Ag/ITO layer). After that, it is electrically connected to the gate wiring 400 formed on the base substrate 101 through the second via hole T2 formed in the planarization layer 106 and the third via hole T3 formed in the gate insulating layer 103.
  • the underlying lateral anode metal layer for example, an ITO/Ag/ITO layer
  • the fourth shield ring 200-3 formed in the same layer as the gate pattern layer 102 and electrically insulated from the gate pattern layer 102 will encounter the gate wiring 400 when performing ring connection.
  • the fourth shield ring 200-3 may be closed by a jumper CL located at a different layer via the third via T3 formed in the gate insulating layer 103. Electrical connection.
  • the jumper line CL may be a portion of the source-drain electrode layer formed on the gate insulating layer 103 (which is electrically insulated from the source electrode 105S and the drain electrode 105D) or formed on the planarization layer 106. A portion of the anode layer (which is electrically insulated from the anode layer 107).
  • the type of the jumper line CL is not limited thereto as long as the corresponding shield ring can be made to the same layer of the conductive layer (for example, the cathode layer 109, the anode layer 107, the source electrode 105S and the drain electrode 105D, or the gate electrode)
  • the pattern layer 102 or the like) may be electrically insulated.
  • embodiments of the present disclosure also provide an embedded touch display panel including the array substrate described above.
  • the shielding ring surrounding the corresponding conductive pattern layer is disposed in the peripheral region of the array substrate, the interference of the clock signal and the spurious signal on the touch signal can be effectively shielded, thereby improving the touch sensitivity.

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Abstract

一种阵列基板（100）以及一种包括该阵列基板（100）的嵌入式触摸显示面板。具体地，该阵列基板（100）包括：相互叠置的多个导电图案层；以及第一屏蔽环（200）。在这样的阵列基板（100）中，第一屏蔽环（200）与所述多个导电图案层中的第一导电图案层同层设置并且位于第一导电图案层周边。

Description

阵列基板和包括其的嵌入式触摸显示面板
对相关申请的交叉引用
本申请要求2017年5月12日提交的中国专利申请号201710335917.0的优先权，该中国专利申请以其整体通过引用并入本文。
技术领域
本公开涉及显示技术领域，并且更具体地，提供了一种阵列基板以及一种包括该阵列基板的嵌入式触摸显示面板。
背景技术
有机发光显示器(Organic Light Emitting Device，OLED)是当今平板显示器研究领域的热点之一。与液晶显示器相比，OLED具有低能耗、生产成本低、自发光、宽视角和响应速度快等优点。目前，OLED已经在手机、PDA、数码相机等显示领域中开始取代传统的LCD显示屏。内嵌式触摸(in cell touch)技术可以与显示面板工艺兼容，并且越来越受到青睐。值得注意的是，当在未来应用于柔性OLED产品时，内嵌式OLED膜集成电路(Film Integrated Circuit，FIC)技术将更加具备优势。这主要是因为目前的柔性OLED触摸方案都是在薄膜封装(Thin Film Encapsulation，TFE)结构上直接制作多层触摸结构。这既增加了制作的难度，同时也增加了制作成本。
然而，对于内嵌式有源矩阵有机发光二极管显示器，由于外界噪声对面板内部信号的干扰，因此可能导致触控灵敏度受到影响。
公开内容
根据本公开的一方面，提供了一种阵列基板。具体地，该阵列基板包括：相互叠置的多个导电图案层；以及第一屏蔽环。进一步地，在上述阵列基板中，第一屏蔽环与所述多个导电图案层中的第一导电图案层同层设置并且位于第一导电图案层周边。
在本公开的一个实施例中，所述多个导电图案层包括栅极图案层、源-漏电极层以及发光器件的阴极层和阳极层。此时，第一导电图案层 是阴极层、阳极层、源-漏电极层和栅极图案层中的一个。
在本公开的一个实施例中，阵列基板还包括第二屏蔽环。具体地，该第二屏蔽环与所述多个导电图案层中的第二导电图案层同层设置并且位于第二导电图案层周边。在这样的情况下，进一步地，第一导电图案层和第二导电图案层是从阴极层、阳极层、源-漏电极层和栅极图案层中选择的两个。
根据本公开的一个实施例，在上述阵列基板中，第一导电图案层和第二导电图案层分别是阴极层和阳极层。作为示例，第一导电图案层是阴极层，并且第二导电图案层是阳极层，或者反之亦然。在这样的情况下，位于阴极层周边的屏蔽环(例如，第一屏蔽环)和位于阳极层周边的屏蔽环(例如，第二屏蔽环)通过形成在阵列基板的像素限定层中的第一通孔彼此电连接。
在本公开的一个实施例中，阵列基板还包括第三屏蔽环，其中第三屏蔽环与所述多个导电图案层中的第三导电图案层同层设置并且位于所述第三导电图案层周边。进一步地，在这样的阵列基板中，第一导电图案层、第二导电图案层和第三导电图案层分别是阴极层、阳极层和源-漏电极层。作为示例，第一导电图案层是阴极层，第二导电图案层是阳极层，并且第三导电图案层是源-漏电极层。在这样的实例中，位于阳极层周边的屏蔽环(例如，第二屏蔽环)和位于阴极层周边的屏蔽环(例如，第一屏蔽环)通过形成在阵列基板的像素限定层中的第一通孔彼此电连接，并且位于阳极层周边的屏蔽环(例如，第二屏蔽环)和位于源-漏电极层周边的屏蔽环(例如，第三屏蔽环)通过形成在平坦化层中的第二通孔彼此电连接。
在本公开的一个实施例中，阵列基板还包括第四屏蔽环，其中第四屏蔽环与所述多个导电图案层中的第四导电图案层同层设置并且位于第四导电图案层周边。进一步地，在还包括第四屏蔽环的阵列基板中，第一导电图案层、第二导电图案层、第三导电图案层和第四导电图案层分别是阴极层、阳极层、源-漏电极层和栅极图案层。作为示例，第一导电图案层是阴极层，第二导电图案层是阳极层，第三导电图案层是源-漏电极层，并且第四导电图案层是栅极图案层。在这样的情况下，位于阳极层周边的屏蔽环(例如，第二屏蔽环)和位于阴极层周边的屏蔽环(例如，第一屏蔽环)通过形成在阵列基板的像素限定层 中的第一通孔彼此电连接，位于阳极层周边的屏蔽环(例如，第二屏蔽环)和位于源-漏电极层周边的屏蔽环(例如，第三屏蔽环)通过形成在阵列基板的平坦化层中的第二通孔彼此电连接，并且位于源-漏电极层周边的屏蔽环(例如，第三屏蔽环)和位于栅极图案层周边的屏蔽环(例如，第四屏蔽环)通过形成在阵列基板的栅极绝缘层中的第三通孔彼此电连接。
在本公开的一个实施例中，阵列基板还包括第二屏蔽环，其中第二屏蔽环与所述多个导电图案层中的第二导电图案层同层设置并且位于所述第二导电图案层周边。
根据本公开的一个实施例，在以上提出的阵列基板中，位于所述第一导电图案层周边的第一屏蔽环和位于所述第二导电图案层周边的第二屏蔽环彼此电连接。
根据本公开的一个实施例，在以上提出的阵列基板中，第一屏蔽环通过跨接方式与第一导电图案层电绝缘。
根据本公开的另一方面，还提供了一种嵌入式触摸显示面板。该嵌入式触摸显示面板包括以上任一个实施例中描述的阵列基板。
附图说明
包括附图以提供对本公开的进一步理解。附图并入本申请并且组成本申请的一部分。附图示出了本公开的实施例，并且与描述一起用于解释本公开的原理。在附图中：
图1是示出了根据本公开的实施例的阵列基板中的第一屏蔽环的平面示意图；
图2是示出了根据本公开的实施例的包括第一屏蔽环的阵列基板的示意性剖视图；
图3是示出了根据本公开的实施例的包括第二屏蔽环的阵列基板的示意性剖视图；
图4是示出了根据本公开的实施例的包括第三屏蔽环的阵列基板的示意性剖视图；
图5是示出了根据本公开的实施例的包括第一屏蔽环、第二屏蔽环和第三屏蔽环的阵列基板的示意性剖视图；
图6是示出了根据本公开的实施例的包括第一屏蔽环、第二屏蔽 环、第三屏蔽环和第四屏蔽环的阵列基板的示意性剖视图；以及
图7是示出了根据本公开的实施例的不同屏蔽环通过跨接方式与相应导电图案层电绝缘的局部平面示意图。
具体实施方式
将理解的是，当元件或层被称作在另一元件或层“上”或者“连接到”另一元件或层时，该元件或层可以直接在另一元件或层上、直接连接到或直接结合到另一元件或层、或者也可以存在中间元件或中间层。相反，当元件被称作“直接”在另一元件或层“上”或者“直接连接到”另一元件或层时，不存在中间元件或中间层。同样的附图标记始终指示同样的元件。如在这里使用的，术语“和/或”包括所列项目中的一个或多个或者其任意组合。
为了便于描述，在这里可使用空间相对术语，如“下”、“在...上方”、“上”、“在...下方”等来描述如图中所示的一个元件或特征与其它元件或特征的关系。将理解的是，空间相对术语意在包含除了在附图中描述的方位之外的装置在使用或操作中的不同方位。
如这里所使用的，除非上下文另外明确指出，否则单数形式的“一个(种)”和“所述(该)”也意图包括复数形式。还将理解的是，当在本说明书中使用术语“包含”和/或“包括”时，说明存在所述特征、整体、步骤、操作、元件和/或组件，但是不排除还存在附加的一个或多个其它特征、整体、步骤、操作、元件、组件和/或它们的组。
在下文中，将参照附图详细地解释本公开。
总体地说，根据本公开的实施例，阵列基板包括：相互叠置的多个导电图案层以及第一屏蔽环，其中第一屏蔽环与所述多个导电图案层中的第一导电图案层同层设置并且位于第一导电图案层周边。
此外，第一屏蔽环还可以设置在阵列基板的周边区域中。在以上提出的阵列基板中，所述多个导电图案层可以包括栅极图案层、源-漏电极层以及发光器件的阴极层和阳极层，并且第一导电图案层是阴极层、阳极层、源-漏电极层和栅极图案层中的一个。
可选地，在具体实施例中，阵列基板还包括第二屏蔽环，其中第二屏蔽环与所述多个导电图案层中的第二导电图案层同层设置并且位于第二导电图案层周边。在一些情况下，第一屏蔽环需要通过跨接方 式与第一导电图案层电绝缘。
例如，参照图1，屏蔽环200设置在阵列基板的周边区域中，即，设置在阵列基板的非显示区域(即，外围区域)中。阵列基板还包括发光器件，并且这样的发光器件包括用作触控电极的阴极109。在这样的情况下，第一屏蔽环200围绕触控电极109设置，以便有效地屏蔽外界噪声对基板内部信号的干扰，从而改善触控灵敏度。
在一个实施例中，第一屏蔽环200可以与集成电路芯片(IC芯片)电连接，并且IC芯片可以向第一屏蔽环200提供接地信号。
另外，发光器件的阴极109可以连接到外接栅极引线。
本文所述的多个导电图案层可以包括栅极图案层、源-漏电极层以及发光器件的阴极层和阳极层，本文所述的第一导电图案层是阴极层、阳极层、源-漏电极层和栅极图案层中的一个。
在一个实施例中，阵列基板还包括与所述多个导电图案层中的第二导电图案层同层设置并且位于第二导电图案层周边的第二屏蔽环，其中第一导电图案层和第二导电图案层是从阴极层、阳极层、源-漏电极层和栅极图案层中选择的两个。
在一个实施例中，第一导电图案层是阴极层，并且第二导电图案层是阳极层。在这样的情况下，位于阳极层周边的第二屏蔽环和位于阴极层周边的第一屏蔽环通过形成在阵列基板的像素限定层中的第一通孔彼此电连接。
在一个实施例中，阵列基板还包括与所述多个导电图案层中的第三导电图案层同层设置并且位于第三导电图案层周边的第三屏蔽环。此时，第一导电图案层、第二导电图案层和第三导电图案层分别是阴极层、阳极层和源-漏电极层。例如，第一导电图案层是阴极层，第二导电图案层是阳极层，并且第三导电图案层是源-漏电极层。
在此情况下，位于阳极层周边的第二屏蔽环和位于阴极层周边的第一屏蔽环通过形成在阵列基板的像素限定层中的第一通孔彼此电连接，并且位于阳极层周边的第二屏蔽环和位于源-漏电极层周边的第三屏蔽环通过形成在平坦化层中的第二通孔彼此电连接。
在一个实施例中，阵列基板还包括与所述多个导电图案层中的第四导电图案层同层设置并且位于第四导电图案层周边的第三屏蔽环。进一步地，第一导电图案层、第二导电图案层、第三导电图案层和第 四导电图案层分别是阴极层、阳极层、源-漏电极层和栅极图案层。例如，第一导电图案层是阴极层，第二导电图案层是阳极层，第三导电图案层是源-漏电极层，并且第四导电图案层是栅极图案层。
在此情况下，位于阳极层周边的第二屏蔽环和位于阴极层周边的第一屏蔽环通过形成在阵列基板的像素限定层中的第一通孔彼此电连接，位于阳极层周边的第二屏蔽环和位于源-漏电极层周边的第三屏蔽环通过形成在阵列基板的平坦化层中的第二通孔彼此电连接，并且位于源-漏电极层周边的第三屏蔽环和位于栅极图案层周边的第四屏蔽环通过形成在阵列基板的栅极绝缘层中的第三通孔彼此电连接。
在一个实施例中，阵列基板还包括与所述多个导电图案层中的第二导电图案层同层设置并且位于所述第二导电图案层周边的第二屏蔽环。
在此情况下，位于第一导电图案层周边的第一屏蔽环和位于第二导电图案层周边的第二屏蔽环彼此电连接。
根据需要，第一屏蔽环可以通过跨接方式与第一导电图案层电绝缘。
下面将参照图2至图6详细地描述根据本公开的实施例的阵列基板中的不同屏蔽环的具体结构。
图2是示出了根据本公开的实施例的包括第一屏蔽环的阵列基板的示意性剖视图。
参照图2，根据本公开的实施例，阵列基板100主要包括：衬底基板101；依次形成在衬底基板101上的栅极图案层102、覆盖栅极图案层102的栅极绝缘层103、形成在栅极绝缘层103上的有源图案层104、分别与有源图案层104接触并部分地覆盖栅极绝缘层103的源电极层105S和漏电极层105D(即，源-漏电极层105S-105D)；以及平坦化层106。阵列基板100还包括形成在平坦化层106上的发光器件以及封装层110，其中，发光器件包括用作触控电极的阴极层109、阳极层107以及设置在阴极层109与阳极层107之间的有机发光层108。另外，像素限定层PDL设置在阴极层109与阳极层107之间。
在图2所示的实施例中，第一屏蔽环200设置在阵列基板100的周边区域中，并且围绕阴极109而形成。在图2的剖视图中，仅示出了设置在阵列基板100的左侧区域中的第一屏蔽环200。但是，在实践 中，第一屏蔽环200可以形成在阵列基板100的任何周边区域中，具体如图1所示。
在本实施例中，第一屏蔽环200与阴极层109同层地形成并且与阴极层109电绝缘。
在一个实施例中，通过在像素限定层PDL和有机发光层108上沉积电极材料层，然后对电极材料层进行例如图案化工艺，可以形成彼此电绝缘的第一屏蔽环200和阴极层109。
如果第一屏蔽环200与阴极层109的外接引线在同一层上相遇，则第一屏蔽环200可以通过跨接方式越过阴极层109的外接引线。也就是说，第一屏蔽环200可以通过位于不同层上的其它导电图案(比如，在栅极绝缘层103上的栅极金属图案，或者在平坦化层106上的阳极金属图案等)进行跨接。因此，第一屏蔽环200能够与阴极层109电绝缘。
图3是示出了根据本公开的实施例的包括第二屏蔽环的阵列基板的示意性剖视图。
参照图3，在本实施例中，除了第二屏蔽环200-1的设置方式不同于前一实施例中的第一屏蔽环200的设置方式之外，根据本实施例的阵列基板100-1具有与第一实施例的阵列基板100类似的构造，并且下面将主要描述二者的不同之处。
在本实施例中，第二屏蔽环200-1不与阴极层109同层地形成，而是与阳极层107同层地形成，并且与阳极层107电绝缘。第二屏蔽环200-1在阵列基板100-1的周边区域中围绕阳极层107而形成。
类似地，在一个实施例中，通过在平坦化层106上沉积电极材料层，然后对电极材料层进行例如图案化工艺，可以形成彼此电绝缘的第二屏蔽环200-1和阳极层107。
必要时，第二屏蔽环200-1也可以通过类似的跨接方式与阳极层107电绝缘。
此外，阵列基板可以包括与阴极层109同层地形成且与阴极层109电绝缘的第一屏蔽环200以及与阳极层107同层地形成且与阳极层107电绝缘的第二屏蔽环200-1二者。在此情况下，可选地，第一屏蔽环200可以通过形成在像素限定层PDL中的第一通孔与第二屏蔽环200-1进行电连接。因此，能够更好地屏蔽时钟信号和寄生信号对触控信号 的干扰。
图4是示出了根据本公开的实施例的包括第三屏蔽环的阵列基板的示意性剖视图。
参照图4，在本实施例中，除了第三屏蔽环200-2的设置方式不同于前一实施例中的第一屏蔽环200的设置方式之外，根据本实施例的阵列基板100-2具有与前一实施例的阵列基板100类似的构造，并且下面将主要描述二者的不同之处。
在本实施例中，第三屏蔽环200-2不与阴极层109同层地形成，而是与源电极105S和漏电极105D同层地形成，并且与源电极105S和漏电极105D电绝缘。第三屏蔽环200-2在阵列基板100-2的周边区域中围绕源电极105S和漏电极105D而形成。
类似地，在一个实施例中，通过在栅极绝缘层103上沉积金属材料层，然后对金属材料层进行例如图案化工艺，可以形成彼此电绝缘的第三屏蔽环200-2与源电极105S和漏电极105D。
必要时，第三屏蔽环200-2也可以通过类似的跨接方式与源电极105S和漏电极105D电绝缘。
图5是示出了根据本公开的实施例的包括第一屏蔽环、第二屏蔽环和第三屏蔽环的阵列基板的示意性剖视图。
参照图5，除了第二和第三屏蔽环之外，根据本实施例的阵列基板100-3具有与前一实施例的阵列基板100类似的构造，并且下面将主要描述二者的不同之处。
在本实施例中，阵列基板包括第一屏蔽环、第二屏蔽环和第三屏蔽环。具体地，第一屏蔽环200与阴极层109同层地形成，并且与阴极层109电绝缘；第二屏蔽环200-1与阳极层107同层地形成，并且与阳极层107电绝缘；以及第三屏蔽环200-2与源电极105S和漏电极105D同层地形成，并且与源电极105S和漏电极105D电绝缘。
如图5所示，第一屏蔽环200可以通过形成在像素限定层PDL中的第一通孔H1与第二屏蔽环200-1电连接，而第二屏蔽环200-1可以通过形成在平坦化层106中的第二通孔H2与第三屏蔽环200-2电连接。因此，第一屏蔽环200、第二屏蔽环200-1和第三屏蔽环200-2这三者相互电连接。
此外，第一屏蔽环200、第二屏蔽环200-1和第三屏蔽环200-2的 形成方法可以分别与在上面的实施例中描述的方法类似。
当然，可以理解的是，第一屏蔽环200、第二屏蔽环200-1和第三屏蔽环200-2也可以不彼此电连接。可替换地，第一屏蔽环200、第二屏蔽环200-1和第三屏蔽环200-2中的两个相互电连接。比如，第一屏蔽环200与第二屏蔽环200-1相互电连接，或者第二屏蔽环200-1和第三屏蔽环200-2相互电连接。
图6是示出了根据本公开的实施例的包括第一屏蔽环、第二屏蔽环、第三屏蔽环和第四屏蔽环的阵列基板的示意性剖视图。
除了第二屏蔽环、第三屏蔽环和第四屏蔽环之外，根据本实施例的阵列基板100-4具有与前一实施例的阵列基板100类似的构造，并且下面将主要描述二者的不同之处。
在本实施例中，阵列基板包括第一屏蔽环、第二屏蔽环、第三屏蔽环和第四屏蔽环。具体地，第一屏蔽环200与阴极层109同层地形成，并且与阴极层109电绝缘；第二屏蔽环200-1与阳极层107同层地形成，并且与阳极层107电绝缘；第三屏蔽环200-2与源电极105S和漏电极105D同层地形成，并且与源电极105S和漏电极105D电绝缘；以及第四屏蔽环200-3与栅极图案层102同层地形成，并且与栅极图案层102电绝缘。
如图6所示，第一屏蔽环200可以通过形成在像素限定层PDL中的第一通孔H1与第二屏蔽环200-1电连接，第二屏蔽环200-1可以通过形成在平坦化层106中的第二通孔H2与第三屏蔽环200-2电连接，并且第三屏蔽环200-2可以通过形成在栅极绝缘层103中的第三通孔H3与第四屏蔽环200-3电连接。在这种情况下，第一屏蔽环200、第二屏蔽环200-1、第三屏蔽环200-2和第四屏蔽环200-3能够相互电连接。
同样，第一屏蔽环200、第二屏蔽环200-1、第三屏蔽环200-2和第四屏蔽环200-3也可以不彼此电连接。可替换地，第一屏蔽环200、第二屏蔽环200-1、第三屏蔽环200-2和第四屏蔽环200-3中的相邻两个屏蔽环可以相互电连接。
在图2至图6中举例说明了根据本公开的一些实施例的包括不同屏蔽环的阵列基板。然而，根据本公开的内容，本公开的阵列基板并不仅仅限于在图2至图6中示出的例子。
图7是示出了根据本公开的实施例的不同屏蔽环通过跨接方式越过与触控电极电连接的栅极布线以便与栅极布线电绝缘的局部平面示意图。
在图7中，发光器件的阴极层109通过像素限定层PDL中的镂空区域T1向下连接，从而与下方的横向阳极金属层(例如，ITO/Ag/ITO层)电连接。在此之后，它通过形成在平坦化层106中的第二过孔T2和形成在栅极绝缘层103中的第三过孔T3与形成在衬底基板101上的栅极布线400电连接。
在此情况下，例如，与栅极图案层102同层地形成且与栅极图案层102电绝缘的第四屏蔽环200-3在进行环连接时将遇到栅极布线400。此时，为了实现与栅极布线400的电绝缘，第四屏蔽环200-3可以经由形成在栅极绝缘层103中的第三过孔T3通过位于不同层的跨接线CL而进行闭合环的电连接。
在一个实施例中，跨接线CL可以是形成在栅极绝缘层103上的部分源-漏电极层(其与源电极105S和漏电极105D电绝缘)，或者是形成在平坦化层106上的部分阳极层(其与阳极层107电绝缘)。然而，在本公开中，跨接线CL的类型不限于此，只要能够使相应屏蔽环与同层的导电层(比如，阴极层109、阳极层107、源电极105S和漏电极105D、或者栅极图案层102等)电绝缘即可。
此外，本公开的实施例还提供了一种嵌入式触摸显示面板，其包括上面描述的阵列基板。
由于在阵列基板的周边区域中设置有围绕相应导电图案层的屏蔽环，所以能够有效地屏蔽时钟信号和寄生信号对触控信号的干扰，从而改善了触控灵敏度。
已经针对附图给出了对本公开的特定示例性实施例的以上描述。这些示例性实施例并不意图是穷举性的或者将本公开局限于所公开的精确形式。明显的是，在以上教导的启示下，本领域普通技术人员能够做出许多修改和变化。因此，本公开的范围并不意图局限于前述的实施例，而是意图由权利要求和它们的等同方案所限定。

Claims (10)

  1. 一种阵列基板，包括：
    相互叠置的多个导电图案层；以及
    第一屏蔽环，所述第一屏蔽环与所述多个导电图案层中的第一导电图案层同层设置并且位于所述第一导电图案层周边。
  2. 根据权利要求1所述的阵列基板，其中
    所述多个导电图案层包括栅极图案层、源-漏电极层以及发光器件的阴极层和阳极层，并且
    所述第一导电图案层是所述阴极层、阳极层、源-漏电极层和栅极图案层中的一个。
  3. 根据权利要求2所述的阵列基板，还包括：
    第二屏蔽环，所述第二屏蔽环与所述多个导电图案层中的第二导电图案层同层设置并且位于所述第二导电图案层周边，其中
    所述第一导电图案层和所述第二导电图案层是从所述阴极层、阳极层、源-漏电极层和栅极图案层中选择的两个。
  4. 根据权利要求3所述的阵列基板，其中
    所述第一导电图案层是阴极层，
    所述第二导电图案层是阳极层，并且
    位于阴极层周边的第一屏蔽环和位于阳极层周边的第二屏蔽环通过形成在阵列基板的像素限定层中的第一通孔彼此电连接。
  5. 根据权利要求3所述的阵列基板，还包括：
    第三屏蔽环，所述第三屏蔽环与所述多个导电图案层中的第三导电图案层同层设置并且位于所述第三导电图案层周边，其中
    所述第一导电图案层是阴极层，所述第二导电图案层是阳极层，而所述第三导电图案层是源-漏电极层，
    位于阴极层周边的第一屏蔽环和位于阳极层周边的第二屏蔽环通过形成在阵列基板的像素限定层中的第一通孔彼此电连接，并且
    位于阳极层周边的第二屏蔽环和位于源-漏电极层周边的第三屏蔽环通过形成在平坦化层中的第二通孔彼此电连接。
  6. 根据权利要求5所述的阵列基板，还包括：
    第四屏蔽环，所述第四屏蔽环与所述多个导电图案层中的第四导 电图案层同层设置并且位于第四导电图案层周边，其中
    所述第四导电图案层是栅极图案层，并且
    位于源-漏电极层周边的第三屏蔽环和位于栅极图案层周边的第四屏蔽环通过形成在阵列基板的栅极绝缘层中的第三通孔彼此电连接。
  7. 根据权利要求2所述的阵列基板，还包括：
    第二屏蔽环，所述第二屏蔽环与所述多个导电图案层中的第二导电图案层同层设置并且位于所述第二导电图案层周边。
  8. 根据权利要求7所述的阵列基板，其中
    位于所述第一导电图案层周边的第一屏蔽环和位于所述第二导电图案层周边的第二屏蔽环彼此电连接。
  9. 根据权利要求1所述的阵列基板，其中
    所述第一屏蔽环通过跨接方式与所述第一导电图案层电绝缘。
  10. 一种嵌入式触摸显示面板，包括根据权利要求1-9中任一项所述的阵列基板。
PCT/CN2018/072083 2017-05-12 2018-01-10 阵列基板和包括其的嵌入式触摸显示面板 WO2018205671A1 (zh)

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