WO2018205653A1 - 公共电压补偿电路单元、显示面板、显示装置和显示面板的公共电压补偿方法 - Google Patents

公共电压补偿电路单元、显示面板、显示装置和显示面板的公共电压补偿方法 Download PDF

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Publication number
WO2018205653A1
WO2018205653A1 PCT/CN2018/070743 CN2018070743W WO2018205653A1 WO 2018205653 A1 WO2018205653 A1 WO 2018205653A1 CN 2018070743 W CN2018070743 W CN 2018070743W WO 2018205653 A1 WO2018205653 A1 WO 2018205653A1
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Prior art keywords
circuit
output
sub
common voltage
control
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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PCT/CN2018/070743
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English (en)
French (fr)
Inventor
赵剑
李环宇
陈沫
高吉磊
张杨
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Priority to US16/087,280 priority Critical patent/US11081078B2/en
Publication of WO2018205653A1 publication Critical patent/WO2018205653A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0257—Reduction of after-image effects

Definitions

  • the present disclosure relates to the field of display devices, and in particular to a common voltage compensation circuit unit, a display panel including the common voltage compensation circuit unit, a display device, and a common voltage using the common voltage compensation circuit unit Compensation method.
  • each pixel unit in the liquid crystal display panel includes a pixel electrode and a common electrode.
  • the electric field formed between the pixel electrode and the common electrode is used to control the deflection of the liquid crystal molecules in the pixel unit.
  • the voltage change on the liquid crystal display panel may cause voltage residual due to the existence of parasitic capacitance or storage capacitance. This voltage residual will affect the correctness of the display voltage, which may cause the afterimage to appear and affect the picture quality.
  • An object of the present disclosure is to provide an improved common voltage compensation circuit unit, a display panel including the common voltage compensation circuit unit, a display device, and a common voltage compensation method using the common voltage compensation circuit unit.
  • a common voltage compensation circuit unit including a trigger signal terminal, a common voltage output terminal, a design common voltage signal terminal, a power signal terminal, a compensation common voltage signal terminal, a reset signal terminal, a clock signal terminal, The trigger signal input sub-circuit, the first output sub-circuit, the control sub-circuit, the second output sub-circuit, and the reset sub-circuit.
  • the trigger signal input sub-circuit is configured to input the trigger signal input sub-circuit input terminal and the trigger signal input sub-circuit in response to receiving a first level signal at an input end of the trigger signal input sub-circuit The output is turned on.
  • An input end of the first output sub-circuit is electrically connected to the compensation common voltage signal end, a control end of the first output sub-circuit is electrically connected to the first node, and an output end of the first output sub-circuit is The common voltage output is electrically connected.
  • the first output sub-circuit is configured to, in response to receiving a third level signal at a control end of the first output sub-circuit, input an input of the first output sub-circuit to the first output sub-circuit
  • the output terminal is turned on, wherein an absolute value of the third level signal is greater than or equal to an absolute value of the first level signal, and a polarity of the third level signal is different from the first level signal The polarity is the same.
  • the first control end of the control sub-circuit is electrically connected to the clock signal end, and the second control end of the control sub-circuit is electrically connected to the second output end of the reset sub-circuit, and the control sub-circuit
  • An input end is electrically connected to the clock signal end, a second input end of the control sub-circuit is electrically connected to the trigger signal end, and a first output end of the control sub-circuit is electrically connected to the first node, And the second output of the control subcircuit is electrically connected to the second node.
  • the control subcircuit is configured to, in response to receiving the first level signal at a first control end of the control subcircuit, the second input of the control subcircuit and the control subcircuit An output is turned on, a first input of the control subcircuit is electrically coupled to a second output of the control subcircuit, and responsive to receiving a second electrical at a second control end of the control subcircuit a flat signal disconnecting the first input of the control subcircuit from the second output of the control subcircuit.
  • a first control end of the second output sub-circuit is electrically connected to the second node
  • a second control end of the second output sub-circuit is electrically connected to the reset signal end
  • the second output sub-circuit a third control terminal is electrically connected to the clock signal end
  • an input end of the second output sub-circuit is electrically connected to the design common voltage signal end
  • an output end of the second output sub-circuit and the common voltage The output is electrically connected.
  • the second output sub-circuit is configured to be responsive to a first control terminal of the second output sub-circuit, a second control terminal of the second output sub-circuit, and a third control terminal of the second output sub-circuit
  • the first level signal is received by at least one of the ones, and the input end of the second output sub-circuit is electrically coupled to the output end of the second output sub-circuit.
  • a first control end of the reset sub-circuit is electrically connected to the reset signal end
  • a second control end of the reset sub-circuit is electrically connected to the second node
  • a third control end of the reset sub-circuit The first node is electrically connected
  • the input end of the reset sub-circuit is electrically connected to the power signal terminal
  • the first output end of the reset sub-circuit is electrically connected to the first node
  • the third of the reset sub-circuit The output is electrically connected to the second node.
  • the reset subcircuit is configured to reset the first level signal in response to receiving the first level signal at at least one of a first control terminal of the reset subcircuit and a second control terminal of the reset subcircuit
  • An input of the subcircuit is electrically coupled to the first output of the reset subcircuit, and responsive to receiving the first level signal at a third control terminal of the reset subcircuit, the reset subcircuit
  • the input terminal is electrically connected to the second output terminal and the third output terminal of the reset sub-circuit.
  • the trigger signal input subcircuit includes a trigger input transistor.
  • the first pole and the control pole of the trigger input transistor are electrically connected to the input end of the trigger signal input sub-circuit, and the second pole of the trigger input transistor is electrically connected to the output end of the trigger signal input sub-circuit.
  • the first output subcircuit includes a display output transistor and a storage capacitor.
  • a control electrode of the display output transistor is electrically connected to a control end of the first output sub-circuit, a first pole of the display output transistor is electrically connected to the compensation common voltage signal end, and a second of the display output transistor The pole is electrically connected to the common voltage output.
  • a first end of the storage capacitor is electrically coupled to the first node, and a second end of the storage capacitor is electrically coupled to an output of the first output sub-circuit.
  • the control subcircuit includes a first control transistor, a second control transistor, and a third control transistor.
  • a control electrode of the first control transistor is electrically connected to a first control end of the control sub-circuit
  • a first pole of the first control transistor is electrically connected to a second input end of the control sub-circuit
  • a second pole of the first control transistor is electrically coupled to the first output of the control subcircuit.
  • a control pole and a first pole of the second control transistor are electrically connected to a first input end of the control sub-circuit
  • a second pole of the second control transistor is electrically connected to a second control end of the control sub-circuit connection.
  • a control electrode of the third control transistor is electrically connected to a second control terminal of the control sub-circuit, a first pole of the third control transistor is electrically connected to a first input end of the control sub-circuit, and A second pole of the third control transistor is electrically coupled to the second output of the control subcircuit.
  • the reset subcircuit includes a first reset transistor, a second reset transistor, a third reset transistor, and a fourth reset transistor.
  • a control electrode of the first reset transistor is electrically connected to a second control terminal of the reset sub-circuit, a first pole of the first reset transistor is electrically connected to an input end of the reset sub-circuit, and the first A second pole of the reset transistor is electrically coupled to the first output of the reset subcircuit.
  • a control electrode of the second reset transistor is electrically connected to a first control terminal of the reset sub-circuit, a first pole of the second reset transistor is electrically connected to an input end of the reset sub-circuit, and the second A second pole of the reset transistor is electrically coupled to the first output of the reset subcircuit.
  • a control electrode of the third reset transistor is electrically connected to a third control terminal of the reset sub-circuit, a first pole of the third reset transistor is electrically connected to an input end of the reset sub-circuit, and the third reset A second pole of the transistor is electrically coupled to a second output of the reset subcircuit.
  • a control electrode of the fourth reset transistor is electrically connected to a third control terminal of the reset sub-circuit, a first pole of the fourth reset transistor is electrically connected to an input end of the reset sub-circuit, and the fourth A second pole of the reset transistor is electrically coupled to a third output of the reset subcircuit.
  • the second output sub-circuit includes a first reset output transistor, a second reset output transistor, and a third reset output transistor.
  • a control electrode of the first reset output transistor is electrically connected to a second control terminal of the second output sub-circuit, and a first pole of the first reset output transistor is electrically connected to an input end of the second output sub-circuit And the second pole of the first reset output transistor is electrically coupled to the output of the second output subcircuit.
  • a control pole of the second reset output transistor is electrically connected to a third control terminal of the second output sub-circuit, and a first pole of the second reset output transistor is electrically connected to an input end of the second output sub-circuit And the second pole of the second reset output transistor is electrically coupled to the output of the second output subcircuit.
  • a control electrode of the third reset output transistor is electrically connected to a first control end of the second output sub-circuit, and a first pole of the third reset output transistor is electrically connected to an input end of the second output sub-circuit And a second pole of the third reset output transistor is electrically coupled to an output of the second output subcircuit.
  • a display panel including a plurality of any one of the above-described common voltage compensation circuit units, a plurality of gate lines, a plurality of common electrode lines, a first clock signal line, and a second Clock signal line, power signal line, design common voltage signal line, and compensation common voltage signal line.
  • each common voltage compensation circuit unit is electrically connected to the corresponding common electrode line, and the trigger signal end of each common voltage compensation circuit unit is electrically connected to the corresponding gate line, and the reset signal of each common voltage compensation circuit unit is The terminal is electrically connected to the corresponding other gate line, and the power signal end of each common voltage compensation circuit unit is electrically connected to the power signal line, and the design common voltage signal end of each common voltage compensation circuit unit is electrically connected to the design common voltage signal line. And the compensation common voltage signal terminal of each common voltage compensation circuit unit is electrically connected to the compensation common voltage signal line.
  • the clock signal terminal of the common voltage compensation circuit unit is electrically connected to the first clock signal line; when the common voltage compensation circuit unit corresponds to the common electrode line of the even row The clock signal terminal of the common voltage compensation circuit unit is electrically connected to the second clock signal line.
  • the compensation common voltage signal line is electrically connected to the common voltage generating chip.
  • the common voltage generating chip is configured to provide a first level signal in response to a first clock signal line or a second clock signal line connected to a clock signal terminal of the common voltage compensation circuit unit, and provide a design common to the compensation common voltage signal line
  • the voltage signal provides a second level signal in response to the first clock signal line or the second clock signal line connected to the clock signal terminal of the common voltage compensation circuit unit, and provides a compensation common voltage signal to the compensation common voltage signal line.
  • the display panel includes a plurality of rows of pixel units, each row of pixel units includes a plurality of pixel units, and the plurality of rows of pixel units are respectively in one-to-one correspondence with the plurality of rows of common electrodes.
  • the common voltage generating chip is configured to calculate the compensated common voltage signal according to formula (1) and formula (2):
  • ComN is a voltage value of a design common voltage signal for the pixel unit of the Nth row corresponding to the common voltage compensation circuit unit;
  • Com'N is a voltage value of a compensation common voltage signal for the pixel unit of the Nth row
  • Vgh is the voltage value of the first level signal
  • Vgl is the voltage value of the second level signal
  • Cgd is a capacitance between a gate and a drain of a thin film transistor of one of the pixel units of the Nth row;
  • Cs is a storage capacitor of the pixel unit
  • Clc is the liquid crystal capacitance of the pixel unit.
  • the common electrode line is in one-to-one correspondence with the common voltage compensation circuit unit.
  • a display device including any of the above display panels is provided.
  • a common voltage compensation method of a display panel using any of the above-described common voltage compensation circuit units includes an input phase, a display output phase, and a reset phase.
  • the first level signal is input from the trigger signal terminal
  • the second level signal is input from the clock signal terminal
  • the second level signal is input from the reset signal terminal
  • the design common voltage signal is input from the compensation common voltage signal terminal.
  • a second level signal is input from the trigger signal terminal, a second level signal is input from the clock signal terminal, and a compensation common voltage signal is input from the compensation common voltage signal terminal.
  • the first level signal is input from the clock signal terminal
  • the second level signal is input from the trigger signal terminal
  • the first level signal is input from the reset signal terminal
  • the design common voltage signal is input from the design common voltage signal terminal.
  • the compensated common voltage signal is calculated according to equations (1) and (2):
  • ComN is a voltage value of a design common voltage signal for the pixel unit of the Nth row corresponding to the common voltage compensation circuit unit;
  • Com'N is a voltage value of a compensation common voltage signal for the pixel unit of the Nth row
  • Vgh is the voltage value of the first level signal
  • Vgl is the voltage value of the second level signal
  • Cgd is a capacitance between a gate and a drain of a thin film transistor of one of the pixel units of the Nth row;
  • Cs is a storage capacitor of the pixel unit
  • Clc is the liquid crystal capacitance of the pixel unit.
  • the effect of the parasitic capacitance on the common voltage input to the common electrode line is eliminated by providing the compensation common voltage in the display output stage, thereby The deflection of the liquid crystal molecules in the pixel unit is precisely controlled, the afterimage is eliminated, and the display effect of the display panel including the common voltage compensation circuit unit is improved.
  • FIG. 1 is a schematic structural diagram of a common voltage compensation circuit unit according to an embodiment of the present disclosure
  • FIG. 2 is a timing diagram of operation signals of a common voltage compensation circuit unit according to an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a specific structure of a common voltage compensation circuit unit according to an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of a portion of a display panel provided by an embodiment of the present disclosure.
  • FIG. 5 is a flowchart of a common voltage compensation method provided by an embodiment of the present disclosure.
  • a common voltage compensation circuit unit including a trigger signal terminal Gate N-1, a common voltage output terminal VcomN, a design common voltage signal terminal Com, a power signal terminal Vss, and compensation.
  • Common voltage signal terminal Com'N reset signal terminal Gate N+1, clock signal terminal CLKB, trigger signal input sub-circuit 100, first output sub-circuit 200, control sub-circuit 300, second output sub-circuit 400, and reset sub-circuit 500.
  • the input end of the trigger signal input sub-circuit 100 is electrically connected to the trigger signal terminal Gate N-1, and the output end of the trigger signal input sub-circuit 100 is electrically connected to the first node PU.
  • the trigger signal input sub-circuit 100 is configured to input the trigger signal to the input of the sub-circuit 100 and the output of the trigger signal input sub-circuit 100 in response to receiving the first level signal at the input of the trigger signal input sub-circuit 100. through.
  • the input end of the first output sub-circuit 200 is electrically connected to the compensation common voltage signal terminal Com'N, the control end of the first output sub-circuit 200 is electrically connected to the first node PU, and the output end of the first output sub-circuit 200 is common to The voltage output terminal Vcom N is electrically connected.
  • the first output sub-circuit 200 is configured to conduct the input of the first output sub-circuit 200 with the output of the first output sub-circuit 200 in response to receiving the third level signal at the control terminal of the first output sub-circuit 200.
  • the absolute value of the third level signal is greater than or equal to the absolute value of the first level signal, and the polarity of the third level signal is the same as the polarity of the first level signal.
  • the first control terminal of the control sub-circuit 300 is electrically connected to the clock signal terminal CLKB, and the second control terminal of the control sub-circuit 300 is electrically connected to the second output terminal of the reset sub-circuit 500, and the first input terminal and the clock of the control sub-circuit 300 are controlled.
  • the signal terminal CLKB is electrically connected
  • the second input end of the control sub-circuit 300 is electrically connected to the trigger signal terminal Gate N-1
  • the first output end of the control sub-circuit 300 is electrically connected to the first node PU
  • the control sub-circuit 300 is The two outputs are electrically connected to the second node PD.
  • the control sub-circuit 300 is configured to, in response to receiving the first level signal at the first control terminal of the control sub-circuit 300, conduct the second input of the control sub-circuit 300 with the first output of the control sub-circuit 300,
  • the first input of the control sub-circuit 300 is electrically connected to the second output of the control sub-circuit 300, and in response to receiving the second level signal at the second control end of the control sub-circuit 300, the control sub-circuit 300 An input is disconnected from the second output of control subcircuit 300.
  • the first control end of the second output sub-circuit 400 is electrically connected to the second node PD, the second control end of the second output sub-circuit 400 is electrically connected to the reset signal terminal Gate N+1, and the third output sub-circuit 400 is third.
  • the control terminal is electrically connected to the clock signal terminal CLKB, the input terminal of the second output sub-circuit 400 is electrically connected to the design common voltage signal terminal Com, and the output terminal of the second output sub-circuit 400 is electrically connected to the common voltage output terminal Vcom N.
  • the second output sub-circuit 400 is configured to be responsive to at least one of a first control terminal of the second output sub-circuit 400, a second control terminal of the second output sub-circuit 400, and a third control terminal of the second output sub-circuit 400
  • the first level signal is received, and the input end of the second output sub-circuit 400 is turned on with the output end of the second output sub-circuit 400.
  • the first control terminal of the reset sub-circuit 500 is electrically connected to the reset signal terminal Gate N+1, and the second control terminal of the reset sub-circuit 500 is electrically connected to the second node PD, and the input terminal of the reset sub-circuit 500 and the power signal terminal Vss are electrically connected.
  • the first output end of the connection sub-circuit 500 is electrically connected to the first node PU, the third control end of the reset sub-circuit 500 is electrically connected to the first node PU, and the third output end and the second node of the reset sub-circuit 500 are The PD is electrically connected.
  • the reset sub-circuit 500 is configured to respond to the input of the reset sub-circuit 500 in response to receiving the first level signal at at least one of the first control terminal of the reset sub-circuit 500 and the second control terminal of the reset sub-circuit 500
  • the first output of the reset sub-circuit 500 is turned on, and in response to receiving the first level signal at the third control terminal, the input of the reset sub-circuit 500 and the second output of the reset sub-circuit 500 and the third The output is turned on.
  • the display panel includes a plurality of gate lines Gate n-2, Gate n, Gate n-1, ... and a plurality of data lines that intersect horizontally and vertically, and each of the gate lines and the data lines cross Corresponds to one pixel unit.
  • the gate lines are used to provide drive signals to each row of pixel cells, and the data lines are used to provide data signals to each column of pixel cells.
  • the display panel further includes a gate driving circuit, and the gate driving circuit includes a shift register unit corresponding to the gate lines in one-to-one, wherein the shift register unit is configured to sequentially supply driving signals to the corresponding gate lines.
  • the output of the Nth stage shift register unit is electrically connected to the Nth gate line.
  • the common voltage compensation circuit unit When used in a display panel, the common voltage compensation circuit unit corresponds to the Nth row of pixel units in the display panel, and the common voltage output terminal VcomN of the common voltage compensation circuit unit passes through the Nth common electrode line and the Nth row
  • the common electrodes of the pixel cells are electrically connected to provide a common voltage signal to the common electrodes of the Nth row of pixel cells.
  • the trigger signal terminal Gate N-1 of the common voltage compensation circuit unit is electrically connected to the N-1th gate line Gate n-1, and the reset signal terminals Gate N+1 and the N+1th gate line of the common voltage compensation circuit unit are connected. Gate n+1 is electrically connected.
  • first level signal indicates a high level signal and the other indicates a low level signal.
  • the transistor used in the common voltage compensation circuit unit is an N-type transistor
  • the first level signal indicates a high level signal
  • the second level signal indicates a low level signal.
  • the transistor used in the common voltage compensation circuit unit is a P-type transistor
  • the first level signal indicates a low level signal
  • the second level signal indicates a high level signal.
  • each duty cycle of the common voltage compensation circuit unit includes three working phases: an input phase t1, a display output phase t2, and a reset phase t3.
  • the operation of the common voltage compensation circuit unit is illustrated by taking the transistor used in the common voltage compensation circuit unit as an N-type transistor as an example.
  • the present disclosure is not limited to this. It is assumed that the signal supplied from the compensation common voltage signal terminal Com'N is a square wave, and the design common voltage signal or the compensation common voltage signal is supplied at different stages.
  • the first level signal is input from the trigger signal terminal Gate N-1
  • the second level signal is input from the clock signal terminal CLKB
  • the second level signal is input from the reset signal terminal Gate N+1
  • the compensation is from the compensation.
  • the common voltage signal terminal ComN inputs a design common voltage signal.
  • the trigger signal input sub-circuit 100 turns on the input of the trigger signal input sub-circuit 100 and the output end of the trigger signal input sub-circuit 100 in response to receiving the first level signal at its input, and thus The first level signal provided by the trigger signal terminal Gate N-1 is stored at the first node PU.
  • the control terminal of the first output sub-circuit 200 Since the control terminal of the first output sub-circuit 200 is electrically connected to the first node PU, the first level signal is received at the control terminal of the first output sub-circuit 200.
  • the third control terminal of the reset sub-circuit 500 receives the first level signal such that the input terminal of the reset sub-circuit 500 is turned on with the second output terminal of the reset sub-circuit 500, and thus the second control of the control sub-circuit 300 A second level signal is received at the end.
  • the third control terminal of the reset sub-circuit 500 receives the first level signal such that the input terminal of the reset sub-circuit 500 is turned on with the third output terminal of the reset sub-circuit 500.
  • a second level signal is received at the first control terminal of the second output sub-circuit 400. Since the control terminal of the first output sub-circuit 200 receives the first level signal, the input terminal of the first output sub-circuit 200 is turned on. Since the signal input from the compensation common voltage signal terminal Com'N at this time is a design common voltage signal, the signal output from the common voltage output terminal VcomN is a design common voltage signal.
  • the second level signal is input from the trigger signal terminal Gate N-1, the second level signal is input from the clock signal terminal CLKB, and the compensation common voltage signal is input from the compensation common voltage signal terminal Com'N. Since the second level signal is received at the input of the trigger signal input sub-circuit 100, the input of the trigger signal input sub-circuit 100 is disconnected from the output. In the case where the input terminal of the trigger signal input sub-circuit 100 is disconnected from the output terminal, the signal at the control terminal of the first output sub-circuit 200 will jump to the third level signal such that the input of the first output sub-circuit 200 The terminal is electrically connected to the output terminal, so that the common voltage output terminal VcomN outputs a compensation common voltage signal.
  • the control terminal of the first output sub-circuit 200 is electrically connected to the third control terminal of the reset sub-circuit 500
  • the input terminal of the reset sub-circuit 500 is electrically connected to the third output terminal of the reset sub-circuit 500, so that A second level signal is received at the second node PD.
  • the first control terminal of the second output sub-circuit 400 is electrically connected to the second node PD
  • the second control terminal of the second output sub-circuit 400 is electrically connected to the reset signal terminal Gate N+1. Therefore, the second output sub-circuit 400
  • the input terminal is disconnected from the output terminal to ensure that the signal outputted by the common voltage output terminal is a compensation common voltage signal.
  • the first level signal is input from the clock signal terminal CLKB
  • the second level signal is input from the trigger signal terminal Gate N-1
  • the first level signal is input from the reset signal terminal Gate N+1. Therefore, the input end of the trigger signal input sub-circuit 100 is disconnected from the output end, and the input end of the reset sub-circuit 500 is electrically connected to the first output end, so that the second level signal is received at the first node PU, thereby The control terminal of an output sub-circuit 200 is reset.
  • the third control terminal of the second output sub-circuit 400 receives the first level signal input from the clock signal terminal CLKB, the input terminal and the output terminal of the second output sub-circuit 400 are turned on, so that the common The signal output from the voltage signal output is a design common voltage signal input from the design common voltage signal terminal Com.
  • the common voltage compensation circuit unit supplies the design common voltage signal to the corresponding common electrode line in the input phase t1 and the reset phase t2 during operation, and provides the compensation common voltage to the corresponding common electrode line in the display output phase t2. signal.
  • the compensation common voltage can be calculated according to the following formula (1) and formula (2):
  • ComN is a voltage value of a design common voltage signal for the pixel unit of the Nth row corresponding to the common voltage compensation circuit unit;
  • Com'N is a voltage value of a compensation common voltage signal for the pixel unit of the Nth row
  • Vgh is the voltage value of the first level signal
  • Vgl is the voltage value of the second level signal
  • Cgd is a capacitance between a gate and a drain of a thin film transistor of one of the pixel units of the Nth row;
  • Cs is a storage capacitor of the pixel unit
  • Clc is the liquid crystal capacitance of the pixel unit.
  • the influence of the parasitic capacitance on the common voltage input to the common electrode line can be eliminated in the display output stage, thereby accurately controlling the deflection of the liquid crystal molecules in the pixel unit, eliminating the afterimage, and improving the display effect of the display panel.
  • the common voltage compensation circuit unit still outputs a design common voltage to the corresponding common electrode line, and thus does not affect the deflection state of the liquid crystal molecules in other pixel units that do not participate in the display output.
  • the common voltage compensation circuit unit utilizes the output signals of the previous stage and the subsequent stage shift register unit as the trigger signal and the reset signal, respectively, it is possible to synchronize with the corresponding shift register unit so as to be able to pass the corresponding common electrode
  • the line controls the voltage on the corresponding common electrode of the display panel at a precise moment, so that a better driving and display effect can be achieved.
  • each sub-circuit is not particularly limited as long as the functions described above can be realized at various stages of the display period.
  • FIG. 3 illustrates a circuit diagram of a common voltage compensation circuit unit in accordance with one embodiment of the present disclosure.
  • the trigger signal input sub-circuit 100 includes a trigger input transistor M1, and the first pole and the control pole of the trigger input transistor M1 are electrically connected to the input end of the trigger signal input sub-circuit 100 (ie, the gate of the trigger input transistor M1 is triggered). And the first pole is electrically connected to the trigger signal terminal Gate N-1), and the second pole of the trigger input transistor M1 is electrically connected to the output end of the trigger signal input sub-circuit 100.
  • the trigger input transistor M1 When the first level signal is input from the trigger signal terminal Gate N-1, the trigger input transistor M1 is turned on, thereby transmitting the first level signal input from the trigger signal terminal Gate N-1 to the first output sub-circuit 200. Control terminal. When the second level signal is input from the trigger signal terminal Gate N-1, the trigger input transistor M1 is turned off.
  • the first output sub-circuit 200 includes a display output transistor M3 and a storage capacitor C1.
  • the control electrode of the display output transistor M3 is electrically connected to the control terminal of the first output sub-circuit 200, and the first electrode of the display output transistor M3 is electrically connected to the compensation common voltage signal terminal Com'N, and the display output is
  • the second pole of transistor M3 is electrically coupled to a common voltage output terminal Vcom N .
  • the first end of the storage capacitor C1 is electrically coupled to the first node PU, and the second end of the storage capacitor C1 is electrically coupled to the output of the first output sub-circuit 200.
  • the display output transistor M3 When the gate of the display output transistor M3 receives the first level signal, the display output transistor M3 is turned on, thereby turning on the compensation common voltage signal terminal Com'N and the common voltage output terminal Vcom N.
  • control sub-circuit 300 includes a first control transistor M13, a second control transistor M9, and a third control transistor M5.
  • the control electrode of the first control transistor M13 is electrically connected to the first control terminal of the control sub-circuit 300 (ie, electrically connected to the clock signal terminal CLKB), and the first pole and control of the first control transistor M13
  • the second input of the sub-circuit 300 is electrically connected (ie, electrically coupled to the trigger signal terminal Gate N-1), and the second electrode of the first control transistor M13 is electrically coupled to the first output of the control sub-circuit 300 (ie, Electrically connected to the first node PU).
  • the control electrode and the first pole of the second control transistor M9 are electrically connected to the first input terminal of the control sub-circuit 300 (ie, electrically connected to the clock signal terminal CLKB), and the second electrode of the second control transistor M9 and the control sub-circuit The second control terminal of 300 is electrically connected.
  • the control electrode of the third control transistor M5 is electrically connected to the second control terminal of the control sub-circuit 300 (ie, electrically connected to the second electrode of the second control transistor M9), and the first pole and the control sub-circuit of the third control transistor M5
  • the first input of the 300 is electrically coupled (ie, electrically coupled to the clock signal terminal CLKB)
  • the second electrode of the third control transistor M5 is electrically coupled to the second output of the control subcircuit (ie, electrically coupled to the second node PD) connection).
  • the first level signal When the first level signal is input from the clock signal terminal CLKB, the first level signal is received at the first control terminal of the control sub-circuit 300 such that both the first control transistor M13 and the second control transistor M9 are turned on.
  • the second level signal when the first level signal is input from the clock signal terminal CLKB, the second level signal is input from the trigger signal terminal Gate N-1, and thus, through the control sub-circuit 300 to the first output sub-circuit 200 The control terminal outputs a second level signal to ensure that the input and output terminals of the first output sub-circuit 200 are disconnected.
  • the conduction of the second control transistor M9 can transmit the first level signal input through the clock signal terminal CLKB to the control electrode of the third control transistor M5, so that the third control transistor M5 is turned on and will eventually pass.
  • the first level signal input from the clock signal terminal CLKB is transmitted to the second node PD.
  • the main purpose of setting the reset sub-circuit 500 is to reset the control terminal of the first output sub-circuit 200 after the end of the display output phase, and to ensure that the common voltage compensation circuit unit outputs the design common voltage signal end in all stages except the display output stage.
  • Com provides a common voltage design.
  • the specific structure of the reset sub-circuit 500 is not particularly limited.
  • the reset sub-circuit 500 may include a first reset transistor M10, a second reset transistor M2, a third reset transistor M8, and a fourth reset transistor M6.
  • the control electrode of the first reset transistor M10 is electrically connected to the second control terminal of the reset sub-circuit 500 (ie, electrically connected to the second node PD), and the first pole of the first reset transistor M10 is reset.
  • the input of the sub-circuit 500 is electrically connected (ie, electrically connected to the power signal terminal Vss), and the second pole of the first reset transistor M10 is electrically coupled to the first output of the reset sub-circuit 500 (ie, with the first node PU) Electrical connection).
  • the control electrode of the second reset transistor M2 is electrically connected to the first control terminal of the reset sub-circuit 500, and the first electrode of the second reset transistor M2 is electrically connected to the input of the reset sub-circuit 500 (ie, electrically connected to the power signal terminal Vss) And the second pole of the second reset transistor M2 is electrically connected to the first output terminal of the reset sub-circuit 500 (ie, electrically connected to the first node PU).
  • the control electrode of the third reset transistor M8 is electrically connected to the third control terminal of the reset sub-circuit 500 (ie, electrically connected to the first node PU), and the first pole of the third reset transistor M8 is electrically connected to the input terminal of the reset sub-circuit 500.
  • the connection ie, electrically connected to the power signal terminal Vss
  • the second pole of the third reset transistor M8 is electrically coupled to the second output of the reset sub-circuit 500 (ie, electrically coupled to the second node PD).
  • the gate of the fourth reset transistor M6 is electrically connected to the third control terminal of the reset sub-circuit 500 (ie, electrically connected to the first node PU), and the first terminal of the fourth reset transistor M6 is electrically connected to the input terminal of the reset sub-circuit 500.
  • the connection ie, electrically connected to the power signal terminal Vss
  • the second pole of the fourth reset transistor M6 is electrically coupled to the third output of the reset sub-circuit 500 (ie, electrically coupled to the second node PD).
  • the reset sub-circuit 500 includes three control terminals, the output signals of the respective output terminals (including the first output terminal, the second output terminal, and the third output terminal) of the reset sub-circuit 500 are controlled by three kinds of control signals.
  • the output of the reset sub-circuit 500 will be described in detail below with reference to FIG. 2, which will not be described here.
  • the primary role of the second output sub-circuit 400 is to ensure that the common voltage compensation circuit unit is capable of outputting a design common voltage signal during the reset phase t3.
  • the specific structure of the second output sub-circuit 400 is also not particularly limited.
  • the second output sub-circuit 400 may include a first reset output transistor M11, a second reset output transistor M12, and a third reset output transistor M4.
  • the control electrode of the first reset output transistor M11 is electrically connected to the second control terminal of the second output sub-circuit 400 (ie, electrically connected to the reset signal terminal Gate N+1), and the first pole and the first reset output transistor M11
  • the input terminal of the two output sub-circuit 400 is electrically connected (ie, electrically connected to the design common voltage signal terminal Com)
  • the second electrode of the first reset output transistor M11 is electrically connected to the output of the second output sub-circuit 400 (ie, Electrically connected to the common voltage output terminal Vcom N).
  • the control electrode of the second reset output transistor M12 is electrically connected to the third control terminal of the second output sub-circuit 400, and the first electrode of the second reset output transistor M12 is electrically connected to the input terminal of the second output sub-circuit 400 (ie, The common voltage signal terminal Com is electrically connected), and the second electrode of the second reset output transistor M12 is electrically connected to the output of the second output sub-circuit 400 (ie, electrically connected to the common voltage output terminal Vcom N).
  • the control electrode of the third reset output transistor M4 is electrically connected to the first control terminal of the second output sub-circuit 400 (ie, electrically connected to the second node PD), and the first and second output terminals of the third reset output transistor M4
  • the input of circuit 400 is electrically coupled (ie, electrically coupled to design common voltage signal terminal Com), and the second pole of third reset output transistor M4 is electrically coupled to the output of second output sub-circuit 400 (ie, with a common voltage)
  • Output Vcom N is electrically connected).
  • the input terminal and the output of the second output sub-circuit 400 The terminal is turned on so that the common voltage output terminal Vcom N outputs a design common voltage signal.
  • transistors are typically three-terminal components.
  • the terminal that controls the transistor to be turned on and off is referred to as its "control electrode”, and the other two terminals are referred to as “first pole” and “second pole”, respectively.
  • first pole can be the drain
  • second pole can be the source.
  • the common voltage compensating circuit unit shown in Fig. 3 it is assumed that all the transistors are N-type transistors, and accordingly, the first level signal is a high level signal, and the second level signal is a low level signal.
  • the signal supplied from the compensation common voltage signal terminal Com'N is a square wave, and the design common voltage signal or the compensation common voltage signal is provided at different stages.
  • one duty cycle of the common voltage compensation circuit unit shown in FIG. 3 includes an input phase t1, a display output phase t2, and a reset phase t3.
  • the first level signal is received from the trigger signal terminal Gate N-1
  • the second level signal is received from the clock signal terminal CLKB
  • the second level signal is received from the reset signal terminal Gate N+1.
  • the first and second poles of the trigger input transistor M1 are turned on, thereby transmitting the first level signal input from the trigger signal terminal Gate N-1 to the control terminal of the first output sub-circuit 200, and the storage capacitor C1 is charged.
  • the first level signal input through the trigger signal terminal Gate N-1 is stored in the storage capacitor C1, and the first level signal is received at the gate electrode of the display output transistor M3, thus, the output transistor is displayed. M3 is turned on.
  • the signal supplied from the compensation common voltage signal terminal Com'N is a design common voltage signal, and therefore, the design common voltage signal is outputted from the common voltage output terminal Vcom.
  • the signal input from the clock signal terminal CLKB is the second level signal
  • the first control transistor M13, the second control transistor M9, and the second reset output transistor M12 are all turned off, the fourth reset transistor M6 and the third reset.
  • the transistor M8 is turned on, and thus the second level signal input from the power signal terminal Vss is transmitted to the gate of the third control transistor M5, so that the third control transistor M5 is also turned off.
  • the second level signal is input from the trigger signal terminal Gate N-1, the second level signal is input from the reset signal terminal Gate N+1, and the second level signal is input from the clock signal terminal CLKB. Therefore, the trigger input transistor M1 is turned off, and the first control transistor M13 is turned off. At this time, the first node PU is in a floating state. Since the display output transistor M3 is turned on in the previous stage t1, the display output transistor M3 is still turned on in the display output stage t2, thereby transmitting the compensated common voltage signal input from the compensation common voltage signal terminal ComN to the storage capacitor C1. Second end.
  • the potential of the first node PU electrically connected to the first end of the storage capacitor C1 will be pulled up to the third level signal, so that the display output transistor M3 remains turned on.
  • the signal output from the common voltage output terminal Vcom N is the compensation common voltage signal supplied from the compensation common voltage signal terminal Com'N.
  • the input terminal and the output terminal of the reset sub-circuit 500 and the second output sub-circuit 400 are both disconnected, so that the output of the common voltage compensation circuit unit is not affected.
  • the first level signal is input from the clock signal terminal CLKB, and therefore, the first control transistor M13 and the second control transistor M9 are turned on, so that the second level signal input from the trigger signal terminal Gate N-1 is turned on. Transfer to the first node PU. Since the second control transistor M9 is turned on, the third control transistor M5 is also turned on to transmit the first level signal input from the clock signal terminal CLKB to the second node PD, thereby causing the third reset output transistor M4 to be guided.
  • the design common voltage input from the design common voltage signal terminal Com is transmitted to the common voltage output terminal Vcom N.
  • the common voltage compensation circuit unit shown in FIG. 3 outputs a compensation common voltage signal in the display output stage and a design common voltage signal in the remaining stages during operation.
  • the compensation common voltage can be calculated according to the following formula:
  • the ComN is a voltage value of a design common voltage signal for the pixel unit of the Nth row corresponding to the common voltage compensation circuit unit;
  • Com'N is a voltage value for compensating the common voltage signal of the pixel unit of the Nth row.
  • Vgh is the voltage value of the first level signal
  • Vgl is a voltage value of the second level signal
  • Cgd is a parasitic capacitance between a gate and a drain of a thin film transistor in one of the pixel cells in the Nth row;
  • Cs is a storage capacitor of the pixel unit
  • Clc is the liquid crystal capacitance of the pixel unit.
  • the size of the thin film transistor, the size of the pixel electrode, and the size of the common electrode are known, and the magnitude of the common voltage, the voltage value of the first level signal, and the voltage of the second level signal are designed.
  • the values are all known, and therefore, the parasitic capacitance between the gate and the drain is easily obtained by calculation. Therefore, the voltage value at which the compensated common voltage signal is obtained can be calculated using the above formula.
  • the display panel includes a plurality of the above-described common voltage compensation circuit units cascaded.
  • the display panel includes a plurality of cascaded common voltage compensation circuit units 100, a plurality of gate lines Gate n-2, Gate n-1, Gate n, and the like, and a plurality of common electrode lines Vcom n-1.
  • Vcom n, Vcom n+1, etc. the first clock signal line CLKa, the second clock signal line CLKb, the power signal line Vss, the design common voltage signal line com, and the compensation common voltage signal line com'.
  • the common voltage output terminal VcomN of each common voltage compensation circuit unit 100 is electrically connected to the corresponding common electrode line Vcom n , and the trigger signal terminal Gate N-1 of each common voltage compensation circuit unit 100 and the corresponding gate line Gate n-1 Electrically connected, the reset signal terminal Gate N+1 of each common voltage compensation circuit unit 100 is electrically connected to the corresponding other gate line Gate n+1, and the power signal terminal Vss and the power signal line of each common voltage compensation circuit unit 100 are electrically connected.
  • the Vss is electrically connected, and the design common voltage signal terminal Com of each common voltage compensation circuit unit 100 is electrically connected to the design common voltage signal line com, and the compensation common voltage signal terminal Com'N of each common voltage compensation circuit unit 100 and the compensation common The voltage signal line com' is electrically connected.
  • the clock signal terminal CLKB of the common voltage compensation circuit unit 100 is electrically connected to the first clock signal line CLKa; when the common voltage compensation circuit unit 100 corresponds to the even line
  • the common signal line terminal CLKB of the common voltage compensation circuit unit 100 is electrically connected to the second clock signal line CLKb.
  • the compensation common voltage signal line com' is electrically connected to the common voltage generating chip 200.
  • the common voltage generating chip 200 supplies the compensation common voltage signal line com' Designing a common voltage signal;
  • the common voltage generating chip 200 compensates the common voltage
  • the signal line com' provides a compensation common voltage signal.
  • FIG. 4 only shows a portion of the display panel, while other components necessary for the display panel are omitted so as not to obscure the understanding of the present disclosure. It should be noted that in FIG. 4, the values of N and n are the same, and the function is only to distinguish each port and the gate line and the common electrode line in the common voltage compensation circuit unit. For convenience of description, the following assumptions N and n are even numbers.
  • the n-1th row common electrode line Vcom n-1 is electrically connected to the common voltage output terminal Vcom N-1 of the corresponding N-1th stage common voltage compensation circuit unit 100.
  • the trigger signal terminal Gate N-2 of the N-1th stage common voltage compensation circuit unit 100 is electrically connected to the n-2th gate line Gate n-2.
  • the clock signal terminal CLKB of the N-1th stage common voltage compensation circuit unit 100 is electrically connected to the first clock signal line CLKa.
  • the compensated common voltage signal terminal Com'N-1 of the N-1th stage common voltage compensation circuit unit 100 is electrically connected to the compensated common voltage signal line com'.
  • the design common voltage terminal Com of the N-1th common voltage compensation circuit unit 100 is electrically connected to the design common voltage signal line com.
  • the power signal terminal Vss of the N-1th common voltage compensation circuit unit 100 is electrically connected to the power signal line Vss.
  • the nth row common electrode line Vcom n is electrically connected to the common voltage output terminal Vcom N of the corresponding Nth stage common voltage compensation circuit unit 100.
  • the trigger signal terminal Gate N-1 of the Nth stage common voltage compensation circuit unit 100 is electrically connected to the n-1th gate line Gate n-1.
  • the clock signal terminal CLKB of the Nth stage common voltage compensation circuit unit 100 is electrically connected to the second clock signal line CLKb.
  • the compensated common voltage signal terminal Com'N of the Nth stage common voltage compensation circuit unit 100 is electrically connected to the compensated common voltage signal line com'.
  • the design common voltage signal terminal Com of the Nth stage common voltage compensation circuit unit 100 is electrically connected to the design common voltage signal line com.
  • the power signal terminal Vss of the Nth stage common voltage compensation circuit unit 100 is electrically connected to the power signal line Vss.
  • the n+1th row common electrode line Vcom n+1 is electrically connected to the common voltage output terminal Vcom N+1 of the corresponding N+1th stage common voltage compensation circuit unit 100.
  • the trigger signal terminal Gate N of the (N+1)th common voltage compensation circuit unit 100 is electrically connected to the nth gate line Gate n.
  • the clock signal terminal CLKB of the (N+1)th common voltage compensation circuit unit 100 is electrically connected to the first clock signal line CLKa.
  • the compensated common voltage signal terminal Com'N+1 of the (N+1)th common voltage compensation circuit unit 100 is electrically connected to the compensated common voltage signal line com'.
  • the design common voltage signal terminal Com of the (N+1)th common voltage compensation circuit unit 100 is electrically connected to the design common voltage signal line com.
  • the power signal terminal Vss of the (N+1)th common voltage compensation circuit unit 100 is electrically connected to the power signal line Vss.
  • the n+2th common electrode line Vcom n+2 is electrically connected to the common voltage output terminal Vcom N+2 of the corresponding N+2th common voltage compensation circuit unit 100.
  • the trigger signal terminal Gate N+1 of the N+2th common voltage compensation circuit unit 100 is electrically connected to the n+1th gate line Gate n.
  • the clock signal terminal CLKB of the N+2th common voltage compensation circuit unit 100 is electrically connected to the second clock signal line CLKb.
  • the compensated common voltage signal terminal Com'N+2 of the N+2th common voltage compensation circuit unit 100 is electrically connected to the compensated common voltage signal line com'.
  • the design common voltage signal terminal Com of the N+2 stage common voltage compensation circuit unit 100 is electrically connected to the design common voltage signal line com.
  • the power signal terminal Vss of the N+2th common voltage compensation circuit unit 100 is electrically connected to the power signal line Vss.
  • the above connection method can ensure that the common voltage compensation circuit unit operates synchronously with the corresponding gate line, thereby performing accurate common voltage compensation for each row of pixel units.
  • the display panel includes a plurality of rows of pixel units, each row of pixel units includes a plurality of pixel units, and the plurality of rows of pixel units are respectively in one-to-one correspondence with the plurality of rows of common electrodes.
  • the common voltage generating chip may calculate the compensated common voltage signal according to the following formula (1) and formula (2):
  • ComN is a voltage value of a design common voltage signal for the pixel unit of the Nth row corresponding to the common voltage compensation circuit unit;
  • Com'N is a voltage value of a compensation common voltage signal for the pixel unit of the Nth row
  • Vgh is the voltage value of the first level signal
  • Vgl is the voltage value of the second level signal
  • Cgd is a capacitance between a gate and a drain of a thin film transistor of one of the pixel units of the Nth row;
  • Cs is a storage capacitor of the pixel unit
  • Clc is the liquid crystal capacitance of the pixel unit.
  • each common electrode line corresponds to a common voltage compensation circuit unit.
  • a display device including the above display panel.
  • the common voltage compensation method 500 includes an input phase 502, a display output phase 504, and a reset phase 506.
  • a first level signal is input from the trigger signal terminal, a second level signal is input from the clock signal terminal, a second level signal is input from the reset signal terminal, and a design common voltage is input from the compensation common voltage signal terminal. signal.
  • a second level signal is input from the trigger signal terminal, a second level signal is input from the clock signal terminal, and a compensation common voltage signal is input from the compensation common voltage signal terminal.
  • a first level signal is input from the clock signal terminal, a second level signal is input from the trigger signal terminal, a first level signal is input from the reset signal terminal, and a design common voltage is input from the design common voltage signal terminal. signal.
  • the common voltage compensation circuit unit by providing the compensation common voltage, the influence of the parasitic capacitance on the common voltage input to the common electrode line can be eliminated in the display output stage, Thereby, the deflection of the liquid crystal molecules in the pixel unit is precisely controlled, the afterimage is eliminated, and the display effect of the display panel is improved.
  • the common voltage compensation circuit unit still outputs a design common voltage to the corresponding common electrode line, and thus does not affect the deflection state of the liquid crystal molecules in other pixel units that do not participate in the display output.
  • the common voltage compensation circuit unit utilizes the output signals of the previous stage and the subsequent stage shift register unit as the trigger signal and the reset signal, respectively, it is possible to synchronize with the corresponding shift register unit so as to be able to pass the corresponding common electrode
  • the line controls the voltage on the corresponding common electrode of the display panel at a precise moment, so that a better driving and display effect can be achieved.

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Abstract

一种公共电压补偿电路单元、显示面板、显示装置和显示面板的公共电压补偿方法，其中，公共电压补偿电路单元包括触发信号端（Gate N-1）、公共电压输出端（VcomN）、设计公共电压信号端（Com）、电源信号端（Vss）、补偿公共电压信号端（Com'N）、复位信号端（Gate N+1）、时钟信号端（CLKB）、触发信号输入子电路（100）、第一输出子电路（200）、控制子电路（300）、第二输出子电路（400）和复位子电路（500）。

Description

公共电压补偿电路单元、显示面板、显示装置和显示面板的公共电压补偿方法
相关申请的交叉引用
本申请要求享有2017年5月10日提交的中国专利申请No.201710326260.1的优先权，其全部公开内容通过引用并入本文。
技术领域
本公开涉及显示设备领域，具体地，涉及一种公共电压补偿电路单元、一种包括该公共电压补偿电路单元的显示面板、一种显示装置，以及一种使用该公共电压补偿电路单元的公共电压补偿方法。
背景技术
随着显示技术的发展，对液晶显示面板的画面质量要求越来越高。典型地，液晶显示面板中的每一个像素单元包括像素电极和公共电极。利用像素电极和公共电极之间形成的电场来控制像素单元中液晶分子的偏转。但是，液晶显示面板上的电压变化由于寄生电容或存储电容的存在，会产生电压残留，该电压残留将影响显示电压的正确性，从而会导致残像的出现，并影响画面质量。
因此，如何消除残像成为本领域亟待解决的技术问题。
发明内容
本公开的目的在于提供一种改进的公共电压补偿电路单元、一种包括该公共电压补偿电路单元的显示面板、一种显示装置，以及一种使用该公共电压补偿电路单元的公共电压补偿方法。
根据本公开的一个方面，提供一种公共电压补偿电路单元，包括触发信号端、公共电压输出端、设计公共电压信号端、电源信号端、补偿公共电压信号端、复位信号端、时钟信号端、触发信号输入子电路、第一输出子电路、控制子电路、第二输出子电路和复位子电路。
所述触发信号输入子电路的输入端与所述触发信号端电连接，并且所述触发信号输入子电路的输出端与第一节点电连接。所述触发信号输入子电路配置成响应于在所述触发信号输入子电路的输入端处接 收到第一电平信号，将所述触发信号输入子电路的输入端与所述触发信号输入子电路的输出端导通。
所述第一输出子电路的输入端与所述补偿公共电压信号端电连接，第一输出子电路的控制端与第一节点电连接，并且所述第一输出子电路的输出端与所述公共电压输出端电连接。所述第一输出子电路配置成响应于在所述第一输出子电路的控制端处接收到第三电平信号，将所述第一输出子电路的输入端与所述第一输出子电路的输出端导通，其中所述第三电平信号的绝对值大于或等于所述第一电平信号的绝对值，并且所述第三电平信号的极性与所述第一电平信号的极性相同。
所述控制子电路的第一控制端与所述时钟信号端电连接，所述控制子电路的第二控制端与所述复位子电路的第二输出端电连接，所述控制子电路的第一输入端与所述时钟信号端电连接，所述控制子电路的第二输入端与所述触发信号端电连接，所述控制子电路的第一输出端与所述第一节点电连接，并且所述控制子电路的第二输出端与第二节点电连接。所述控制子电路配置成响应于在所述控制子电路的第一控制端处接收到所述第一电平信号，将所述控制子电路的第二输入端与所述控制子电路的第一输出端导通，将所述控制子电路的第一输入端与所述控制子电路的第二输出端导通，并且响应于在所述控制子电路的第二控制端接收到第二电平信号，将所述控制子电路的第一输入端与所述控制子电路的第二输出端断开。
所述第二输出子电路的第一控制端与所述第二节点电连接，所述第二输出子电路的第二控制端与所述复位信号端电连接，所述第二输出子电路的第三控制端与所述时钟信号端电连接，所述第二输出子电路的输入端与所述设计公共电压信号端电连接，并且所述第二输出子电路的输出端与所述公共电压输出端电连接。所述第二输出子电路配置成响应于在所述第二输出子电路的第一控制端、所述第二输出子电路的第二控制端和所述第二输出子电路的第三控制端中的至少一者处接收到所述第一电平信号，将所述第二输出子电路的输入端与所述第二输出子电路的输出端导通。
所述复位子电路的第一控制端与所述复位信号端电连接，所述复位子电路的第二控制端与所述第二节点电连接，所述复位子电路的第三控制端与所述第一节点电连接，所述复位子电路的输入端与电源信 号端电连接，所述复位子电路的第一输出端与所述第一节点电连接，并且所述复位子电路的第三输出端与所述第二节点电连接。所述复位子电路配置成响应于在所述复位子电路的第一控制端和所述复位子电路的第二控制端中的至少一个处接收到所述第一电平信号，将所述复位子电路的输入端与所述复位子电路的第一输出端导通，并且响应于在所述复位子电路的第三控制端处接收到所述第一电平信号，将所述复位子电路的输入端与所述复位子电路的第二输出端和第三输出端导通。
根据一些实施例，所述触发信号输入子电路包括触发输入晶体管。所述触发输入晶体管的第一极和控制极与所述触发信号输入子电路的输入端电连接，并且所述触发输入晶体管的第二极与所述触发信号输入子电路的输出端电连接。
根据一些实施例，所述第一输出子电路包括显示输出晶体管和存储电容器。所述显示输出晶体管的控制极与所述第一输出子电路的控制端电连接，所述显示输出晶体管的第一极与所述补偿公共电压信号端电连接，所述显示输出晶体管的第二极与所述公共电压输出端电连接。所述存储电容器的第一端与所述第一节点电连接，并且所述存储电容器的第二端与第一输出子电路的输出端电连接。
根据一些实施例，所述控制子电路包括第一控制晶体管、第二控制晶体管和第三控制晶体管。所述第一控制晶体管的控制极与所述控制子电路的第一控制端电连接，所述第一控制晶体管的第一极与所述控制子电路的第二输入端电连接，并且所述第一控制晶体管的第二极与所述控制子电路的第一输出端电连接。所述第二控制晶体管的控制极和第一极与所述控制子电路的第一输入端电连接，并且所述第二控制晶体管的第二极与所述控制子电路的第二控制端电连接。所述第三控制晶体管的控制极与所述控制子电路的第二控制端电连接，所述第三控制晶体管的第一极与所述控制子电路的第一输入端电连接，并且所述第三控制晶体管的第二极与所述控制子电路的第二输出端电连接。
根据一些实施例，所述复位子电路包括第一复位晶体管、第二复位晶体管、第三复位晶体管和第四复位晶体管。所述第一复位晶体管的控制极与所述复位子电路的第二控制端电连接，所述第一复位晶体管的第一极与所述复位子电路的输入端电连接，并且所述第一复位晶 体管的第二极与所述复位子电路的第一输出端电连接。所述第二复位晶体管的控制极与所述复位子电路的第一控制端电连接，所述第二复位晶体管的第一极与所述复位子电路的输入端电连接，并且所述第二复位晶体管的第二极与所述复位子电路的第一输出端电连接。所述第三复位晶体管的控制极与所述复位子电路的第三控制端电连接，所述第三复位晶体管的第一极与所述复位子电路的输入端电连接，所述第三复位晶体管的第二极与所述复位子电路的第二输出端电连接。所述第四复位晶体管的控制极与所述复位子电路的第三控制端电连接，所述第四复位晶体管的第一极与所述复位子电路的输入端电连接，并且所述第四复位晶体管的第二极与所述复位子电路的第三输出端电连接。
根据一些实施例，所述第二输出子电路包括第一复位输出晶体管、第二复位输出晶体管和第三复位输出晶体管。所述第一复位输出晶体管的控制极与所述第二输出子电路的第二控制端电连接，所述第一复位输出晶体管的第一极与所述第二输出子电路的输入端电连接，并且所述第一复位输出晶体管的第二极与所述第二输出子电路的输出端电连接。所述第二复位输出晶体管的控制极与所述第二输出子电路的第三控制端电连接，所述第二复位输出晶体管的第一极与所述第二输出子电路的输入端电连接，并且所述第二复位输出晶体管的第二极与所述第二输出子电路的输出端电连接。所述第三复位输出晶体管的控制极与所述第二输出子电路的第一控制端电连接，所述第三复位输出晶体管的第一极与所述第二输出子电路的输入端电连接，并且所述第三复位输出晶体管的第二极与所述第二输出子电路的输出端电连接。
根据本公开的另一方面，提供了一种显示面板，包括级联的多个上述任一种公共电压补偿电路单元、多条栅线、多条公共电极线、第一时钟信号线、第二时钟信号线、电源信号线、设计公共电压信号线和补偿公共电压信号线。
每一个公共电压补偿电路单元的公共电压输出端与相应的公共电极线电连接，每一个公共电压补偿电路单元的触发信号端与相应的栅线电连接，每一个公共电压补偿电路单元的复位信号端与相应的另一栅线电连接，每一个公共电压补偿电路单元的电源信号端与电源信号线电连接，每一个公共电压补偿电路单元的设计公共电压信号端与设计公共电压信号线电连接，并且每一个公共电压补偿电路单元的补偿 公共电压信号端与补偿公共电压信号线电连接。
当公共电压补偿电路单元对应于奇数行的公共电极线时，所述公共电压补偿电路单元的时钟信号端与第一时钟信号线电连接；当公共电压补偿电路单元对应于偶数行的公共电极线时，所述公共电压补偿电路单元的时钟信号端与第二时钟信号线电连接。
补偿公共电压信号线与公共电压生成芯片电连接。所述公共电压生成芯片配置成，响应于与公共电压补偿电路单元的时钟信号端连接的第一时钟信号线或第二时钟信号线提供第一电平信号，向补偿公共电压信号线提供设计公共电压信号，响应于与公共电压补偿电路单元的时钟信号端连接的第一时钟信号线或第二时钟信号线提供第二电平信号，向补偿公共电压信号线提供补偿公共电压信号。
根据一些实施例，上述显示面板包括多行像素单元，每行像素单元包括多个像素单元，所述多行像素单元分别与多行公共电极一一对应。
所述公共电压生成芯片配置成根据公式(1)和公式(2)计算所述补偿公共电压信号：
ComN-Com’N＝ΔVp     (1)
Figure PCTCN2018070743-appb-000001
其中，ComN是用于与公共电压补偿电路单元对应的第N行像素单元的设计公共电压信号的电压值；
Com’N是用于所述第N行像素单元的补偿公共电压信号的电压值；
Vgh是第一电平信号的电压值；
Vgl是第二电平信号的电压值；
Cgd是所述第N行像素单元中的一个像素单元的薄膜晶体管的栅极与漏极之间的电容；
Cs是所述像素单元的存储电容；
Clc是所述像素单元的液晶电容。
根据一些实施例，所述公共电极线与所述公共电压补偿电路单元 一一对应。
根据本公开的又一方面，提供了一种显示装置，包括上述任一种显示面板。
根据本公开另外的方面，提供了一种显示面板的公共电压补偿方法，其使用上述任一种公共电压补偿电路单元。所述方法包括输入阶段、显示输出阶段和复位阶段。
在输入阶段，从触发信号端输入第一电平信号，从时钟信号端输入第二电平信号，从复位信号端输入第二电平信号，并且从补偿公共电压信号端输入设计公共电压信号。
在显示输出阶段，从触发信号端输入第二电平信号，从时钟信号端输入第二电平信号，并且从补偿公共电压信号端输入补偿公共电压信号。
在复位阶段，从时钟信号端输入第一电平信号，从触发信号端输入第二电平信号，从复位信号端输入第一电平信号，并且从设计公共电压信号端输入设计公共电压信号。
根据一些实施例，根据公式(1)和公式(2)计算所述补偿公共电压信号：
ComN-Com’N＝ΔVp     (1)
Figure PCTCN2018070743-appb-000002
其中，ComN是用于与公共电压补偿电路单元对应的第N行像素单元的设计公共电压信号的电压值；
Com’N是用于所述第N行像素单元的补偿公共电压信号的电压值；
Vgh是第一电平信号的电压值；
Vgl是第二电平信号的电压值；
Cgd是所述第N行像素单元中的一个像素单元的薄膜晶体管的栅极与漏极之间的电容；
Cs是所述像素单元的存储电容；
Clc是所述像素单元的液晶电容。
在本公开所提供的公共电压补偿电路单元、显示面板、显示装置以及公共电压补偿方法中，通过在显示输出阶段提供补偿公共电压来消除寄生电容对输入至公共电极线的公共电压的影响，从而精确地控制像素单元中液晶分子的偏转，消除残像，提高包括所述公共电压补偿电路单元的显示面板的显示效果。
附图说明
附图是用来提供对本公开的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本公开，但并不构成对本公开的限制。在附图中：
图1是本公开实施例所提供的公共电压补偿电路单元的结构示意图；
图2是本公开实施例所提供的公共电压补偿电路单元的工作信号时序图；
图3是本公开实施例所提供的公共电压补偿电路单元的具体结构示意图；
图4是本公开实施例所提供的显示面板的一部分的示意图；以及
图5是本公开实施例提供的公共电压补偿方法的流程图。
具体实施方式
以下结合附图对本公开的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本公开，并不用于限制本公开。
作为本公开的一个方面，提供一种公共电压补偿电路单元，如图1所示，包括触发信号端Gate N-1、公共电压输出端VcomN、设计公共电压信号端Com、电源信号端Vss、补偿公共电压信号端Com’N、复位信号端Gate N+1、时钟信号端CLKB、触发信号输入子电路100、第一输出子电路200、控制子电路300、第二输出子电路400和复位子电路500。
触发信号输入子电路100的输入端与触发信号端Gate N-1电连接，触发信号输入子电路100的输出端与第一节点PU电连接。触发信号输入子电路100配置成响应于在触发信号输入子电路100的输入端处接 收到第一电平信号，将触发信号输入子电路100的输入端与触发信号输入子电路100的输出端导通。
第一输出子电路200的输入端与补偿公共电压信号端Com’N电连接，第一输出子电路200的控制端与第一节点PU电连接，并且第一输出子电路200的输出端与公共电压输出端Vcom N电连接。第一输出子电路200配置成响应于在第一输出子电路200的控制端接收到第三电平信号，将第一输出子电路200的输入端与第一输出子电路200的输出端导通，其中第三电平信号的绝对值大于或等于第一电平信号的绝对值，并且第三电平信号的极性与第一电平信号的极性相同。
控制子电路300的第一控制端与时钟信号端CLKB电连接，控制子电路300的第二控制端与复位子电路500的第二输出端电连接，控制子电路300的第一输入端与时钟信号端CLKB电连接，控制子电路300的第二输入端与触发信号端Gate N-1电连接，控制子电路300的第一输出端与第一节点PU电连接，并且控制子电路300的第二输出端与第二节点PD电连接。控制子电路300配置成响应于在控制子电路300的第一控制端接收到第一电平信号，将控制子电路300的第二输入端与控制子电路300的第一输出端导通，将控制子电路300的第一输入端与控制子电路300的第二输出端导通，并且响应于在控制子电路300的第二控制端接收到第二电平信号，将控制子电路300的第一输入端与控制子电路300的第二输出端断开。
第二输出子电路400的第一控制端与第二节点PD电连接，第二输出子电路400的第二控制端与复位信号端Gate N+1电连接，第二输出子电路400的第三控制端与时钟信号端CLKB电连接，第二输出子电路400的输入端与设计公共电压信号端Com电连接，并且第二输出子电路400的输出端与公共电压输出端Vcom N电连接。第二输出子电路400配置成响应于在第二输出子电路400的第一控制端、第二输出子电路400的第二控制端和第二输出子电路400的第三控制端中的至少一者处接收到第一电平信号，将第二输出子电路400的输入端与第二输出子电路400的输出端导通。
复位子电路500的第一控制端与复位信号端Gate N+1电连接，复位子电路500的第二控制端与第二节点PD电连接，复位子电路500的输入端与电源信号端Vss电连接，复位子电路500的第一输出端与第 一节点PU电连接，复位子电路500的第三控制端与第一节点PU电连接，并且复位子电路500的第三输出端与第二节点PD电连接。复位子电路500配置成响应于在复位子电路500的第一控制端和复位子电路500的第二控制端中的至少一个处接收到第一电平信号，将复位子电路500的输入端与复位子电路500的第一输出端导通，并且响应于在第三控制端处接收到第一电平信号，将复位子电路500的输入端与复位子电路500的第二输出端和第三输出端导通。
如本领域技术人员所知的，显示面板包括横纵交叉的多条栅线Gate n-2，Gate n，Gate n-1……和多条数据线，并且栅线和数据线的每一个交叉对应于一个像素单元。栅线用于向每一行像素单元提供驱动信号，并且数据线用于向每一列像素单元提供数据信号。显示面板还包括控制极驱动电路，并且控制极驱动电路包括与栅线一一对应的移位寄存器单元，其中移位寄存器单元用于逐级向相应的栅线提供驱动信号。具体地，第N级移位寄存器单元的输出端与第N条栅线电连接。
当使用在显示面板中时，上述公共电压补偿电路单元对应于显示面板中的第N行像素单元，并且公共电压补偿电路单元的公共电压输出端VcomN通过第N条公共电极线而与第N行像素单元的公共电极电连接，以便向第N行像素单元的公共电极提供公共电压信号。公共电压补偿电路单元的触发信号端Gate N-1与第N-1条栅线Gate n-1电连接，并且公共电压补偿电路单元的复位信号端Gate N+1与第N+1条栅线Gate n+1电连接。
如本文所使用的，术语“第一电平信号”和“第二电平信号”中的一者指示高电平信号，并且另一者指示低电平信号。例如，当公共电压补偿电路单元中所使用的晶体管为N型晶体管时，第一电平信号指示高电平信号，并且第二电平信号指示低电平信号。相反，当公共电压补偿电路单元中所使用的晶体管为P型晶体管时，第一电平信号指示低电平信号，并且第二电平信号指示高电平信号。。
以下结合图2来描述如图2所示的公共电压补偿电路单元的工作过程。如图2所示，公共电压补偿电路单元的每个工作周期包括三个工作阶段：输入阶段t1、显示输出阶段t2和复位阶段t3。需要指出的是，在图2中，以公共电压补偿电路单元中所使用的晶体管为N型晶体管为例来说明公共电压补偿电路单元的工作过程。但是，本公开不 限于此。假定补偿公共电压信号端Com’N提供的信号为方波，并且在不同的阶段提供设计公共电压信号或补偿公共电压信号。
在输入阶段t1，从触发信号端Gate N-1输入第一电平信号，从时钟信号端CLKB输入第二电平信号，从复位信号端Gate N+1输入第二电平信号，并且从补偿公共电压信号端ComN输入设计公共电压信号。此时，触发信号输入子电路100响应于在其输入端处接收到第一电平信号，将触发信号输入子电路100的输入端与触发信号输入子电路100的输出端导通，并且因而将通过触发信号端Gate N-1提供的第一电平信号存储在第一节点PU处。由于第一输出子电路200的控制端与第一节点PU电连接，因此，在第一输出子电路200的控制端处接收到第一电平信号。同时，复位子电路500的第三控制端接收到第一电平信号，使得复位子电路500的输入端与复位子电路500的第二输出端导通，因而在控制子电路300的第二控制端处接收到第二电平信号。并且，复位子电路500的第三控制端接收到第一电平信号，使得复位子电路500的输入端与复位子电路500的第三输出端导通。因此，在第二输出子电路400的第一控制端处接收到第二电平信号。由于第一输出子电路200的控制端接收到第一电平信号，因此，第一输出子电路200的输入端与输出端导通。由于此时从补偿公共电压信号端Com’N输入的信号为设计公共电压信号，因此，公共电压输出端VcomN输出的信号为设计公共电压信号。
在显示输出阶段t2，从触发信号端Gate N-1输入第二电平信号，从时钟信号端CLKB输入第二电平信号，并且从补偿公共电压信号端Com’N输入补偿公共电压信号。由于在触发信号输入子电路100的输入端处接收到第二电平信号，因此，触发信号输入子电路100的输入端与输出端断开。在触发信号输入子电路100的输入端与输出端断开的情况下，第一输出子电路200的控制端处的信号将跳变至第三电平信号，使得第一输出子电路200的输入端与输出端导通，进而使得公共电压输出端VcomN输出补偿公共电压信号。与此同时，由于第一输出子电路200的控制端与复位子电路500的第三控制端电连接，因此，复位子电路500的输入端与复位子电路500的第三输出端导通，使得在第二节点PD处接收到第二电平信号。由于第二输出子电路400的第一控制端与第二节点PD电连接，第二输出子电路400的第二控制端与 复位信号端Gate N+1电连接，因此，第二输出子电路400的输入端与输出端之间断开，确保公共电压输出端此时输出的信号为补偿公共电压信号。
在复位阶段t3，从时钟信号端CLKB输入第一电平信号，从触发信号端Gate N-1输入第二电平信号，并且从复位信号端Gate N+1输入第一电平信号。因此，触发信号输入子电路100的输入端与输出端断开，复位子电路500的输入端与第一输出端导通，使得在第一节点PU处接收到第二电平信号，从而对第一输出子电路200的控制端进行复位。与此同时，由于第二输出子电路400的第三控制端接收到从时钟信号端CLKB输入的第一电平信号，因此，第二输出子电路400的输入端与输出端导通，使得公共电压信号输出端输出的信号为从设计公共电压信号端Com输入的设计公共电压信号。
通过上述描述可知，公共电压补偿电路单元在工作时，在输入阶段t1以及复位阶段t2向相应的公共电极线提供设计公共电压信号，并且在显示输出阶段t2向相应的公共电极线提供补偿公共电压信号。
需要指出的是，从补偿公共电压信号端Com’N输入的补偿公共电压的值是经过补偿后计算获得的。在这样的计算中，需要综合考虑寄生电容在显示阶段对液晶分子偏转的影响。例如，可以按照以下的公式(1)和公式(2)来计算补偿公共电压：
ComN-Com’N＝ΔVp    (1)
Figure PCTCN2018070743-appb-000003
其中，ComN是用于与公共电压补偿电路单元对应的第N行像素单元的设计公共电压信号的电压值；
Com’N是用于所述第N行像素单元的补偿公共电压信号的电压值；
Vgh是第一电平信号的电压值；
Vgl是第二电平信号的电压值；
Cgd是所述第N行像素单元中的一个像素单元的薄膜晶体管的栅极与漏极之间的电容；
Cs是所述像素单元的存储电容；并且
Clc是所述像素单元的液晶电容。
通过该补偿公共电压，可以在显示输出阶段消除寄生电容对输入至公共电极线的公共电压的影响，从而精确地控制像素单元中的液晶分子的偏转，消除残像，提高显示面板的显示效果。
此外，在除显示输出阶段之外的其他阶段，公共电压补偿电路单元仍旧向相应的公共电极线输出设计公共电压，因此不会影响其他不参与显示输出的像素单元中的液晶分子的偏转状态。
进一步地，由于公共电压补偿电路单元分别利用前一级和后一级移位寄存单元的输出信号作为触发信号以及复位信号，因此能够与相应的移位寄存器单元同步，使得能够通过相应的公共电极线在精确的时刻控制显示面板的相应公共电极上的电压，从而可以实现更好的驱动和显示效果。
在本公开中，对各个子电路的具体结构并没有特殊的限制，只要能够在显示周期的各个阶段实现上文中所述的功能即可。
图3示出根据本公开的一个实施例的公共电压补偿电路单元的电路图。
具体地，触发信号输入子电路100包括触发输入晶体管M1，该触发输入晶体管M1的第一极和控制极与该触发信号输入子电路100的输入端电连接(即，触发输入晶体管M1的控制极和第一极与触发信号端Gate N-1电连接)，触发输入晶体管M1的第二极与触发信号输入子电路100的输出端电连接。
当从触发信号端Gate N-1输入第一电平信号时，触发输入晶体管M1导通，从而将从触发信号端Gate N-1输入的第一电平信号传输至第一输出子电路200的控制端。当从触发信号端Gate N-1输入第二电平信号时，触发输入晶体管M1截止。
根据示例实施例，第一输出子电路200包括显示输出晶体管M3和存储电容器C1。如图3中所示，显示输出晶体管M3的控制极与第一输出子电路200的控制端电连接，显示输出晶体管M3的第一极与补偿公共电压信号端Com’N电连接，并且显示输出晶体管M3的第二极与公共电压输出端Vcom N电连接。存储电容器C1的第一端与第一节点PU电连接，并且存储电容器C1的第二端与第一输出子电路200 的输出端电连接。
当显示输出晶体管M3的控制极接收到第一电平信号时，显示输出晶体管M3导通，从而将补偿公共电压信号端Com’N与公共电压输出端Vcom N导通。
根据示例实施例，控制子电路300包括第一控制晶体管M13、第二控制晶体管M9和第三控制晶体管M5。
如图3中所示，第一控制晶体管M13的控制极与控制子电路300的第一控制端电连接(即，与时钟信号端CLKB电连接)，第一控制晶体管M13的第一极与控制子电路300的第二输入端电连接(即，与触发信号端Gate N-1电连接)，并且第一控制晶体管M13的第二极与控制子电路300的第一输出端电连接(即，与第一节点PU电连接)。
第二控制晶体管M9的控制极和第一极与控制子电路300的第一输入端电连接(即，与时钟信号端CLKB电连接)，并且第二控制晶体管M9的第二极与控制子电路300的第二控制端电连接。
第三控制晶体管M5的控制极与控制子电路300的第二控制端电连接(即，与第二控制晶体管M9的第二极电连接)，第三控制晶体管M5的第一极与控制子电路300的第一输入端电连接(即，与时钟信号端CLKB电连接)，并且第三控制晶体管M5的第二极与控制子电路的第二输出端电连接(即，与第二节点PD电连接)。
当从时钟信号端CLKB输入第一电平信号时，在控制子电路300的第一控制端接收到第一电平信号，使得第一控制晶体管M13和第二控制晶体管M9均导通。如图2中所示，当从时钟信号端CLKB输入第一电平信号时，从触发信号端Gate N-1输入第二电平信号，因此，通过控制子电路300向第一输出子电路200的控制端输出第二电平信号，确保第一输出子电路200的输入端与输出端之间是断开的。与此同时，第二控制晶体管M9的导通可以将通过时钟信号端CLKB输入的第一电平信号传输至第三控制晶体管M5的控制极，使得第三控制晶体管M5导通，并最终将通过时钟信号端CLKB输入的第一电平信号传输至第二节点PD。
当从第一时钟信号端CLKB输入第二电平信号时，第一控制晶体管M13和第二控制晶体管M9均截止。
设置复位子电路500的主要目的是在显示输出阶段结束后对第一 输出子电路200的控制端进行复位，确保公共电压补偿电路单元在除显示输出阶段外的其余阶段均输出设计公共电压信号端Com提供的设计公共电压。
在本公开中，对复位子电路500的具体结构并不做特殊的限制。例如，在图3中所示的示例中，复位子电路500可以包括第一复位晶体管M10、第二复位晶体管M2、第三复位晶体管M8和第四复位晶体管M6。
如图3中所示，第一复位晶体管M10的控制极与复位子电路500的第二控制端电连接(即，与第二节点PD电连接)，第一复位晶体管M10的第一极与复位子电路500的输入电连接(即，与电源信号端Vss电连接)，并且第一复位晶体管M10的第二极与该复位子电路500的第一输出端电连接(即，与第一节点PU电连接)。
第二复位晶体管M2的控制极与复位子电路500的第一控制端电连接，第二复位晶体管M2的第一极与复位子电路500的输入电连接(即，与电源信号端Vss电连接)，并且第二复位晶体管M2的第二极与复位子电路500的第一输出端电连接(即，与第一节点PU电连接)。
第三复位晶体管M8的控制极与复位子电路500的第三控制端电连接(即，与第一节点PU电连接)，第三复位晶体管M8的第一极与复位子电路500的输入端电连接(即，与电源信号端Vss电连接)，并且第三复位晶体管M8的第二极与复位子电路500的第二输出端电连接(即，与第二节点PD电连接)。
第四复位晶体管M6的控制极与复位子电路500的第三控制端电连接(即，与第一节点PU电连接)，第四复位晶体管M6的第一极与复位子电路500的输入端电连接(即，与电源信号端Vss电连接)，并且第四复位晶体管M6的第二极与复位子电路500的第三输出端电连接(即，与第二节点PD电连接)。
由于复位子电路500包括三个控制端，因此，通过三种控制信号来控制复位子电路500的各个输出端(包括第一输出端、第二输出端和第三输出端)的输出信号。下文中将结合图2来详细描述复位子电路500的输出情况，这里先不赘述。
在本公开中，第二输出子电路400的主要作用在于确保公共电压补偿电路单元在复位阶段t3能够输出设计公共电压信号。对第二输出 子电路400的具体结构也不做特殊的限定。例如，如图3中所示，第二输出子电路400可以包括第一复位输出晶体管M11、第二复位输出晶体管M12和第三复位输出晶体管M4。
第一复位输出晶体管M11的控制极与第二输出子电路400的第二控制端电连接(即，与复位信号端Gate N+1电连接)，第一复位输出晶体管M11的第一极与第二输出子电路400的输入端电连接(即，与设计公共电压信号端Com电连接)，并且第一复位输出晶体管M11的第二极与第二输出子电路400的输出端电连接(即，与公共电压输出端Vcom N电连接)。
第二复位输出晶体管M12的控制极与第二输出子电路400的第三控制端电连接，第二复位输出晶体管M12的第一极与第二输出子电路400的输入端电连接(即，与设计公共电压信号端Com电连接)，并且第二复位输出晶体管M12的第二极与第二输出子电路400的输出端电连接(即，与公共电压输出端Vcom N电连接)。
第三复位输出晶体管M4的控制极与第二输出子电路400的第一控制端电连接(即，与第二节点PD电连接)，第三复位输出晶体管M4的第一极与第二输出子电路400的输入端电连接(即，与设计公共电压信号端Com电连接)，并且第三复位输出晶体管M4的第二极与第二输出子电路400的输出端电连接(即，与公共电压输出端Vcom N电连接)。
当在第一复位输出晶体管M11、第二复位输出晶体管M12和第三复位输出晶体管M4中的任意一者的控制极接收到第一电平信号时，第二输出子电路400的输入端和输出端导通，使得公共电压输出端Vcom N输出设计公共电压信号。
如本领域技术人员所知的，晶体管一般为三端元件。在本文中，将控制晶体管导通和截止的端称为其“控制极”，将另外的两个端分别称为“第一极”和“第二极”。例如，在场效应晶体管的情况下，其控制极为栅极，其第一极可以为漏极，并且其第二极可以为源极。
下面结合图2和图3详细介绍本公开的实施例所提供的公共电压补偿电路单元的具体工作过程。
在图3中所示的公共电压补偿电路单元中，假定所有的晶体管均为N型晶体管，相应地，第一电平信号为高电平信号，并且第二电平 信号为低电平信号。补偿公共电压信号端Com’N提供的信号为方波，并且在不同的阶段提供设计公共电压信号或补偿公共电压信号。
如图2所示，如图3所示的公共电压补偿电路单元的一个工作周期包括输入阶段t1、显示输出阶段t2和复位阶段t3。
在输入阶段t1，从触发信号端Gate N-1接收到第一电平信号，从时钟信号端CLKB接收到第二电平信号，并且从复位信号端Gate N+1接收到第二电平信号。因此，触发输入晶体管M1的第一极和第二极导通，从而将从触发信号端Gate N-1输入的第一电平信号传输至第一输出子电路200的控制端，并对存储电容器C1进行充电。在输入阶段t1，通过触发信号端Gate N-1输入的第一电平信号存储在存储电容器C1中，并且使得在显示输出晶体管M3的控制极接收到第一电平信号，因此，显示输出晶体管M3导通。此时，补偿公共电压信号端Com’N提供的信号为设计公共电压信号，因此，从公共电压输出端Vcom输出设计公共电压信号。同时，由于从时钟信号端CLKB输入的信号为第二电平信号，因此，第一控制晶体管M13、第二控制晶体管M9、第二复位输出晶体管M12均截止，第四复位晶体管M6和第三复位晶体管M8导通，因而将从电源信号端Vss输入的第二电平信号传输至第三控制晶体管M5的控制极，使得第三控制晶体管M5也截止。
在显示输出阶段t2，从触发信号端Gate N-1输入第二电平信号，从复位信号端Gate N+1输入第二电平信号，并且从时钟信号端CLKB输入第二电平信号。因此，触发输入晶体管M1截止，第一控制晶体管M13截止。此时，第一节点PU处于浮置状态。由于在前一阶段t1，显示输出晶体管M3导通，因此在显示输出阶段t2，显示输出晶体管M3仍旧导通，从而将从补偿公共电压信号端ComN输入的补偿公共电压信号传输至存储电容器C1的第二端。此时，由于存储电容器C1的自举作用，与存储电容器C1的第一端电连接的第一节点PU的电位将被上拉至第三电平信号，使得显示输出晶体管M3保持导通。此时，从公共电压输出端Vcom N输出的信号为补偿公共电压信号端Com’N提供的补偿公共电压信号。在该阶段，复位子电路500和第二输出子电路400的输入端以及输出端之间均断开，因此不会影响到公共电压补偿电路单元的输出。
在复位阶段t3，从时钟信号端CLKB输入第一电平信号，因此， 第一控制晶体管M13和第二控制晶体管M9导通，从而将从触发信号端Gate N-1输入的第二电平信号传输至第一节点PU。由于第二控制晶体管M9导通，因此使得第三控制晶体管M5也导通，以将从时钟信号端CLKB输入的第一电平信号传输至第二节点PD，因而使得第三复位输出晶体管M4导通，从而将从设计公共电压信号端Com输入的设计公共电压传输至公共电压输出端Vcom N。
通过上述描述可知，如图3所示的公共电压补偿电路单元在工作时，在显示输出阶段输出补偿公共电压信号，而在其余阶段输出设计公共电压信号。
可以按照如下公式来计算补偿公共电压：
ComN-Com’N＝ΔVp
Figure PCTCN2018070743-appb-000004
其中，ComN为用于与公共电压补偿电路单元对应的第N行像素单元的设计公共电压信号的电压值；
Com’N为用于所述第N行像素单元的补偿公共电压信号的电压值。
Vgh为第一电平信号的电压值；
Vgl为第二电平信号的电压值；
Cgd为所述第N行像素单元中的一个像素单元中的薄膜晶体管的栅极与漏极之间的寄生电容；
Cs为所述像素单元的存储电容；并且
Clc为所述像素单元的液晶电容。
对于特定像素单元而言，薄膜晶体管的尺寸、像素电极的尺寸、公共电极的尺寸都是已知的，并且设计公共电压的大小、第一电平信号的电压值、第二电平信号的电压值均是已知的，因此，栅极与漏极之间的寄生电容是容易通过计算获得的。因此，利用上述公式可以计算获得所述补偿公共电压信号的电压值。
作为本公开的另一个方面，提供一种显示面板，包括级联的多个上述公共电压补偿电路单元。如图4所示，该显示面板包括级联的多 个公共电压补偿电路单元100、多条栅线Gate n-2、Gate n-1、Gate n等、多条公共电极线Vcom n-1，Vcom n，Vcom n+1等、第一时钟信号线CLKa、第二时钟信号线CLKb、电源信号线Vss、设计公共电压信号线com和补偿公共电压信号线com’。。
每一个公共电压补偿电路单元100的公共电压输出端VcomN与相应的公共电极线Vcom n电连接，每一个公共电压补偿电路单元100的触发信号端Gate N-1与相应的栅线Gate n-1电连接，每一个公共电压补偿电路单元100的复位信号端Gate N+1与相应的另一栅线Gate n+1电连接，每一个公共电压补偿电路单元100的电源信号端Vss与电源信号线Vss电连接，每一个公共电压补偿电路单元100的设计公共电压信号端Com与设计公共电压信号线com电连接，并且每一个公共电压补偿电路单元100的补偿公共电压信号端Com’N与补偿公共电压信号线com’电连接。
当公共电压补偿电路单元100对应于奇数行的公共电极线时，该公共电压补偿电路单元100的时钟信号端CLKB与第一时钟信号线CLKa电连接；当公共电压补偿电路单元100对应于偶数行的公共电极线时，该公共电压补偿电路单元100的时钟信号端CLKB与第二时钟信号线CLKb电连接。
补偿公共电压信号线com’与公共电压生成芯片200电连接。当与公共电压补偿电路单元100的时钟信号端CLKB连接的第一时钟信号线CLKa或第二时钟信号线CLKb提供第一电平信号时，公共电压生成芯片200向补偿公共电压信号线com’提供设计公共电压信号；当与公共电压补偿电路单元100的时钟信号端CLKB连接的第一时钟信号线CLKa或第二时钟信号线CLKb提供第二电平信号时，公共电压生成芯片200向补偿公共电压信号线com’提供补偿公共电压信号。
将理解到，图4仅仅示出了显示面板的一部分，而省略了其它对于显示面板而言必要的部件，以免使本公开的理解模糊。需要指出的是，在图4中，N与n的值相同，其作用仅仅是区分公共电压补偿电路单元中的各个端口与栅线、公共电极线。为了便于描述，以下假设N、n均为偶数。
如图4中所示，第n-1行公共电极线Vcom n-1与相应的第N-1级公共电压补偿电路单元100的公共电压输出端Vcom N-1电连接。该第 N-1级公共电压补偿电路单元100的触发信号端Gate N-2与第n-2行栅线Gate n-2电连接。第N-1级公共电压补偿电路单元100的时钟信号端CLKB与第一时钟信号线CLKa电连接。第N-1级公共电压补偿电路单元100的补偿公共电压信号端Com’N-1与补偿公共电压信号线com’电连接。第N-1级公共电压补偿电路单元100的设计公共电压端Com与设计公共电压信号线com电连接。第N-1级公共电压补偿电路单元100的电源信号端Vss与电源信号线Vss电连接。
第n行公共电极线Vcom n与相应的第N级公共电压补偿电路单元100的公共电压输出端Vcom N电连接。第N级公共电压补偿电路单元100的触发信号端Gate N-1与第n-1行栅线Gate n-1电连接。第N级公共电压补偿电路单元100的时钟信号端CLKB与第二时钟信号线CLKb电连接。第N级公共电压补偿电路单元100的补偿公共电压信号端Com’N与补偿公共电压信号线com’电连接。第N级公共电压补偿电路单元100的设计公共电压信号端Com与设计公共电压信号线com电连接。第N级公共电压补偿电路单元100的电源信号端Vss与电源信号线Vss电连接。
第n+1行公共电极线Vcom n+1与相应的第N+1级公共电压补偿电路单元100的公共电压输出端Vcom N+1电连接。该第N+1级公共电压补偿电路单元100的触发信号端Gate N与第n行栅线Gate n电连接。第N+1级公共电压补偿电路单元100的时钟信号端CLKB与第一时钟信号线CLKa电连接。第N+1级公共电压补偿电路单元100的补偿公共电压信号端Com’N+1与补偿公共电压信号线com’电连接。第N+1级公共电压补偿电路单元100的设计公共电压信号端Com与设计公共电压信号线com电连接。第N+1级公共电压补偿电路单元100的电源信号端Vss与电源信号线Vss电连接。
第n+2行公共电极线Vcom n+2与相应的第N+2级公共电压补偿电路单元100的公共电压输出端Vcom N+2电连接。第N+2级公共电压补偿电路单元100的触发信号端Gate N+1与第n+1行栅线Gate n电连接。第N+2级公共电压补偿电路单元100的时钟信号端CLKB与第二时钟信号线CLKb电连接。第N+2级公共电压补偿电路单元100的补偿公共电压信号端Com’N+2与补偿公共电压信号线com’电连接。第N+2级公共电压补偿电路单元100的设计公共电压信号端Com与设 计公共电压信号线com电连接。第N+2级公共电压补偿电路单元100的电源信号端Vss与电源信号线Vss电连接。
上述连接方式可以确保公共电压补偿电路单元与相应的栅线同步动作，从而对各行像素单元进行精确的公共电压补偿。
如上文中所述，显示面板包括多行像素单元，每行像素单元包括多个像素单元，并且所述多行像素单元分别与多行公共电极一一对应。
所述公共电压生成芯片可以根据以下的公式(1)和公式(2)计算所述补偿公共电压信号：
ComN-Com’N＝ΔVp     (1)
Figure PCTCN2018070743-appb-000005
其中，ComN是用于与公共电压补偿电路单元对应的第N行像素单元的设计公共电压信号的电压值；
Com’N是用于所述第N行像素单元的补偿公共电压信号的电压值；
Vgh是第一电平信号的电压值；
Vgl是第二电平信号的电压值；
Cgd是所述第N行像素单元中的一个像素单元的薄膜晶体管的栅极与漏极之间的电容；
Cs是所述像素单元的存储电容；
Clc是所述像素单元的液晶电容。
在示例实施例中，为了使得各个像素单元均能够准确地显示图像，每条公共电极线均对应有公共电压补偿电路单元。
作为本公开的又一方面，提供一种显示装置，包括上述显示面板。
作为本公开另外的方面，提供一种公共电压补偿方法，其使用上述任一种公共电压补偿电路单元。如图5所示，所述公共电压补偿方法500包括输入阶段502、显示输出阶段504和复位阶段506。
在输入阶段502中，从触发信号端输入第一电平信号，从时钟信号端输入第二电平信号，从复位信号端输入第二电平信号，并且从补偿公共电压信号端输入设计公共电压信号。
在显示输出阶段504中，从触发信号端输入第二电平信号，从时钟信号端输入第二电平信号，并且从补偿公共电压信号端输入补偿公共电压信号。
在复位阶段506中，从时钟信号端输入第一电平信号，从触发信号端输入第二电平信号，从复位信号端输入第一电平信号，并且从设计公共电压信号端输入设计公共电压信号。
在本公开所提供的公共电压补偿电路单元、显示面板、显示装置以及公共电压补偿方法中，通过提供补偿公共电压，可以在显示输出阶段消除寄生电容对输入至公共电极线的公共电压的影响，从而精确地控制像素单元中的液晶分子的偏转，消除残像，提高显示面板的显示效果。
此外，在除显示输出阶段之外的其他阶段，公共电压补偿电路单元仍旧向相应的公共电极线输出设计公共电压，因此不会影响其他不参与显示输出的像素单元中的液晶分子的偏转状态。
进一步地，由于公共电压补偿电路单元分别利用前一级和后一级移位寄存单元的输出信号作为触发信号以及复位信号，因此能够与相应的移位寄存器单元同步，使得能够通过相应的公共电极线在精确的时刻控制显示面板的相应公共电极上的电压，从而可以实现更好的驱动和显示效果。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (12)

  1. 一种公共电压补偿电路单元，包括触发信号端、公共电压输出端、设计公共电压信号端、电源信号端、补偿公共电压信号端、复位信号端、时钟信号端、触发信号输入子电路、第一输出子电路、控制子电路、第二输出子电路和复位子电路，其中
    所述触发信号输入子电路的输入端与所述触发信号端电连接，所述触发信号输入子电路的输出端与第一节点电连接，并且所述触发信号输入子电路配置成响应于在所述触发信号输入子电路的输入端处接收到第一电平信号，将所述触发信号输入子电路的输入端与所述触发信号输入子电路的输出端导通；
    所述第一输出子电路的输入端与所述补偿公共电压信号端电连接，第一输出子电路的控制端与第一节点电连接，所述第一输出子电路的输出端与所述公共电压输出端电连接，并且所述第一输出子电路配置成响应于在所述第一输出子电路的控制端处接收到第三电平信号，将所述第一输出子电路的输入端与所述第一输出子电路的输出端导通，其中所述第三电平信号的绝对值大于或等于所述第一电平信号的绝对值，并且所述第三电平信号的极性与所述第一电平信号的极性相同；
    所述控制子电路的第一控制端与所述时钟信号端电连接，所述控制子电路的第二控制端与所述复位子电路的第二输出端电连接，所述控制子电路的第一输入端与所述时钟信号端电连接，所述控制子电路的第二输入端与所述触发信号端电连接，所述控制子电路的第一输出端与所述第一节点电连接，所述控制子电路的第二输出端与第二节点电连接，并且所述控制子电路配置成响应于在所述控制子电路的第一控制端处接收到所述第一电平信号，将所述控制子电路的第二输入端与所述控制子电路的第一输出端导通，将所述控制子电路的第一输入端与所述控制子电路的第二输出端导通，并且响应于在所述控制子电路的第二控制端接收到第二电平信号，将所述控制子电路的第一输入端与所述控制子电路的第二输出端断开；
    所述第二输出子电路的第一控制端与所述第二节点电连接，所述第二输出子电路的第二控制端与所述复位信号端电连接，所述第二输出子电路的第三控制端与所述时钟信号端电连接，所述第二输出子电 路的输入端与所述设计公共电压信号端电连接，所述第二输出子电路的输出端与所述公共电压输出端电连接，并且所述第二输出子电路配置成响应于在所述第二输出子电路的第一控制端、所述第二输出子电路的第二控制端和所述第二输出子电路的第三控制端中的至少一者处接收到所述第一电平信号，将所述第二输出子电路的输入端与所述第二输出子电路的输出端导通；
    所述复位子电路的第一控制端与所述复位信号端电连接，所述复位子电路的第二控制端与所述第二节点电连接，所述复位子电路的第三控制端与所述第一节点电连接，所述复位子电路的输入端与电源信号端电连接，所述复位子电路的第一输出端与所述第一节点电连接，所述复位子电路的第三输出端与所述第二节点电连接，并且所述复位子电路配置成响应于在所述复位子电路的第一控制端和所述复位子电路的第二控制端中的至少一个处接收到所述第一电平信号，将所述复位子电路的输入端与所述复位子电路的第一输出端导通，并且响应于在所述复位子电路的第三控制端处接收到所述第一电平信号，将所述复位子电路的输入端与所述复位子电路的第二输出端和第三输出端导通。
  2. 根据权利要求1所述的公共电压补偿电路单元，其中，所述触发信号输入子电路包括触发输入晶体管，所述触发输入晶体管的第一极和控制极与所述触发信号输入子电路的输入端电连接，并且所述触发输入晶体管的第二极与所述触发信号输入子电路的输出端电连接。
  3. 根据权利要求1所述的公共电压补偿电路单元，其中，所述第一输出子电路包括显示输出晶体管和存储电容器，所述显示输出晶体管的控制极与所述第一输出子电路的控制端电连接，所述显示输出晶体管的第一极与所述补偿公共电压信号端电连接，所述显示输出晶体管的第二极与所述公共电压输出端电连接，所述存储电容器的第一端与所述第一节点电连接，并且所述存储电容器的第二端与第一输出子电路的输出端电连接。
  4. 根据权利要求1所述的公共电压补偿电路单元，其中，所述控制子电路包括第一控制晶体管、第二控制晶体管和第三控制晶体管，
    所述第一控制晶体管的控制极与所述控制子电路的第一控制端电连接，所述第一控制晶体管的第一极与所述控制子电路的第二输入端 电连接，并且所述第一控制晶体管的第二极与所述控制子电路的第一输出端电连接；
    所述第二控制晶体管的控制极和第一极与所述控制子电路的第一输入端电连接，并且所述第二控制晶体管的第二极与所述控制子电路的第二控制端电连接；
    所述第三控制晶体管的控制极与所述控制子电路的第二控制端电连接，所述第三控制晶体管的第一极与所述控制子电路的第一输入端电连接，并且所述第三控制晶体管的第二极与所述控制子电路的第二输出端电连接。
  5. 根据权利要求1所述的公共电压补偿电路单元，其中，所述复位子电路包括第一复位晶体管、第二复位晶体管、第三复位晶体管和第四复位晶体管，
    所述第一复位晶体管的控制极与所述复位子电路的第二控制端电连接，所述第一复位晶体管的第一极与所述复位子电路的输入端电连接，并且所述第一复位晶体管的第二极与所述复位子电路的第一输出端电连接；
    所述第二复位晶体管的控制极与所述复位子电路的第一控制端电连接，所述第二复位晶体管的第一极与所述复位子电路的输入端电连接，并且所述第二复位晶体管的第二极与所述复位子电路的第一输出端电连接；
    所述第三复位晶体管的控制极与所述复位子电路的第三控制端电连接，所述第三复位晶体管的第一极与所述复位子电路的输入端电连接，所述第三复位晶体管的第二极与所述复位子电路的第二输出端电连接；
    所述第四复位晶体管的控制极与所述复位子电路的第三控制端电连接，所述第四复位晶体管的第一极与所述复位子电路的输入端电连接，所述第四复位晶体管的第二极与所述复位子电路的第三输出端电连接。
  6. 根据权利要求1所述的公共电压补偿电路单元，其中，所述第二输出子电路包括第一复位输出晶体管、第二复位输出晶体管和第三复位输出晶体管，
    所述第一复位输出晶体管的控制极与所述第二输出子电路的第二 控制端电连接，所述第一复位输出晶体管的第一极与所述第二输出子电路的输入端电连接，并且所述第一复位输出晶体管的第二极与所述第二输出子电路的输出端电连接；
    所述第二复位输出晶体管的控制极与所述第二输出子电路的第三控制端电连接，所述第二复位输出晶体管的第一极与所述第二输出子电路的输入端电连接，并且所述第二复位输出晶体管的第二极与所述第二输出子电路的输出端电连接；
    所述第三复位输出晶体管的控制极与所述第二输出子电路的第一控制端电连接，所述第三复位输出晶体管的第一极与所述第二输出子电路的输入端电连接，并且所述第三复位输出晶体管的第二极与所述第二输出子电路的输出端电连接。
  7. 一种显示面板，包括级联的多个根据权利要求1至6中任意一项所述的公共电压补偿电路单元、多条栅线、多条公共电极线、第一时钟信号线、第二时钟信号线、电源信号线、设计公共电压信号线和补偿公共电压信号线，其中
    每一个公共电压补偿电路单元的公共电压输出端与相应的公共电极线电连接，每一个公共电压补偿电路单元的触发信号端与相应的栅线电连接，每一个公共电压补偿电路单元的复位信号端与相应的另一栅线电连接，每一个公共电压补偿电路单元的电源信号端与电源信号线电连接，每一个公共电压补偿电路单元的设计公共电压信号端与设计公共电压信号线电连接，并且每一个公共电压补偿电路单元的补偿公共电压信号端与补偿公共电压信号线电连接；
    当公共电压补偿电路单元对应于奇数行的公共电极线时，所述公共电压补偿电路单元的时钟信号端与第一时钟信号线电连接；当公共电压补偿电路单元对应于偶数行的公共电极线时，所述公共电压补偿电路单元的时钟信号端与第二时钟信号线电连接；
    补偿公共电压信号线与公共电压生成芯片电连接，所述公共电压生成芯片配置成，响应于与公共电压补偿电路单元的时钟信号端连接的第一时钟信号线或第二时钟信号线提供第一电平信号，向补偿公共电压信号线提供设计公共电压信号，响应于与公共电压补偿电路单元的时钟信号端连接的第一时钟信号线或第二时钟信号线提供第二电平信号，向补偿公共电压信号线提供补偿公共电压信号。
  8. 根据权利要求7所述的显示面板，包括多行像素单元，每行像素单元包括多个像素单元，所述多行像素单元分别与多行公共电极一一对应，并且
    所述公共电压生成芯片配置成根据公式(1)和公式(2)计算所述补偿公共电压信号：
    ComN-Com’N＝ΔVp   (1)
    Figure PCTCN2018070743-appb-100001
    其中，ComN是用于与公共电压补偿电路单元对应的第N行像素单元的设计公共电压信号的电压值；
    Com’N是用于所述第N行像素单元的补偿公共电压信号的电压值；
    Vgh是第一电平信号的电压值；
    Vgl是第二电平信号的电压值；
    Cgd是所述第N行像素单元中的一个像素单元的薄膜晶体管的栅极与漏极之间的电容；
    Cs是所述像素单元的存储电容；
    Clc是所述像素单元的液晶电容。
  9. 根据权利要求7或8所述的显示面板，其中，所述公共电极线与所述公共电压补偿电路单元一一对应。
  10. 一种显示装置，包括根据权利要求7至9中任意一项所述的显示面板。
  11. 一种显示面板的公共电压补偿方法，使用根据权利要求1至6中任意一项所述的公共电压补偿电路单元，包括输入阶段、显示输出阶段和复位阶段，其中
    在输入阶段，从触发信号端输入第一电平信号，从时钟信号端输入第二电平信号，从复位信号端输入第二电平信号，并且从补偿公共电压信号端输入设计公共电压信号；
    在显示输出阶段，从触发信号端输入第二电平信号，从时钟信号端输入第二电平信号，并且从补偿公共电压信号端输入补偿公共电压 信号；
    在复位阶段，从时钟信号端输入第一电平信号，从触发信号端输入第二电平信号，从复位信号端输入第一电平信号，并且从设计公共电压信号端输入设计公共电压信号。
  12. 根据权利要求11所述的方法，其中，根据公式(1)和公式(2)计算所述补偿公共电压信号：
    ComN-Com’N＝ΔVp   (1)
    Figure PCTCN2018070743-appb-100002
    其中，ComN是用于与公共电压补偿电路单元对应的第N行像素单元的设计公共电压信号的电压值；
    Com’N是用于所述第N行像素单元的补偿公共电压信号的电压值；
    Vgh是第一电平信号的电压值；
    Vgl是第二电平信号的电压值；
    Cgd是所述第N行像素单元中的一个像素单元的薄膜晶体管的栅极与漏极之间的电容；
    Cs是所述像素单元的存储电容；
    Clc是所述像素单元的液晶电容。
PCT/CN2018/070743 2017-05-10 2018-01-04 公共电压补偿电路单元、显示面板、显示装置和显示面板的公共电压补偿方法 Ceased WO2018205653A1 (zh)

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