WO2018189773A1 - Power conversion device - Google Patents

Power conversion device Download PDF

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Publication number
WO2018189773A1
WO2018189773A1 PCT/JP2017/014633 JP2017014633W WO2018189773A1 WO 2018189773 A1 WO2018189773 A1 WO 2018189773A1 JP 2017014633 W JP2017014633 W JP 2017014633W WO 2018189773 A1 WO2018189773 A1 WO 2018189773A1
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WO
WIPO (PCT)
Prior art keywords
circuit
current
snubber circuit
power converter
snubber
Prior art date
Application number
PCT/JP2017/014633
Other languages
French (fr)
Japanese (ja)
Inventor
祐輔 圖子
林　哲也
山上　滋春
貴之 猪狩
賢太郎 秦
敏祐 甲斐
Original Assignee
日産自動車株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日産自動車株式会社 filed Critical 日産自動車株式会社
Priority to JP2019512054A priority Critical patent/JP6717426B2/en
Priority to PCT/JP2017/014633 priority patent/WO2018189773A1/en
Publication of WO2018189773A1 publication Critical patent/WO2018189773A1/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac

Definitions

  • the present invention relates to a power conversion device.
  • the snubber circuit is a first in which a snubber capacitor and a first diode are connected in series.
  • a series circuit and a second series circuit in which a second diode and a transistor are connected in series.
  • the first series circuit is connected to the output terminal of the rectifier circuit, and one end of the second series circuit is connected to the first series.
  • the problem to be solved by the present invention is to provide a power conversion device that suppresses switching loss of a switching element of an inverter circuit and increases efficiency.
  • the present invention includes an inverter circuit having a switching element, a transformer connected to the inverter circuit, a rectifier circuit that rectifies power output from the transformer, and a snubber circuit that suppresses vibration of a current flowing through the rectifier circuit. And the above problem is solved by setting the snubber circuit characteristics such that when the output current of the power converter decreases, the suppression level of the oscillating current increases.
  • the switching loss of the switching element can be suppressed and the efficiency can be increased.
  • FIG. 1 is a block diagram of a power conversion apparatus according to the present embodiment.
  • FIG. 2 is a circuit diagram of the power conversion apparatus according to the present embodiment.
  • FIG. 3 is a graph showing current or voltage characteristics in the circuit of the power conversion device shown in FIG.
  • FIG. 4 is a graph showing current or voltage characteristics in the circuit of the power conversion device shown in FIG.
  • FIG. 5 is a graph showing current or voltage characteristics in the circuit of the power conversion device shown in FIG.
  • FIG. 6 is a front view of a component in which the filter inductor and the variable resistor shown in FIG. 2 are integrated.
  • FIG. 7A is a circuit diagram of a secondary circuit of a power conversion device according to a modification of the present embodiment.
  • FIG. 7A is a circuit diagram of a secondary circuit of a power conversion device according to a modification of the present embodiment.
  • FIG. 7B is a circuit diagram of a circuit on the secondary side of the power conversion device according to the modification of the present embodiment.
  • FIG. 7C is a circuit diagram of a circuit on the secondary side of the power conversion device according to the modification of the present embodiment.
  • FIG. 7D is a circuit diagram of a circuit on the secondary side of the power conversion device according to the modification of the present embodiment.
  • FIG. 8 is a circuit diagram of a secondary circuit of a power conversion device according to another embodiment of the present invention.
  • FIG. 9 is a block diagram of a power converter according to another embodiment of the present invention.
  • FIG. 10A is a circuit diagram of the snubber circuit shown in FIG. FIG.
  • FIG. 10B is a circuit diagram of a snubber circuit of a power conversion device according to a modification of the present embodiment.
  • FIG. 10C is a circuit diagram of a snubber circuit of a power conversion device according to a modification of the present embodiment.
  • FIG. 10D is a circuit diagram of a snubber circuit of a power conversion device according to a modification of the present embodiment.
  • FIG. 11 is a circuit diagram of a snubber circuit of a power conversion device according to a modification of the present embodiment.
  • FIG. 1 is a block diagram of a power conversion apparatus according to the present embodiment.
  • the power converter according to this embodiment is an insulation type DC-DC converter.
  • the power conversion device includes an inverter circuit 10, a transformer 20, a rectifier 30, a filter circuit 40, a snubber circuit 50, and a controller 100.
  • the inverter circuit 10 converts DC power input from the input terminal into AC power.
  • the transformer 20 is a transformer for ensuring insulation, and boosts or steps down the voltage.
  • the transformer 20 is connected to the output of the inverter circuit 10.
  • the inverter circuit 10 is connected to the primary side of the transformer 20, and the rectifier 30, the filter circuit 40, and the snubber circuit 50 are connected to the secondary side of the transformer 20.
  • the rectifier 30 rectifies the power input from the secondary side of the transformer 20 and outputs it to the filter circuit 40.
  • the rectifier 30 converts AC power input from the transformer 20 into DC power.
  • the filter circuit 40 suppresses vibration of power output from the rectifier 30.
  • the snubber circuit 50 suppresses the oscillating current generated in the circuit of the power conversion device.
  • the snubber circuit 50 is connected to at least one of the rectifier 30 and the filter circuit 40. For example, when the current rectified by the rectifier 30 changes sharply in a short time, a surge voltage is generated at the input terminal of the filter circuit 40. In order to suppress this surge voltage, a snubber circuit 50 is connected.
  • the controller 100 controls on / off of the switching elements included in the inverter circuit 10.
  • FIG. 2 is a circuit diagram of the power conversion apparatus according to the present embodiment.
  • the inverter circuit 10 includes switching elements S1 to S4, freewheeling diodes D1 to D4, capacitors 11 to 14, and a smoothing capacitor 15.
  • the switching elements S1 to S4 are MOSFETs. Note that the switching elements S1 to S4 may be transistors such as IGBTs.
  • the switching elements S1 to S4 are connected to form a full bridge circuit. Switching element S1 and switching element S2 are connected in series, and switching element S3 and switching element S4 are connected in series.
  • the connection point between the switching element S1 and the switching element S2 is connected to one end of the primary side coil 21 of the transformer 20, and the connection point between the switching element S3 and the switching element S4 is the other side of the primary side coil 21 of the transformer 20. Connected to the end.
  • Free-wheeling diodes D1-D4 and capacitors 11-14 are connected to the switching elements S1-S4, respectively.
  • the free-wheeling diodes D1 to D4 are connected in parallel to the switching elements S1 to S4 so that the conducting direction of the free-wheeling diodes D1 to Dd is opposite to the current conducting direction (forward direction) of the switching elements S1 to S4. ing.
  • the freewheeling diodes D1 to D4 may be parasitic diodes of the switching elements S1 to S4, and the capacitors 11 to 14 may be parasitic capacitances of the switching elements S1 to S4.
  • a smoothing capacitor 15 is connected between the input terminals of the inverter circuit 10.
  • the transformer 20 has a primary side coil 21 and secondary side coils 22a, 22b.
  • the primary coil 21 is connected to the output of the inverter circuit 10.
  • the secondary side of the transformer 20 is a center tap type, and wiring is connected to a connection point between the secondary side coil 22a and the secondary side coil 22b.
  • the primary side coil 21 and the secondary side coils 22a and 22b are insulated.
  • the transformer 20 boosts or lowers the voltage according to the winding ratio (Np / Ns) between the primary side coil 21 and the secondary side coils 22a, 22b.
  • the rectifier 30 has a diode D31 and a diode D32.
  • the anode terminal of the diode D31 is connected to the secondary coil 22a, and the cathode terminal of the diode D31 is connected to the filter inductor 41.
  • the anode terminal of the diode D32 is connected to the secondary coil 22b, and the cathode terminal of the diode D32 is connected to a connection point connecting the cathode terminal of the diode D31 and the filter inductor 41.
  • the filter circuit 40 is an LC filter and includes a filter inductor 41 and a filter capacitor 42.
  • the filter inductor 41 is connected to the positive power line.
  • the filter capacitor 42 is connected to the output side of the filter circuit 40, and is connected between the positive power line and the negative power line.
  • the negative power line is connected to a connection point between the secondary coil 22a and the secondary coil 22b.
  • the rectifier 30 and the filter circuit 40 correspond to a secondary side rectifier circuit.
  • the snubber circuit 50 includes a capacitor 51 and a variable resistor 52.
  • the capacitor 51 and the variable resistor 52 are connected in series, and a series circuit of the capacitor 51 and the variable resistor 52 is connected in parallel to the filter inductor 41.
  • the controller 100 controls on / off of the switching elements S1 to S4, so that the two half bridges output square wave voltages.
  • the controller 100 controls the switching elements S1 to S4 so that the duty ratio of the square wave voltage is 50%.
  • the alternating current flows through the primary side coil 21 of the transformer 20 by shifting the phase of the two square wave voltages.
  • An AC voltage is applied to the transformer 20, and power is transmitted to the secondary side of the transformer 20.
  • the switching operation of the switching elements S1 to S4 is soft switching
  • a circuit configuration in which partial resonance occurs in a circuit on the primary side of the power converter is provided.
  • the partial resonance is generated in the LC circuit including the drain-source capacitance of the switching elements S1 to S4 and the leakage inductance (L rec ) of the transformer. Since the partial resonance occurs during the dead time period of the switching elements S1 to S4, the switching elements S1 to S4 are turned on by zero voltage switching (ZVS), so that the switching operation of the switching elements S1 to S4 is Soft switching.
  • ZVS zero voltage switching
  • the drain-source capacitance (hereinafter also referred to as DS capacitance) of the switching elements S1 to S4 is charged, so that the voltage rise between the drain and source is delayed. Thereby, the overlap period of the voltage and current at the time of turn-off can be shortened, and soft switching can be realized.
  • the discharge of the DS capacities of the switching elements S1 to S4 must end during the dead time period.
  • the discharge of the DS capacitor ends during the dead period, even if the switching elements S1 to S4 are turned on, the discharge current of the DS capacitor does not flow to the switching elements S1 to S4 that are turned on.
  • the overlapping period of voltage and current is shortened, and soft switching can be realized.
  • the switching elements S1 to S4 are turned on during the dead time period when the discharge of the DS capacitor is not completed, the DS capacitor discharge current flows to the turned-on switching element. As a result, the switching loss increases.
  • a current that urges the discharge must flow to the primary side of the transformer 20. That is, when the primary side current of the transformer 20 is low during the dead time period, the DS capacity discharge current becomes small, and thus the DS capacity discharge does not end during the dead time period. Further, when the direction of the primary current of the transformer 20 changes during the dead time period, the forward current flows to the free wheel diodes D1 to D4 connected to the switching elements S1 to S4 in the off state, The DS capacities of the switching elements S1 to S4 to be turned on are charged. Therefore, the turn-on operation of the switching elements S1 to S4 becomes hard switching, and the output voltage of the inverter circuit 10 becomes unstable.
  • FIG. 3 shows the characteristics of the input voltage (V L , V R ) of the primary side winding 21, the characteristics of the primary side current (I TR ) of the transformer 20, and the currents flowing through the diodes D 31 and D 32 of the rectifier 30 (I 4 is a graph showing characteristics of D1 and I D2 ), current (I L ) characteristics of the filter inductor 41, and voltage (V rec ) characteristics of the filter inductor 41.
  • the input voltage (V L ) corresponds to one output voltage of the two half bridges of the inverter circuit 10
  • the input voltage (V R ) corresponds to the other output voltage.
  • the primary current (I TR ) of the transformer 20 increases with a positive slope.
  • the primary side current (I TR ) is expressed by the following formula (1) according to the relationship between the input voltage (V in ) and the leakage inductance (L s ).
  • the transformer secondary side of the current (I D1) is a current value obtained by multiplying turns ratio (Np / Ns) to the transformer primary current (I TR) match.
  • the slope of the primary side current (I TR ) becomes gentler than the slope between time t 1 and t 2 (slope shown by equation (1)).
  • the primary current (I TR ) changes at the time t 2
  • the current (I L ) flowing through the filter inductor 41 changes abruptly, so that a surge voltage (V rec ) is likely to be generated at the output of the rectifier 30.
  • V rec the point at which the current (I L ) of the filter inductor 41 changes sharply is represented by a circle surrounded by a dotted line, and a surge voltage is likely to occur at the dotted line portion.
  • the primary current (I TR ) gradually increases with a constant slope after time t 2 and gradually decreases with a constant slope after time t 3 .
  • Time t 3 is timing when the output voltage (V R ) of the half bridge of the inverter circuit 10 rises.
  • the primary current (I TR ) greatly decreases at the timing (time t 4 ) when the output voltage (V L ) of the half bridge of the inverter circuit 10 falls.
  • the output current (I L ) of the filter inductor 41 gradually increases with a constant slope after time t 2 and gradually decreases with a constant slope after time t 3 .
  • the output current (I L ) gradually increases again at time t 5 .
  • Transformer secondary side of the current (I D2) are timing value of current multiplied by the turns ratio of the (Np / Ns) to the transformer primary current (I TR) coincide is time t 5.
  • the output current of the power converter (I out) is the characteristics when the output current (I out) is lower than when shown in FIG. 3
  • FIG. 4 shows the input voltage characteristics (V L , V R ), the primary side current characteristics (I TR ), and the current characteristics of the diodes D31 and D32 in order from the top of FIG. 4 in the same manner as the voltage / current characteristics shown in FIG. (I D1 , I D2 ), a current characteristic (I L ) of the filter inductor 41, and a voltage characteristic (V rec ) of the filter inductor 41 are shown.
  • FIG. 4 shows the characteristics when the output current of the power converter is lower than the output current (I out ) at the time shown in FIG.
  • the rising and falling timings of the output voltages (V L , V R ) of the half bridge of the inverter circuit 10 are the same as those in FIG.
  • the output current (I out ) is low, the current (I L ) of the filter inductor 41 is low, and the primary current (I TR ) has a linear relationship with the current (I L ) of the filter inductor 41. Therefore, the primary side current (I TR ) is also reduced.
  • a dead time period (t d ) is from time t 1 to time t 2 . That is, when the output current (I out ) is low, the primary current (I TR ) is low in the dead time period (t d ). In the dead time period (t d ), when the primary side current (I TR ) becomes low enough that the DS capacity of the switching elements S1 to S4 cannot be discharged, the switching operation of the switching elements S1 to S4 is hard. It becomes switching.
  • a surge voltage is likely to occur at the end timing (t 2 , t 4, etc.) of the dead time period (t d ).
  • an oscillating current is generated by charging and discharging the junction capacitances of the diodes D31 and D32 included in the rectifier 30.
  • the oscillating current on the secondary side resonates via the transformer 20 due to the leakage in inductor (L s ) on the primary side of the transformer 20. That is, the primary-side current is vibrated by the secondary-side oscillating current.
  • FIG. 5 shows the characteristics of the input voltage (V L ) of the primary winding 21, the switching operation characteristics of the switching elements S 1 and S 2 (and the configuration of the drive signals of the switching elements S 1 and S 2), and the primary of the transformer 20.
  • the characteristics of the side currents (I TR_ réelle , I TR_b ) are shown.
  • a high level of the switching operation characteristic indicates an on state, and a low level indicates an off state.
  • the primary side current (I TR_ réelle ) indicates a current when the vibration suppression level by the snubber circuit 50 is high
  • the primary side current (I TR_b ) indicates a current when the vibration suppression level of the snubber circuit 50 is low.
  • the primary current of the transformer 20 (I TR_ réelle, I TR_b) is flowing in the negative direction.
  • the DS capacity is discharged. If the vibration suppression level of the snubber circuit 50 is high, since the current vibration of the secondary side is suppressed, the primary current does not vibrate, between the time t 1 to time t 2, the primary side The direction of the current ( ITR_ réelle ) remains negative and does not change.
  • a negative current continues to flow on the primary side of the transformer 20, so that the DS capacity is discharged during the dead time period.
  • the turn-on operation of the switching element S1 is soft switching.
  • the vibration suppression level of the snubber circuit 50 should be high.
  • increasing the vibration level of the snubber circuit 50 increases the loss of the snubber circuit.
  • the vibration suppression level characteristic hereinafter also referred to as vibration suppression characteristic
  • the vibration suppression level becomes small, and the loss of the snubber circuit 50 can be suppressed.
  • the vibration suppression level is high, and the soft switching operation of the switching elements S1 to S4 can be realized while suppressing the secondary-side vibration current.
  • FIG. 6 is a front view of a component in which the filter inductor 41 and the variable resistor 52 are integrated.
  • the filter inductor 41 has a magnetic core 411 and an inductor coil 412.
  • the magnetic core 411 is a magnetic body that covers the inductor coil 412 and the variable resistor 52.
  • the inductor coil 412 is a pair of coils.
  • the current flowing through the inductor coil 412 is the current of the filter inductor 41 and corresponds to the output current (I out ) of the power converter.
  • the variable resistor 52 is a magnetoresistive element such as an MR element or a GMR element.
  • the variable resistor 52 is provided in the gap of the magnetic core 411.
  • the inductor coil 412 When the output current of the rectifier circuit 31 flows through the inductor coil 412, the inductor coil 412 generates a magnetic field and forms a magnetic circuit in the magnetic core 411.
  • the variable resistor 52 is disposed in the magnetic circuit.
  • the magnetic field generated by the inductor coil 412 is proportional to the current of the filter inductor 41.
  • the variable resistor 52 has a positive characteristic with respect to the magnetic field, and the resistance value of the variable resistor 52 increases as the magnetic field strength increases.
  • the snubber circuit 50 is connected in parallel with the filter inductor 41, and the resistance value of the snubber circuit 50 increases as the current of the filter inductor 41 increases. The higher the resistance value of the snubber circuit 50, the lower the level of vibration current suppression by the snubber circuit 50.
  • the suppression level by the snubber circuit 50 becomes higher.
  • the higher the current of the filter inductor 41, the higher the resistance value of the snubber circuit 50 and the lower the level of vibration current suppression by the snubber circuit 50 the magnetic field intensity generated in the filter inductor becomes a parameter having a correlation with the output current, and the suppression level of the oscillating current by the snubber circuit 50 changes according to the parameter.
  • the surge voltage becomes high because the vibration suppression level by the snubber circuit 50 is lowered, the peak value of the surge voltage is suppressed below the reference value.
  • the reference value is an upper limit value of a voltage determined by a rated voltage of a circuit element included in the power converter, and is set in advance.
  • the output current (I out ) of the power converter and the current of the filter inductor 41 are low, and the level of suppression of vibration by the snubber circuit 50 is high. Therefore, since the secondary side oscillation current is suppressed, the direction of the primary side current does not change during the dead time period and is maintained in the negative direction. Thereby, when the output current (I out ) of the power converter is low, soft switching of the switching elements S1 to S4 can be realized. The current range enabling soft switching is widened with respect to the magnitude of the output current (I out ) of the power converter.
  • the output current (I out ) of the power converter and the current of the filter inductor 41 are increased, and the loss of the snubber circuit 50 is reduced.
  • the power conversion device includes the inverter circuit 10, the transformer 20, the rectifier 30, and the snubber circuit 50.
  • the snubber circuit 50 has a characteristic that when the output current of the power conversion device decreases, the level of suppression of vibration current by the snubber circuit 50 increases. Thereby, the switching loss of a switching element can be suppressed and efficiency can be improved.
  • the switching elements S1 to S4 operate by soft switching using LC resonance. Thereby, switching loss is suppressed and efficiency can be improved.
  • the level of suppression of the oscillating current by the snubber circuit 50 changes according to a parameter having a correlation with the output current of the power converter.
  • variable resistor 52 is composed of a magnetoresistive element, and the magnetoresistive element is arranged in a magnetic circuit generated by the filter inductor 41.
  • the filter inductor 41 is arranged in the gap of the magnetic core 411. Thereby, vibration suppression characteristics can be realized with a simple configuration.
  • the diodes D31 and D32 are configured by devices that do not operate in reverse recovery operation. Thereby, when the output current of the power converter is high, the surge voltage is suppressed, so that the level of vibration current suppression by the snubber circuit can be further reduced. As a result, the loss of the snubber circuit can be reduced.
  • the variable resistor 52 included in the snubber circuit 50 may be a resistance having positive temperature characteristics.
  • the resistor having a positive temperature characteristic is, for example, a PTC resistor.
  • variable resistor 52 when the variable resistor 52 is a resistor having a positive temperature characteristic, the variable resistor 52 may be disposed in the vicinity of the transformer 20 or the rectifier 30. When a current flows through the power conversion device, elements included in the transformer 20 or the rectifier 30 generate heat. The variable resistor 52 is disposed in the vicinity of the transformer 20 or the rectifier 30, so that the variable resistor 52 can exchange heat with an element serving as a heat source. Thereby, vibration suppression characteristics can be realized with a simple configuration.
  • the capacitor 51 included in the snubber circuit 50 may be a capacitor having negative temperature characteristics.
  • the capacitance of the capacitor 51 decreases. Therefore, the effect of suppressing the oscillating current by the snubber circuit 50 is reduced, and the loss of the snubber circuit 50 is suppressed.
  • the snubber circuit 50 can be configured to have vibration suppression characteristics.
  • the capacitor 51 when the capacitor 51 is a capacitor having a negative temperature characteristic, the capacitor 51 may be disposed in the vicinity of the transformer 20 or the rectifier 30.
  • the capacitor 51 When a current flows through the power conversion device, elements included in the transformer 20 or the rectifier 30 generate heat.
  • the capacitor 51 is disposed in the vicinity of the transformer 20 or the rectifier 30, so that the capacitor 51 can exchange heat with an element serving as a heat source. Thereby, vibration suppression characteristics can be realized with a simple configuration.
  • the capacitor 51 or the variable resistor 52 according to the modification may be arranged adjacent to the temperature-dependent filter inductor 41, the magnetic core 411, and the diodes D31 and D32. Thereby, the electrostatic capacitance of the capacitor 51 or the resistance value of the variable resistor 52 is likely to change with respect to temperature.
  • the snubber circuit 50 does not need to be connected in parallel to the filter inductor 41 as shown in FIG. 2, but is connected between the filter inductor 41 and the reference potential of the output voltage as shown in FIG. 7A or 7B. Also good.
  • the reference potential of the output voltage corresponds to the negative potential of the output voltage of the power converter.
  • the snubber circuit 50 includes a capacitor 51, a diode 53, and a resistor 54.
  • the capacitor 51 is connected to the cathode of the diode 53, and the series circuit of the capacitor 51 and the diode 53 is connected between the pair of power supply lines of the filter circuit 40.
  • One end of the resistor 54 is connected to a connection point connecting the capacitor 51 and the diode 53, and the other end of the resistor 54 is connected to a connection point connecting the filter inductor 41 and the filter capacitor 42.
  • the snubber circuit 50 includes a capacitor 51 and a resistor 54.
  • a series circuit of the capacitor 51 and the resistor 54 is connected between a pair of power supply lines of the filter circuit 40.
  • the rectifier 30 may be a full bridge rectifier circuit as shown in FIGS. 7C and 7D.
  • 7C and 7D are circuit diagrams on the secondary side of the power conversion device according to the modification.
  • the configuration of the filter circuit 40 is the same as described above.
  • the secondary coil of the transformer 20 is configured by a single coil.
  • the rectifier 30 is configured by a full bridge circuit of diodes D31 to D34.
  • the snubber circuit 50 is connected in parallel to the diodes D31 to D34.
  • the snubber circuit 50 includes a capacitor 51 and a resistor 54, and the capacitor 51 and the resistor 54 are connected in series.
  • the secondary coil of the transformer 20 is formed of a single coil.
  • the rectifier 30 is configured by a full bridge circuit of diodes D31 to D34.
  • the snubber circuit 50 has the same configuration as the snubber circuit 50 shown in FIG. 7A.
  • the connection form between the filter circuit 40 and the snubber circuit 50 is the same as the connection form shown in FIG. 7A.
  • the rectifying element included in the rectifier 30 is not limited to the diodes D31 to D34, and may be a circuit configuration in which a diode and a transistor such as a MOSFET are connected in parallel.
  • the rectifier circuit may be a synchronous rectifier circuit that synchronizes the on / off operation of each transistor.
  • the diodes D31 and D32 included in the rectifier 30 may be devices that do not involve reverse recovery operation, such as Schottky barrier diodes.
  • a surge voltage is generated by charging / discharging the junction capacitance of the diodes D31 and D32, and an oscillating current is generated in the secondary side circuit of the power converter by the surge voltage.
  • the oscillating current does not depend on the current value flowing through the diodes D31 and D32, but depends on the voltage applied to the diodes D31 and D32. Therefore, the surge voltage can be suppressed when the secondary current increases. Thereby, the vibration suppression level in the high current region is suppressed, the loss of the snubber circuit 50 is reduced, and the efficiency is improved.
  • the level of suppression of the oscillating current by the snubber circuit 50 is set to a plurality of levels according to the magnitude of the output current of the power converter.
  • the configuration of the snubber circuit 50 is different from that of the first embodiment in the power conversion device according to this embodiment, and the description of the first embodiment is used as appropriate for other configurations.
  • FIG. 8 is a circuit diagram of the secondary side of the power conversion device.
  • the snubber circuit 50 includes a capacitor 51, resistors 54a and 54b, and a transistor 55.
  • the capacitor 51, the transistor 55, and the resistor 54a are connected in series, and the series circuit of the capacitor 51, the transistor 55, and the resistor 54a is connected in parallel to the filter inductor 41.
  • the control terminal (base terminal or gate terminal) of the transistor 55 is connected to the power supply line on the positive side of the filter circuit 40 via the resistor 54b.
  • the current input from the rectifier 30 to the filter circuit 40 is branched at the connection point between the filter inductor 41 and the resistor 54b.
  • the control current (base current or gate current) flowing through the control terminal of the transistor 55 is a current that is inversely proportional to the output current (I out ) of the power converter.
  • the collector-emitter between the transistors functions as a variable resistor. That is, when the output current (I out ) of the power conversion device decreases, the control current of the transistor 55 increases and the resistance of the transistor 55 decreases. Therefore, when the resistance value of the snubber circuit 50 decreases, the level of suppression of the oscillating current by the snubber circuit 50 increases.
  • the snubber circuit 50 can be configured so that the characteristics of the snubber circuit 50 have vibration suppression characteristics.
  • the level of suppression of the oscillating current by the snubber circuit 50 is a plurality of levels.
  • the plurality of suppression levels change according to the magnitude of the output current of the power converter.
  • the level of suppression of the oscillating current by the snubber circuit 50 is set to a plurality of levels according to the magnitude of the output current (I out ).
  • the suppression level can be changed in multiple steps while having a correlation with the output current (I out ), so that the efficiency is improved.
  • the snubber circuit 50 includes a transistor 55, and the relationship between the current at the control terminal of the transistor and the output current (I out ) of the power converter is inversely proportional. Thereby, vibration suppression characteristics can be realized with a simple configuration.
  • the transistor 55 may be a switching element that can be energized in both directions. Further, the transistor 55 is a normally-on switching element, and the secondary side circuit of the power converter is configured such that the negative bias voltage of the gate of the transistor 55 increases as the output current (I out ) increases. Good. Thereby, since the characteristic of the snubber circuit 50 can be made into a vibration suppression characteristic, efficiency can be improved, suppressing the switching loss of a switching element.
  • the snubber circuit 50 includes a switch, and vibration suppression characteristics are realized by controlling on / off of the switch.
  • the power converter according to the present embodiment differs from the first embodiment in the configuration of the snubber circuit 50 and the control of the snubber circuit 50.
  • the other configurations are the same as those in the first embodiment or the second embodiment. The description is incorporated as appropriate.
  • FIG. 9 is a block diagram of the power converter according to the present embodiment.
  • the power converter includes a current sensor 200 in addition to the inverter circuit 10 and the like.
  • the current sensor 200 is connected to the output side of the filter circuit 40 and detects the output current (I out ) of the power converter.
  • the current sensor 200 outputs the detected current to the controller 100.
  • a sensor such as a Hall current sensor is used.
  • the controller 100 switches on and off the switches included in the snubber circuit 50 according to the detected voltage acquired from the current sensor 200.
  • the current sensor 20 may be connected to the input side of the filter circuit 40.
  • the snubber circuit 50 has at least a switch 56.
  • the switch 56 is a semiconductor switch.
  • the switch 56 is not limited to a semiconductor switch, and may be a mechanical contact switch.
  • FIG. 10A A specific circuit configuration of the snubber circuit 50 is shown in FIG. 10A.
  • FIG. 10A is a circuit diagram of the snubber circuit 50.
  • the snubber circuit 50 includes a capacitor 51, resistors 54a and 54b, and a switch 56.
  • the capacitor 51 and the resistor 54a are connected in series.
  • the resistor 54b and the switch 56 are connected in series.
  • a series circuit of the resistor 54b and the switch 56 is connected in parallel to the resistor 54a.
  • the resistance value of the snubber circuit 50 is a combined resistance value of the resistor 54a and the resistor 54b.
  • the resistance value of the snubber circuit 50 is the resistance value of the resistor 54a.
  • the resistance value of the snubber circuit 50 changes according to whether the switch 56 is turned on or off, the level of suppression of the oscillating current by the snubber circuit 50 changes. That is, the switch 56 is a switch that switches the suppression level of the snubber circuit 50.
  • the controller 100 outputs a driving voltage or a driving current for controlling on / off of the switch 56 to the snubber circuit 50.
  • a power supply for driving is built in the snubber circuit 50.
  • the controller 100 stores a current threshold value in a memory.
  • the current threshold is a threshold for determining whether the switch is turned on or off, and is set in advance.
  • the controller 100 compares the current threshold value with the detected current of the current sensor 200, and switches the switch 56 on and off according to the comparison result.
  • controller 100 may be divided into control for the inverter circuit 10 and control for the snubber circuit 50. Moreover, the structure which the control signal for switching on / off of the switch 56 is insulated may be sufficient. Thereby, the threshold value for varying the vibration suppression level of the snubber circuit can be adjusted.
  • the controller 100 controls the switch 56 as follows.
  • the controller 100 turns off the switch 56 and increases the resistance value of the snubber circuit 50.
  • the suppression level of the snubber circuit 50 becomes a low level, and the loss of the snubber circuit 50 is suppressed.
  • the controller 100 turns on the switch 56 to lower the resistance value of the snubber circuit 50. Since the suppression level of the snubber circuit 50 becomes high and the vibration suppression effect by the snubber circuit 50 increases, a soft switching operation can be realized.
  • the snubber circuit 50 includes the switch 56 that switches the suppression level, and the controller 100 switches the switch 56 on and off according to the magnitude of the current detected by the current sensor 200.
  • vibration suppression characteristics can be obtained while controlling the vibration suppression level in multiple stages according to the magnitude of the output current (I out ).
  • the snubber circuit 50 is not limited to the circuit configuration shown in FIG. Examples of other circuit configurations are shown in FIGS. 10B to 10D. 10B to 10D are circuit diagrams of a snubber circuit 50 according to a modification.
  • the snubber circuit 50 includes capacitors 51a and 51b, a resistor 54, and a switch 56.
  • a capacitor 51a and a resistor 54 are connected in series, and a capacitor 51b and a switch 56 are connected in series.
  • a series circuit of the capacitor 51b and the switch 56 is connected in parallel to the capacitor 51b.
  • the suppression level of the snubber circuit 50 can be switched in multiple stages by switching the capacitance of the snubber circuit 50 by turning on and off the switch 56.
  • the snubber circuit 50 includes capacitors 51a and 51b, a resistor 54, and a switch 56.
  • the capacitors 51a and 51b and the resistor 54 are connected in series.
  • the switch 56 is connected in parallel to the capacitor 51b.
  • the suppression level of the snubber circuit 50 can be switched in multiple stages by switching the capacitance of the snubber circuit 50 by turning on and off the switch 56.
  • the snubber circuit 50 includes a capacitor 51, resistors 54a and 54b, and a switch 56.
  • the capacitor 51, the resistor 54a, and the resistor 54b are connected in series.
  • the switch 56 is connected in parallel with the resistor 54a.
  • the snubber circuit 50 may be a circuit combining the circuits shown in FIGS. 10A to 10D, and the conduction circuit and the non-conduction circuit may be switched in accordance with the magnitude of the output current (I out ).
  • the snubber circuit 50 may include a plurality of protection circuits having different suppression levels.
  • FIG. 11 is a circuit diagram of a snubber circuit 50 according to a modification. As shown in FIG. 11, the snubber circuit 50 includes switches 56a and 56b and protection circuits 57a to 57c.
  • the protection circuits 57a to 57c are series circuits in which capacitors 51a to 51c and resistors 54a to 54c are connected in series.
  • the capacitors 51a to 51c are capacitors having different capacitances, and the resistors 54a to 54c are resistors having different resistance values.
  • the protection circuits 57a to 57c are independent snubber circuits, and are circuits having different vibration suppression levels.
  • the switch 56a is connected between the protection circuit 57a and the protection circuit 57b, and the switch 56b is connected between the protection circuit 57b and the protection circuit 57c.
  • the controller 100 switches between conduction and non-conduction of the protection circuits 57a to 57c by switching the switches 56 and 56b on and off according to the magnitude of the detected current detected by the current sensor 200. Thereby, the suppression level of the snubber circuit 50 can be switched in multiple stages.
  • the snubber circuit 50 may be connected to the rectifier 30 or the filter circuit 40 via a switch. Then, the controller 100 turns off the switch and disconnects the snubber circuit 50 in accordance with the magnitude of the output current (I out ). Thereby, when the vibration suppression by the snubber circuit 50 is unnecessary, the snubber circuit 50 can be cut off, so that the efficiency can be improved.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

A power conversion device comprising an inverter circuit 10 having switching elements S1-S6, a transformer 20 connected to the inverter circuit 10, a rectifier circuit that rectifies the power outputted from the transformer 20, and a snubber circuit 50 that suppresses oscillation of the current flowing to the rectifier circuit. The snubber circuit 50 has characteristics such that when the current outputted from the power conversion device decreases, the level of suppression level of the oscillating current increases.

Description

電力変換装置Power converter
　本発明は、電力変換装置に関するものである。 The present invention relates to a power conversion device.
　従来より、インバータと、整流回路と、整流回路に接続される平滑回路と、スナバ回路とを備えた電力変換装置において、スナバ回路は、スナバコンデンサと第１ダイオードとが直列に接続された第１直列回路と、第２のダイオードとトランジスタとが直列に接続された第２直列回路とを具備し、第１直列回路を整流回路の出力端に接続し、第２直列回路の一端を第１直列回路のスナバコンデンサと第１のダイオードの直列接続点に接続し、その他端を平滑回路の平滑インダクタと平滑コンデンサの直列接続点に接続し、第２直列回路のトランジスタのベース端子にツェナーダイオードを接続して、第２直列回路の第２のダイオードとトランジスタの直列接続点の電位を所定値に制御するものが知られている（特許文献１）。 Conventionally, in a power converter including an inverter, a rectifier circuit, a smoothing circuit connected to the rectifier circuit, and a snubber circuit, the snubber circuit is a first in which a snubber capacitor and a first diode are connected in series. A series circuit; and a second series circuit in which a second diode and a transistor are connected in series. The first series circuit is connected to the output terminal of the rectifier circuit, and one end of the second series circuit is connected to the first series. Connect the snubber capacitor of the circuit to the series connection point of the first diode, connect the other end to the series connection point of the smoothing inductor and smoothing capacitor of the smoothing circuit, and connect the Zener diode to the base terminal of the transistor of the second series circuit And what controls the electric potential of the 2nd diode of a 2nd series circuit and the series connection point of a transistor to a predetermined value is known (patent document 1).
特開２０１１－２４４５５９号公報JP2011-244559A 特開２０１３－１１６０２１号公報JP 2013-1116021 A
　しかしながら、インバータのスイッチング素子の損失が大きく、効率がよくないという問題があった。 However, there is a problem that the switching element loss of the inverter is large and the efficiency is not good.
　本発明が解決しようとする課題は、インバータ回路のスイッチング素子のスイッチング損失を抑制し、効率を高めた電力変換装置を提供することである。 The problem to be solved by the present invention is to provide a power conversion device that suppresses switching loss of a switching element of an inverter circuit and increases efficiency.
　本発明は、スイッチング素子を有するインバータ回路と、インバータ回路に接続される変圧器と、変圧器からの出力される電力を整流する整流回路と、整流回路に流れる電流の振動を抑制するスナバ回路とを備え、スナバ回路の特性を、電力変換装置の出力電流が低くなると、振動電流の抑制レベルがより高くなるようにすることによって上記課題を解決する。 The present invention includes an inverter circuit having a switching element, a transformer connected to the inverter circuit, a rectifier circuit that rectifies power output from the transformer, and a snubber circuit that suppresses vibration of a current flowing through the rectifier circuit. And the above problem is solved by setting the snubber circuit characteristics such that when the output current of the power converter decreases, the suppression level of the oscillating current increases.
　本発明によれば、スイッチング素子のスイッチング損失を抑制し、効率を高めることができる。 According to the present invention, the switching loss of the switching element can be suppressed and the efficiency can be increased.
図１は、本実施形態に係る電力変換装置のブロック図である。FIG. 1 is a block diagram of a power conversion apparatus according to the present embodiment. 図２は、本実施形態に係る電力変換装置の回路図である。FIG. 2 is a circuit diagram of the power conversion apparatus according to the present embodiment. 図３は、図２に示す電力変換装置に回路における電流又は電圧特性を示すグラフである。FIG. 3 is a graph showing current or voltage characteristics in the circuit of the power conversion device shown in FIG. 図４は、図２に示す電力変換装置に回路における電流又は電圧特性を示すグラフである。FIG. 4 is a graph showing current or voltage characteristics in the circuit of the power conversion device shown in FIG. 図５は、図２に示す電力変換装置に回路における電流又は電圧特性を示すグラフである。FIG. 5 is a graph showing current or voltage characteristics in the circuit of the power conversion device shown in FIG. 図６は、図２に示すフィルタインダクタと可変抵抗を一体化した構成部品の正面図である。FIG. 6 is a front view of a component in which the filter inductor and the variable resistor shown in FIG. 2 are integrated. 図７Ａは、本実施形態の変形例に係る電力変換装置の２次側の回路の回路図である。FIG. 7A is a circuit diagram of a secondary circuit of a power conversion device according to a modification of the present embodiment. 図７Ｂは、本実施形態の変形例に係る電力変換装置の２次側の回路の回路図である。FIG. 7B is a circuit diagram of a circuit on the secondary side of the power conversion device according to the modification of the present embodiment. 図７Ｃは、本実施形態の変形例に係る電力変換装置の２次側の回路の回路図である。FIG. 7C is a circuit diagram of a circuit on the secondary side of the power conversion device according to the modification of the present embodiment. 図７Ｄは、本実施形態の変形例に係る電力変換装置の２次側の回路の回路図である。FIG. 7D is a circuit diagram of a circuit on the secondary side of the power conversion device according to the modification of the present embodiment. 図８は、本発明の他の実施形態に係る電力変換装置の２次側の回路の回路図である。FIG. 8 is a circuit diagram of a secondary circuit of a power conversion device according to another embodiment of the present invention. 図９は、本発明の他の実施形態に係る電力変換装置のブロック図である。FIG. 9 is a block diagram of a power converter according to another embodiment of the present invention. 図１０Ａは、図９に示すスナバ回路の回路図である。FIG. 10A is a circuit diagram of the snubber circuit shown in FIG. 図１０Ｂは、本実施形態の変形例に係る電力変換装置のスナバ回路の回路図である。FIG. 10B is a circuit diagram of a snubber circuit of a power conversion device according to a modification of the present embodiment. 図１０Ｃは、本実施形態の変形例に係る電力変換装置のスナバ回路の回路図である。FIG. 10C is a circuit diagram of a snubber circuit of a power conversion device according to a modification of the present embodiment. 図１０Ｄは、本実施形態の変形例に係る電力変換装置のスナバ回路の回路図である。FIG. 10D is a circuit diagram of a snubber circuit of a power conversion device according to a modification of the present embodiment. 図１１は、本実施形態の変形例に係る電力変換装置のスナバ回路の回路図である。FIG. 11 is a circuit diagram of a snubber circuit of a power conversion device according to a modification of the present embodiment.
　以下、本発明の実施形態を図面に基づいて説明する。　 Hereinafter, embodiments of the present invention will be described with reference to the drawings. *
《第１実施形態》
　図１は、本実施形態に係る電力変換装置のブロック図である。本実施形態に係る電力変換装置は絶縁型のＤＣ－ＤＣコンバータである。図１に示すように、電力変換装置は、インバータ回路１０、変圧器２０、整流器３０、フィルタ回路４０、スナバ回路５０、及びコントローラ１００を備えている。 << First Embodiment >>
FIG. 1 is a block diagram of a power conversion apparatus according to the present embodiment. The power converter according to this embodiment is an insulation type DC-DC converter. As shown in FIG. 1, the power conversion device includes an inverter circuit 10, a transformer 20, a rectifier 30, a filter circuit 40, a snubber circuit 50, and a controller 100.
　インバータ回路１０は、入力端子より入力される直流電力を交流電力に変換する。変圧器２０は、絶縁を確保するためのトランスであり、電圧を昇圧又は降圧する。変圧器２０は、インバータ回路１０の出力に接続されている。変圧器２０の１次側にはインバータ回路１０が接続され、変圧器２０の２次側には、整流器３０、フィルタ回路４０及びスナバ回路５０が接続されている。 The inverter circuit 10 converts DC power input from the input terminal into AC power. The transformer 20 is a transformer for ensuring insulation, and boosts or steps down the voltage. The transformer 20 is connected to the output of the inverter circuit 10. The inverter circuit 10 is connected to the primary side of the transformer 20, and the rectifier 30, the filter circuit 40, and the snubber circuit 50 are connected to the secondary side of the transformer 20.
　整流器３０は、変圧器２０の２次側から入力される電力を整流し、フィルタ回路４０に出力する。整流器３０は、変圧器２０から入力される交流電力を直流電力に変換する。フィルタ回路４０は、整流器３０から出力される電力の振動を抑制する。 The rectifier 30 rectifies the power input from the secondary side of the transformer 20 and outputs it to the filter circuit 40. The rectifier 30 converts AC power input from the transformer 20 into DC power. The filter circuit 40 suppresses vibration of power output from the rectifier 30.
　スナバ回路５０は、電力変換装置の回路内で発生する振動電流を抑制する。スナバ回路５０は、整流器３０及びフィルタ回路４０の少なくとも何れか一方の回路に接続されている。例えば、整流器３０で整流された電流が短時間で急峻に変化する場合に、フィルタ回路４０の入力端にはサージ電圧が発生する。このサージ電圧を抑制するためには、スナバ回路５０が接続されている。 The snubber circuit 50 suppresses the oscillating current generated in the circuit of the power conversion device. The snubber circuit 50 is connected to at least one of the rectifier 30 and the filter circuit 40. For example, when the current rectified by the rectifier 30 changes sharply in a short time, a surge voltage is generated at the input terminal of the filter circuit 40. In order to suppress this surge voltage, a snubber circuit 50 is connected.
　コントローラ１００は、インバータ回路１０に含まれるスイッチング素子のオン、オフを制御する。 The controller 100 controls on / off of the switching elements included in the inverter circuit 10.
　本実施形態に係る電力変換装置の回路図の一例を、図２を用いて説明する。図２は、本実施形態に係る電力変換装置の回路図である。 An example of a circuit diagram of the power conversion device according to the present embodiment will be described with reference to FIG. FIG. 2 is a circuit diagram of the power conversion apparatus according to the present embodiment.
　インバータ回路１０は、スイッチング素子Ｓ１～Ｓ４、還流ダイオードＤ１～Ｄ４、コンデンサ１１～１４、及び平滑コンデンサ１５を有している。スイッチング素子Ｓ１～Ｓ４はＭＯＳＦＥＴである。なお、スイッチング素子Ｓ１～Ｓ４はＩＧＢＴ等のトランジスタでもよい。スイッチング素子Ｓ１～Ｓ４はフルブリッジ回路になるよう接続されている。スイッチング素子Ｓ１とスイッチング素子Ｓ２が直列に接続され、スイッチング素子Ｓ３とスイッチング素子Ｓ４が直列に接続されている。スイッチング素子Ｓ１とスイッチング素子Ｓ２との接続点が変圧器２０の１次側コイル２１の一端に接続され、スイッチング素子Ｓ３とスイッチング素子Ｓ４との接続点が変圧器２０の１次側コイル２１の他端に接続されている。スイッチング素子Ｓ１～Ｓ４には、還流ダイオードＤ１～Ｄ４及びコンデンサ１１～１４がそれぞれ接続されている。還流ダイオードＤ１～Ｄｄの導通方向が、スイッチング素子Ｓ１～Ｓ４の電流の導通方向（順方向）と逆向きになるように、還流ダイオードＤ１～Ｄ４はスイッチング素子Ｓ１～Ｓ４に対して並列に接続されている。なお、還流ダイオードＤ１～Ｄ４はスイッチング素子Ｓ１～Ｓ４の寄生ダイオードでもよく、コンデンサ１１～１４はスイッチング素子Ｓ１～Ｓ４の寄生容量としてもよい。インバータ回路１０の入力端子間には、平滑コンデンサ１５が接続されている。 The inverter circuit 10 includes switching elements S1 to S4, freewheeling diodes D1 to D4, capacitors 11 to 14, and a smoothing capacitor 15. The switching elements S1 to S4 are MOSFETs. Note that the switching elements S1 to S4 may be transistors such as IGBTs. The switching elements S1 to S4 are connected to form a full bridge circuit. Switching element S1 and switching element S2 are connected in series, and switching element S3 and switching element S4 are connected in series. The connection point between the switching element S1 and the switching element S2 is connected to one end of the primary side coil 21 of the transformer 20, and the connection point between the switching element S3 and the switching element S4 is the other side of the primary side coil 21 of the transformer 20. Connected to the end. Free-wheeling diodes D1-D4 and capacitors 11-14 are connected to the switching elements S1-S4, respectively. The free-wheeling diodes D1 to D4 are connected in parallel to the switching elements S1 to S4 so that the conducting direction of the free-wheeling diodes D1 to Dd is opposite to the current conducting direction (forward direction) of the switching elements S1 to S4. ing. Note that the freewheeling diodes D1 to D4 may be parasitic diodes of the switching elements S1 to S4, and the capacitors 11 to 14 may be parasitic capacitances of the switching elements S1 to S4. A smoothing capacitor 15 is connected between the input terminals of the inverter circuit 10.
　変圧器２０は、１次側コイル２１及び２次側コイル２２а、２２ｂを有している。１次側コイル２１は、インバータ回路１０の出力に接続されている。変圧器２０の２次側はセンタータップ型になっており、２次側コイル２２аと２次側コイル２２ｂの接続点には配線が接続されている。１次側コイル２１と２次側コイル２２а、２２ｂとの間は絶縁されている。変圧器２０は、１次側コイル２１と２次側コイル２２а、２２ｂとの巻線比（Ｎｐ／Ｎｓ）で電圧を昇圧又は降圧する。 The transformer 20 has a primary side coil 21 and secondary side coils 22a, 22b. The primary coil 21 is connected to the output of the inverter circuit 10. The secondary side of the transformer 20 is a center tap type, and wiring is connected to a connection point between the secondary side coil 22a and the secondary side coil 22b. The primary side coil 21 and the secondary side coils 22a and 22b are insulated. The transformer 20 boosts or lowers the voltage according to the winding ratio (Np / Ns) between the primary side coil 21 and the secondary side coils 22a, 22b.
　整流器３０は、ダイオードＤ３１及びダイオードＤ３２を有している。ダイオードＤ３１のアノード端子は２次側コイル２２аに接続されており、ダイオードＤ３１のカソード端子はフィルタインダクタ４１に接続されている。ダイオードＤ３２のアノード端子は２次側コイル２２ｂに接続されており、ダイオードＤ３２のカソード端子は、ダイオードＤ３１のカソード端子とフィルタインダクタ４１とを接続する接続点に接続されている。 The rectifier 30 has a diode D31 and a diode D32. The anode terminal of the diode D31 is connected to the secondary coil 22a, and the cathode terminal of the diode D31 is connected to the filter inductor 41. The anode terminal of the diode D32 is connected to the secondary coil 22b, and the cathode terminal of the diode D32 is connected to a connection point connecting the cathode terminal of the diode D31 and the filter inductor 41.
　フィルタ回路４０は、ＬＣフィルタであり、フィルタインダクタ４１及びフィルタコンデンサ４２を有している。フィルタインダクタ４１は正側の電源ラインに接続されている。フィルタコンデンサ４２は、フィルタ回路４０の出力側に接続され、正側の電源ラインと負側の電源ラインとの間に接続されている。負側の電源ラインは、２次側コイル２２аと２次側コイル２２ｂとの接続点に接続されている。なお、整流器３０及びフィルタ回路４０が、２次側の整流回路に相当する。 The filter circuit 40 is an LC filter and includes a filter inductor 41 and a filter capacitor 42. The filter inductor 41 is connected to the positive power line. The filter capacitor 42 is connected to the output side of the filter circuit 40, and is connected between the positive power line and the negative power line. The negative power line is connected to a connection point between the secondary coil 22a and the secondary coil 22b. The rectifier 30 and the filter circuit 40 correspond to a secondary side rectifier circuit.
　スナバ回路５０は、コンデンサ５１と可変抵抗５２を備えている。コンデンサ５１と可変抵抗５２は直列に接続されており、コンデンサ５１と可変抵抗５２との直列回路がフィルタインダクタ４１に対して並列に接続されている。 The snubber circuit 50 includes a capacitor 51 and a variable resistor 52. The capacitor 51 and the variable resistor 52 are connected in series, and a series circuit of the capacitor 51 and the variable resistor 52 is connected in parallel to the filter inductor 41.
　次に、本実施形態に電力変換装置の回路動作を説明する。 Next, the circuit operation of the power conversion apparatus will be described in this embodiment.
　コントローラ１００がスイッチング素子Ｓ１～Ｓ４のオン、オフを制御することで、２つのハーフブリッジは方形波電圧を出力する。コントローラ１００は、方形波電圧のデューティ比が５０％になるように、スイッチング素子Ｓ１～Ｓ４を制御する。２つの方形波電圧の位相がシフトすることで、交流電流が変圧器２０の１次側コイル２１に流れる。交流電圧が変圧器２０に印加され、変圧器２０の２次側に電力が伝わる。 The controller 100 controls on / off of the switching elements S1 to S4, so that the two half bridges output square wave voltages. The controller 100 controls the switching elements S1 to S4 so that the duty ratio of the square wave voltage is 50%. The alternating current flows through the primary side coil 21 of the transformer 20 by shifting the phase of the two square wave voltages. An AC voltage is applied to the transformer 20, and power is transmitted to the secondary side of the transformer 20.
　本実施形態では、スイッチング素子Ｓ１～Ｓ４のスイッチング動作がソフトスイッチングとなるために、部分共振が、電力変換装置の１次側の回路で発生するような回路構成を備えている。部分共振は、スイッチング素子Ｓ１～Ｓ４のドレイン－ソース間の容量と、変圧器の漏れインダクタンス（Ｌｒｅｃ）とのＬＣ回路で発生させている。部分共振がスイッチング素子Ｓ１～Ｓ４のデッドタイム期間中に発生することで、スイッチング素子Ｓ１～Ｓ４はセロベクトルスイッチング（ＺＶＳ：Zero Voltage Switching）でターンオンするために、スイッチング素子Ｓ１～Ｓ４のスイッチング動作はソフトスイッチングとなる。 In the present embodiment, since the switching operation of the switching elements S1 to S4 is soft switching, a circuit configuration in which partial resonance occurs in a circuit on the primary side of the power converter is provided. The partial resonance is generated in the LC circuit including the drain-source capacitance of the switching elements S1 to S4 and the leakage inductance (L rec ) of the transformer. Since the partial resonance occurs during the dead time period of the switching elements S1 to S4, the switching elements S1 to S4 are turned on by zero voltage switching (ZVS), so that the switching operation of the switching elements S1 to S4 is Soft switching.
　またスイッチング素子Ｓ１～Ｓ４のターンオフ時には、スイッチング素子Ｓ１～Ｓ４のドレイン－ソース間容量（以下ＤＳ容量とも称す）が充電されるため、ドレイン－ソース間の電圧上昇が遅れる。これにより、ターンオフ時における電圧と電流との重なり期間を短くし、ソフトスイッチングを実現できる。 Also, when the switching elements S1 to S4 are turned off, the drain-source capacitance (hereinafter also referred to as DS capacitance) of the switching elements S1 to S4 is charged, so that the voltage rise between the drain and source is delayed. Thereby, the overlap period of the voltage and current at the time of turn-off can be shortened, and soft switching can be realized.
　ターンオン時にソフトスイッチングを実現するためには、スイッチング素子Ｓ１～Ｓ４のＤＳ容量の放電がデッドタイム期間中に終なければならない。デッド期間中に、ＤＳ容量の放電が終わる場合には、スイッチング素子Ｓ１～Ｓ４をターンオンさせたとしても、ＤＳ容量の放電電流がターンオンするスイッチング素子Ｓ１～Ｓ４に流れることは無いため、ターンオフ時における電圧と電流との重なり期間は短くなり、ソフトスイッチングを実現できる。一方、デッドタイム期間中に、ＤＳ容量の放電が終わっていない状態で、スイッチング素子Ｓ１～Ｓ４のターンオンした場合には、ＤＳ容量の放電電流が、ターンオンしたスイッチング素子に流れてしまうため、ハードスイッチングになってしまい、スイッチング損失が大きくなる。 In order to realize soft switching at turn-on, the discharge of the DS capacities of the switching elements S1 to S4 must end during the dead time period. When the discharge of the DS capacitor ends during the dead period, even if the switching elements S1 to S4 are turned on, the discharge current of the DS capacitor does not flow to the switching elements S1 to S4 that are turned on. The overlapping period of voltage and current is shortened, and soft switching can be realized. On the other hand, when the switching elements S1 to S4 are turned on during the dead time period when the discharge of the DS capacitor is not completed, the DS capacitor discharge current flows to the turned-on switching element. As a result, the switching loss increases.
　デットタイム期間中に、ＤＳ容量の放電を行うためには、放電を促す程度の電流が変圧器２０の１次側に流れなければならない。つまり、デットタイム期間中、変圧器２０の１次側電流が低い場合には、ＤＳ容量の放電電流が小さくなるため、ＤＳ容量の放電がデッドタイム期間中に終わらないことになる。また、デッドタイム期間中に、変圧器２０の１次側電流の向きが変化した場合には、順方向電流が、オフ状態のスイッチング素子Ｓ１～Ｓ４に接続された還流ダイオードＤ１～Ｄ４に流れ、ターンオンしようとしているスイッチング素子Ｓ１～Ｓ４のＤＳ容量が充電される。そのため、スイッチング素子Ｓ１～Ｓ４のターンオン動作はハードスイッングとなり、インバータ回路１０の出力電圧が不安定になる。 In order to discharge the DS capacity during the dead time period, a current that urges the discharge must flow to the primary side of the transformer 20. That is, when the primary side current of the transformer 20 is low during the dead time period, the DS capacity discharge current becomes small, and thus the DS capacity discharge does not end during the dead time period. Further, when the direction of the primary current of the transformer 20 changes during the dead time period, the forward current flows to the free wheel diodes D1 to D4 connected to the switching elements S1 to S4 in the off state, The DS capacities of the switching elements S1 to S4 to be turned on are charged. Therefore, the turn-on operation of the switching elements S1 to S4 becomes hard switching, and the output voltage of the inverter circuit 10 becomes unstable.
　次に、変圧器２０に流れる電流と、電力変換装置の出力電流との関係を説明する。図３は、１次側巻線２１の入力電圧（ＶＬ、ＶＲ）の特性、変圧器２０の１次側電流（ＩＴＲ）の特性、整流器３０のダイオードＤ３１、Ｄ３２に流れる電流（ＩＤ１、ＩＤ２）の特性、フィルタインダクタ４１の電流（ＩＬ）特性、及びフィルタインダクタ４１の電圧（Ｖｒｅｃ）特性を示すグラフである。入力電圧（ＶＬ）は、インバータ回路１０の２つのハーフブリッジのうち一方の出力電圧に相当し、入力電圧（ＶＲ）は、他方の出力電圧に相当する。 Next, the relationship between the current flowing through the transformer 20 and the output current of the power conversion device will be described. FIG. 3 shows the characteristics of the input voltage (V L , V R ) of the primary side winding 21, the characteristics of the primary side current (I TR ) of the transformer 20, and the currents flowing through the diodes D 31 and D 32 of the rectifier 30 (I 4 is a graph showing characteristics of D1 and I D2 ), current (I L ) characteristics of the filter inductor 41, and voltage (V rec ) characteristics of the filter inductor 41. The input voltage (V L ) corresponds to one output voltage of the two half bridges of the inverter circuit 10, and the input voltage (V R ) corresponds to the other output voltage.
　図３に示すように、時刻ｔ１で、インバータ回路１０のハーフブリッジの出力電圧（ＶＬ）が立ち上がると、変圧器２０の１次側電流（ＩＴＲ）は、正の傾きで増加する。このとき、１次側電流（ＩＴＲ）は、入力電圧（Ｖｉｎ）と漏れインダクタンス（Ｌｓ）との関係により、下記式（１）で表される。 As shown in FIG. 3, when the output voltage (V L ) of the half bridge of the inverter circuit 10 rises at time t 1 , the primary current (I TR ) of the transformer 20 increases with a positive slope. At this time, the primary side current (I TR ) is expressed by the following formula (1) according to the relationship between the input voltage (V in ) and the leakage inductance (L s ).
Figure JPOXMLDOC01-appb-M000001
Figure JPOXMLDOC01-appb-M000001
　１次側電流（ＩＴＲ）が、式（１）の傾きで変化している間に、整流器３０のダイオードＤ３１に流れる電流（ＩＤ１）は増加しつつ、ダイオードＤ３２に流れる電流（ＩＤ２）減少する。すなわち、整流器３０の２次側の電流は還流している。 While the primary current (I TR ) changes with the slope of the equation (1), the current (I D1 ) that flows through the diode D31 of the rectifier 30 increases and the current (I D2 ) that flows through the diode D32 increases. Decrease. That is, the current on the secondary side of the rectifier 30 is circulating.
　そして、時刻ｔ２で、変圧器の２次側の電流（ＩＤ１）が、変圧器の１次側電流（ＩＴＲ）に巻線比（Ｎｐ／Ｎｓ）を乗じた電流値が一致する。時刻ｔ２で、１次側電流（ＩＴＲ）の傾きは、時刻ｔ１からｔ２までの間の傾き（式（１）で示される傾き）よりも緩やかになり、下記式（２）で表される。 Then, at time t 2, the transformer secondary side of the current (I D1) is a current value obtained by multiplying turns ratio (Np / Ns) to the transformer primary current (I TR) match. At time t 2 , the slope of the primary side current (I TR ) becomes gentler than the slope between time t 1 and t 2 (slope shown by equation (1)). expressed.
Figure JPOXMLDOC01-appb-M000002
Figure JPOXMLDOC01-appb-M000002
　時刻ｔ２における１次電流（ＩＴＲ）の変化に伴い、フィルタインダクタ４１に流れる電流（ＩＬ）が急峻に変化するため、サージ電圧（Ｖｒｅｃ）が整流器３０の出力で発生し易くなる。図３において、フィルタインダクタ４１の電流（ＩＬ）が急峻に変化するポイントは、点線で囲う円で表され、サージ電圧は点線の部分で発生し易い。 As the primary current (I TR ) changes at the time t 2 , the current (I L ) flowing through the filter inductor 41 changes abruptly, so that a surge voltage (V rec ) is likely to be generated at the output of the rectifier 30. In FIG. 3, the point at which the current (I L ) of the filter inductor 41 changes sharply is represented by a circle surrounded by a dotted line, and a surge voltage is likely to occur at the dotted line portion.
　１次電流（ＩＴＲ）は、時刻ｔ２以降、一定の傾きで緩やかに増加し、時刻ｔ３以降、一定の傾きで緩やかに減少する。時刻ｔ３は、インバータ回路１０のハーフブリッジの出力電圧（ＶＲ）が立ち上がるタイミングである。そして、インバータ回路１０のハーフブリッジの出力電圧（ＶＬ）が立ち下がるタイミング（時刻ｔ４）で、１次電流（ＩＴＲ）は大きく減少する。 The primary current (I TR ) gradually increases with a constant slope after time t 2 and gradually decreases with a constant slope after time t 3 . Time t 3 is timing when the output voltage (V R ) of the half bridge of the inverter circuit 10 rises. The primary current (I TR ) greatly decreases at the timing (time t 4 ) when the output voltage (V L ) of the half bridge of the inverter circuit 10 falls.
　フィルタインダクタ４１の出力電流（ＩＬ）は、時刻ｔ２以降、一定の傾きで緩やかに増加し、時刻ｔ３以降、一定の傾きで緩やかに減少する。そして、出力電流（ＩＬ）は、時刻ｔ５で再び緩やかに増加する。変圧器の２次側の電流（ＩＤ２）が、変圧器の１次側電流（ＩＴＲ）に巻線比（Ｎｐ／Ｎｓ）を乗じた電流値が一致するタイミングが時刻ｔ５である。 The output current (I L ) of the filter inductor 41 gradually increases with a constant slope after time t 2 and gradually decreases with a constant slope after time t 3 . The output current (I L ) gradually increases again at time t 5 . Transformer secondary side of the current (I D2) are timing value of current multiplied by the turns ratio of the (Np / Ns) to the transformer primary current (I TR) coincide is time t 5.
　すなわち、時刻ｔ２から時刻ｔ４までの間に、電力が電力変換装置の入力から出力に伝わっており、１次側電流（ＩＴＲ）と出力電流（ＩＬ）は緩やかに変化する。そして、時刻ｔ２から時刻ｔ４までの間では、出力電流（ＩＬ）の絶対値は、１次側電流（ＩＴＲ）の絶対値に巻線比（Ｎｐ／Ｎｓ）を乗じた値となる。また、電力変換装置の出力電流（Ｉｏｕｔ）は、フィルタインダクタ４１の電流（ＩＬ）を平均化した値なるため、出力電流（Ｉｏｕｔ）の平均は、電流（ＩＬ）の平均と一致する。 That is, between time t 2 and time t 4 , power is transmitted from the input to the output of the power converter, and the primary current (I TR ) and the output current (I L ) change gently. From time t 2 to time t 4 , the absolute value of the output current (I L ) is obtained by multiplying the absolute value of the primary current (I TR ) by the winding ratio (Np / Ns). Become. In addition, since the output current (I out ) of the power converter is a value obtained by averaging the current (I L ) of the filter inductor 41, the average of the output current (I out ) matches the average of the current (I L ). To do.
　次に、電力変換装置の出力電流（Ｉｏｕｔ）が図３に示した時の出力電流（Ｉｏｕｔ）よりも低い時の特性について、図４を用いて説明する。図４は、図３に示す電圧電流特性と同様に、図４の上から順に、入力電圧特性（ＶＬ、ＶＲ）、１次側電流特性（ＩＴＲ）、ダイオードＤ３１、Ｄ３２の電流特性（ＩＤ１、ＩＤ２）、フィルタインダクタ４１の電流特性（ＩＬ）、及びフィルタインダクタ４１の電圧特性（Ｖｒｅｃ）を示す。図４は、電力変換装置の出力電流が図３に示した時の出力電流（Ｉｏｕｔ）よりも低い時の特性を示す。 Then, the output current of the power converter (I out) is the characteristics when the output current (I out) is lower than when shown in FIG. 3 will be described with reference to FIG. 4 shows the input voltage characteristics (V L , V R ), the primary side current characteristics (I TR ), and the current characteristics of the diodes D31 and D32 in order from the top of FIG. 4 in the same manner as the voltage / current characteristics shown in FIG. (I D1 , I D2 ), a current characteristic (I L ) of the filter inductor 41, and a voltage characteristic (V rec ) of the filter inductor 41 are shown. FIG. 4 shows the characteristics when the output current of the power converter is lower than the output current (I out ) at the time shown in FIG.
　インバータ回路１０のハーフブリッジの出力電圧（ＶＬ、ＶＲ）の立ち上がり及び立下りのタイミングは、図３と同様である。出力電流（Ｉｏｕｔ）が低い場合には、フィルタインダクタ４１の電流（ＩＬ）は低くなる、１次側電流（ＩＴＲ）は、フィルタインダクタ４１の電流（ＩＬ）と線形の関係にあるため、１次側電流（ＩＴＲ）も低くなる。 The rising and falling timings of the output voltages (V L , V R ) of the half bridge of the inverter circuit 10 are the same as those in FIG. When the output current (I out ) is low, the current (I L ) of the filter inductor 41 is low, and the primary current (I TR ) has a linear relationship with the current (I L ) of the filter inductor 41. Therefore, the primary side current (I TR ) is also reduced.
　時刻ｔ１から時刻ｔ２までの間は、デットタイム期間（ｔｄ）となる。すなわち、出力電流（Ｉｏｕｔ）が低い場合には、デットタイム期間（ｔｄ）において、１次側電流（ＩＴＲ）が低くなる。そして、デットタイム期間（ｔｄ）に、１次側電流（ＩＴＲ）が、スイッチング素子Ｓ１～Ｓ４のＤＳ容量を放電できない程度まで低くなる場合には、スイッチング素子Ｓ１～Ｓ４のスイッチング動作がハードスイッチングになってしまう。 A dead time period (t d ) is from time t 1 to time t 2 . That is, when the output current (I out ) is low, the primary current (I TR ) is low in the dead time period (t d ). In the dead time period (t d ), when the primary side current (I TR ) becomes low enough that the DS capacity of the switching elements S1 to S4 cannot be discharged, the switching operation of the switching elements S1 to S4 is hard. It becomes switching.
　また、デットタイム期間（ｔｄ）の終点のタイミング（ｔ２、ｔ４等）では、サージ電圧が発生し易い。サージ電圧が、電力変換装置の２次側の回路で発生した場合には、整流器３０に含まれるダイオードＤ３１、Ｄ３２の接合容量の充放電によって、振動電流が発生する。２次側の振動電流は、変圧器２０を介して、変圧器２０の１次側の漏れインインダクタ（Ｌｓ）により共振する。すなわち、２次側の振動電流により１次側の電流が振動する。 Further, a surge voltage is likely to occur at the end timing (t 2 , t 4, etc.) of the dead time period (t d ). When a surge voltage is generated in the secondary circuit of the power converter, an oscillating current is generated by charging and discharging the junction capacitances of the diodes D31 and D32 included in the rectifier 30. The oscillating current on the secondary side resonates via the transformer 20 due to the leakage in inductor (L s ) on the primary side of the transformer 20. That is, the primary-side current is vibrated by the secondary-side oscillating current.
　デッドタイム期間中において、１次側の振動電流による影響を、図５を用いて説明する。図５は、１次側巻線２１の入力電圧（ＶＬ）の特性、スイッチング素子Ｓ１、Ｓ２のスイッチング動作特性（スイッチング素子Ｓ１、Ｓ２の駆動信号のと構成）、及び変圧器２０の１次側電流（ＩＴＲ＿а、ＩＴＲ＿ｂ）の特性を示す。スイッチング動作特性のハイレベルはオン状態を示し、ローレベルはオフ状態を示す。１次側電流（ＩＴＲ＿а）は、スナバ回路５０による振動抑制レベルが高い時の電流を示し、１次側電流（ＩＴＲ＿ｂ）は、スナバ回路５０の振動抑制レベルが低い時の電流を示す。 The influence of the oscillating current on the primary side during the dead time period will be described with reference to FIG. FIG. 5 shows the characteristics of the input voltage (V L ) of the primary winding 21, the switching operation characteristics of the switching elements S 1 and S 2 (and the configuration of the drive signals of the switching elements S 1 and S 2), and the primary of the transformer 20. The characteristics of the side currents (I TR_а , I TR_b ) are shown. A high level of the switching operation characteristic indicates an on state, and a low level indicates an off state. The primary side current (I TR_а ) indicates a current when the vibration suppression level by the snubber circuit 50 is high, and the primary side current (I TR_b ) indicates a current when the vibration suppression level of the snubber circuit 50 is low.
　時刻ｔ１で、スイッチング素子Ｓ２がターンオフした時に、変圧器２０の１次側電流（ＩＴＲ＿а、ＩＴＲ＿ｂ）は負方向に流れている。変圧器２０の１次側に負電流が流れている場合には、ＤＳ容量の放電が行われる。スナバ回路５０の振動抑制レベルが高い場合には、２次側の電流振動が抑制されるため、１次側の電流は振動せず、時刻ｔ１から時刻ｔ２までの間で、１次側電流（ＩＴＲ＿а）の電流の向きは負方向のままで変わらない。デッドタイム期間中、変圧器２０の１次側には、負方向の電流が継続して流れるため、デットタイム期間中にＤＳ容量の放電が行われる。そして、デットタイム期間の終了時に、スイッチング素子Ｓ１のターンオン動作はソフトスイッチングになる。 At time t 1, when the switching element S2 is turned off, the primary current of the transformer 20 (I TR_а, I TR_b) is flowing in the negative direction. When a negative current flows through the primary side of the transformer 20, the DS capacity is discharged. If the vibration suppression level of the snubber circuit 50 is high, since the current vibration of the secondary side is suppressed, the primary current does not vibrate, between the time t 1 to time t 2, the primary side The direction of the current ( ITR_а ) remains negative and does not change. During the dead time period, a negative current continues to flow on the primary side of the transformer 20, so that the DS capacity is discharged during the dead time period. At the end of the dead time period, the turn-on operation of the switching element S1 is soft switching.
　一方、スナバ回路５０の振動抑制レベルが低い場合には、２次側の電流振動が抑制されないため、２次側の電流振動が１次側でも発生する。１次側電流（ＩＴＲ＿а）が低い状態で、１次側の電流が振動すると、時刻ｔ１から時刻ｔ２までの間に、１次側電流（ＩＴＲ＿ｂ）の電流の向きは、負方向から正方向に変化する。上側のスイッチング素子Ｓ１がターンオンになる前に、１次側電流（ＩＴＲ＿ｂ）が正になると、順方向電流が、下側のスイッチング素子Ｓ２の還流ダイオードＤ２に流れる。上側スイッチング素子Ｓ１のターンオンになる時（時刻ｔ２）に、本来であれば、入力電圧（Ｖｉｎ）に相当する電圧が、変圧器２０の１次側巻線２１に入力される。しかしながら、還流ダイオードＤ２が導通しているため、１次側巻線２１に印加される電圧は基準電圧（入力電圧の負側の電位）となり、インバータ回路１０の出力電圧は不安定な状態となる。さらに、デッドタイム期間中に、１次側電流（ＩＴＲ＿ｂ）の向きが負から正に変わることで、上側のスイッチング素子Ｓ１のＤＳ容量が充電される。そのため、スイッチング素子Ｓ１のスイッチング動作がハードスイッチングになり、スイッチング損失が大きくなる。 On the other hand, when the vibration suppression level of the snubber circuit 50 is low, secondary-side current vibration is not suppressed, and secondary-side current vibration also occurs on the primary side. When the primary side current (I TR — ) is low and the primary side current oscillates, the direction of the primary side current (I TR — b ) is negative in the direction from time t 1 to time t 2. Changes in the positive direction. If the primary current ( ITR_b ) becomes positive before the upper switching element S1 is turned on, a forward current flows through the free wheel diode D2 of the lower switching element S2. When the upper switching element S1 is turned on (time t 2 ), a voltage corresponding to the input voltage (V in ) is input to the primary winding 21 of the transformer 20. However, since the freewheeling diode D2 is conductive, the voltage applied to the primary winding 21 is the reference voltage (the negative potential of the input voltage), and the output voltage of the inverter circuit 10 is in an unstable state. . Furthermore, during the dead time period, the direction of the primary side current ( ITR_b ) changes from negative to positive, so that the DS capacity of the upper switching element S1 is charged. Therefore, the switching operation of the switching element S1 becomes hard switching, and the switching loss increases.
　すなわち、デッドタイム期間中に振動電流を抑制するためには、スナバ回路５０の振動抑制レベルは高い方がよい。しかしながら、スナバ回路の５０の振動レベルを高くすると、スナバ回路の損失が増大する。特に、出力電流（Ｉｏｕｔ）が高い場合には、デットタイム期間の１次側電流（ＩＴＲ）は、スイッチング素子Ｓ１～Ｓ４のＤＳ容量を放電するために十分に高く、１次側電流（ＩＴＲ）の向きが、２次側の振動電流の発生により影響を受けることも少ない。すなわち、スナバ回路５０のよる振動抑制レベルの特性（以下、振動抑制特性とも称す）は、出力電流（Ｉｏｕｔ）が低くなると、振動抑制レベルがより高くなればよい。これにより、出力電流（Ｉｏｕｔ）が高いときには、振動抑制レベルが小さくなり、スナバ回路５０の損失を抑制できる。また、出力電流（Ｉｏｕｔ）が低いときには、振動抑制レベルが高くなり、２次側振動電流を抑制しつつ、スイッチング素子Ｓ１～Ｓ４のソフトスイッチング動作を実現できる。 That is, in order to suppress the oscillating current during the dead time period, the vibration suppression level of the snubber circuit 50 should be high. However, increasing the vibration level of the snubber circuit 50 increases the loss of the snubber circuit. In particular, when the output current (I out ) is high, the primary side current (I TR ) during the dead time period is sufficiently high to discharge the DS capacities of the switching elements S1 to S4. The direction of I TR ) is less affected by the generation of secondary side oscillating current. In other words, the vibration suppression level characteristic (hereinafter also referred to as vibration suppression characteristic) by the snubber circuit 50 only needs to be higher when the output current (I out ) is lower. As a result, when the output current (I out ) is high, the vibration suppression level becomes small, and the loss of the snubber circuit 50 can be suppressed. When the output current (I out ) is low, the vibration suppression level is high, and the soft switching operation of the switching elements S1 to S4 can be realized while suppressing the secondary-side vibration current.
　本実施形態では、スナバ回路５０の特性が上記の振動抑制特性となるために、スナバ回路５０が以下に説明する構造で構成されている。図６は、フィルタインダクタ４１と可変抵抗５２を一体化した構成部品の正面図である。 In this embodiment, since the characteristic of the snubber circuit 50 is the above-described vibration suppression characteristic, the snubber circuit 50 has a structure described below. FIG. 6 is a front view of a component in which the filter inductor 41 and the variable resistor 52 are integrated.
　フィルタインダクタ４１は、磁性体コア４１１とインダクタコイル４１２を有している。磁性体コア４１１は、インダクタコイル４１２と可変抵抗５２を覆う磁性体である。インダクタコイル４１２は、一対のコイルである。インダクタコイル４１２に流れる電流は、フィルタインダクタ４１の電流であり、電力変換装置の出力電流（Ｉｏｕｔ）に相当する。 The filter inductor 41 has a magnetic core 411 and an inductor coil 412. The magnetic core 411 is a magnetic body that covers the inductor coil 412 and the variable resistor 52. The inductor coil 412 is a pair of coils. The current flowing through the inductor coil 412 is the current of the filter inductor 41 and corresponds to the output current (I out ) of the power converter.
　可変抵抗５２は、ＭＲ素子又はＧＭＲ素子等の磁気抵抗素子である。可変抵抗５２は磁性体コア４１１のギャップに設けられている。整流回路３１の出力電流がインダクタコイル４１２に流れると、インダクタコイル４１２は磁界を発生し、磁性体コア４１１において磁気回路を形成する。可変抵抗５２は、磁気回路内に配置されている。インダクタコイル４１２で発生する磁界は、フィルタインダクタ４１の電流に比例する。また、可変抵抗５２は、磁界に対して正の特性をもっており、磁界強度が高いほど、可変抵抗５２の抵抗値は大きくなる。スナバ回路５０は、フィルタインダクタ４１と並列に接続されており、フィルタインダクタ４１の電流が高くなるほど、スナバ回路５０の抵抗値が高くなる。スナバ回路５０の抵抗値が高いほど、スナバ回路５０による振動電流の抑制レベルは低くなる。 The variable resistor 52 is a magnetoresistive element such as an MR element or a GMR element. The variable resistor 52 is provided in the gap of the magnetic core 411. When the output current of the rectifier circuit 31 flows through the inductor coil 412, the inductor coil 412 generates a magnetic field and forms a magnetic circuit in the magnetic core 411. The variable resistor 52 is disposed in the magnetic circuit. The magnetic field generated by the inductor coil 412 is proportional to the current of the filter inductor 41. The variable resistor 52 has a positive characteristic with respect to the magnetic field, and the resistance value of the variable resistor 52 increases as the magnetic field strength increases. The snubber circuit 50 is connected in parallel with the filter inductor 41, and the resistance value of the snubber circuit 50 increases as the current of the filter inductor 41 increases. The higher the resistance value of the snubber circuit 50, the lower the level of vibration current suppression by the snubber circuit 50.
　フィルタインダクタ４１の電流が小さくなるほど、スナバ回路５０の抵抗値は低くなるため、スナバ回路５０による抑制レベルは高くなる。一方、フィルタインダクタ４１の電流が高くなるほど、スナバ回路５０の抵抗値は高くなり、スナバ回路５０による振動電流の抑制レベルは低くなる。すなわち、フィルタインダクタで発生する磁界強度が出力電流と相関性をもつパラメータとなり、スナバ回路５０による振動電流の抑制レベルは、パラメータに応じて変化する。なお、スナバ回路５０による振動抑制レベルが低下することで、サージ電圧が高くなるが、サージ電圧のピーク値は基準値以下に抑制されている。基準値は、電力変換装置に含まれる回路素子の定格電圧等により決まる電圧の上限値であり、予め設定される。 Since the resistance value of the snubber circuit 50 becomes lower as the current of the filter inductor 41 becomes smaller, the suppression level by the snubber circuit 50 becomes higher. On the other hand, the higher the current of the filter inductor 41, the higher the resistance value of the snubber circuit 50 and the lower the level of vibration current suppression by the snubber circuit 50. That is, the magnetic field intensity generated in the filter inductor becomes a parameter having a correlation with the output current, and the suppression level of the oscillating current by the snubber circuit 50 changes according to the parameter. In addition, although the surge voltage becomes high because the vibration suppression level by the snubber circuit 50 is lowered, the peak value of the surge voltage is suppressed below the reference value. The reference value is an upper limit value of a voltage determined by a rated voltage of a circuit element included in the power converter, and is set in advance.
　１次側の電流が低い場合には、電力変換装置の出力電流（Ｉｏｕｔ）及びフィルタインダクタ４１の電流が低くなり、スナバ回路５０による振動の抑制レベルが高くなる。そのため、２次側の振動電流が抑制されるため、デットタイム期間中に１次側の電流の向きは変わらず、負方向で維持される。これにより、電力変換装置の出力電流（Ｉｏｕｔ）が低い場合に、スイッチング素子Ｓ１～Ｓ４のソフトスイッチングを実現できる。電力変換装置の出力電流（Ｉｏｕｔ）の大きさに対して、ソフトスイッチングを可能とする電流範囲が広がる。 When the primary side current is low, the output current (I out ) of the power converter and the current of the filter inductor 41 are low, and the level of suppression of vibration by the snubber circuit 50 is high. Therefore, since the secondary side oscillation current is suppressed, the direction of the primary side current does not change during the dead time period and is maintained in the negative direction. Thereby, when the output current (I out ) of the power converter is low, soft switching of the switching elements S1 to S4 can be realized. The current range enabling soft switching is widened with respect to the magnitude of the output current (I out ) of the power converter.
　また、１次側の電流が高い場合には、電力変換装置の出力電流（Ｉｏｕｔ）及びフィルタインダクタ４１の電流が高くなり、スナバ回路５０の損失が低減される。 Further, when the primary side current is high, the output current (I out ) of the power converter and the current of the filter inductor 41 are increased, and the loss of the snubber circuit 50 is reduced.
　上記のように、本実施形態に係る電力変換装置は、インバータ回路１０、変圧器２０、整流器３０、及びスナバ回路５０を備えている。スナバ回路５０は、電力変換装置の出力電流が低くなると、スナバ回路５０による振動電流の抑制レベルがより高くなる特性を有している。これにより、スイッチング素子のスイッチング損失を抑制し、効率を高めることができる。 As described above, the power conversion device according to this embodiment includes the inverter circuit 10, the transformer 20, the rectifier 30, and the snubber circuit 50. The snubber circuit 50 has a characteristic that when the output current of the power conversion device decreases, the level of suppression of vibration current by the snubber circuit 50 increases. Thereby, the switching loss of a switching element can be suppressed and efficiency can be improved.
　また本実施形態において、スイッチング素子Ｓ１～Ｓ４は、ＬＣ共振を利用したソフトスイッチングで動作する。これにより、スイッチング損失が抑制され、効率を向上できる。 In the present embodiment, the switching elements S1 to S4 operate by soft switching using LC resonance. Thereby, switching loss is suppressed and efficiency can be improved.
　また本実施形態において、スナバ回路５０による振動電流の抑制レベルは、電力変換装置の出力電流と相関性をもつパラメータに応じて変化する。これにより、振動電流の抑制レベルが受動的に変化するため、単純な構成で振動抑制特性を実現できる。 In this embodiment, the level of suppression of the oscillating current by the snubber circuit 50 changes according to a parameter having a correlation with the output current of the power converter. Thereby, since the suppression level of an oscillating current changes passively, a vibration suppression characteristic is realizable with a simple structure.
　また本実施形態において、可変抵抗５２は磁気抵抗素子で構成されており、磁気抵抗素子は、フィルタインダクタ４１で発生する磁気回路内に配置されている。これにより、スナバ回路５０の抵抗が受動的に変化するため、単純な構成で振動抑制特性を実現できる。 In the present embodiment, the variable resistor 52 is composed of a magnetoresistive element, and the magnetoresistive element is arranged in a magnetic circuit generated by the filter inductor 41. Thereby, since the resistance of the snubber circuit 50 changes passively, the vibration suppression characteristic can be realized with a simple configuration.
　また本実施形態において、フィルタインダクタ４１は、磁性体コア４１１のギャップに配置されている。これにより、単純な構成で振動抑制特性を実現できる。 In this embodiment, the filter inductor 41 is arranged in the gap of the magnetic core 411. Thereby, vibration suppression characteristics can be realized with a simple configuration.
　また本実施形態において、ダイオードＤ３１、Ｄ３２は、逆回復動作で動作しないデバイスにより構成されている。これにより、電力変換装置の出力電流が高い場合に、サージ電圧が抑制されることで、スナバ回路による振動電流の抑制レベルをより低くすることができる。その結果として、スナバ回路の損失を低減できる。 In this embodiment, the diodes D31 and D32 are configured by devices that do not operate in reverse recovery operation. Thereby, when the output current of the power converter is high, the surge voltage is suppressed, so that the level of vibration current suppression by the snubber circuit can be further reduced. As a result, the loss of the snubber circuit can be reduced.
　なお、本実施形態の変形例として、スナバ回路５０が振動抑制特性をもつために、スナバ回路５０に含まれる可変抵抗５２は、正の温度特性をもつ抵抗としてもよい。正の温度特性をもつ抵抗は、例えばＰＴＣ抵抗である。電流がスナバ回路５０に流れると、可変抵抗５２の温度は、自己発熱により上昇する。可変抵抗５２の温度が上昇すると可変抵抗５２の抵抗が高くなるため、スナバ回路５０による振動電流の抑制効果が低減し、スナバ回路５０の損失が抑制される。これにより、単純な構成で振動抑制特性を実現できる。 As a modification of the present embodiment, since the snubber circuit 50 has vibration suppression characteristics, the variable resistor 52 included in the snubber circuit 50 may be a resistance having positive temperature characteristics. The resistor having a positive temperature characteristic is, for example, a PTC resistor. When current flows through the snubber circuit 50, the temperature of the variable resistor 52 rises due to self-heating. When the temperature of the variable resistor 52 rises, the resistance of the variable resistor 52 increases, so that the effect of suppressing the oscillating current by the snubber circuit 50 is reduced and the loss of the snubber circuit 50 is suppressed. Thereby, vibration suppression characteristics can be realized with a simple configuration.
　また、可変抵抗５２を、正の温度特性をもつ抵抗とした場合に、可変抵抗５２は、変圧器２０又は整流器３０の近接に配置されてもよい。電力変換装置に電流が流れると、変圧器２０又は整流器３０に含まれる素子が熱を発生する。可変抵抗５２は、変圧器２０又は整流器３０の近接に配置されることで、可変抵抗５２は、熱源となる素子と熱交換可能な状態となる。これにより、単純な構成で振動抑制特性を実現できる。 Further, when the variable resistor 52 is a resistor having a positive temperature characteristic, the variable resistor 52 may be disposed in the vicinity of the transformer 20 or the rectifier 30. When a current flows through the power conversion device, elements included in the transformer 20 or the rectifier 30 generate heat. The variable resistor 52 is disposed in the vicinity of the transformer 20 or the rectifier 30, so that the variable resistor 52 can exchange heat with an element serving as a heat source. Thereby, vibration suppression characteristics can be realized with a simple configuration.
　また、本実施形態の変形例として、スナバ回路５０が振動抑制特性をもつために、スナバ回路５０に含まれるコンデンサ５１は、負の温度特性をもつコンデンサであってもよい。電流がスナバ回路５０に流れ、コンデンサ５１の温度が上昇すると、コンデンサ５１の静電容量が低下するため、スナバ回路５０による振動電流の抑制効果が低減し、スナバ回路５０の損失が抑制される。これにより、スナバ回路５０が振動抑制特性をもつように構成できる。 As a modification of the present embodiment, since the snubber circuit 50 has vibration suppression characteristics, the capacitor 51 included in the snubber circuit 50 may be a capacitor having negative temperature characteristics. When the current flows into the snubber circuit 50 and the temperature of the capacitor 51 rises, the capacitance of the capacitor 51 decreases. Therefore, the effect of suppressing the oscillating current by the snubber circuit 50 is reduced, and the loss of the snubber circuit 50 is suppressed. Thereby, the snubber circuit 50 can be configured to have vibration suppression characteristics.
　また、コンデンサ５１を、負の温度特性をもつコンデンサとした場合に、コンデンサ５１は、変圧器２０又は整流器３０の近接に配置されてもよい。電力変換装置に電流が流れると、変圧器２０又は整流器３０に含まれる素子が熱を発生する。コンデンサ５１は、変圧器２０又は整流器３０の近接に配置されることで、コンデンサ５１は、熱源となる素子と熱交換可能な状態となる。これにより、単純な構成で振動抑制特性を実現できる。 Further, when the capacitor 51 is a capacitor having a negative temperature characteristic, the capacitor 51 may be disposed in the vicinity of the transformer 20 or the rectifier 30. When a current flows through the power conversion device, elements included in the transformer 20 or the rectifier 30 generate heat. The capacitor 51 is disposed in the vicinity of the transformer 20 or the rectifier 30, so that the capacitor 51 can exchange heat with an element serving as a heat source. Thereby, vibration suppression characteristics can be realized with a simple configuration.
　なお、変形例に係るコンデンサ５１又は可変抵抗５２は、温度依存性をもつフィルタインダクタ４１、磁性体コア４１１、ダイオードＤ３１、Ｄ３２に隣接するように配置されてもよい。これにより、コンデンサ５１の静電容量又は可変抵抗５２の抵抗値は、温度に対して変化しやすくなる。 Note that the capacitor 51 or the variable resistor 52 according to the modification may be arranged adjacent to the temperature-dependent filter inductor 41, the magnetic core 411, and the diodes D31 and D32. Thereby, the electrostatic capacitance of the capacitor 51 or the resistance value of the variable resistor 52 is likely to change with respect to temperature.
　なお、スナバ回路５０は、図２に示すようにフィルタインダクタ４１に並列に接続する必要はなく、図７Ａ又は図７Ｂに示すようにフィルタインダクタ４１と出力電圧の基準電位との間に接続されてもよい。出力電圧の基準電位は、電力変換装置の出力電圧の負側の電位に相当する。 The snubber circuit 50 does not need to be connected in parallel to the filter inductor 41 as shown in FIG. 2, but is connected between the filter inductor 41 and the reference potential of the output voltage as shown in FIG. 7A or 7B. Also good. The reference potential of the output voltage corresponds to the negative potential of the output voltage of the power converter.
　図７Ａ及び図７Ｂは、変形例に係る電力変換装置の２次側の回路図である。整流器３０及びフィルタ回路４０の構成は、上記構成と同様である。図７Ａに示すように、スナバ回路５０は、コンデンサ５１、ダイオード５３、及び抵抗５４を有している。コンデンサ５１はダイオード５３のカソードに接続されており、コンデンサ５１とダイオード５３の直列回路は、フィルタ回路４０の一対の電源ラインの間に接続されている。抵抗５４の一端は、コンデンサ５１とダイオード５３とを接続する接続点に接続されており、抵抗５４の他端は、フィルタインダクタ４１とフィルタコンデンサ４２とを接続する接続点に接続されている。 7A and 7B are circuit diagrams of the secondary side of the power conversion device according to the modification. The configurations of the rectifier 30 and the filter circuit 40 are the same as those described above. As illustrated in FIG. 7A, the snubber circuit 50 includes a capacitor 51, a diode 53, and a resistor 54. The capacitor 51 is connected to the cathode of the diode 53, and the series circuit of the capacitor 51 and the diode 53 is connected between the pair of power supply lines of the filter circuit 40. One end of the resistor 54 is connected to a connection point connecting the capacitor 51 and the diode 53, and the other end of the resistor 54 is connected to a connection point connecting the filter inductor 41 and the filter capacitor 42.
　図７Ｂに示すように、スナバ回路５０は、コンデンサ５１及び抵抗５４を有している。コンデンサ５１と抵抗５４の直列回路は、フィルタ回路４０の一対の電源ラインの間に接続されている。 As shown in FIG. 7B, the snubber circuit 50 includes a capacitor 51 and a resistor 54. A series circuit of the capacitor 51 and the resistor 54 is connected between a pair of power supply lines of the filter circuit 40.
　なお、整流器３０は、図７Ｃ及び図７Ｄに示すように、フルブリッジ整流回路でもよい。図７Ｃ及び図７Ｄは、変形例に係る電力変換装置の２次側の回路図である。フィルタ回路４０の構成は、上記と同様である。図７Ｃに示すように、変圧器２０の２次側のコイルは、単一のコイルで構成されている。整流器３０は、ダイオードＤ３１～Ｄ３４のフルブリッジ回路で構成されている。スナバ回路５０は、ダイオードＤ３１～Ｄ３４にそれぞれ並列に接続されている。スナバ回路５０はコンデンサ５１と抵抗５４を有し、コンデンサ５１と抵抗５４は直列に接続されている。 The rectifier 30 may be a full bridge rectifier circuit as shown in FIGS. 7C and 7D. 7C and 7D are circuit diagrams on the secondary side of the power conversion device according to the modification. The configuration of the filter circuit 40 is the same as described above. As shown in FIG. 7C, the secondary coil of the transformer 20 is configured by a single coil. The rectifier 30 is configured by a full bridge circuit of diodes D31 to D34. The snubber circuit 50 is connected in parallel to the diodes D31 to D34. The snubber circuit 50 includes a capacitor 51 and a resistor 54, and the capacitor 51 and the resistor 54 are connected in series.
　図７Ｄに示すように、変圧器２０の２次側のコイルは、単一のコイルで構成されている。整流器３０は、ダイオードＤ３１～Ｄ３４のフルブリッジ回路で構成されている。スナバ回路５０は、図７Ａに示すスナバ回路５０と同様の構成である。フィルタ回路４０とスナバ回路５０との接続形態は、図７Ａに示す接続形態と同様である。 As shown in FIG. 7D, the secondary coil of the transformer 20 is formed of a single coil. The rectifier 30 is configured by a full bridge circuit of diodes D31 to D34. The snubber circuit 50 has the same configuration as the snubber circuit 50 shown in FIG. 7A. The connection form between the filter circuit 40 and the snubber circuit 50 is the same as the connection form shown in FIG. 7A.
　なお、整流器３０に含まれる整流素子は、ダイオードＤ３１～Ｄ３４に限らず、ダイオードと、ＭＯＳＦＥＴ等のトランジスタとを並列に接続した回路構成でもよい。トランジスタを用いる場合には、整流回路は、各トランジスタのオン、オフ動作を同期させた同期整流回路とすればよい。 The rectifying element included in the rectifier 30 is not limited to the diodes D31 to D34, and may be a circuit configuration in which a diode and a transistor such as a MOSFET are connected in parallel. When a transistor is used, the rectifier circuit may be a synchronous rectifier circuit that synchronizes the on / off operation of each transistor.
　整流器３０に含まれるダイオードＤ３１、Ｄ３２は、ショットキーバリアダイオードなど、逆回復動作を伴わないデバイスでもよい。サージ電圧がダイオードＤ３１、Ｄ３２の接合容量の充放電により発生し、振動電流がサージ電圧によって電力変換装置の２次側回路で発生する。ダイオードＤ３１、Ｄ３２が逆回復動作を伴わないデバイスである場合には、振動電流は、ダイオードＤ３１、Ｄ３２に流れる電流値に依存せず、ダイオードＤ３１、Ｄ３２への印加電圧に依存する。そのため、２次側の電流が増加した場合に、サージ電圧を抑制できる。これにより、高電流領域における振動抑制レベルが抑制され、スナバ回路５０の損失を低減し、効率が向上する。 The diodes D31 and D32 included in the rectifier 30 may be devices that do not involve reverse recovery operation, such as Schottky barrier diodes. A surge voltage is generated by charging / discharging the junction capacitance of the diodes D31 and D32, and an oscillating current is generated in the secondary side circuit of the power converter by the surge voltage. When the diodes D31 and D32 are devices that do not involve a reverse recovery operation, the oscillating current does not depend on the current value flowing through the diodes D31 and D32, but depends on the voltage applied to the diodes D31 and D32. Therefore, the surge voltage can be suppressed when the secondary current increases. Thereby, the vibration suppression level in the high current region is suppressed, the loss of the snubber circuit 50 is reduced, and the efficiency is improved.
《第２実施形態》
　本発明の他の実施形態に係る電力変換装置を説明する。本実施形態では、スナバ回路５０による振動電流の抑制レベルが、電力変換装置の出力電流の大きさに応じて複数のレベルに設定されている。本実施形態に係る電力変換装置は、第１実施形態に対して、スナバ回路５０の構成が異なっており、他の構成については、第１実施形態の記載を適宜、援用する。 << Second Embodiment >>
A power converter according to another embodiment of the present invention will be described. In the present embodiment, the level of suppression of the oscillating current by the snubber circuit 50 is set to a plurality of levels according to the magnitude of the output current of the power converter. The configuration of the snubber circuit 50 is different from that of the first embodiment in the power conversion device according to this embodiment, and the description of the first embodiment is used as appropriate for other configurations.
　図８は、電力変換装置の２次側の回路図である。スナバ回路５０は、コンデンサ５１、抵抗５４ａ、５４ｂ、及びトランジスタ５５を有している。コンデンサ５１、トランジスタ５５及び抵抗５４ａは直列に接続されており、コンデンサ５１、トランジスタ５５及び抵抗５４ａの直列回路は、フィルタインダクタ４１に対して並列に接続されている。トランジスタ５５の制御端子（ベース端子又はゲート端子）は、抵抗５４ｂを介して、フィルタ回路４０の正側の電源ラインに接続されている。整流器３０からフィルタ回路４０に入力される電流は、フィルタインダクタ４１と抵抗５４ｂとの接続点で分岐される。そのため、トランジスタ５５の制御端子に流れる制御電流（ベース電流又はゲート電流）は、電力変換装置の出力電流（Ｉｏｕｔ）に対して反比例した電流となる。トランジスタのコレクタエミッタ間は可変抵抗として機能する。すなわち、電力変換装置の出力電流（Ｉｏｕｔ）が低くなると、トランジスタ５５の制御電流は高くなり、トランジスタ５５の抵抗が小さくなる。そのため、スナバ回路５０の抵抗値が小さくなると、スナバ回路５０による振動電流の抑制レベルは高くなる。これにより、スナバ回路５０の特性が振動抑制特性をもつように、スナバ回路５０を構成することができる。 FIG. 8 is a circuit diagram of the secondary side of the power conversion device. The snubber circuit 50 includes a capacitor 51, resistors 54a and 54b, and a transistor 55. The capacitor 51, the transistor 55, and the resistor 54a are connected in series, and the series circuit of the capacitor 51, the transistor 55, and the resistor 54a is connected in parallel to the filter inductor 41. The control terminal (base terminal or gate terminal) of the transistor 55 is connected to the power supply line on the positive side of the filter circuit 40 via the resistor 54b. The current input from the rectifier 30 to the filter circuit 40 is branched at the connection point between the filter inductor 41 and the resistor 54b. Therefore, the control current (base current or gate current) flowing through the control terminal of the transistor 55 is a current that is inversely proportional to the output current (I out ) of the power converter. The collector-emitter between the transistors functions as a variable resistor. That is, when the output current (I out ) of the power conversion device decreases, the control current of the transistor 55 increases and the resistance of the transistor 55 decreases. Therefore, when the resistance value of the snubber circuit 50 decreases, the level of suppression of the oscillating current by the snubber circuit 50 increases. Thus, the snubber circuit 50 can be configured so that the characteristics of the snubber circuit 50 have vibration suppression characteristics.
　また、トランジスタ５５のコレクタエミッタ間又はドレインソース間の抵抗が、制御電流に対して多段階で変化するように、トランジスタ５５を構成することで、スナバ回路５０による振動電流の抑制レベルが複数のレベルとなり、複数の抑制レベルは電力変換装置の出力電流の大きさに応じて変化する。これにより、ソフトスイッチングで動作可能な、出力電流（Ｉｏｕｔ）の範囲を拡大しつつ、スナバ回路５０の損失を低減できる。 Further, by configuring the transistor 55 such that the resistance between the collector and emitter or between the drain and source of the transistor 55 changes in multiple steps with respect to the control current, the level of suppression of the oscillating current by the snubber circuit 50 is a plurality of levels. Thus, the plurality of suppression levels change according to the magnitude of the output current of the power converter. Thereby, the loss of the snubber circuit 50 can be reduced while expanding the range of the output current (I out ) operable by soft switching.
　上記のように、本実施形態では、スナバ回路５０による振動電流の抑制レベルが出力電流（Ｉｏｕｔ）の大きさに応じて複数のレベルに設定されている。これにより、出力電流（Ｉｏｕｔ）に対して相関性をもたせつつ、抑制レベルを多段階で変化させることができるため、効率が向上する。 As described above, in this embodiment, the level of suppression of the oscillating current by the snubber circuit 50 is set to a plurality of levels according to the magnitude of the output current (I out ). As a result, the suppression level can be changed in multiple steps while having a correlation with the output current (I out ), so that the efficiency is improved.
　また本実施規定において、スナバ回路５０はトランジスタ５５を有し、トランジスタの制御端子の電流と電力変換装置の出力電流（Ｉｏｕｔ）との関係が反比例になっている。これにより、単純な構成で振動抑制特性を実現できる。 In this implementation rule, the snubber circuit 50 includes a transistor 55, and the relationship between the current at the control terminal of the transistor and the output current (I out ) of the power converter is inversely proportional. Thereby, vibration suppression characteristics can be realized with a simple configuration.
　なお、トランジスタ５５は両方向に通電可能なスイッチング素子としてもよい。またトランジスタ５５は、ノーマリオンのスイッチング素子とし、出力電流（Ｉｏｕｔ）が高いほど、トランジスタ５５のゲートの負バイアス電圧が増加するように、電力変換装置の２次側の回路が構成されてもよい。これにより、スナバ回路５０の特性を振動抑制特性とすることができるため、スイッチング素子のスイッチング損失を抑制しつつ、効率を高めることができる。 Note that the transistor 55 may be a switching element that can be energized in both directions. Further, the transistor 55 is a normally-on switching element, and the secondary side circuit of the power converter is configured such that the negative bias voltage of the gate of the transistor 55 increases as the output current (I out ) increases. Good. Thereby, since the characteristic of the snubber circuit 50 can be made into a vibration suppression characteristic, efficiency can be improved, suppressing the switching loss of a switching element.
《第３実施形態》
　本発明の他の実施形態に係る電力変換装置を説明する。本実施形態では、スナバ回路５０がスイッチを有しており、スイッチのオン、オフを制御することで、振動抑制特性を実現している。本実施形態に係る電力変換装置は、第１実施形態に対して、スナバ回路５０の構成及びスナバ回路５０の制御が異なっており、他の構成については、第１実施形態又は第２実施形態の記載を適宜、援用する。 << Third Embodiment >>
A power converter according to another embodiment of the present invention will be described. In the present embodiment, the snubber circuit 50 includes a switch, and vibration suppression characteristics are realized by controlling on / off of the switch. The power converter according to the present embodiment differs from the first embodiment in the configuration of the snubber circuit 50 and the control of the snubber circuit 50. The other configurations are the same as those in the first embodiment or the second embodiment. The description is incorporated as appropriate.
　図９は、本実施形態に係る電力変換装置のブロック図である。電力変換装置は、インバータ回路１０等に加えて、電流センサ２００を備えている。電流センサ２００は、フィルタ回路４０の出力側に接続されており、電力変換装置の出力電流（Ｉｏｕｔ）を検出する。電流センサ２００は、検出電流をコントローラ１００に出力する。電流センサ２００には、ホール電流センサ等のセンサが使用される。コントローラ１００は、電流センサ２００から取得した検出電圧に応じて、スナバ回路５０に含まれるスイッチのオン、オフを切り替える。なお、電流センサ２０は、フィルタ回路４０の入力側に接続されてもよい。 FIG. 9 is a block diagram of the power converter according to the present embodiment. The power converter includes a current sensor 200 in addition to the inverter circuit 10 and the like. The current sensor 200 is connected to the output side of the filter circuit 40 and detects the output current (I out ) of the power converter. The current sensor 200 outputs the detected current to the controller 100. As the current sensor 200, a sensor such as a Hall current sensor is used. The controller 100 switches on and off the switches included in the snubber circuit 50 according to the detected voltage acquired from the current sensor 200. Note that the current sensor 20 may be connected to the input side of the filter circuit 40.
　スナバ回路５０は、少なくともスイッチ５６を有している。スイッチ５６は半導体スイッチである。スイッチ５６は、半導体スイッチに限らず、機械的な接点スイッチでもよい。スナバ回路５０の具体的な回路構成を、図１０Ａに示す。図１０Ａはスナバ回路５０の回路図である。スナバ回路５０は、コンデンサ５１、抵抗５４а、５４ｂ、及びスイッチ５６を有している。コンデンサ５１と抵抗５４аは直列に接続されている。抵抗５４ｂとスイッチ５６は直列に接続されている。抵抗５４ｂとスイッチ５６の直列回路は、抵抗５４аに対して並列に接続されている。 The snubber circuit 50 has at least a switch 56. The switch 56 is a semiconductor switch. The switch 56 is not limited to a semiconductor switch, and may be a mechanical contact switch. A specific circuit configuration of the snubber circuit 50 is shown in FIG. 10A. FIG. 10A is a circuit diagram of the snubber circuit 50. The snubber circuit 50 includes a capacitor 51, resistors 54a and 54b, and a switch 56. The capacitor 51 and the resistor 54a are connected in series. The resistor 54b and the switch 56 are connected in series. A series circuit of the resistor 54b and the switch 56 is connected in parallel to the resistor 54a.
　スイッチ５６がオン状態の場合に、スナバ回路５０の抵抗値は抵抗５４аと抵抗５４ｂとの合成抵抗の値となる。スイッチ５６がオフ状態の場合に、スナバ回路５０の抵抗値は抵抗５４аの抵抗値となる。スナバ回路５０の抵抗値がスイッチ５６のオン、オフに応じて変わることで、スナバ回路５０による振動電流の抑制レベルが変わる。すなわち、スイッチ５６は、スナバ回路５０の抑制レベルを切り換えるスイッチである。 When the switch 56 is in the ON state, the resistance value of the snubber circuit 50 is a combined resistance value of the resistor 54a and the resistor 54b. When the switch 56 is off, the resistance value of the snubber circuit 50 is the resistance value of the resistor 54a. When the resistance value of the snubber circuit 50 changes according to whether the switch 56 is turned on or off, the level of suppression of the oscillating current by the snubber circuit 50 changes. That is, the switch 56 is a switch that switches the suppression level of the snubber circuit 50.
　コントローラ１００は、スイッチ５６のオン、オフを制御するための駆動電圧又は駆動電流をスナバ回路５０に出力する。駆動用の電源はスナバ回路５０に内蔵されている。コントローラ１００は、電流閾値をメモリに記憶している。電流閾値は、スイッチンのオン、オフの切替を判断するための閾値であって、予め設定されている。コントローラ１００は、電流閾値と電流センサ２００の検出電流とを比較し、比較結果に応じてスイッチ５６のオン、オフを切り替える。 The controller 100 outputs a driving voltage or a driving current for controlling on / off of the switch 56 to the snubber circuit 50. A power supply for driving is built in the snubber circuit 50. The controller 100 stores a current threshold value in a memory. The current threshold is a threshold for determining whether the switch is turned on or off, and is set in advance. The controller 100 compares the current threshold value with the detected current of the current sensor 200, and switches the switch 56 on and off according to the comparison result.
　なお、コントローラ１００は、インバータ回路１０の制御用と、スナバ回路５０の制御用に分けてもよい。また、スイッチ５６のオン、オフを切り替えるための制御信号が絶縁されるような構成でもよい。これにより、スナバ回路の振動抑制レベルを可変させるための閾値を調整することができる。 Note that the controller 100 may be divided into control for the inverter circuit 10 and control for the snubber circuit 50. Moreover, the structure which the control signal for switching on / off of the switch 56 is insulated may be sufficient. Thereby, the threshold value for varying the vibration suppression level of the snubber circuit can be adjusted.
　スナバ回路５０の抵抗値が、スイッチ５６のオンで低くなり、スイッチ５６のオフで高くなる場合には、コントローラ１００は以下のようにスイッチ５６を制御する。電流センサの検出電流（Ｉｏｕｔ）が電流閾値以上である場合には、コントローラ１００は、スイッチ５６をオフにして、スナバ回路５０の抵抗値をより高くする。スナバ回路５０の抑制レベルは低レベルになり、スナバ回路５０の損失が抑制される。一方、電流センサの検出電流（Ｉｏｕｔ）が電流閾値未満である場合には、コントローラ１００は、スイッチ５６をオンにして、スナバ回路５０の抵抗値をより低くする。スナバ回路５０の抑制レベルは高レベルになり、スナバ回路５０による振動抑制効果が高まるため、ソフトスイッチング動作を実現できる。 When the resistance value of the snubber circuit 50 becomes low when the switch 56 is turned on and becomes high when the switch 56 is turned off, the controller 100 controls the switch 56 as follows. When the detected current (I out ) of the current sensor is equal to or greater than the current threshold, the controller 100 turns off the switch 56 and increases the resistance value of the snubber circuit 50. The suppression level of the snubber circuit 50 becomes a low level, and the loss of the snubber circuit 50 is suppressed. On the other hand, when the detected current (I out ) of the current sensor is less than the current threshold, the controller 100 turns on the switch 56 to lower the resistance value of the snubber circuit 50. Since the suppression level of the snubber circuit 50 becomes high and the vibration suppression effect by the snubber circuit 50 increases, a soft switching operation can be realized.
　上記のように、本実施形態では、スナバ回路５０は、抑制レベルを切り換えるスイッチ５６を有し、コントローラ１００は、電流センサ２００の検出電流の大きさに応じてスイッチ５６のオン、オフを切り替える。これにより、出力電流（Ｉｏｕｔ）の大きさに応じて、振動抑制レベルを多段階で制御しつつ、振動抑制特性を得ることができる。 As described above, in the present embodiment, the snubber circuit 50 includes the switch 56 that switches the suppression level, and the controller 100 switches the switch 56 on and off according to the magnitude of the current detected by the current sensor 200. As a result, vibration suppression characteristics can be obtained while controlling the vibration suppression level in multiple stages according to the magnitude of the output current (I out ).
　なお、スナバ回路５０は、図１０Ａに示す回路構成に限らず、他の回路構成でもよい。他の回路構成の例を、図１０Ｂ～１０Ｄに示す。図１０Ｂ～図１０Ｄは、変形例に係るスナバ回路５０の回路図である。 Note that the snubber circuit 50 is not limited to the circuit configuration shown in FIG. Examples of other circuit configurations are shown in FIGS. 10B to 10D. 10B to 10D are circuit diagrams of a snubber circuit 50 according to a modification.
　図１０Ｂに示すように、スナバ回路５０は、コンデンサ５１а、５１ｂ、抵抗５４、スイッチ５６を有している。コンデンサ５１аと抵抗５４が直列に接続され、コンデンサ５１ｂとスイッチ５６が直列に接続されている。コンデンサ５１ｂとスイッチ５６の直列回路は、コンデンサ５１ｂに並列に接続されている。スナバ回路５０の静電容量が、スイッチ５６のオン、オフにより切り替わることで、スナバ回路５０の抑制レベルを多段階で切り換えることができる。 As shown in FIG. 10B, the snubber circuit 50 includes capacitors 51a and 51b, a resistor 54, and a switch 56. A capacitor 51a and a resistor 54 are connected in series, and a capacitor 51b and a switch 56 are connected in series. A series circuit of the capacitor 51b and the switch 56 is connected in parallel to the capacitor 51b. The suppression level of the snubber circuit 50 can be switched in multiple stages by switching the capacitance of the snubber circuit 50 by turning on and off the switch 56.
　図１０Ｃに示すように、スナバ回路５０は、コンデンサ５１а、５１ｂ、抵抗５４、スイッチ５６を有している。コンデンサ５１а、５１ｂ及び抵抗５４は直列に接続されている。スイッチ５６は、コンデンサ５１ｂに並列に接続されている。スナバ回路５０の静電容量が、スイッチ５６のオン、オフにより切り替わることで、スナバ回路５０の抑制レベルを多段階で切り換えることができる。 As shown in FIG. 10C, the snubber circuit 50 includes capacitors 51a and 51b, a resistor 54, and a switch 56. The capacitors 51a and 51b and the resistor 54 are connected in series. The switch 56 is connected in parallel to the capacitor 51b. The suppression level of the snubber circuit 50 can be switched in multiple stages by switching the capacitance of the snubber circuit 50 by turning on and off the switch 56.
　図１０Ｄに示すように、スナバ回路５０は、コンデンサ５１、抵抗５４а、５４ｂ、スイッチ５６を有している。コンデンサ５１、抵抗５４а及び抵抗５４ｂは直列に接続されている。スイッチ５６は、抵抗５４аに並列に接続されている。スナバ回路５０の抵抗値が、スイッチ５６のオン、オフにより切り替わることで、スナバ回路５０の抑制レベルを多段階で切り換えることができる。 As shown in FIG. 10D, the snubber circuit 50 includes a capacitor 51, resistors 54a and 54b, and a switch 56. The capacitor 51, the resistor 54a, and the resistor 54b are connected in series. The switch 56 is connected in parallel with the resistor 54a. When the resistance value of the snubber circuit 50 is switched by turning on / off the switch 56, the suppression level of the snubber circuit 50 can be switched in multiple stages.
　なお、スナバ回路５０は、図１０Ａ～図１０Ｄに示す回路を組み合わせた回路としてもよく、出力電流（Ｉｏｕｔ）の大きさに応じて、導通回路及び非導通回路を切り換えてもよい。 Note that the snubber circuit 50 may be a circuit combining the circuits shown in FIGS. 10A to 10D, and the conduction circuit and the non-conduction circuit may be switched in accordance with the magnitude of the output current (I out ).
　なお、本実施形態の変形例として、スナバ回路５０は、抑制レベルの異なる複数の保護回路を有してもよい。図１１は、変形例に係るスナバ回路５０の回路図である。図１１に示すように、スナバ回路５０は、スイッチ５６а、５６ｂ及び保護回路５７а～５７ｃを有している。保護回路５７а～５７ｃは、コンデンサ５１а～５１ｃと抵抗５４а～５４ｃとを直列した直列回路である。コンデンサ５１а～５１ｃは互いに静電容量の異なるコンデンサである、抵抗５４а～５４ｃ互いに抵抗値の異なる抵抗である。つまり、保護回路５７а～５７ｃは、それぞれ独立したスナバ回路であり、互いに振動抑制レベルの異なる回路である。スイッチ５６аは保護回路５７аと保護回路５７ｂとの間に接続され、スイッチ５６ｂは保護回路５７ｂと保護回路５７ｃとの間に接続されている。 As a modification of the present embodiment, the snubber circuit 50 may include a plurality of protection circuits having different suppression levels. FIG. 11 is a circuit diagram of a snubber circuit 50 according to a modification. As shown in FIG. 11, the snubber circuit 50 includes switches 56a and 56b and protection circuits 57a to 57c. The protection circuits 57a to 57c are series circuits in which capacitors 51a to 51c and resistors 54a to 54c are connected in series. The capacitors 51a to 51c are capacitors having different capacitances, and the resistors 54a to 54c are resistors having different resistance values. That is, the protection circuits 57a to 57c are independent snubber circuits, and are circuits having different vibration suppression levels. The switch 56a is connected between the protection circuit 57a and the protection circuit 57b, and the switch 56b is connected between the protection circuit 57b and the protection circuit 57c.
　コントローラ１００は、電流センサ２００により検出された検出電流の大きさに応じて、スイッチ５６、５６ｂのオン、オフにより切り替わることで、保護回路５７а～５７ｃの導通、非導通を切り換える。これにより、スナバ回路５０の抑制レベルを多段階で切り換えることができる。 The controller 100 switches between conduction and non-conduction of the protection circuits 57a to 57c by switching the switches 56 and 56b on and off according to the magnitude of the detected current detected by the current sensor 200. Thereby, the suppression level of the snubber circuit 50 can be switched in multiple stages.
　なお、本実施形態の変形例として、スナバ回路５０は、スイッチを介して、整流器３０又はフィルタ回路４０に接続されてもよい。そして、コントローラ１００は、出力電流（Ｉｏｕｔ）の大きさに応じて、スイッチをオフにしてスナバ回路５０を切り離す。これにより、スナバ回路５０による振動抑制が不要な場合には、スナバ回路５０を切り離すことができるため、効率を向上させることができる。 As a modification of the present embodiment, the snubber circuit 50 may be connected to the rectifier 30 or the filter circuit 40 via a switch. Then, the controller 100 turns off the switch and disconnects the snubber circuit 50 in accordance with the magnitude of the output current (I out ). Thereby, when the vibration suppression by the snubber circuit 50 is unnecessary, the snubber circuit 50 can be cut off, so that the efficiency can be improved.
１０…インバータ回路
１１～１４…コンデンサ
１５…平滑コンデンサ
２０…変圧器
２１…１次側コイル
２２、２２а、２２ｂ…２次側コイル
３０…整流回路
４０…フィルタ回路
５０…スナバ回路
１００…コントローラ
２００…電流センサ
Ｄ１～Ｄ４…還流ダイオード
Ｄ３１～３４…ダイオード
Ｓ１～Ｓ４…スイッチング素子 DESCRIPTION OF SYMBOLS 10 ... Inverter circuits 11-14 ... Capacitor 15 ... Smoothing capacitor 20 ... Transformer 21 ... Primary side coil 22, 22a, 22b ... Secondary side coil 30 ... Rectifier circuit 40 ... Filter circuit 50 ... Snubber circuit 100 ... Controller 200 ... Current sensors D1 to D4 ... Freewheeling diodes D31 to 34 ... Diodes S1 to S4 ... Switching elements

Claims (16)

  1. 　電力変換装置において、
    　スイッチング素子を有するインバータ回路と、
    　前記インバータ回路に接続される変圧器と、
    　前記変圧器から出力される電力を整流する整流回路と、
    　前記整流回路に流れる電流の振動を抑制するスナバ回路とを備え、
    前記スナバ回路は、前記電力変換装置の出力電流が低くなると、振動電流の抑制レベルがより高くなる特性をもつ電力変換装置。     In the power converter,
    An inverter circuit having a switching element;
    A transformer connected to the inverter circuit;
    A rectifier circuit for rectifying the power output from the transformer;
    A snubber circuit that suppresses vibration of the current flowing through the rectifier circuit,
    The snubber circuit is a power converter having a characteristic that when the output current of the power converter decreases, the suppression level of the oscillating current increases.
  2. 　前記抑制レベルは、前記出力電流の大きさに応じた複数のレベルに設定されている請求項１記載の電力変換装置。 The power conversion device according to claim 1, wherein the suppression level is set to a plurality of levels according to the magnitude of the output current.
  3. 　前記スイッチング素子は、ＬＣ共振を利用したソフトスイッチングで動作する
    請求項１又は２記載の電力変換装置。     The power conversion device according to claim 1, wherein the switching element operates by soft switching using LC resonance.
  4. 　前記抑制レベルは、前記出力電流と相関性をもつパラメータに応じて変化する
    請求項１～３のいずれか一項に記載の電力変換装置。     The power conversion device according to any one of claims 1 to 3, wherein the suppression level changes according to a parameter having a correlation with the output current.
  5. 　前記整流回路はインダクタを有し、
    　前記スナバ回路は磁気抵抗素子を有し、
    　前記磁気抵抗素子は、前記インダクタで発生する磁気回路内に配置されている
    請求項１～４のいずれか一項に記載の電力変換装置。     The rectifier circuit has an inductor;
    The snubber circuit has a magnetoresistive element;
    The power conversion device according to any one of claims 1 to 4, wherein the magnetoresistive element is arranged in a magnetic circuit generated by the inductor.
  6. 　前記インダクタは、磁性体コアを有し、
    　前記磁気抵抗素子は前記磁性体コアのギャップに配置されている
    請求項５記載の電力変換装置。     The inductor has a magnetic core,
    The power converter according to claim 5, wherein the magnetoresistive element is disposed in a gap of the magnetic core.
  7. 　前記スナバ回路は、正の温度特性をもつ抵抗素子を有する
    請求項１～４のいずれか一項に記載の電力変換装置。     The power converter according to any one of claims 1 to 4, wherein the snubber circuit includes a resistance element having a positive temperature characteristic.
  8. 　前記抵抗素子は、前記整流回路又は前記変圧器の少なくとも何れか一方に近接して配置されている
    請求項７記載の電力変換装置。     The power converter according to claim 7, wherein the resistance element is disposed in proximity to at least one of the rectifier circuit and the transformer.
  9. 　前記スナバ回路は、負の温度特性をもつ静電容量素子を有する
    請求項１～４のいずれか一項に記載の電力変換装置。     The power converter according to any one of claims 1 to 4, wherein the snubber circuit includes a capacitive element having a negative temperature characteristic.
  10. 　前記静電容量素子は、前記整流回路又は前記変圧器の少なくとも何れか一方に近接して配置されている
    請求項９記載の電力変換装置。     The power converter according to claim 9, wherein the electrostatic capacitance element is disposed in proximity to at least one of the rectifier circuit and the transformer.
  11. 　前記スナバ回路は、トランジスタを有し、
    　前記トランジスタの制御端子に流れる電流と前記出力電流との関係が反比例である
    請求項１～４のいずれか一項に記載の電力変換装置。     The snubber circuit has a transistor,
    The power converter according to any one of claims 1 to 4, wherein a relationship between a current flowing through a control terminal of the transistor and the output current is inversely proportional.
  12. 　前記出力電流を検出するセンサと、
    　前記スナバ回路を制御するコントローラとを備え、
    前記スナバ回路は、前記抑制レベルを切り換えるスイッチを有し、
    前記コントローラは、前記センサにより検出された検出電流に応じて、前記スイッチのオン、オフを切り換える
    請求項１～４のいずれか一項に記載の電力変換装置。     A sensor for detecting the output current;
    A controller for controlling the snubber circuit,
    The snubber circuit has a switch for switching the suppression level,
    The power converter according to any one of claims 1 to 4, wherein the controller switches on and off of the switch according to a detection current detected by the sensor.
  13. 　前記出力電流を検出するセンサと、
    　前記スナバ回路を制御するコントローラとを備え、
    前記スナバ回路は、前記抑制レベルの異なる複数の保護回路を有し、
    前記コントローラは、前記センサにより検出された検出電流に応じて、前記保護回路の導通及び非導通を切り換える
    請求項１～４のいずれか一項に記載の電力変換装置。     A sensor for detecting the output current;
    A controller for controlling the snubber circuit,
    The snubber circuit has a plurality of protection circuits with different suppression levels,
    The power converter according to any one of claims 1 to 4, wherein the controller switches between conduction and non-conduction of the protection circuit in accordance with a detection current detected by the sensor.
  14. 　前記スナバ回路は、スイッチ、抵抗及びコンデンサの少なくともいずれか１つの回路素子を有する
    請求項１２又は１３記載の電力変換装置。     The power converter according to claim 12 or 13, wherein the snubber circuit includes at least one circuit element of a switch, a resistor, and a capacitor.
  15. 　前記スナバ回路を制御するコントローラを備え、
    前記コントローラは、前記出力電流の値に応じて、前記スナバ回路の導通と非導通とを切り換える
    請求項１～４のいずれか一項に記載の電力変換装置。     A controller for controlling the snubber circuit;
    The power converter according to any one of claims 1 to 4, wherein the controller switches between conduction and non-conduction of the snubber circuit according to the value of the output current.
  16. 　前記整流回路は、ショットキーバリアダイオードを有する
    請求項１～１５のいずれか一項に記載の電力変換装置。     The power converter according to any one of claims 1 to 15, wherein the rectifier circuit includes a Schottky barrier diode.
PCT/JP2017/014633 2017-04-10 2017-04-10 Power conversion device WO2018189773A1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009027764A (en) * 2007-07-17 2009-02-05 Fuji Electric Systems Co Ltd Snubber circuit
JP2017042001A (en) * 2015-08-21 2017-02-23 矢崎総業株式会社 Power supply
JP2017055561A (en) * 2015-09-09 2017-03-16 株式会社東芝 Power source supply device, and power source supply method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009027764A (en) * 2007-07-17 2009-02-05 Fuji Electric Systems Co Ltd Snubber circuit
JP2017042001A (en) * 2015-08-21 2017-02-23 矢崎総業株式会社 Power supply
JP2017055561A (en) * 2015-09-09 2017-03-16 株式会社東芝 Power source supply device, and power source supply method

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