WO2018188657A1 - Procédé et système de traitement de branchement - Google Patents

Procédé et système de traitement de branchement Download PDF

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Publication number
WO2018188657A1
WO2018188657A1 PCT/CN2018/083053 CN2018083053W WO2018188657A1 WO 2018188657 A1 WO2018188657 A1 WO 2018188657A1 CN 2018083053 W CN2018083053 W CN 2018083053W WO 2018188657 A1 WO2018188657 A1 WO 2018188657A1
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WO
WIPO (PCT)
Prior art keywords
branch
instruction
address
processor core
storage device
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PCT/CN2018/083053
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English (en)
Chinese (zh)
Inventor
林正浩
Original Assignee
上海芯豪微电子有限公司
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Filing date
Publication date
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Publication of WO2018188657A1 publication Critical patent/WO2018188657A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead

Definitions

  • the present invention relates to the field of electronic computers and microprocessors.
  • Control related Hazards also known as branches
  • Current mainstream microprocessors use branch prediction (branch Prediction) way to eliminate branch loss.
  • 1 is an embodiment of a conventional microprocessor processing condition branching mode.
  • 101 is the branch target buffer (Branch Target Buffer , BTB)
  • 105 is the instruction cache
  • 108 is the processor core.
  • a typical BTB stores the branch instruction address and the corresponding branch target instruction address, as well as its branch prediction.
  • BTB The complex branch instruction address stored in 101 is compared to the instruction address 106 generated by 108. If there is a match, the control signal 103 is output according to the branch prediction 102 stored in the matched BTB line. To control the selector 104.
  • 104 selects the branch target address in the BTB match row to be supplied to 105. If there is no match, or there is a match but the branch is predicted not to branch, 104 select The sequential address on 106 is provided to 105.
  • the instruction cache 105 provides branch targets or sequential instructions to the processor core via the bus 107 based on the branch target or sequential address. carried out. This eliminates the loss of the branch.
  • branch predictions have unpredictable prediction errors.
  • branch instructions to generate branch decisions (branch The decision is not the same as the branch prediction, and the processing result of each pipeline segment before the pipeline segment in which the branch judgment is generated in the processor pipeline must be cleared, and a selected instruction from the branch judgment is re-executed, resulting in performance loss.
  • the present invention is directed to the deficiencies of the prior art, and proposes a branch processing method and system, which is characterized in that the branch target and the sequential two instructions are determined by the branch generated by the processor core to select an instruction for the processor core to execute, so there is no branch. Loss; branch prediction is not used, so processor performance loss due to branch prediction errors is completely ruled out.
  • an instruction address is provided by a processor core that provides a sequential instruction that is also compared to a branch instruction address stored in the BTB.
  • the branch target instruction is directly provided by the BTB based on the matching result.
  • the BTB provides a branch target instruction address according to the matching result, the branch target instruction address addresses the storage device, and the branch destination address is provided by the storage device.
  • the branch generated by the processor core determines the select order instruction or the branch target instruction for execution by the processor core.
  • the branch decision is decoded by the branch instruction.
  • the branch decision is generated by the branch instruction decoding in conjunction with the execution of the branch instruction or the result of the previous instruction.
  • the invention eliminates the performance loss caused by the branch prediction, and saves the chip area occupied by the branch prediction device and the power consumption consumed.
  • Figure 1 is an embodiment of a conventional branch processing branch.
  • FIG. 3 is another embodiment of the branching processing branch of the present invention.
  • Fig. 4 is another embodiment of the branching processing branch of the present invention.
  • Figure 5 is another embodiment of the branching processing branch of the present invention.
  • Figure 4 is a preferred embodiment of the invention.
  • 115 is the branch instruction address / The BTB of the branch target instruction pair
  • 105 is the instruction memory (memory)
  • 116 is the selector
  • 108 is the processor core.
  • Processor core 108 generates branch decisions 110 To control the selector 116.
  • 108 Generate instruction address 106 .
  • 106 Addressing Instruction Memory 105, 105 provides sequential instructions 111.
  • 106 also with BTB 115 Branch instruction address comparison stored in . If a branch instruction address in 115 matches the instruction address 106, the BTB 115 provides a branch target instruction corresponding to the branch instruction address. .
  • the address (sequential address) of the first instruction after the branch instruction is sent is sent by the address instruction memory 105, 105 via the bus 111 to the first instruction after the branch instruction is provided. If BTB115 The branch instruction address matches the branch instruction address in 106, and the BTB115 outputs the branch target instruction via the bus 112. So the two inputs 112 and 111 of the selector 116 There is a branch target instruction, and the first instruction (fall-through instruction) after the branch instruction waits for the selection of the branch judgment 110 generated by the processor core.
  • 116 selects the branch instruction and the first instruction 111 passes through the bus 107.
  • 106 continues to provide subsequent sequential addresses (in this case, the addresses of the two instructions after the branch instruction), and the addressing instruction memories 105, 105 provide sequential instructions.
  • the 116 select branch target instruction 112 is provided to bus 108 via bus 107. carried out.
  • the processor core 108 simultaneously computes the address of the first instruction (sequential instruction) after the branch instruction while executing the branch instruction.
  • 106 provides the address of the first instruction after the branch target instruction, addressing the instruction memory 105 , 105 provides the first instruction after the branch target instruction. Thereafter, 106 provides the sequential instruction address after the branch target instruction (in this case, the two instruction addresses after the branch target), and the instruction memory 105 is addressed. Provides subsequent instructions for the branch target instruction.
  • the present invention simultaneously provides two instructions of a branch to the processor core, and selects by branch judgment to implement the lossless branch.
  • the invention does not rely on branch prediction, and avoids losses caused by branch prediction ( Mis-prediction penalty ).
  • processor 108 When the processor 108 decodes the instruction sent via 107, it finds that the instruction is a branch instruction, and the corresponding branch instruction address is in BTB. The case where no match is found in 115 is BTB missing.
  • control selector 116 selects sequence instruction 111 for processor core 108 carried out.
  • processor 108 sends the branch target instruction address via instruction address 106 to address instruction memory 105.
  • 105 by 111 provides a branch target instruction, at which point selector 116 selects 111 to send to processor core 108 for execution. And establish the branch instruction address in BTB 115 / Branch target instruction pair. Thereafter, processor 108 sends a subsequent address of the branch target address via instruction address 106, and address instruction memory 105 provides instructions to 108.
  • the processor core 108 provides the instruction address 106. Is the sequential instruction address (including the branch instruction address).
  • the instruction address 106 when the branch decision 110 is 'branch' and the BTB 115 matches the hit.
  • the address of the subsequent instruction that is the branch target instruction.
  • the sequential instruction address is the number of bytes added by the previous instruction address plus one instruction.
  • Figure 3 is another embodiment of the branching processing branch of the present invention.
  • 101 is the storage branch instruction address / The branch target instruction address pair (pair) BTB
  • 125 is the instruction memory with two read ports
  • 116 is the selector
  • 108 is the processor core.
  • 108 Generate Instruction Address 106
  • 106 Addresses the first read port of instruction memory 125, which provides sequential instructions 111.
  • 106 also with 101 Branch instruction address comparison in .
  • BTB 101 Provide the corresponding branch target instruction address.
  • the branch target instruction address addresses the second read port of the instruction memory 125 via which the corresponding branch target instruction 112 is provided.
  • Processor core 108 also produces branch decisions 110 To control the selector 116. If the value of 110 is 'no branch', then 116 selects the branch instruction and the first instruction 111 is provided to 108 for execution via bus 107. Such as 110 The value is 'branch', then the 116 select branch target instruction 112 is provided to 108 for execution via bus 107.
  • the instruction address 106 and the branch judgment 110 are generated in this embodiment and FIG. 2
  • the manner of production in the examples is the same.
  • the processing method in the case where the BTB is missing in this embodiment is also the same as that in the embodiment of Fig. 2.
  • Fig. 4 is another embodiment of the branching processing branch of the present invention.
  • 101 is the storage branch instruction address / BTB of the branch target instruction address pair
  • 105 is the instruction memory
  • 118 is the instruction buffer
  • 204 and 116 are selectors
  • 113 is the adder.
  • 108 is the processor core.
  • the instruction buffer 118 is a memory with read and write control and address addressing. Due to the instruction buffer 118 Only sequential instructions are provided, the stored instruction address space is contiguous, in a small range, so 118 capacity can be small, such as only accommodating one instruction line or instruction block to meet the requirements of the present invention.
  • Instruction memory 105 is another discrete memory that is addressed by additional read and write control and address. 105 responsible for providing branch target instructions, which require a larger address space and therefore require a larger storage capacity than 118. The branch instruction address and its corresponding branch target instruction pair are stored in the BTB101. Processor core 108 The instruction address 106, 106 is addressed to address the instruction buffers 118, 118 to provide sequential instructions over the bus 111. 106 also with 101 Branch instruction address comparison stored in .
  • BTB 101 A branch target instruction address corresponding to the branch instruction address is provided, and the selector 204 is also controlled to select the branch target instruction address provided by the BTB101.
  • the branch target instruction address addresses the instruction memory 105, 105
  • the corresponding branch target instruction is provided via bus 112.
  • 106 provides the first instruction address after the branch instruction, and addresses the instruction buffer 118, 118 through the bus 111. Provide the first instruction after the branch instruction.
  • Processor core 108 also generates branch decisions 110 to control selector 116.
  • the value of 110 is 'no branch', then 116 selects the branch instruction on bus 111 and the first instruction passes bus 107. Provided to processor core 108 for execution. Thereafter, the address on 106 is the address of the second instruction after the branch instruction, and the control instruction buffer 118 Provide the second instruction after the branch instruction. If the first instruction after the branch instruction is not a branch instruction, the value of the branch decision 110 at this time is 'no branch', and the control selector 116 selects 118. The second instruction is provided by the processor core 108 after the branch instruction is provided. Subsequent instructions of the branch instruction in the instruction buffer are executed in this order.
  • the 116 branch target instruction on bus 112 is provided to bus 108 via bus 107. carried out.
  • the instruction memory 105 provides the instruction line in which the branch target instruction is located, and stores it in the instruction buffer 118.
  • the address on 106 is the address of the first instruction after the branch target instruction
  • the control instruction buffer 118 Provides the first instruction after the branch target instruction. If the branch target instruction itself is not a branch instruction, the value of the branch decision 110 at this time is 'no branch', and the control selector 116 selects 118.
  • the first instruction after the provided branch target instruction is executed by the processor core 108. Subsequent instructions of the branch target instruction in the instruction buffer 118 are executed in this order.
  • selector 204 selects the bus.
  • the address on 106 because the value of the branch decision 110 is 'branch', but the BTB does not match, the processor core 108 generates a bus 106.
  • the address sent is the branch target instruction address.
  • the branch target instruction address addressing instruction memory 105 provides the instruction line in which the branch target instruction is located via bus 112.
  • Branch judgment control selector 116 with value of 'branch' The branch target instruction on select bus 112 is executed by bus 107 for processor core 108.
  • the instruction line on 112 is stored in the instruction buffer 118. Will also branch instruction address / The branch target instruction address pair is stored in BTB101 for later use.
  • the processor core 108 generates the address of the first instruction after the branch target instruction is sent via the bus 106, and reads 118.
  • the middle instruction by which the time value is 'no branch', is judged by the selector 116 selected for processing by the processor core 108.
  • the instruction buffer is executed in this order. Subsequent instructions for branch target instructions in .
  • Adder 113 will be the instruction address 106
  • the row address portion of the upper address plus the number of bytes in the instruction line gives the row address of the next row in sequence.
  • the intra-block offset address in the instruction address points to the last instruction of the instruction buffer 118, make 118
  • the selector 204 selects the address of the next row in the order of the output of the adder 113 to address the instruction memory 105.
  • the next line of instructions is provided for storage in the instruction buffer 118.
  • instruction address 106 addressing 118 provides processor core 108 with instructions for the next row in sequence for execution.
  • the instruction address 106 and the branch determination 110 are generated in the same manner as in the embodiment of Fig. 2 in this embodiment. Occurred in this embodiment
  • the processing when BTB is missing is also similar to the processing in the embodiment of Figure 2.
  • the branch target instruction address on the address bus 106 output by the processor core at this time passes through the selector 204. Addressing the instruction memory 105.
  • the selector 116 is still controlled by the branch decision 110 to select the branch target instruction provided by the instruction memory 105. That is, the selector 116 is judged by the branch at any time. 110 control.
  • a typical processor core pipeline has five pipeline segments, fetch ( I ), decode ( D ), execute (E), and fetch ( M ), and write back the segment (W).
  • Branch judgments can usually be generated in either D or E segments. The above three embodiments are based on branch judgment in D The hypothesis generated by the segment, or the branch judgment is generated early enough, one of the two instructions after the branch instruction can be selected for processing by the processor core.
  • processor core 108 The sequential address is generated, and the address of an instruction after the branch instruction is generated after the branch instruction address is generated. Thereafter, if the value judged by the branch is 'no branch', then 108 The address of the second instruction after the branch instruction is generated. If the value judged by the branch is 'branch', then 108 the address of the first instruction after the branch target instruction is generated.
  • Figure 5 is another embodiment of the branching processing branch of the present invention.
  • Figure 5 is the branch judgment in E The embodiment generated by the segment, or the branch judgment is not generated enough, and after the partial processing of both instructions is required, the branch judges to select one of the two partial processing results for further processing by the processor core.
  • 101 is a BTB storing a branch instruction address/branch target instruction address pair
  • 105 is an instruction memory
  • 118 is the instruction buffer (buffer)
  • 113 is the adder
  • 204 and 116 are the selectors
  • 117 and 119 are the instruction decoders
  • 128 Is a processor core without an instruction decoder. 128 generating an instruction address is output via bus 106, and an instruction address on bus 106 addresses instruction buffer 118, 118 provides sequential instruction 111, 111 is decoded by the instruction decoder 117.
  • the branch decision 110 with a value of 'no branch' selects the instruction decode result of 117 for execution by processor core 128.
  • the instruction address sequence on bus 106 points to the next instruction, and control instruction buffer 118 sends the corresponding instruction to decoder 117 Decoding. If the branch instruction address in BTB 101 matches the instruction address on bus 106, BTB101 The address of the first instruction after the branch target instruction is sent in the next cycle, except for the corresponding branch target instruction address when the match is sent.
  • the control causes the bus 106 The upper address is the subsequent address of one of the above two addresses. Specifically, when the branch judgment value is 'no branch', the bus 106 The upper instruction address is the address of the third instruction after the branch instruction; when the branch judgment value is 'branch', the instruction address on the bus 106 is the address of the second instruction after the branch target instruction. Control the branch of the selector 116 to determine the bus 110 then keeps the value of the 'branch' for one cycle when its value is 'branch'. The value at 110 is then determined by the new branch.
  • the address on bus 106 is also compared to the address of the stored branch instruction in 101. If a branch instruction address and instruction address in 101 106 match, then BTB 101 provides the corresponding branch target instruction address, and also controls selector 204 to select BTB101 The branch target instruction address provided.
  • the branch target instruction address addressing instruction memory 105, 105 provides the corresponding branch target instruction 112, 112 which is decoded by the instruction decoder 119. at this time 106 provides the first instruction address after the branch instruction, the address instruction buffer 108, 118 provides the branch instruction, and the first instruction 111, 111 is decoded by the instruction decoder 117.
  • Processor core 128 also generates a branch decision 110 to control the selector 116.
  • branch judgment 110 is 'no branch'
  • 116 selects the branch instruction and the first instruction 111 passes the instruction decoder 117.
  • the decoded result is provided to 128 for execution via bus 207.
  • the processor core 128 provides the address of the subsequent instruction such as the second instruction via the bus 106 via the bus 106, and addresses the instruction buffer 118.
  • the sequential instructions are decoded by the decoder 117, selected by the selector 116, and processed by the processor core 128 via the bus 207.
  • the selector 116 selects the branch target instruction 112 via the instruction decoder 119.
  • the decoded result is provided to 128 for execution via bus 207.
  • the instruction memory 105 provides the instruction line in which the branch target instruction is located, and stores it in the instruction buffer 118. Thereafter, the processor core 128 is routed through the bus.
  • 106 provides the address of the subsequent instruction such as the second instruction after the branch instruction, addresses the instruction buffer 118, and provides the sequential instruction to be decoded by the decoder 117; BTB101 The address of the first instruction after the branch target instruction is sent, the instruction memory 105 is addressed, and the first instruction is decoded by the decoder 119 after the branch instruction is provided.
  • the value on 110 is reserved as 'branch', and the selector is controlled.
  • the decoding result of the 116 select decoder 119 is sent to the processor core 128 via the bus 207 for processing. Thereafter, if the value on 110 is 'no branch', then control selector 116 selects from the instruction buffer. 118.
  • the instruction decoded by the instruction decoder 117 (in this case, the sequential instruction after the branch target instruction) is processed by the processor core.
  • Processor core 128 The pipeline in the middle is divided into a front-end pipeline and a back-end pipeline. The pipeline segment before the pipeline segment that determines the branch judgment is the front-end pipeline, and the pipeline segment starting from the branch judgment pipeline segment is called the back-end pipeline.
  • the end pipeline is executed.
  • 117 in Figure 5 is a front-end pipeline
  • 119 is another front-end pipeline
  • 128 It is the back-end pipeline
  • the functions of other modules are the same as above.
  • Branch Decisions Generated by Back-End Pipeline 128 110 Control Selector 116 Select Front-End Pipeline 117 or 119
  • the intermediate result of the output is sent to the back-end pipeline 128 for execution. If branch judgment 110 is 'no branch', then 116 selects the branch instruction and the first instruction and the second instruction 111 pass the front-end pipeline.
  • the intermediate result of 117 is provided to 128 for execution via bus 207.
  • branch decision 110 is 'branch' (two consecutive cycles)
  • selector 116 After the branch target instruction and the branch target are selected, the intermediate result of the first instruction 112 via the front-end pipeline 119 is supplied to the 128 for execution via the bus 207.
  • Simultaneous instruction memory 105 The instruction line where the branch target instruction is located is stored in the instruction buffer 118.
  • the processing method when BTB is missing in this embodiment is also the same as FIG. 4
  • the treatment in the examples is the same.
  • the embodiment is determined by the branch, and the cache organization method for controlling the execution of one of the two instruction decoding results generated by the two instruction decoders (or the front-end pipeline) for the processor core (or the back-end pipeline) is based on the graph. 4
  • Example of the cache organization mode of the embodiment. Can also be shown in Figure 2 and Figure 3.
  • Embodiment or other cache organization manner providing a first instruction after a branch instruction and a branch target instruction to two independent instruction decoders (or front-end pipelines), and selecting two decoding results (intermediate results) by branch judgment One is executed by the processor core (back-end pipeline).
  • BTB Stores the branch target instruction address and the address of the first instruction after the branch target instruction.
  • the processor core 106 provides an instruction that matches the branch instruction address stored in the BTB
  • BTB The branch target instruction is provided, and the address of the first instruction after the branch target instruction is also provided to address the second memory, and then the second memory 105 provides the first instruction after the branch instruction.
  • the sequential address addressing instruction reads the sequential instructions in buffer 118.
  • the branch decision 110 generated by the processor core controls the selector 116.
  • the branch target has one instruction for the processor core 108 to process, and also makes the address on 106 from BTB After the branch target instruction, the first instruction starts to increment as the subsequent address.
  • the increment can be the number of bytes of an instruction.
  • the instruction line output from the second memory 105 is also stored in the instruction buffer 118. For subsequent address reading.
  • 116 selects the instruction from the instruction buffer 118 for the processor core 108. Processing also causes the address on 106 to be incremented as a subsequent address. The increment can be the number of bytes of an instruction.
  • the functions, operations, and the like of the remaining modules are the same as those of the above-mentioned FIG. 4 and FIG. 5, and are not described again.
  • FIG. 3 to Figure 5 is a sequential instruction address provided by the processor core (or back-end pipeline) to address a memory to provide sequential instructions; by the branch target buffer (BTB) a matching sequence instruction that provides a branch target instruction address corresponding to a branch instruction address in the sequential instruction address to address a memory to provide a branch target instruction; a branch judgment selection order instruction generated by the processor core (or back-end pipeline) execution instruction or Branch target instructions are executed by the processor core (back-end pipeline).
  • Figure 2 shows the example by BTB The branch target instruction is directly provided, and the rest is the same as FIG. 3 to FIG. 5.

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Abstract

L'invention concerne un procédé de traitement de branche, applicable à un ordinateur/microprocesseur, qui est caractérisé en ce que : selon une adresse d'instruction fournie par un noyau de processeur, une instruction de séquence est fournie, un BTB mappe l'adresse d'instruction pour fournir une instruction cible de branchement, et une branche générée par le noyau de processeur sélectionne une des deux instructions pour être traitée par le noyau de processeur. En conséquence, il n'y a pas de perte de branche, et aucune prédiction de branche n'est utilisée, de telle sorte que la perte de performance d'un processeur due à des erreurs de prédiction de branche est éliminée.
PCT/CN2018/083053 2017-04-13 2018-04-13 Procédé et système de traitement de branchement WO2018188657A1 (fr)

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CN201710282065.3 2017-04-13

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102117198A (zh) * 2009-12-31 2011-07-06 上海芯豪微电子有限公司 一种分支处理方法
CN102662640A (zh) * 2012-04-12 2012-09-12 苏州睿云智芯微电子有限公司 双重分支目标缓冲器和分支目标处理系统及处理方法
CN102855121A (zh) * 2011-06-29 2013-01-02 上海芯豪微电子有限公司 分支处理方法与系统
CN103838550A (zh) * 2012-11-26 2014-06-04 上海芯豪微电子有限公司 一种分支处理系统和方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102117198A (zh) * 2009-12-31 2011-07-06 上海芯豪微电子有限公司 一种分支处理方法
CN102855121A (zh) * 2011-06-29 2013-01-02 上海芯豪微电子有限公司 分支处理方法与系统
CN102662640A (zh) * 2012-04-12 2012-09-12 苏州睿云智芯微电子有限公司 双重分支目标缓冲器和分支目标处理系统及处理方法
CN103838550A (zh) * 2012-11-26 2014-06-04 上海芯豪微电子有限公司 一种分支处理系统和方法

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