WO2018188657A1 - Branch processing method and system - Google Patents

Branch processing method and system Download PDF

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Publication number
WO2018188657A1
WO2018188657A1 PCT/CN2018/083053 CN2018083053W WO2018188657A1 WO 2018188657 A1 WO2018188657 A1 WO 2018188657A1 CN 2018083053 W CN2018083053 W CN 2018083053W WO 2018188657 A1 WO2018188657 A1 WO 2018188657A1
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Prior art keywords
branch
instruction
address
processor core
storage device
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PCT/CN2018/083053
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French (fr)
Chinese (zh)
Inventor
林正浩
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上海芯豪微电子有限公司
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Publication of WO2018188657A1 publication Critical patent/WO2018188657A1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead

Definitions

  • the present invention relates to the field of electronic computers and microprocessors.
  • Control related Hazards also known as branches
  • Current mainstream microprocessors use branch prediction (branch Prediction) way to eliminate branch loss.
  • 1 is an embodiment of a conventional microprocessor processing condition branching mode.
  • 101 is the branch target buffer (Branch Target Buffer , BTB)
  • 105 is the instruction cache
  • 108 is the processor core.
  • a typical BTB stores the branch instruction address and the corresponding branch target instruction address, as well as its branch prediction.
  • BTB The complex branch instruction address stored in 101 is compared to the instruction address 106 generated by 108. If there is a match, the control signal 103 is output according to the branch prediction 102 stored in the matched BTB line. To control the selector 104.
  • 104 selects the branch target address in the BTB match row to be supplied to 105. If there is no match, or there is a match but the branch is predicted not to branch, 104 select The sequential address on 106 is provided to 105.
  • the instruction cache 105 provides branch targets or sequential instructions to the processor core via the bus 107 based on the branch target or sequential address. carried out. This eliminates the loss of the branch.
  • branch predictions have unpredictable prediction errors.
  • branch instructions to generate branch decisions (branch The decision is not the same as the branch prediction, and the processing result of each pipeline segment before the pipeline segment in which the branch judgment is generated in the processor pipeline must be cleared, and a selected instruction from the branch judgment is re-executed, resulting in performance loss.
  • the present invention is directed to the deficiencies of the prior art, and proposes a branch processing method and system, which is characterized in that the branch target and the sequential two instructions are determined by the branch generated by the processor core to select an instruction for the processor core to execute, so there is no branch. Loss; branch prediction is not used, so processor performance loss due to branch prediction errors is completely ruled out.
  • an instruction address is provided by a processor core that provides a sequential instruction that is also compared to a branch instruction address stored in the BTB.
  • the branch target instruction is directly provided by the BTB based on the matching result.
  • the BTB provides a branch target instruction address according to the matching result, the branch target instruction address addresses the storage device, and the branch destination address is provided by the storage device.
  • the branch generated by the processor core determines the select order instruction or the branch target instruction for execution by the processor core.
  • the branch decision is decoded by the branch instruction.
  • the branch decision is generated by the branch instruction decoding in conjunction with the execution of the branch instruction or the result of the previous instruction.
  • the invention eliminates the performance loss caused by the branch prediction, and saves the chip area occupied by the branch prediction device and the power consumption consumed.
  • Figure 1 is an embodiment of a conventional branch processing branch.
  • FIG. 3 is another embodiment of the branching processing branch of the present invention.
  • Fig. 4 is another embodiment of the branching processing branch of the present invention.
  • Figure 5 is another embodiment of the branching processing branch of the present invention.
  • Figure 4 is a preferred embodiment of the invention.
  • 115 is the branch instruction address / The BTB of the branch target instruction pair
  • 105 is the instruction memory (memory)
  • 116 is the selector
  • 108 is the processor core.
  • Processor core 108 generates branch decisions 110 To control the selector 116.
  • 108 Generate instruction address 106 .
  • 106 Addressing Instruction Memory 105, 105 provides sequential instructions 111.
  • 106 also with BTB 115 Branch instruction address comparison stored in . If a branch instruction address in 115 matches the instruction address 106, the BTB 115 provides a branch target instruction corresponding to the branch instruction address. .
  • the address (sequential address) of the first instruction after the branch instruction is sent is sent by the address instruction memory 105, 105 via the bus 111 to the first instruction after the branch instruction is provided. If BTB115 The branch instruction address matches the branch instruction address in 106, and the BTB115 outputs the branch target instruction via the bus 112. So the two inputs 112 and 111 of the selector 116 There is a branch target instruction, and the first instruction (fall-through instruction) after the branch instruction waits for the selection of the branch judgment 110 generated by the processor core.
  • 116 selects the branch instruction and the first instruction 111 passes through the bus 107.
  • 106 continues to provide subsequent sequential addresses (in this case, the addresses of the two instructions after the branch instruction), and the addressing instruction memories 105, 105 provide sequential instructions.
  • the 116 select branch target instruction 112 is provided to bus 108 via bus 107. carried out.
  • the processor core 108 simultaneously computes the address of the first instruction (sequential instruction) after the branch instruction while executing the branch instruction.
  • 106 provides the address of the first instruction after the branch target instruction, addressing the instruction memory 105 , 105 provides the first instruction after the branch target instruction. Thereafter, 106 provides the sequential instruction address after the branch target instruction (in this case, the two instruction addresses after the branch target), and the instruction memory 105 is addressed. Provides subsequent instructions for the branch target instruction.
  • the present invention simultaneously provides two instructions of a branch to the processor core, and selects by branch judgment to implement the lossless branch.
  • the invention does not rely on branch prediction, and avoids losses caused by branch prediction ( Mis-prediction penalty ).
  • processor 108 When the processor 108 decodes the instruction sent via 107, it finds that the instruction is a branch instruction, and the corresponding branch instruction address is in BTB. The case where no match is found in 115 is BTB missing.
  • control selector 116 selects sequence instruction 111 for processor core 108 carried out.
  • processor 108 sends the branch target instruction address via instruction address 106 to address instruction memory 105.
  • 105 by 111 provides a branch target instruction, at which point selector 116 selects 111 to send to processor core 108 for execution. And establish the branch instruction address in BTB 115 / Branch target instruction pair. Thereafter, processor 108 sends a subsequent address of the branch target address via instruction address 106, and address instruction memory 105 provides instructions to 108.
  • the processor core 108 provides the instruction address 106. Is the sequential instruction address (including the branch instruction address).
  • the instruction address 106 when the branch decision 110 is 'branch' and the BTB 115 matches the hit.
  • the address of the subsequent instruction that is the branch target instruction.
  • the sequential instruction address is the number of bytes added by the previous instruction address plus one instruction.
  • Figure 3 is another embodiment of the branching processing branch of the present invention.
  • 101 is the storage branch instruction address / The branch target instruction address pair (pair) BTB
  • 125 is the instruction memory with two read ports
  • 116 is the selector
  • 108 is the processor core.
  • 108 Generate Instruction Address 106
  • 106 Addresses the first read port of instruction memory 125, which provides sequential instructions 111.
  • 106 also with 101 Branch instruction address comparison in .
  • BTB 101 Provide the corresponding branch target instruction address.
  • the branch target instruction address addresses the second read port of the instruction memory 125 via which the corresponding branch target instruction 112 is provided.
  • Processor core 108 also produces branch decisions 110 To control the selector 116. If the value of 110 is 'no branch', then 116 selects the branch instruction and the first instruction 111 is provided to 108 for execution via bus 107. Such as 110 The value is 'branch', then the 116 select branch target instruction 112 is provided to 108 for execution via bus 107.
  • the instruction address 106 and the branch judgment 110 are generated in this embodiment and FIG. 2
  • the manner of production in the examples is the same.
  • the processing method in the case where the BTB is missing in this embodiment is also the same as that in the embodiment of Fig. 2.
  • Fig. 4 is another embodiment of the branching processing branch of the present invention.
  • 101 is the storage branch instruction address / BTB of the branch target instruction address pair
  • 105 is the instruction memory
  • 118 is the instruction buffer
  • 204 and 116 are selectors
  • 113 is the adder.
  • 108 is the processor core.
  • the instruction buffer 118 is a memory with read and write control and address addressing. Due to the instruction buffer 118 Only sequential instructions are provided, the stored instruction address space is contiguous, in a small range, so 118 capacity can be small, such as only accommodating one instruction line or instruction block to meet the requirements of the present invention.
  • Instruction memory 105 is another discrete memory that is addressed by additional read and write control and address. 105 responsible for providing branch target instructions, which require a larger address space and therefore require a larger storage capacity than 118. The branch instruction address and its corresponding branch target instruction pair are stored in the BTB101. Processor core 108 The instruction address 106, 106 is addressed to address the instruction buffers 118, 118 to provide sequential instructions over the bus 111. 106 also with 101 Branch instruction address comparison stored in .
  • BTB 101 A branch target instruction address corresponding to the branch instruction address is provided, and the selector 204 is also controlled to select the branch target instruction address provided by the BTB101.
  • the branch target instruction address addresses the instruction memory 105, 105
  • the corresponding branch target instruction is provided via bus 112.
  • 106 provides the first instruction address after the branch instruction, and addresses the instruction buffer 118, 118 through the bus 111. Provide the first instruction after the branch instruction.
  • Processor core 108 also generates branch decisions 110 to control selector 116.
  • the value of 110 is 'no branch', then 116 selects the branch instruction on bus 111 and the first instruction passes bus 107. Provided to processor core 108 for execution. Thereafter, the address on 106 is the address of the second instruction after the branch instruction, and the control instruction buffer 118 Provide the second instruction after the branch instruction. If the first instruction after the branch instruction is not a branch instruction, the value of the branch decision 110 at this time is 'no branch', and the control selector 116 selects 118. The second instruction is provided by the processor core 108 after the branch instruction is provided. Subsequent instructions of the branch instruction in the instruction buffer are executed in this order.
  • the 116 branch target instruction on bus 112 is provided to bus 108 via bus 107. carried out.
  • the instruction memory 105 provides the instruction line in which the branch target instruction is located, and stores it in the instruction buffer 118.
  • the address on 106 is the address of the first instruction after the branch target instruction
  • the control instruction buffer 118 Provides the first instruction after the branch target instruction. If the branch target instruction itself is not a branch instruction, the value of the branch decision 110 at this time is 'no branch', and the control selector 116 selects 118.
  • the first instruction after the provided branch target instruction is executed by the processor core 108. Subsequent instructions of the branch target instruction in the instruction buffer 118 are executed in this order.
  • selector 204 selects the bus.
  • the address on 106 because the value of the branch decision 110 is 'branch', but the BTB does not match, the processor core 108 generates a bus 106.
  • the address sent is the branch target instruction address.
  • the branch target instruction address addressing instruction memory 105 provides the instruction line in which the branch target instruction is located via bus 112.
  • Branch judgment control selector 116 with value of 'branch' The branch target instruction on select bus 112 is executed by bus 107 for processor core 108.
  • the instruction line on 112 is stored in the instruction buffer 118. Will also branch instruction address / The branch target instruction address pair is stored in BTB101 for later use.
  • the processor core 108 generates the address of the first instruction after the branch target instruction is sent via the bus 106, and reads 118.
  • the middle instruction by which the time value is 'no branch', is judged by the selector 116 selected for processing by the processor core 108.
  • the instruction buffer is executed in this order. Subsequent instructions for branch target instructions in .
  • Adder 113 will be the instruction address 106
  • the row address portion of the upper address plus the number of bytes in the instruction line gives the row address of the next row in sequence.
  • the intra-block offset address in the instruction address points to the last instruction of the instruction buffer 118, make 118
  • the selector 204 selects the address of the next row in the order of the output of the adder 113 to address the instruction memory 105.
  • the next line of instructions is provided for storage in the instruction buffer 118.
  • instruction address 106 addressing 118 provides processor core 108 with instructions for the next row in sequence for execution.
  • the instruction address 106 and the branch determination 110 are generated in the same manner as in the embodiment of Fig. 2 in this embodiment. Occurred in this embodiment
  • the processing when BTB is missing is also similar to the processing in the embodiment of Figure 2.
  • the branch target instruction address on the address bus 106 output by the processor core at this time passes through the selector 204. Addressing the instruction memory 105.
  • the selector 116 is still controlled by the branch decision 110 to select the branch target instruction provided by the instruction memory 105. That is, the selector 116 is judged by the branch at any time. 110 control.
  • a typical processor core pipeline has five pipeline segments, fetch ( I ), decode ( D ), execute (E), and fetch ( M ), and write back the segment (W).
  • Branch judgments can usually be generated in either D or E segments. The above three embodiments are based on branch judgment in D The hypothesis generated by the segment, or the branch judgment is generated early enough, one of the two instructions after the branch instruction can be selected for processing by the processor core.
  • processor core 108 The sequential address is generated, and the address of an instruction after the branch instruction is generated after the branch instruction address is generated. Thereafter, if the value judged by the branch is 'no branch', then 108 The address of the second instruction after the branch instruction is generated. If the value judged by the branch is 'branch', then 108 the address of the first instruction after the branch target instruction is generated.
  • Figure 5 is another embodiment of the branching processing branch of the present invention.
  • Figure 5 is the branch judgment in E The embodiment generated by the segment, or the branch judgment is not generated enough, and after the partial processing of both instructions is required, the branch judges to select one of the two partial processing results for further processing by the processor core.
  • 101 is a BTB storing a branch instruction address/branch target instruction address pair
  • 105 is an instruction memory
  • 118 is the instruction buffer (buffer)
  • 113 is the adder
  • 204 and 116 are the selectors
  • 117 and 119 are the instruction decoders
  • 128 Is a processor core without an instruction decoder. 128 generating an instruction address is output via bus 106, and an instruction address on bus 106 addresses instruction buffer 118, 118 provides sequential instruction 111, 111 is decoded by the instruction decoder 117.
  • the branch decision 110 with a value of 'no branch' selects the instruction decode result of 117 for execution by processor core 128.
  • the instruction address sequence on bus 106 points to the next instruction, and control instruction buffer 118 sends the corresponding instruction to decoder 117 Decoding. If the branch instruction address in BTB 101 matches the instruction address on bus 106, BTB101 The address of the first instruction after the branch target instruction is sent in the next cycle, except for the corresponding branch target instruction address when the match is sent.
  • the control causes the bus 106 The upper address is the subsequent address of one of the above two addresses. Specifically, when the branch judgment value is 'no branch', the bus 106 The upper instruction address is the address of the third instruction after the branch instruction; when the branch judgment value is 'branch', the instruction address on the bus 106 is the address of the second instruction after the branch target instruction. Control the branch of the selector 116 to determine the bus 110 then keeps the value of the 'branch' for one cycle when its value is 'branch'. The value at 110 is then determined by the new branch.
  • the address on bus 106 is also compared to the address of the stored branch instruction in 101. If a branch instruction address and instruction address in 101 106 match, then BTB 101 provides the corresponding branch target instruction address, and also controls selector 204 to select BTB101 The branch target instruction address provided.
  • the branch target instruction address addressing instruction memory 105, 105 provides the corresponding branch target instruction 112, 112 which is decoded by the instruction decoder 119. at this time 106 provides the first instruction address after the branch instruction, the address instruction buffer 108, 118 provides the branch instruction, and the first instruction 111, 111 is decoded by the instruction decoder 117.
  • Processor core 128 also generates a branch decision 110 to control the selector 116.
  • branch judgment 110 is 'no branch'
  • 116 selects the branch instruction and the first instruction 111 passes the instruction decoder 117.
  • the decoded result is provided to 128 for execution via bus 207.
  • the processor core 128 provides the address of the subsequent instruction such as the second instruction via the bus 106 via the bus 106, and addresses the instruction buffer 118.
  • the sequential instructions are decoded by the decoder 117, selected by the selector 116, and processed by the processor core 128 via the bus 207.
  • the selector 116 selects the branch target instruction 112 via the instruction decoder 119.
  • the decoded result is provided to 128 for execution via bus 207.
  • the instruction memory 105 provides the instruction line in which the branch target instruction is located, and stores it in the instruction buffer 118. Thereafter, the processor core 128 is routed through the bus.
  • 106 provides the address of the subsequent instruction such as the second instruction after the branch instruction, addresses the instruction buffer 118, and provides the sequential instruction to be decoded by the decoder 117; BTB101 The address of the first instruction after the branch target instruction is sent, the instruction memory 105 is addressed, and the first instruction is decoded by the decoder 119 after the branch instruction is provided.
  • the value on 110 is reserved as 'branch', and the selector is controlled.
  • the decoding result of the 116 select decoder 119 is sent to the processor core 128 via the bus 207 for processing. Thereafter, if the value on 110 is 'no branch', then control selector 116 selects from the instruction buffer. 118.
  • the instruction decoded by the instruction decoder 117 (in this case, the sequential instruction after the branch target instruction) is processed by the processor core.
  • Processor core 128 The pipeline in the middle is divided into a front-end pipeline and a back-end pipeline. The pipeline segment before the pipeline segment that determines the branch judgment is the front-end pipeline, and the pipeline segment starting from the branch judgment pipeline segment is called the back-end pipeline.
  • the end pipeline is executed.
  • 117 in Figure 5 is a front-end pipeline
  • 119 is another front-end pipeline
  • 128 It is the back-end pipeline
  • the functions of other modules are the same as above.
  • Branch Decisions Generated by Back-End Pipeline 128 110 Control Selector 116 Select Front-End Pipeline 117 or 119
  • the intermediate result of the output is sent to the back-end pipeline 128 for execution. If branch judgment 110 is 'no branch', then 116 selects the branch instruction and the first instruction and the second instruction 111 pass the front-end pipeline.
  • the intermediate result of 117 is provided to 128 for execution via bus 207.
  • branch decision 110 is 'branch' (two consecutive cycles)
  • selector 116 After the branch target instruction and the branch target are selected, the intermediate result of the first instruction 112 via the front-end pipeline 119 is supplied to the 128 for execution via the bus 207.
  • Simultaneous instruction memory 105 The instruction line where the branch target instruction is located is stored in the instruction buffer 118.
  • the processing method when BTB is missing in this embodiment is also the same as FIG. 4
  • the treatment in the examples is the same.
  • the embodiment is determined by the branch, and the cache organization method for controlling the execution of one of the two instruction decoding results generated by the two instruction decoders (or the front-end pipeline) for the processor core (or the back-end pipeline) is based on the graph. 4
  • Example of the cache organization mode of the embodiment. Can also be shown in Figure 2 and Figure 3.
  • Embodiment or other cache organization manner providing a first instruction after a branch instruction and a branch target instruction to two independent instruction decoders (or front-end pipelines), and selecting two decoding results (intermediate results) by branch judgment One is executed by the processor core (back-end pipeline).
  • BTB Stores the branch target instruction address and the address of the first instruction after the branch target instruction.
  • the processor core 106 provides an instruction that matches the branch instruction address stored in the BTB
  • BTB The branch target instruction is provided, and the address of the first instruction after the branch target instruction is also provided to address the second memory, and then the second memory 105 provides the first instruction after the branch instruction.
  • the sequential address addressing instruction reads the sequential instructions in buffer 118.
  • the branch decision 110 generated by the processor core controls the selector 116.
  • the branch target has one instruction for the processor core 108 to process, and also makes the address on 106 from BTB After the branch target instruction, the first instruction starts to increment as the subsequent address.
  • the increment can be the number of bytes of an instruction.
  • the instruction line output from the second memory 105 is also stored in the instruction buffer 118. For subsequent address reading.
  • 116 selects the instruction from the instruction buffer 118 for the processor core 108. Processing also causes the address on 106 to be incremented as a subsequent address. The increment can be the number of bytes of an instruction.
  • the functions, operations, and the like of the remaining modules are the same as those of the above-mentioned FIG. 4 and FIG. 5, and are not described again.
  • FIG. 3 to Figure 5 is a sequential instruction address provided by the processor core (or back-end pipeline) to address a memory to provide sequential instructions; by the branch target buffer (BTB) a matching sequence instruction that provides a branch target instruction address corresponding to a branch instruction address in the sequential instruction address to address a memory to provide a branch target instruction; a branch judgment selection order instruction generated by the processor core (or back-end pipeline) execution instruction or Branch target instructions are executed by the processor core (back-end pipeline).
  • Figure 2 shows the example by BTB The branch target instruction is directly provided, and the rest is the same as FIG. 3 to FIG. 5.

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Abstract

A branch processing method, applicable to a computer/microprocessor, is characterized in that: according to an instruction address provided by a processor kernel, a sequence instruction is provided, a BTB maps the instruction address to provide a branch target instruction, and a branch generated by the processor kernel selects one of the two instructions for being processed by the processor kernel. Accordingly, there is no branch loss, and no branch prediction is used, so that the performance loss of a processor due to branch prediction errors is eliminated.

Description

一种分支处理方法与系统  Branch processing method and system 技术领域Technical field
本发明涉及电子计算机和微处理器领域。  The present invention relates to the field of electronic computers and microprocessors.
背景技术Background technique
控制相关(control hazards)也称为分支（Branch），是处理器流水线性能损失的一大原因。当前的主流微处理器使用分支预测（branch prediction）的方式以消除分支损失。图1是现有微处理器处理条件分支方式的实施例。其中101是 分支目标缓冲器 (Branch Target Buffer ， BTB) ， 105 是指令缓存， 108 是处理器核。典型的 BTB 中存储分支指令地址与相应的分支目标指令地址，以及其分支预测。 BTB 101 中存储的复数条分支指令地址与 108 产生的指令地址 106 相比较。如有匹配，根据匹配的 BTB 行中存储的分支预测 102 ，输出控制信号 103 以控制选择器 104 。如分支预测为分支， 104 选择 BTB 匹配行中的分支目标地址向 105 提供。如无匹配，或有匹配但分支预测为不分支， 104 选择 106 上的顺序地址向 105 提供。指令缓存 105 根据分支目标或顺序地址经总线 107 提供分支目标或顺序指令供处理器核 108 执行。如此消除了分支的损失。 Control related Hazards, also known as branches, is a major cause of processor pipeline performance loss. Current mainstream microprocessors use branch prediction (branch Prediction) way to eliminate branch loss. 1 is an embodiment of a conventional microprocessor processing condition branching mode. Where 101 is the branch target buffer (Branch Target Buffer , BTB) , 105 is the instruction cache, and 108 is the processor core. A typical BTB stores the branch instruction address and the corresponding branch target instruction address, as well as its branch prediction. BTB The complex branch instruction address stored in 101 is compared to the instruction address 106 generated by 108. If there is a match, the control signal 103 is output according to the branch prediction 102 stored in the matched BTB line. To control the selector 104. If the branch is predicted to be a branch, 104 selects the branch target address in the BTB match row to be supplied to 105. If there is no match, or there is a match but the branch is predicted not to branch, 104 select The sequential address on 106 is provided to 105. The instruction cache 105 provides branch targets or sequential instructions to the processor core via the bus 107 based on the branch target or sequential address. carried out. This eliminates the loss of the branch.
技术问题 technical problem
但分支预测有无法避免的预测错误。如处理器核执行分支指令产生的分支判断（branch decision）与分支预测不相同，则必须清除处理器流水线中产生分支判断的流水线段之前各流水线段的处理结果，从分支判断选择的一支指令开始重新执行，导致性能损失。 But branch predictions have unpredictable prediction errors. As the processor core executes branch instructions to generate branch decisions (branch The decision is not the same as the branch prediction, and the processing result of each pipeline segment before the pipeline segment in which the branch judgment is generated in the processor pipeline must be cleared, and a selected instruction from the branch judgment is re-executed, resulting in performance loss.
技术解决方案Technical solution
本发明针对现有技术的不足，提出一种分支处理方法与系统，其特征是提供分支目标及顺序两支指令由处理器核产生的分支判断选择一支指令供处理器核执行，因此没有分支损失；也不使用分支预测，因此完全排除了分支预测错误导致的处理器性能损失。 The present invention is directed to the deficiencies of the prior art, and proposes a branch processing method and system, which is characterized in that the branch target and the sequential two instructions are determined by the branch generated by the processor core to select an instruction for the processor core to execute, so there is no branch. Loss; branch prediction is not used, so processor performance loss due to branch prediction errors is completely ruled out.
本发明中由处理器核提供指令地址，该指令地址寻址存储装置提供顺序指令，该指令地址也与BTB中存储的分支指令地址比较。由BTB根据匹配结果直接提供分支目标指令。或由BTB根据匹配结果提供分支目标指令地址，该分支目标指令地址寻址存储装置，由存储装置提供分支目标地址。处理器核产生的分支判断选择顺序指令或分支目标指令供处理器核执行。当执行无条件分支指令时，分支判断经分支指令译码生成。当执行条件分支指令时，分支判断经分支指令译码结合执行分支指令或之前指令产生的结果生成。 In the present invention, an instruction address is provided by a processor core that provides a sequential instruction that is also compared to a branch instruction address stored in the BTB. The branch target instruction is directly provided by the BTB based on the matching result. Or the BTB provides a branch target instruction address according to the matching result, the branch target instruction address addresses the storage device, and the branch destination address is provided by the storage device. The branch generated by the processor core determines the select order instruction or the branch target instruction for execution by the processor core. When an unconditional branch instruction is executed, the branch decision is decoded by the branch instruction. When a conditional branch instruction is executed, the branch decision is generated by the branch instruction decoding in conjunction with the execution of the branch instruction or the result of the previous instruction.
有益效果Beneficial effect
本发明消除了分支预测导致的性能损失，节省了分支预测装置所占据的芯片面积与消耗的功耗。  The invention eliminates the performance loss caused by the branch prediction, and saves the chip area occupied by the branch prediction device and the power consumption consumed.
附图说明DRAWINGS
虽然该发明可以以多种形式的修改和替换来扩展，说明书中也列出了一些具体的实施图例并进行详细阐述。应当理解的是，发明者的出发点不是将该发明限于所阐述的 特定实施例，正相反，发明者的出发点在于保护所有基于由本权利声明定义的精神或范围内进行的改进、等效转换和修改。 Although the invention may be modified in various forms of modifications and substitutions, some specific embodiments of the invention are set forth in the specification and detailed. It should be understood that the inventor's starting point is not to limit the invention to the stated The specific embodiments, on the contrary, the inventor's starting point is to protect all modifications, equivalent transformations and modifications made within the spirit or scope defined by the claims.
图 1 是现有以分支预测处理分支的实施例 。 Figure 1 is an embodiment of a conventional branch processing branch.
图 2 是本发明所述以分支判断处理分支的实施例。 2 is an embodiment of the branching processing processing branch of the present invention.
图 3 是本发明所述以分支判断处理分支的另一个实施例。 Figure 3 is another embodiment of the branching processing branch of the present invention.
图 4 是本发明所述以分支判断处理分支的另一个实施例。 Fig. 4 is another embodiment of the branching processing branch of the present invention.
图 5 是本发明所述以分支判断处理分支的另一个实施例。 Figure 5 is another embodiment of the branching processing branch of the present invention.
本发明的最佳实施方式BEST MODE FOR CARRYING OUT THE INVENTION
图 4 是本发明的最佳实施例。  Figure 4 is a preferred embodiment of the invention.
本发明的实施方式Embodiments of the invention
图 2 是本发明所述以分支判断处理分支的实施例。此实施例中， 115 是存储分支指令地址 / 分支目标指令对的 BTB ， 105 是指令存储器（ memory ）， 116 是选择器， 108 是处理器核。处理器核 108 产生分支判断 110 以控制选择器 116 。 108 产生指令地址 106 。 106 寻址指令存储器 105 ， 105 提供顺序指令 111 。 106 也与 BTB 115 中存储的分支指令地址比较。如果 115 中的一个分支指令地址与指令地址 106 匹配，则 BTB 115 提供与该分支指令地址相应的分支目标指令 112 。 2 is an embodiment of the branching processing processing branch of the present invention. In this embodiment, 115 is the branch instruction address / The BTB of the branch target instruction pair, 105 is the instruction memory (memory), 116 is the selector, and 108 is the processor core. Processor core 108 generates branch decisions 110 To control the selector 116. 108 Generate instruction address 106 . 106 Addressing Instruction Memory 105, 105 provides sequential instructions 111. 106 also with BTB 115 Branch instruction address comparison stored in . If a branch instruction address in 115 matches the instruction address 106, the BTB 115 provides a branch target instruction corresponding to the branch instruction address. .
在送出分支指令的地址后， 108 经指令地址 106 送出分支指令后第一条指令的地址（顺序地址）以寻址指令存储器 105 ， 105 经总线 111 送出提供分支指令后第一条指令。如果 BTB115 中有分支指令地址与 106 上分支指令地址匹配，此时 BTB115 经总线 112 输出分支目标指令。因此选择器 116 的两个输入 112 及 111 上有分支目标指令，及分支指令后第一条指令（ fall-through 指令），等待处理器核产生的分支判断 110 的选择。 After the address of the branch instruction is sent, 108 is passed through the instruction address 106. The address (sequential address) of the first instruction after the branch instruction is sent is sent by the address instruction memory 105, 105 via the bus 111 to the first instruction after the branch instruction is provided. If BTB115 The branch instruction address matches the branch instruction address in 106, and the BTB115 outputs the branch target instruction via the bus 112. So the two inputs 112 and 111 of the selector 116 There is a branch target instruction, and the first instruction (fall-through instruction) after the branch instruction waits for the selection of the branch judgment 110 generated by the processor core.
当分支判断 110 值为'不分支'时， 116 选择分支指令后第一条指令 111 经总线 107 提供给 108 执行。 106 继续提供后续顺序地址 ( 此时为分支指令后两条指令的地址 ) ，寻址指令存储器 105 ， 105 提供顺序指令。 When the branch judges that the value of 110 is 'no branch', 116 selects the branch instruction and the first instruction 111 passes through the bus 107. Provided to 108 for execution. 106 continues to provide subsequent sequential addresses (in this case, the addresses of the two instructions after the branch instruction), and the addressing instruction memories 105, 105 provide sequential instructions.
当分支判断 110 值为'分支'时， 116 选择分支目标指令 112 经总线 107 提供给 108 执行。处理器核 108 在执行分支指令时同时计算分支指令后第一条指令（顺序指令）的地址。 106 提供分支目标指令后第一条指令的地址，寻址指令存储器 105 ， 105 提供分支目标指令后第一条指令。之后， 106 提供分支目标指令后的顺序指令地址（此时为分支目标后两条指令地址），寻址指令存储器 105 提供分支目标指令的后续指令。 When the branch determines 110 that the value is 'branch', the 116 select branch target instruction 112 is provided to bus 108 via bus 107. carried out. The processor core 108 simultaneously computes the address of the first instruction (sequential instruction) after the branch instruction while executing the branch instruction. 106 provides the address of the first instruction after the branch target instruction, addressing the instruction memory 105 , 105 provides the first instruction after the branch target instruction. Thereafter, 106 provides the sequential instruction address after the branch target instruction (in this case, the two instruction addresses after the branch target), and the instruction memory 105 is addressed. Provides subsequent instructions for the branch target instruction.
如此，本发明同时向处理器核提供一个分支的两支指令，以分支判断做选择，实现无损分支。本发明不依靠分支预测，避免了分支预测带来的损失（ mis-prediction penalty ）。 In this way, the present invention simultaneously provides two instructions of a branch to the processor core, and selects by branch judgment to implement the lossless branch. The invention does not rely on branch prediction, and avoids losses caused by branch prediction ( Mis-prediction penalty ).
当处理器 108 译码经 107 送入的指令发现该指令是分支指令，而相应的分支指令地址在 BTB 115 中未获得匹配的情形为 BTB 缺失。 BTB 缺失时如分支判断 110 为'不分支'，则控制选择器 116 选择顺序指令 111 供处理器核 108 执行。 BTB 缺失时如分支判断 110 为'分支'，则处理器 108 经指令地址 106 送出分支目标指令地址以寻址指令存储器 105 。 105 经 111 提供分支目标指令，此时选择器 116 要选择 111 送往处理器核 108 执行。并且在 BTB 115 中建立该分支指令地址 / 分支目标指令对。之后，处理器 108 经指令地址 106 送出分支目标地址的后续地址，寻址指令存储器 105 向 108 提供指令。 When the processor 108 decodes the instruction sent via 107, it finds that the instruction is a branch instruction, and the corresponding branch instruction address is in BTB. The case where no match is found in 115 is BTB missing. When BTB is missing, if branch decision 110 is 'no branch', control selector 116 selects sequence instruction 111 for processor core 108 carried out. When BTB is missing, if branch decision 110 is 'branch', then processor 108 sends the branch target instruction address via instruction address 106 to address instruction memory 105. 105 by 111 provides a branch target instruction, at which point selector 116 selects 111 to send to processor core 108 for execution. And establish the branch instruction address in BTB 115 / Branch target instruction pair. Thereafter, processor 108 sends a subsequent address of the branch target address via instruction address 106, and address instruction memory 105 provides instructions to 108.
也就是说，当分支判断 110 为'不分支'时，处理器核 108 提供的指令地址 106 为顺序指令地址（包括分支指令地址）。当分支判断 110 为'分支'且 BTB115 匹配命中时，所述指令地址 106 为分支目标指令的后续指令的地址。当分支判断 110 为'分支'且 BTB 匹配不命中时，所述指令地址 106 为分支目标指令的地址。这里顺序指令地址是由前一指令地址加一条指令的字节数。当指令译码为非分支指令，或是条件分支指令但分支条件不满足时，分支判断为'不分支'。当指令译码为无条件分支指令，或是条件分支指令且分支条件满足时，分支判断为'分支'。 That is, when the branch decision 110 is 'no branch', the processor core 108 provides the instruction address 106. Is the sequential instruction address (including the branch instruction address). The instruction address 106 when the branch decision 110 is 'branch' and the BTB 115 matches the hit. The address of the subsequent instruction that is the branch target instruction. The instruction address 106 when the branch decision 110 is 'branch' and the BTB match misses The address of the instruction for the branch target. Here, the sequential instruction address is the number of bytes added by the previous instruction address plus one instruction. When the instruction is decoded as a non-branch instruction, or a conditional branch instruction but the branch condition is not satisfied, the branch is judged as 'no branch'. When the instruction is decoded as an unconditional branch instruction, or a conditional branch instruction and the branch condition is satisfied, the branch is judged as 'branch'.
图 3 是本发明所述以分支判断处理分支的另一个实施例。此实施例中， 101 是存储分支指令地址 / 分支目标指令地址对（ pair ）的 BTB ， 125 是具有两个读口（ read port ）的指令存储器， 116 是选择器， 108 是处理器核。 108 产生指令地址 106 ， 106 寻址指令存储器 125 的第一个读口，该第一读口提供顺序指令 111 。 106 也与 101 中的分支指令地址比较。 Figure 3 is another embodiment of the branching processing branch of the present invention. In this embodiment, 101 is the storage branch instruction address / The branch target instruction address pair (pair) BTB, 125 is the instruction memory with two read ports, 116 is the selector, and 108 is the processor core. 108 Generate Instruction Address 106, 106 Addresses the first read port of instruction memory 125, which provides sequential instructions 111. 106 also with 101 Branch instruction address comparison in .
如果 101 中的一个分支指令地址与指令地址 106 匹配，则 BTB 101 提供相应的分支目标指令地址。该分支目标指令地址寻址指令存储器 125 的第二个读口，经该第二读口提供相应的分支目标指令 112 。此时 106 提供分支指令后第一条指令的地址，寻址指令存储器 125 的第一读口，该第一读口提供分支指令后第一条指令 111 。处理器核 108 也产生分支判断 110 以控制选择器 116 。如 110 的值为'不分支'，则 116 选择分支指令后第一条指令 111 经总线 107 提供给 108 执行。如 110 值为'分支'，则 116 选择分支目标指令 112 经总线 107 提供给 108 执行。 If a branch instruction address in 101 matches the instruction address 106, then BTB 101 Provide the corresponding branch target instruction address. The branch target instruction address addresses the second read port of the instruction memory 125 via which the corresponding branch target instruction 112 is provided. At this time 106 The address of the first instruction after the branch instruction is provided, and the first read port of the instruction memory 125 is addressed, and the first read port provides the first instruction 111 after the branch instruction. Processor core 108 also produces branch decisions 110 To control the selector 116. If the value of 110 is 'no branch', then 116 selects the branch instruction and the first instruction 111 is provided to 108 for execution via bus 107. Such as 110 The value is 'branch', then the 116 select branch target instruction 112 is provided to 108 for execution via bus 107.
本实施例中指令地址 106 以及分支判断 110 的产生方式与图 2 实施例中产生方式相同。本实施例中发生 BTB 缺失时的处理方式也与图 2 实施例中处理方式相同。 The instruction address 106 and the branch judgment 110 are generated in this embodiment and FIG. 2 The manner of production in the examples is the same. The processing method in the case where the BTB is missing in this embodiment is also the same as that in the embodiment of Fig. 2.
图 4 是本发明所述以分支判断处理分支的另一个实施例。此实施例中， 101 是存储分支指令地址 / 分支目标指令地址对的 BTB ， 105 是指令存储器， 118 是指令缓冲器 (buffer) ， 204 与 116 是选择器， 113 是加法器， 108 是处理器核。指令缓冲器 118 是一个存储器，有读写控制及地址寻址。由于指令缓冲器 118 仅提供顺序指令，其存储的指令地址空间连续，在一个较小的范围中，因此 118 容量可以较小，比如仅容纳一个指令行或指令块已可满足本发明的要求。 Fig. 4 is another embodiment of the branching processing branch of the present invention. In this embodiment, 101 is the storage branch instruction address / BTB of the branch target instruction address pair, 105 is the instruction memory, 118 is the instruction buffer, 204 and 116 are selectors, and 113 is the adder. 108 is the processor core. The instruction buffer 118 is a memory with read and write control and address addressing. Due to the instruction buffer 118 Only sequential instructions are provided, the stored instruction address space is contiguous, in a small range, so 118 capacity can be small, such as only accommodating one instruction line or instruction block to meet the requirements of the present invention.
指令存储器 105 是另一个分立的存储器，由另外的读写控制及地址寻址。 105 负责提供分支目标指令，其地址空间要求较大，因此需要较 118 更大的存储容量。 BTB101 中存储分支指令地址及其相应的分支目标指令对。处理器核 108 产生指令地址 106 ， 106 寻址指令缓冲器 118 ， 118 通过总线 111 提供顺序指令。 106 也与 101 中存储的分支指令地址比较。 Instruction memory 105 is another discrete memory that is addressed by additional read and write control and address. 105 Responsible for providing branch target instructions, which require a larger address space and therefore require a larger storage capacity than 118. The branch instruction address and its corresponding branch target instruction pair are stored in the BTB101. Processor core 108 The instruction address 106, 106 is addressed to address the instruction buffers 118, 118 to provide sequential instructions over the bus 111. 106 also with 101 Branch instruction address comparison stored in .
如果 101 存储中的一个分支指令地址与指令地址 106 匹配，则 BTB 101 提供与该分支指令地址对应的分支目标指令地址，也控制选择器 204 选择 BTB101 提供的分支目标指令地址。该分支目标指令地址寻址指令存储器 105 ， 105 通过总线 112 提供相应的分支目标指令。此时 106 提供分支指令后第一条指令地址，寻址指令缓冲器 118 ， 118 通过总线 111 提供分支指令后第一条指令。处理器核 108 也产生分支判断 110 以控制选择器 116 。 If a branch instruction address in the 101 store matches the instruction address 106, then BTB 101 A branch target instruction address corresponding to the branch instruction address is provided, and the selector 204 is also controlled to select the branch target instruction address provided by the BTB101. The branch target instruction address addresses the instruction memory 105, 105 The corresponding branch target instruction is provided via bus 112. At this time, 106 provides the first instruction address after the branch instruction, and addresses the instruction buffer 118, 118 through the bus 111. Provide the first instruction after the branch instruction. Processor core 108 also generates branch decisions 110 to control selector 116.
如 110 的值为'不分支'，则 116 选择总线 111 上的分支指令后第一条指令经总线 107 提供给处理器核 108 执行。此后 106 上的地址为分支指令后第二条指令的地址，控制指令缓冲器 118 提供分支指令后第二条指令。如果分支指令后第一条指令不是分支指令，此时的分支判断 110 的值为'不分支'，控制选择器 116 选择 118 提供的分支指令后第二条指令供处理器核 108 执行。如此顺序执行指令缓冲器中的分支指令的后续指令。 If the value of 110 is 'no branch', then 116 selects the branch instruction on bus 111 and the first instruction passes bus 107. Provided to processor core 108 for execution. Thereafter, the address on 106 is the address of the second instruction after the branch instruction, and the control instruction buffer 118 Provide the second instruction after the branch instruction. If the first instruction after the branch instruction is not a branch instruction, the value of the branch decision 110 at this time is 'no branch', and the control selector 116 selects 118. The second instruction is provided by the processor core 108 after the branch instruction is provided. Subsequent instructions of the branch instruction in the instruction buffer are executed in this order.
如 110 的值为'分支'，则 116 选择总线 112 上的分支目标指令经总线 107 提供给 108 执行。同时指令存储器 105 提供分支目标指令所在的指令行，存入指令缓冲器 118 。此后 106 上的地址为分支目标指令后第一条指令的地址，控制指令缓冲器 118 提供分支目标指令后第一条指令。如果分支目标指令本身不是分支指令，此时的分支判断 110 的值为'不分支'，控制选择器 116 选择 118 提供的分支目标指令后第一条指令供处理器核 108 执行。如此顺序执行指令缓冲器 118 中的分支目标指令的后续指令。 If the value of 110 is 'branch', the 116 branch target instruction on bus 112 is provided to bus 108 via bus 107. carried out. At the same time, the instruction memory 105 provides the instruction line in which the branch target instruction is located, and stores it in the instruction buffer 118. After that, the address on 106 is the address of the first instruction after the branch target instruction, and the control instruction buffer 118 Provides the first instruction after the branch target instruction. If the branch target instruction itself is not a branch instruction, the value of the branch decision 110 at this time is 'no branch', and the control selector 116 selects 118. The first instruction after the provided branch target instruction is executed by the processor core 108. Subsequent instructions of the branch target instruction in the instruction buffer 118 are executed in this order.
如 BTB101 中存储的分支指令地址没有与 106 上的分支指令地址匹配，选择器 204 选择总线 106 上的地址。此时因为分支判断 110 的值为'分支'，但 BTB 没有匹配，处理器核 108 产生经总线 106 送出的地址为分支目标指令地址。该分支目标指令地址寻址指令存储器 105 经总线 112 提供分支目标指令所在的指令行。值为'分支'的分支判断控制选择器 116 选择总线 112 上的分支目标指令经总线 107 供处理器核 108 执行。同时将 112 上的指令行存入指令缓冲器 118 。也将分支指令地址 / 分支目标指令地址对存入 BTB101 供以后使用。 此后处理器核 108 产生经总线 106 送出分支目标指令后第一条指令的地址，读取 118 中指令，由此时值为'不分支'的分支判断 110 控制的选择器 116 选择，供处理器核 108 处理。如此顺序执行指令缓冲器 118 中的分支目标指令的后续指令。 If the branch instruction address stored in BTB101 does not match the branch instruction address on 106, selector 204 selects the bus. The address on 106. At this point, because the value of the branch decision 110 is 'branch', but the BTB does not match, the processor core 108 generates a bus 106. The address sent is the branch target instruction address. The branch target instruction address addressing instruction memory 105 provides the instruction line in which the branch target instruction is located via bus 112. Branch judgment control selector 116 with value of 'branch' The branch target instruction on select bus 112 is executed by bus 107 for processor core 108. At the same time, the instruction line on 112 is stored in the instruction buffer 118. Will also branch instruction address / The branch target instruction address pair is stored in BTB101 for later use. Thereafter, the processor core 108 generates the address of the first instruction after the branch target instruction is sent via the bus 106, and reads 118. The middle instruction, by which the time value is 'no branch', is judged by the selector 116 selected for processing by the processor core 108. The instruction buffer is executed in this order. Subsequent instructions for branch target instructions in .
加法器 113 将指令地址 106 上的地址中的行地址部分加上一个指令行中的字节数，得到顺序下一行的行地址。当指令地址中的块内偏移地址指向指令缓冲器 118 最后一条指令，使 118 提供该指令到处理器核 108 执行时，选择器 204 选择加法器 113 输出的顺序下一行的地址以寻址指令存储器 105 。 105 提供顺序下一行指令供存入指令缓冲器 118 。之后，指令地址 106 寻址 118 向处理器核 108 提供顺序下一行的指令供执行。 Adder 113 will be the instruction address 106 The row address portion of the upper address plus the number of bytes in the instruction line gives the row address of the next row in sequence. When the intra-block offset address in the instruction address points to the last instruction of the instruction buffer 118, make 118 When the instruction is provided to the processor core 108, the selector 204 selects the address of the next row in the order of the output of the adder 113 to address the instruction memory 105. 105 The next line of instructions is provided for storage in the instruction buffer 118. Thereafter, instruction address 106 addressing 118 provides processor core 108 with instructions for the next row in sequence for execution.
本实施例中指令地址 106 以及分支判断 110 的产生方式与图 2 实施例中产生方式相同。本实施例中发生 BTB 缺失时的处理方式也与图 2 实施例中处理方式类似。但是发生 BTB 缺失时，以此时处理器核输出的地址总线 106 上的分支目标指令地址经选择器 204 寻址指令存储器 105 。选择器 116 则仍由分支判断 110 控制，选择指令存储器 105 提供的分支目标指令。即选择器 116 任何时候都由分支判断 110 控制。 The instruction address 106 and the branch determination 110 are generated in the same manner as in the embodiment of Fig. 2 in this embodiment. Occurred in this embodiment The processing when BTB is missing is also similar to the processing in the embodiment of Figure 2. However, when the BTB is missing, the branch target instruction address on the address bus 106 output by the processor core at this time passes through the selector 204. Addressing the instruction memory 105. The selector 116 is still controlled by the branch decision 110 to select the branch target instruction provided by the instruction memory 105. That is, the selector 116 is judged by the branch at any time. 110 control.
一个典型的处理器核流水线有五个流水线段，取指（ I ）段，译码段（ D ），执行段 (E), 访存段（ M ），以及写回段（ W ）。分支判断通常可以在 D 段或 E 段产生。以上三个实施例都是基于分支判断在 D 段产生的假设，或者说分支判断产生得足够早，可以选择分支指令后的两支指令中的一支供处理器核处理。在图 4 的实施例中，处理器核 108 产生顺序地址，在产生分支指令地址后产生分支指令后一条指令的地址。此后如分支判断的值为'不分支'，则 108 产生分支指令后第二条指令的地址。如分支判断的值为'分支'，则 108 产生分支目标指令后第一条指令的地址。 A typical processor core pipeline has five pipeline segments, fetch ( I ), decode ( D ), execute (E), and fetch ( M ), and write back the segment (W). Branch judgments can usually be generated in either D or E segments. The above three embodiments are based on branch judgment in D The hypothesis generated by the segment, or the branch judgment is generated early enough, one of the two instructions after the branch instruction can be selected for processing by the processor core. In the embodiment of FIG. 4, processor core 108 The sequential address is generated, and the address of an instruction after the branch instruction is generated after the branch instruction address is generated. Thereafter, if the value judged by the branch is 'no branch', then 108 The address of the second instruction after the branch instruction is generated. If the value judged by the branch is 'branch', then 108 the address of the first instruction after the branch target instruction is generated.
图 5 是本发明所述以分支判断处理分支的另一个实施例。图 5 是分支判断在 E 段产生的实施例，或者说是分支判断产生得不够早，需要对两支指令都做部分处理后，由分支判断选择两个部分处理结果中的一个供处理器核进一步处理的实施例。 Figure 5 is another embodiment of the branching processing branch of the present invention. Figure 5 is the branch judgment in E The embodiment generated by the segment, or the branch judgment is not generated enough, and after the partial processing of both instructions is required, the branch judges to select one of the two partial processing results for further processing by the processor core.
此实施例中， 101 是存储分支指令地址 / 分支目标指令地址对的 BTB ， 105 是指令存储器， 118 是指令缓冲器 (buffer) ， 113 是加法器， 204 与 116 是选择器， 117 及 119 是指令译码器， 128 是不带指令译码器的处理器核。 128 产生指令地址经总线 106 输出，总线 106 上的指令地址寻址指令缓冲器 118 ， 118 提供顺序指令 111 ， 111 由指令译码器 117 译码。值为'不分支'的分支判断 110 选择 117 的指令译码结果供处理器核 128 执行。 In this embodiment, 101 is a BTB storing a branch instruction address/branch target instruction address pair, and 105 is an instruction memory. 118 is the instruction buffer (buffer), 113 is the adder, 204 and 116 are the selectors, 117 and 119 are the instruction decoders, 128 Is a processor core without an instruction decoder. 128 generating an instruction address is output via bus 106, and an instruction address on bus 106 addresses instruction buffer 118, 118 provides sequential instruction 111, 111 is decoded by the instruction decoder 117. The branch decision 110 with a value of 'no branch' selects the instruction decode result of 117 for execution by processor core 128.
总线 106 上的指令地址顺序指向下一条指令，控制指令缓冲器 118 送出相应指令供译码器 117 译码。如果 BTB 101 中的分支指令地址与总线 106 上的指令地址匹配， BTB101 除匹配时送出对应的分支目标指令地址外，在下一周期送出分支目标指令后第一条指令的地址。在分支判断产生时，控制使总线 106 上地址为上述两个地址中的一个的后续地址。具体地说，当分支判断值为'不分支'时，总线 106 上指令地址为分支指令后第三条指令的地址；当分支判断值为'分支'时，总线 106 上指令地址为分支目标指令后第二条指令的地址。控制选择器 116 的分支判断总线 110 则在其值为'分支'时，继续保留该为'分支'的值一个周期。之后才由新的分支判断决定 110 上的值。 The instruction address sequence on bus 106 points to the next instruction, and control instruction buffer 118 sends the corresponding instruction to decoder 117 Decoding. If the branch instruction address in BTB 101 matches the instruction address on bus 106, BTB101 The address of the first instruction after the branch target instruction is sent in the next cycle, except for the corresponding branch target instruction address when the match is sent. When the branch judgment is made, the control causes the bus 106 The upper address is the subsequent address of one of the above two addresses. Specifically, when the branch judgment value is 'no branch', the bus 106 The upper instruction address is the address of the third instruction after the branch instruction; when the branch judgment value is 'branch', the instruction address on the bus 106 is the address of the second instruction after the branch target instruction. Control the branch of the selector 116 to determine the bus 110 then keeps the value of the 'branch' for one cycle when its value is 'branch'. The value at 110 is then determined by the new branch.
总线 106 上的地址也与 101 中的存储分支指令地址比较。如果 101 中的一个分支指令地址与指令地址 106 匹配，则 BTB 101 提供相应的分支目标指令地址，也控制选择器 204 选择 BTB101 提供的分支目标指令地址。该分支目标指令地址寻址指令存储器 105 ， 105 提供相应的分支目标指令 112 ， 112 由指令译码器 119 译码。此时 106 提供分支指令后第一条指令地址，寻址指令缓冲器 108 ， 118 提供分支指令后第一条指令 111 ， 111 由指令译码器 117 译码。处理器核 128 也产生分支判断 110 以控制选择器 116 。 The address on bus 106 is also compared to the address of the stored branch instruction in 101. If a branch instruction address and instruction address in 101 106 match, then BTB 101 provides the corresponding branch target instruction address, and also controls selector 204 to select BTB101 The branch target instruction address provided. The branch target instruction address addressing instruction memory 105, 105 provides the corresponding branch target instruction 112, 112 which is decoded by the instruction decoder 119. at this time 106 provides the first instruction address after the branch instruction, the address instruction buffer 108, 118 provides the branch instruction, and the first instruction 111, 111 is decoded by the instruction decoder 117. Processor core 128 also generates a branch decision 110 to control the selector 116.
如分支判断 110 为'不分支'，则 116 选择分支指令后第一条指令 111 经指令译码器 117 译码的结果经总线 207 提供给 128 执行。此后，处理器核 128 经总线 106 提供分支指令后第二条指令等后续指令的地址，寻址指令缓冲器 118 ，提供顺序指令经译码器 117 译码后，由选择器 116 选择，经总线 207 供处理器核 128 处理。 If the branch judgment 110 is 'no branch', then 116 selects the branch instruction and the first instruction 111 passes the instruction decoder 117. The decoded result is provided to 128 for execution via bus 207. Thereafter, the processor core 128 provides the address of the subsequent instruction such as the second instruction via the bus 106 via the bus 106, and addresses the instruction buffer 118. The sequential instructions are decoded by the decoder 117, selected by the selector 116, and processed by the processor core 128 via the bus 207.
如分支判断 110 为'分支'，则选择器 116 选择分支目标指令 112 经指令译码器 119 译码的结果经总线 207 提供给 128 执行。同时指令存储器 105 提供分支目标指令所在的指令行，存入指令缓冲器 118 。此后，处理器核 128 经总线 106 提供分支指令后第二条指令等后续指令的地址，寻址指令缓冲器 118 ，提供顺序指令经译码器 117 译码； BTB101 送出分支目标指令后第一条指令的地址，寻址指令存储器 105 ，提供分支指令后第一条指令经译码器 119 译码。此时 110 上值保留为'分支'，控制选择器 116 选择译码器 119 的译码结果经总线 207 送给处理器核 128 处理。之后，如 110 上值为'不分支'，则控制选择器 116 选择来自指令缓冲器 118 ，经指令译码器 117 译码的指令（此时为分支目标指令后的顺序指令）供处理器核处理。 If the branch decision 110 is 'branch', the selector 116 selects the branch target instruction 112 via the instruction decoder 119. The decoded result is provided to 128 for execution via bus 207. At the same time, the instruction memory 105 provides the instruction line in which the branch target instruction is located, and stores it in the instruction buffer 118. Thereafter, the processor core 128 is routed through the bus. 106 provides the address of the subsequent instruction such as the second instruction after the branch instruction, addresses the instruction buffer 118, and provides the sequential instruction to be decoded by the decoder 117; BTB101 The address of the first instruction after the branch target instruction is sent, the instruction memory 105 is addressed, and the first instruction is decoded by the decoder 119 after the branch instruction is provided. At this time, the value on 110 is reserved as 'branch', and the selector is controlled. The decoding result of the 116 select decoder 119 is sent to the processor core 128 via the bus 207 for processing. Thereafter, if the value on 110 is 'no branch', then control selector 116 selects from the instruction buffer. 118. The instruction decoded by the instruction decoder 117 (in this case, the sequential instruction after the branch target instruction) is processed by the processor core.
其他的操作与图 4 实施例相同。本实施例是以指令译码器为例，但是也可以将其扩展为包含其他处理器核功能的流水线段。将处理器核 128 中的流水线划分为前端流水线及后端流水线。称产生分支判断的流水线段之前的流水线段为前端流水线，称从分支判断流水线段开始的流水线段为后端流水线。处理器核 128 中为'分支'及'不分支'两组指令各安排一个前端流水线段，由分支判断选择两个前端流水线段输出的两个中间结果，将被选择的中间结果送到处理器核中的后端流水线执行。 Other operations and Figure 4 The examples are the same. This embodiment is an example of an instruction decoder, but it can also be extended to a pipeline segment that includes other processor core functions. Processor core 128 The pipeline in the middle is divided into a front-end pipeline and a back-end pipeline. The pipeline segment before the pipeline segment that determines the branch judgment is the front-end pipeline, and the pipeline segment starting from the branch judgment pipeline segment is called the back-end pipeline. Processor core 128 In the middle of the 'branch' and 'no branch' two sets of instructions each arrange a front-end pipeline segment, the branch selects the two intermediate results of the output of the two front-end pipeline segments, and sends the selected intermediate result to the processor core. The end pipeline is executed.
在这种组织形式中，图 5 中的 117 是一个前端流水线， 119 是另一个前端流水线， 128 是后端流水线，而其他模块的功能如同上述同样。后端流水线 128 产生的分支判断 110 控制选择器 116 选择前端流水线 117 或 119 输出的中间结果，送到后端流水线 128 执行。如分支判断 110 为'不分支'，则 116 选择分支指令后第一条指令及后第二条指令 111 经前端流水线 117 的中间结果经总线 207 提供给 128 执行。如分支判断 110 为'分支'（连续两个周期），则选择器 116 选择分支目标指令及分支目标后第一条指令 112 经前端流水线 119 的中间结果经总线 207 提供给 128 执行。同时指令存储器 105 提供分支目标指令所在的指令行，存入指令缓冲器 118 。 In this form of organization, 117 in Figure 5 is a front-end pipeline, and 119 is another front-end pipeline, 128 It is the back-end pipeline, and the functions of other modules are the same as above. Branch Decisions Generated by Back-End Pipeline 128 110 Control Selector 116 Select Front-End Pipeline 117 or 119 The intermediate result of the output is sent to the back-end pipeline 128 for execution. If branch judgment 110 is 'no branch', then 116 selects the branch instruction and the first instruction and the second instruction 111 pass the front-end pipeline. The intermediate result of 117 is provided to 128 for execution via bus 207. If branch decision 110 is 'branch' (two consecutive cycles), then selector 116 After the branch target instruction and the branch target are selected, the intermediate result of the first instruction 112 via the front-end pipeline 119 is supplied to the 128 for execution via the bus 207. Simultaneous instruction memory 105 The instruction line where the branch target instruction is located is stored in the instruction buffer 118.
本实施例中发生 BTB 缺失时的处理方式也与图 4 实施例中处理方式相同。本实施例由分支判断，以控制选择两个指令译码器（或前端流水线）产生的两个指令译码结果中的一个供处理器核（或后端流水线）执行的缓存组织方式是基于图 4 实施例的缓存组织方式举例说明。也可以以图 2 及图 3 实施例或其他缓存组织方式，提供分支指令后第一条指令以及分支目标指令至两个独立的指令译码器（或前端流水线），由分支判断选择两个译码结果（中间结果）中的一个供处理器核（后端流水线）执行。 The processing method when BTB is missing in this embodiment is also the same as FIG. 4 The treatment in the examples is the same. The embodiment is determined by the branch, and the cache organization method for controlling the execution of one of the two instruction decoding results generated by the two instruction decoders (or the front-end pipeline) for the processor core (or the back-end pipeline) is based on the graph. 4 Example of the cache organization mode of the embodiment. Can also be shown in Figure 2 and Figure 3. Embodiment or other cache organization manner, providing a first instruction after a branch instruction and a branch target instruction to two independent instruction decoders (or front-end pipelines), and selecting two decoding results (intermediate results) by branch judgment One is executed by the processor core (back-end pipeline).
可以进一步结合图 2 与图 4 或图 5 的实施例，在 BTB 中存储分支目标指令地址以及分支目标指令后第一条指令的地址。如此，当处理器核经 106 提供的指令与 BTB 中存储的分支指令地址匹配时， BTB 提供分支目标指令，也提供分支目标指令后第一条指令的地址以寻址第二存储器，之后第二存储器 105 提供分支指令后第一条指令。同时 106 上的顺序地址寻址指令读缓冲 118 中的顺序指令。处理器核产生的分支判断 110 控制选择器 116 。 Can be further combined with the embodiment of Figure 2 and Figure 4 or Figure 5, in BTB Stores the branch target instruction address and the address of the first instruction after the branch target instruction. Thus, when the processor core 106 provides an instruction that matches the branch instruction address stored in the BTB, BTB The branch target instruction is provided, and the address of the first instruction after the branch target instruction is also provided to address the second memory, and then the second memory 105 provides the first instruction after the branch instruction. And 106 The sequential address addressing instruction reads the sequential instructions in buffer 118. The branch decision 110 generated by the processor core controls the selector 116.
如 110 上值为'分支'， 116 选择来自 BTB 或第二存储器 105 的分支目标一支的指令供处理器核 108 处理，也使 106 上地址从来自 BTB 的分支目标指令后第一条指令开始做增量作为后续地址。所述增量可以是一条指令的字节数。同时也将第二存储器 105 输出的指令行存入指令缓冲器 118 供后续地址读取。 If the value on 110 is 'branch', 116 selects from BTB or the second memory 105 The branch target has one instruction for the processor core 108 to process, and also makes the address on 106 from BTB After the branch target instruction, the first instruction starts to increment as the subsequent address. The increment can be the number of bytes of an instruction. The instruction line output from the second memory 105 is also stored in the instruction buffer 118. For subsequent address reading.
如 110 上值为'不分支'， 116 选择来自指令缓冲器 118 的顺序一支的指令供处理器核 108 处理，也使 106 上地址做增量作为后续地址。所述增量可以是一条指令的字节数。其余模块功能，操作等与上述图 4 、图 5 实施例相同，不再赘述。 If the value on 110 is 'no branch', 116 selects the instruction from the instruction buffer 118 for the processor core 108. Processing also causes the address on 106 to be incremented as a subsequent address. The increment can be the number of bytes of an instruction. The functions, operations, and the like of the remaining modules are the same as those of the above-mentioned FIG. 4 and FIG. 5, and are not described again.
本发明的实施例，从图 2 到图 5 ，包括上述结合图2与图 4 或图 5 的实施例，都不使用分支预测。图 3 至图 5 是由处理器核（或后端流水线）提供顺序指令地址寻址一个存储器以提供顺序指令；由分支目标缓冲器（ BTB ）匹配顺序指令，提供与顺序指令地址中的分支指令地址对应的分支目标指令地址寻址一个存储器提供分支目标指令；由处理器核（或后端流水线）执行指令产生的分支判断选择顺序指令或分支目标指令供处理器核（后端流水线）执行。不论是顺序执行，或是分支跳转，都没有分支损失（ branch penalty ）。因为没有分支预测，也就没有预测错误（ mis-prediction ）带来的损失。图 2 实施例则由 BTB 直接提供分支目标指令，其余与图 3 至图 5 相同。 Embodiments of the present invention, from Figures 2 through 5, including the embodiments described above in connection with Figures 2 and 4 or 5, do not use branch prediction. Figure 3 to Figure 5 is a sequential instruction address provided by the processor core (or back-end pipeline) to address a memory to provide sequential instructions; by the branch target buffer (BTB) a matching sequence instruction that provides a branch target instruction address corresponding to a branch instruction address in the sequential instruction address to address a memory to provide a branch target instruction; a branch judgment selection order instruction generated by the processor core (or back-end pipeline) execution instruction or Branch target instructions are executed by the processor core (back-end pipeline). No branch loss, whether it is sequential execution or branch jump ( Branch penalty ). Because there is no branch prediction, there is no loss caused by mis-prediction. Figure 2 shows the example by BTB The branch target instruction is directly provided, and the rest is the same as FIG. 3 to FIG. 5.
虽然本发明的实施例仅仅对本发明的结构特征和 / 或方法过程进行了描述，但本发明的权利要求并不只局限与所述特征和过程。所述特征和过程只是实现本发明权利要求的几种例子。应当理解的是，上述实施例中列出的多个部件只是为了便于描述，还可以包含其他部件，或某些部件可以被组合或省去。所述多个部件可以分布在多个系统中，可以是物理存在的或虚拟的，也可以用硬件实现（如集成电路）、用软件实现或由软硬件组合实现。 Although the embodiments of the present invention are only for the structural features of the present invention and / The method process is described, but the claims of the present invention are not limited only to the features and processes described. The features and processes are merely a few examples of implementing the claims of the invention. It should be understood that the various components listed in the above embodiments are merely for convenience of description, and may include other components, or some components may be combined or omitted. The plurality of components may be distributed among multiple systems, may be physically present or virtual, or may be implemented in hardware (such as an integrated circuit), implemented in software, or implemented in a combination of hardware and software.
根据对上述较优的实施例的说明，无论本领域的技术发展有多快，也无论将来可能取得何种目前尚不易预测的进展，本发明均可以由本领域普通技术人员根据本发明的原理对相应的参数、配置进行相适应的替换、调整和改进，所有这些替换、调整和改进都应属于本发明所附权利要求的保护范围。 In accordance with the description of the preferred embodiments described above, the present invention may be practiced by one of ordinary skill in the art in accordance with the principles of the present invention, regardless of how fast the art is developed, and which progress may be made in the future, which is not readily predictable. Corresponding parameters, configurations, adaptations, adjustments and improvements are intended to be included within the scope of the appended claims.
工业实用性Industrial applicability
序列表自由内容Sequence table free content

Claims (10)

  1. 一种分支（Branch）处理方法，其特征是提供分支指令后的分支目标及顺序两支指令由处理器核产生的分支判断选择一支指令供处理器核执行； A branch processing method, characterized in that the branch target and the sequential two instructions after the branch instruction are determined by the branch generated by the processor core to select an instruction for the processor core to execute;
    分支目标缓冲器BTB中成对存储分支指令地址、以及相应的分支目标指令地址；The branch target buffer BTB stores the branch instruction address and the corresponding branch target instruction address in pairs;
    由处理器核提供指令地址，该指令地址寻址第一存储装置，由第一存储装置提供顺序指令；Providing, by the processor core, an instruction address, the instruction address addressing the first storage device, and the first storage device providing the sequential instruction;
    该指令地址也与分支目标缓冲器（BTB）中存储的分支指令地址匹配，如处理器核指令地址与BTB中存储的一条分支指令地址匹配，则BTB提供与该分支指令地址对应的分支目标指令地址；The instruction address also matches the branch instruction address stored in the branch target buffer (BTB). If the processor core instruction address matches a branch instruction address stored in the BTB, the BTB provides a branch target instruction corresponding to the branch instruction address. address;
    该分支目标指令地址寻址第二存储装置，由第二存储装置提供分支目标指令；The branch target instruction address addresses the second storage device, and the second storage device provides the branch target instruction;
    如果处理器核产生的分支判断为'不分支'，选择第一存储装置提供的顺序指令供处理器核处理；If the branch generated by the processor core is determined to be 'no branch', the sequential instructions provided by the first storage device are selected for processing by the processor core;
    如果处理器核产生的分支判断为'分支'，选择第二存储装置提供的分支目标指令供处理器核处理。If the branch generated by the processor core is determined to be a 'branch', the branch target instruction provided by the second storage device is selected for processing by the processor core.
  2. 根据权利要求1所述的分支处理方法，其特征在于如果处理器核提供的指令在BTB中没有匹配，而处理器核产生的相应分支判断为'分支'，则以处理器核此时产生的分支目标指令地址寻址第二存储装置；The branch processing method according to claim 1, wherein if the instruction provided by the processor core does not match in the BTB, and the corresponding branch generated by the processor core is determined to be a 'branch', the processor core generates the current time. The branch target instruction address addresses the second storage device;
    第二存储装置输出分支目标指令；The second storage device outputs a branch target instruction;
    值为'分支'的分支判断选择第二存储装置提供的分支目标指令供处理器处理；以及The branch whose value is 'branch' determines the branch target instruction provided by the second storage device for processing by the processor;
    将分支指令地址/分支目标指令地址对存入BTB。The branch instruction address/branch target instruction address pair is stored in the BTB.
  3. 根据权利要求1所述的分支处理方法，其特征在于所述第一存储装置与第二存储装置为同一存储装置的第一及第二读口；The branch processing method according to claim 1, wherein the first storage device and the second storage device are first and second read ports of the same storage device;
    该第一读口由独立的地址寻址；以及The first read port is addressed by a separate address;
    该第二读口由另一个独立的地址寻址。The second read is addressed by another independent address.
  4. 根据权利要求1所述的分支处理方法，其特征在于所述第一存储装置与第二存储装置为复数个分立的存储装置；The branch processing method according to claim 1, wherein said first storage device and said second storage device are a plurality of discrete storage devices;
    该第一存储装置由独立的地址寻址；以及The first storage device is addressed by a separate address;
    该第二存储装置由另一个独立的地址寻址。The second storage device is addressed by another independent address.
  5. 根据权利要求4所述的分支处理方法，其特征在于所述第一存储装置能存储复数条指令；The branch processing method according to claim 4, wherein said first storage means is capable of storing a plurality of instructions;
    当处理器核产生的分支判断为分支时，由第二存储装置输出的复数条指令存入第一存储装置。When the branch generated by the processor core is determined to be a branch, the plurality of instructions output by the second storage device are stored in the first storage device.
  6. 根据权利要求5所述的分支处理方法，其特征在于将处理器核提供的指令地址中的指令行地址，与一个指令行中含有的字节数相加得到顺序下一指令行的指令行地址；The branch processing method according to claim 5, wherein the instruction row address in the instruction address provided by the processor core is added to the number of bytes included in an instruction line to obtain the instruction row address of the next instruction line. ;
    当指令行地址中的块内偏移地址指向第一存储装置中最后一条指令时，以所述顺序下一指令行的行地址寻址第二存储装置，由第二存储装置提供顺序下一指令行，将该指令行存入第一存储装置。When the intra-block offset address in the instruction line address points to the last instruction in the first storage device, the second storage device is addressed in the row address of the next instruction line in the sequence, and the next instruction is provided by the second storage device. Row, the command line is stored in the first storage device.
  7. 根据权利要求1所述的分支处理方法，其特征在于具有两个独立的指令译码器；The branch processing method according to claim 1, characterized by having two independent instruction decoders;
    第一指令译码器译码由处理器核提供指令地址寻址第一存储装置所提供的顺序指令；The first instruction decoder decodes the sequential instruction provided by the first storage device by the processor core providing the instruction address;
    第二指令译码器译码第二存储装置所提供的指令；The second instruction decoder decodes the instruction provided by the second storage device;
    如果处理器核产生的分支判断为'不分支'，选择第一指令译码器提供的顺序指令供处理器核处理；If the branch generated by the processor core is judged as 'no branch', the sequential instruction provided by the first instruction decoder is selected for processing by the processor core;
    如果处理器核产生的分支判断为'分支'，选择第二指令译码器提供的分支目标指令供处理器处理。If the branch generated by the processor core is judged to be a 'branch', the branch target instruction provided by the second instruction decoder is selected for processing by the processor.
  8. 根据权利要求1所述的分支处理方法，其特征在于将处理器流水线分为前端流水线及后端流水线，前端流水线是产生分支判断的流水线段之前的处理器核流水线，后端流水线是从产生分支判断的流水线段开始的处理器核流水线段；The branch processing method according to claim 1, wherein the processor pipeline is divided into a front-end pipeline and a back-end pipeline, and the front-end pipeline is a processor core pipeline before the pipeline segment that generates the branch judgment, and the back-end pipeline is generated from the branch. The processor core pipeline segment starting from the determined pipeline segment;
    处理器核具有两组前端流水线以及一组后端流水线；The processor core has two sets of front-end pipelines and a set of back-end pipelines;
    第一组前端流水线处理由第一存储装置提供的顺序指令；The first set of front-end pipelines processes sequential instructions provided by the first storage device;
    第二组前端流水线处理由第二存储装置提供的指令；a second set of front end pipelines processing instructions provided by the second storage device;
    如果处理器核产生的分支判断为'不分支'，选择第一组前端流水线的输出供后端流水线处理；If the branch generated by the processor core is judged as 'no branch', the output of the first set of front-end pipelines is selected for processing by the back-end pipeline;
    如果处理器核产生的分支判断为'分支'，选择第二组前端流水线提供的输出供后端流水线处理。If the branch generated by the processor core is judged to be a 'branch', the output provided by the second set of front-end pipelines is selected for processing by the back-end pipeline.
  9. 一种分支（Branch）处理方法，其特征是提供分支指令后的分支目标及顺序两支指令由处理器核产生的分支判断选择一支指令供处理器核执行；A branch processing method, characterized in that the branch target and the sequential two instructions after the branch instruction are determined by the branch generated by the processor core to select an instruction for the processor core to execute;
    分支目标缓冲器BTB中成对存储分支指令地址、以及相应的分支目标指令；The branch target buffer BTB stores the branch instruction address and the corresponding branch target instruction in pairs;
    由处理器核提供指令地址，该指令地址寻址第一存储装置，由第一存储装置提供顺序指令；Providing, by the processor core, an instruction address, the instruction address addressing the first storage device, and the first storage device providing the sequential instruction;
    该指令地址也与分支目标缓冲器（BTB）中存储的分支指令地址匹配，如处理器核指令地址与BTB中存储的一条分支指令地址匹配，则BTB提供与该分支指令地址对应的分支目标指令；The instruction address also matches the branch instruction address stored in the branch target buffer (BTB). If the processor core instruction address matches a branch instruction address stored in the BTB, the BTB provides a branch target instruction corresponding to the branch instruction address. ;
    如果处理器核产生的分支判断为'不分支'，选择第一存储装置提供的顺序指令供处理器核处理；If the branch generated by the processor core is determined to be 'no branch', the sequential instructions provided by the first storage device are selected for processing by the processor core;
    如果处理器核产生的分支判断为'分支'，选择BTB提供的分支目标指令供处理器核处理。If the branch generated by the processor core is judged to be a 'branch', the branch target instruction provided by the BTB is selected for processing by the processor core.
  10. 根据权利要求9所述的分支处理方法，其特征在于分支目标缓冲器BTB中除成对存储分支指令地址、以及相应的分支目标指令外，还存储相应的分支目标指令后一条指令的地址；The branch processing method according to claim 9, wherein the branch target buffer BTB stores, in addition to the paired storage branch instruction address and the corresponding branch target instruction, an address of a subsequent instruction of the corresponding branch target instruction;
    由处理器核提供指令地址，该指令地址寻址第一存储装置，由第一存储装置提供顺序指令；Providing, by the processor core, an instruction address, the instruction address addressing the first storage device, and the first storage device providing the sequential instruction;
    该指令地址也与分支目标缓冲器（BTB）中存储的分支指令地址匹配，如处理器核指令地址与BTB中存储的一条分支指令地址匹配，则BTB提供与该分支指令地址对应的分支目标指令，也提供分支目标指令后一条指令的地址以寻址第二存储器提供分支目标指令后第一条指令；The instruction address also matches the branch instruction address stored in the branch target buffer (BTB). If the processor core instruction address matches a branch instruction address stored in the BTB, the BTB provides a branch target instruction corresponding to the branch instruction address. , also providing the address of an instruction after the branch target instruction to address the first instruction after the second memory provides the branch target instruction;
    如果处理器核产生的分支判断为'不分支'，选择第一存储装置提供的顺序指令供处理器核处理；If the branch generated by the processor core is determined to be 'no branch', the sequential instructions provided by the first storage device are selected for processing by the processor core;
    如果处理器核产生的分支判断为'分支'，选择BTB提供的分支目标指令或第二存储器提供的分支目标指令后第一条指令供处理器核处理，在BTB提供的分支目标指令后一条指令的地址上做增量作为处理器核提供的指令地址。If the branch generated by the processor core is determined to be a 'branch', the branch instruction provided by the BTB or the branch instruction provided by the second memory is selected to be processed by the processor core, and the instruction is followed by the branch target instruction provided by the BTB. The increment is used as the address of the instruction provided by the processor core.
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CN102855121A (en) * 2011-06-29 2013-01-02 上海芯豪微电子有限公司 Branching processing method and system
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