WO2018184294A1 - 薄膜晶体管及其制作方法、阵列基板 - Google Patents

薄膜晶体管及其制作方法、阵列基板 Download PDF

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WO2018184294A1
WO2018184294A1 PCT/CN2017/088394 CN2017088394W WO2018184294A1 WO 2018184294 A1 WO2018184294 A1 WO 2018184294A1 CN 2017088394 W CN2017088394 W CN 2017088394W WO 2018184294 A1 WO2018184294 A1 WO 2018184294A1
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layer
gate insulating
insulating layer
oxygen
thin film
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李子然
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01332—Making the insulator
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention belongs to the field of display technologies, and in particular, to a thin film transistor, a method for fabricating the same, and an array substrate.
  • an active layer made of IGZO is grown on the gate insulating layer, that is, the material of the gate insulating layer is selected and the quality of the surface of the gate insulating layer is IGZO.
  • the device performance of thin film transistors has a great impact.
  • the gate insulating layer of IGZO thin film transistor is generally made of tetraethyl orthosilicate (TEOS) or silicon dioxide (SiO 2 ), which has poor surface flatness and some oxygen vacancy defects on the surface, which will make its surface state. It is unstable, and thus, the interface with the IGZO active layer material deposited thereon is also changed.
  • the front channel layer of the thin film transistor device is formed near this interface and is a carrier transmission channel in the thin film transistor device. Therefore, after depositing the active layer, a high concentration defect state is formed at the interface with the gate insulating layer, and these defect states trap carriers and reduce carrier mobility, thereby making the characteristics of the device unstable. This causes the device reverse current to increase or the breakdown voltage to decrease.
  • the present invention provides a thin film transistor capable of improving surface characteristics of a gate insulating layer, a method of fabricating the same, and an array substrate.
  • a thin film transistor including: a gate electrode on a substrate; a gate insulating layer on the substrate and the gate, a surface of the gate insulating layer is performed a planarization process; an oxygen-rich layer on the gate insulating layer; an active layer on the oxygen-rich layer; a source and a drain on the active layer; The source and the passivation layer on the drain.
  • the specific method for planarizing the surface of the gate insulating layer comprises: treating the surface of the gate insulating layer with hydrofluoric acid with a mass percentage of 0.5% to 2% for 30 s to 120 s.
  • the surface of the gate insulating layer is treated with 20 PPM to 30 PPM of ozone water for 60 s to 90 s to form an oxygen-rich layer on the gate insulating layer.
  • the active layer is made of indium gallium zinc oxide.
  • an array substrate comprising: a substrate; the thin film transistor described above disposed on the substrate; a pixel electrode on a passivation layer of the thin film transistor, the blunt The via layer has a via hole exposing the drain, and the pixel electrode is connected to the drain through the via hole.
  • a method of fabricating a thin film transistor includes: forming a gate on a substrate; forming a gate insulating layer on the substrate and the gate; a surface of the gate insulating layer is planarized; an oxygen-rich layer is formed on the gate insulating layer; an active layer is formed on the oxygen-rich layer; and a source is formed on the active layer And a drain; forming a passivation layer on the active layer, the source, and the drain.
  • the specific method for planarizing the surface of the gate insulating layer comprises: treating the surface of the gate insulating layer with a mass percentage of 0.5% to 2% of hydrofluoric acid for 30 s to 120 s.
  • a specific method for forming an oxygen-rich layer on the gate insulating layer comprises: treating the surface of the gate insulating layer with 60 to 90 s with 20 PPM to 30 PPM of ozone water.
  • a specific method for forming an active layer on the oxygen-rich layer includes: depositing an indium gallium zinc oxide layer on the oxygen-rich layer, and patterning the indium gallium zinc oxide layer deal with.
  • the surface of the gate insulating layer is flattened by planarizing the surface of the gate insulating layer and forming an oxygen-rich layer on the surface of the gate insulating layer, and oxygen vacancies on the surface of the gate insulating layer The defects are improved to stabilize the surface state of the gate insulating layer.
  • FIG. 1 is a schematic structural view of an array substrate according to an embodiment of the present invention.
  • FIGS. 2A through 2I are flowcharts showing the fabrication of an array substrate in accordance with an embodiment of the present invention.
  • FIG. 1 is a schematic structural view of an array substrate according to an embodiment of the present invention.
  • an array substrate includes: a substrate 100 , a thin film transistor 200 , and a pixel electrode 300 ; wherein the thin film transistor 200 and the pixel electrode 300 are both disposed on the substrate 100 , and the thin film transistor 200 and the pixel electrode 300 The drain connection.
  • the substrate 100 may be a transparent glass substrate or a resin substrate.
  • the thin film transistor 200 includes a gate electrode 210, a gate insulating layer 220, an oxygen-rich layer 230, an active layer 240, a source 250a, a drain 250b, and a passivation layer 260.
  • the gate 210 is disposed on the substrate 100.
  • the gate electrode 210 may be a single metal layer formed of molybdenum (Mo) or the like, or may be formed of molybdenum/aluminum (Mo/Al), molybdenum/titanium (Mo/Ti), molybdenum/copper (Mo/Cu), or the like. Multi-layer metal layer.
  • the gate insulating layer 220 is disposed on the substrate 100 and the gate 210.
  • the gate insulating layer 220 may be made of silicon oxide, silicon nitride/silicon oxide, and the thickness of the gate insulating layer 220 is to between.
  • the surface of the gate insulating layer 220 is planarized by a method in which the surface of the gate insulating layer 220 is treated with hydrofluoric acid having a mass percentage of 0.5% to 2% for 30 s to 120 s.
  • the surface of the gate insulating layer 220 is treated with hydrofluoric acid having a mass percentage of 1% for 60 s.
  • the oxygen-rich layer 230 is disposed on the gate insulating layer 220.
  • the surface of the gate insulating layer 220 is treated with 20 PPM (parts per million by weight) to 30 PPM of ozone water for 60 s to 90 s to form an oxygen-rich layer 230.
  • the surface of the gate insulating layer 220 is treated with 25 PPM of ozone water for 75 s.
  • the active layer 240 is disposed on the oxygen-rich layer 230.
  • the active layer 240 is made of indium gallium zinc oxide (IGZO).
  • the source 250a and the drain 250b are disposed on the active layer 240 with a space between the source 250a and the drain 250b.
  • the source 250a and the drain 250b also extend to the oxygen-rich layer 230, respectively, thereby completely covering the area on the oxygen-rich layer 230 except the area occupied by the active layer 240.
  • the passivation layer 260 is disposed on the source 250a, the drain 250b, and the active layer 240.
  • the passivation layer 260 may be made of silicon oxide (SiO x ).
  • the passivation layer 260 has a via 261 therein that exposes a portion of the drain 250b.
  • the pixel electrode 300 is disposed on the passivation layer 260, and the pixel electrode 300 is in contact with the exposed drain 250b through the via 261.
  • 2A through 2I are flowcharts showing the fabrication of an array substrate in accordance with an embodiment of the present invention.
  • Step 1 Referring to FIG. 2A, a substrate 100 is provided.
  • the substrate 100 may be a transparent glass substrate or a resin substrate.
  • a gate electrode 210 is formed on the substrate 100.
  • the gate electrode 210 may be a single metal layer formed of molybdenum (Mo) or the like, or may be formed of molybdenum/aluminum (Mo/Al), molybdenum/titanium (Mo/Ti), molybdenum/copper (Mo/Cu), or the like. Multi-layer metal layer.
  • Step 3 Referring to FIG. 2C, a gate insulating layer 220 is formed on the substrate 100 and the gate 210, and the surface of the gate insulating layer 220 is planarized.
  • the gate insulating layer 220 may be made of silicon oxide, silicon nitride/silicon oxide, and the thickness of the gate insulating layer 220 is to between.
  • a specific method of planarizing the surface of the gate insulating layer 220 is to treat the surface of the gate insulating layer 220 with hydrofluoric acid having a mass percentage of 0.5% to 2% for 30 s to 120 s.
  • the surface of the gate insulating layer 220 is treated with hydrofluoric acid having a mass percentage of 1% for 60 s.
  • Step 4 Referring to FIG. 2D, an oxygen-rich layer 230 is formed on the gate insulating layer 220.
  • a specific method of forming the oxygen-rich layer 230 includes treating the surface of the gate insulating layer 220 with 60 P to 90 s with 20 PPM (parts per million by weight) to 30 PPM of ozone water.
  • the surface of the gate insulating layer 220 is treated with 25 PPM of ozone water for 75 s.
  • Step 5 Referring to FIG. 2E, an active layer 240 is formed on the oxygen-rich layer 230.
  • the active layer 240 may be made of indium gallium zinc oxide (IGZO).
  • Step 6 Referring to FIG. 2F, a source 250a and a drain 250b are formed on the active layer 240; wherein there is a space between the source 250a and the drain 250b.
  • the source 250a and the drain 250b also extend to the oxygen-rich layer 230, respectively, thereby completely covering the area on the oxygen-rich layer 230 except the area occupied by the active layer 240.
  • Step 7 Referring to FIG. 2G, a passivation layer 260 is formed on the source 250a, the drain 250b, and the active layer 240.
  • the passivation layer 260 may be made of silicon oxide (SiO x ).
  • the passivation layer 260 has a via 261 therein that exposes a portion of the drain 250b.
  • Step 8 Referring to FIG. 2H, a via hole 261 is formed in the passivation layer 260, which exposes a portion of the drain 250b.
  • Step 9 Referring to FIG. 2I, a pixel electrode 300 is formed on the passivation layer 260. The pixel electrode 300 is in contact with the exposed drain 250b through the via 261.
  • the surface of the gate insulating layer is flattened by planarizing the surface of the gate insulating layer and forming an oxygen-rich layer on the surface of the gate insulating layer, and the gate insulating layer is insulated.
  • the oxygen vacancy defects on the surface of the layer are improved, thereby stabilizing the surface state of the gate insulating layer.

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Abstract

公开了一种薄膜晶体管，其包括：在基板（100）上的栅极（210）；在基板（100）和栅极（210）上的栅极绝缘层（220），所述栅极绝缘层（220）的表面被进行平整化处理；在所述栅极绝缘层（220）上的富氧层（230）；在所述富氧层（230）上的有源层（240）；在所述有源层（240）上的源极（250a）和漏极（250b）；在所述有源层（240）、所述源极（250a）和所述漏极（250b）上的钝化层（260）。还提供了该薄膜晶体管的制作方法及具有该薄膜晶体管的阵列基板。通过对栅极绝缘层的表面进行平整化以及在栅极绝缘层的表面形成富氧层，从而使栅极绝缘层的表面平整，并且栅极绝缘层的表面的氧空缺缺陷被改善，进而使栅极绝缘层的表面状态稳定。

Description

薄膜晶体管及其制作方法、阵列基板 技术领域
本发明属于显示技术领域，具体地讲，涉及一种薄膜晶体管及其制作方法、阵列基板。
背景技术
在IGZO(铟镓锌氧化物)薄膜晶体管中，由IGZO制作成的有源层生长在栅极绝缘层之上，也就是说栅极绝缘层材料的选择与栅极绝缘层表面的质量对IGZO薄膜晶体管的器件性能有极大影响。
目前，IGZO薄膜晶体管的栅极绝缘层普遍采用正硅酸乙酯(TEOS)或二氧化硅(SiO2)制成，其表面平整性较差且表面存在一些氧空缺缺陷，会使其表面状态不稳定，由此，与沉积在其上的IGZO有源层材料间的界面也发生改变。而薄膜晶体管器件的前沟道层就形成在这一界面附近，是薄膜晶体管器件中载流子的传输通道。因此沉积有源层后，在与栅极绝缘层的界面处会形成高浓度的缺陷态，这些缺陷态会俘获载流子而降低载流子的迁移率，使器件的特性变得不稳定，从而造成器件反向电流加大或击穿电压降低。
发明内容
为了解决上述现有技术存在的问题，本发明提供了一种能够改善栅极绝缘层表面特性的薄膜晶体管及其制作方法、阵列基板。
根据本发明的一方面，提供了一种薄膜晶体管，其包括：在基板上的栅极；在所述基板和所述栅极上的栅极绝缘层，所述栅极绝缘层的表面被进行平整化处理；在所述栅极绝缘层上的富氧层；在所述富氧层上的有源层；在所述有源层上的源极和漏极；在所述有源层、所述源极和所述漏极上的钝化层。
可选地，所述栅极绝缘层的表面被进行平整化处理的具体方法包括：所述栅极绝缘层的表面被质量百分比为0.5％～2％的氢氟酸处理30s～120s。
可选地，所述栅极绝缘层的表面被20PPM～30PPM的臭氧水处理60s～90s，以形成在所述栅极绝缘层上的富氧层。
可选地，所述有源层由铟镓锌氧化物制成。
根据本发明的另一方面，还提供了一种阵列基板，其包括：基板；上述的薄膜晶体管，设置于所述基板上；在所述薄膜晶体管的钝化层上的像素电极，所述钝化层中具有暴露出所述漏极的过孔，所述像素电极通过所述过孔与所述漏极连接。
根据本发明的又一方面，又提供了一种薄膜晶体管的制作方法，其包括：在基板上制作形成栅极；在所述基板和所述栅极上制作形成栅极绝缘层，并对所述栅极绝缘层的表面进行平整化处理；在所述栅极绝缘层上制作形成富氧层；在所述富氧层上制作形成有源层；在所述有源层上制作形成源极和漏极；在所述有源层、所述源极和所述漏极上制作形成钝化层。
可选地，对所述栅极绝缘层的表面进行平整化处理的具体方法包括：利用质量百分比为0.5％～2％的氢氟酸对所述栅极绝缘层的表面处理30s～120s。
可选地，在所述栅极绝缘层上制作形成富氧层的具体方法包括：利用20PPM～30PPM的臭氧水对所述栅极绝缘层的表面处理60s～90s。
可选地，在所述富氧层上制作形成有源层的具体方法包括：在所述富氧层上沉积形成铟镓锌氧化物层，并对所述铟镓锌氧化物层进行图案化处理。
本发明的有益效果：通过对栅极绝缘层的表面进行平整化以及在栅极绝缘层的表面形成富氧层，从而使栅极绝缘层的表面平整，并且栅极绝缘层的表面的氧空缺缺陷被改善，进而使栅极绝缘层的表面状态稳定。
附图说明
通过结合附图进行的以下描述，本发明的实施例的上述和其它方面、特点和优点将变得更加清楚，附图中：
图1是根据本发明的实施例的阵列基板的结构示意图；
图2A至图2I是根据本发明的实施例的阵列基板的制作流程图。
具体实施方式
以下，将参照附图来详细描述本发明的实施例。然而，可以以许多不同的形式来实施本发明，并且本发明不应该被解释为限制于这里阐述的具体实施例。相反，提供这些实施例是为了解释本发明的原理及其实际应用，从而使本领域的其他技术人员能够理解本发明的各种实施例和适合于特定预期应用的各种修改。
在附图中，为了清楚器件，夸大了层和区域的厚度。相同的标号在附图中始终表示相同的元件。
也将理解的是，在一元件被称为设置于另一元件“之上”或“上”时，它可以直接设置于该另一元件上，或者也可以存在中间元件。
图1是根据本发明的实施例的阵列基板的结构示意图。
参照图1，根据本发明的实施例的阵列基板包括：基板100、薄膜晶体管200、像素电极300；其中，薄膜晶体管200和像素电极300均设置在基板100上，并且薄膜晶体管200与像素电极300的漏极连接。
具体地，基板100可以是透明的玻璃基板或者树脂基板。
薄膜晶体管200包括：栅极210、栅极绝缘层220、富氧层230、有源层240、源极250a、漏极250b、钝化层260。
栅极210设置于基板100上。栅极210可以是由钼(Mo)等形成的单层金属层，也可以是由钼/铝(Mo/Al)、钼/钛(Mo/Ti)、钼/铜(Mo/Cu)等形成的多层金属层。
栅极绝缘层220设置于基板100和栅极210上。栅极绝缘层220可以由氧化硅、氮化硅/氧化硅制成，并且栅极绝缘层220的厚度在
Figure PCTCN2017088394-appb-000001
至
Figure PCTCN2017088394-appb-000002
之间。
在本实施例中，栅极绝缘层220的表面被进行平整化处理，其具体方法为：栅极绝缘层220的表面被质量百分比为0.5％～2％的氢氟酸处理30s～120s。优选地，利用质量百分比为1％的氢氟酸对栅极绝缘层220的表面处理60s。
富氧层230设置于栅极绝缘层220上。具体地，栅极绝缘层220的表面被20PPM(百万分比浓度)～30PPM的臭氧水处理60s～90s，以形成富氧层230。优选地，以25PPM的臭氧水对栅极绝缘层220的表面处理75s。这样，通过在栅极绝缘层220表面上形成富氧层230，可以消除栅极绝缘层220表面的氧空缺缺陷。
有源层240设置于富氧层230上。有源层240由铟镓锌氧化物(IGZO)制成。
源极250a和漏极250b设置于有源层240上，并且源极250a和漏极250b之间具有间隔。此外，源极250a和漏极250b还分别延伸至富氧层230上，从而将富氧层230上的除有源层240所占区域之外的区域全部覆盖。
钝化层260设置于源极250a、漏极250b和有源层240上。钝化层260可以由氧化硅(SiOx)制成。钝化层260中具有过孔261，该过孔261将漏极250b的部分暴露。
像素电极300设置于钝化层260上，并且像素电极300通过过孔261而与暴露的漏极250b连接接触。
以下，将对根据本发明的实施例的阵列基板的制作方法进行详细描述。图2A至图2I是根据本发明的实施例的阵列基板的制作流程图。
根据本发明的实施例的阵列基板的制作方法包括：
步骤一：参照图2A，提供一基板100。基板100可以是透明的玻璃基板或者树脂基板。
步骤二：参照图2B，在基板100上制作形成栅极210。栅极210可以是由钼(Mo)等形成的单层金属层，也可以是由钼/铝(Mo/Al)、钼/钛(Mo/Ti)、钼/铜(Mo/Cu)等形成的多层金属层。
步骤三：参照图2C，在基板100和栅极210上制作形成栅极绝缘层220，并对栅极绝缘层220的表面进行平整化处理。栅极绝缘层220可以由氧化硅、氮化硅/氧化硅制成，并且栅极绝缘层220的厚度在
Figure PCTCN2017088394-appb-000003
至
Figure PCTCN2017088394-appb-000004
之间。
这里，对栅极绝缘层220的表面进行平整化处理的具体方法为：利用质量百分比为0.5％～2％的氢氟酸对栅极绝缘层220的表面处理30s～120s。优选地，利用质量百分比为1％的氢氟酸对栅极绝缘层220的表面处理60s。
步骤四：参照图2D，在栅极绝缘层220上制作形成富氧层230。这里，形成富氧层230的具体方法包括：利用20PPM(百万分比浓度)～30PPM的臭氧水对栅极绝缘层220的表面处理60s～90s。优选地，利用25PPM的臭氧水对栅极绝缘层220的表面处理75s。这样，通过在栅极绝缘层220表面上形成富氧层230，可以消除栅极绝缘层220表面的氧空缺缺陷。
步骤五：参照图2E，在富氧层230上制作形成有源层240。有源层240可以由铟镓锌氧化物(IGZO)制成。
步骤六：参照图2F，在有源层240上制作形成源极250a和漏极250b；其中，源极250a和漏极250b之间具有间隔。此外，源极250a和漏极250b还分别延伸至富氧层230上，从而将富氧层230上的除有源层240所占区域之外的区域全部覆盖。
步骤七：参照图2G，在源极250a、漏极250b和有源层240上制作形成钝化层260。钝化层260可以由氧化硅(SiOx)制成。钝化层260中具有过孔261，该过孔261将漏极250b的部分暴露。
通过上述步骤二至步骤七，完成了薄膜晶体管200的制作。
步骤八：参照图2H，在钝化层260中制作形成过孔261，该过孔261将漏极250b的部分暴露。
步骤九：参照图2I，在钝化层260上制作形成像素电极300，该像素电极300通过过孔261而与暴露的漏极250b连接接触。
综上所述，根据本发明的实施例，通过对栅极绝缘层的表面进行平整化以及在栅极绝缘层的表面形成富氧层，从而使栅极绝缘层的表面平整，并且栅极绝缘层的表面的氧空缺缺陷被改善，进而使栅极绝缘层的表面状态稳定。
虽然已经参照特定实施例示出并描述了本发明，但是本领域的技术人员将 理解：在不脱离由权利要求及其等同物限定的本发明的精神和范围的情况下，可在此进行形式和细节上的各种变化。

Claims (12)

  1. 一种薄膜晶体管，其中，包括：
    在基板上的栅极；
    在所述基板和所述栅极上的栅极绝缘层，所述栅极绝缘层的表面被进行平整化处理；
    在所述栅极绝缘层上的富氧层；
    在所述富氧层上的有源层；
    在所述有源层上的源极和漏极；
    在所述有源层、所述源极和所述漏极上的钝化层。
  2. 根据权利要求1所述的薄膜晶体管，其中，所述栅极绝缘层的表面被进行平整化处理的具体方法包括：所述栅极绝缘层的表面被质量百分比为0.5％～2％的氢氟酸处理30s～120s。
  3. 根据权利要求1所述的薄膜晶体管，其中，所述栅极绝缘层的表面被20PPM～30PPM的臭氧水处理60s～90s，以形成在所述栅极绝缘层上的富氧层。
  4. 根据权利要求1所述的薄膜晶体管，其中，所述有源层由铟镓锌氧化物制成。
  5. 一种阵列基板，其中，包括：
    基板；
    在基板上的栅极；
    在所述基板和所述栅极上的栅极绝缘层，所述栅极绝缘层的表面被进行平整化处理；
    在所述栅极绝缘层上的富氧层；
    在所述富氧层上的有源层；
    在所述有源层上的源极和漏极；
    在所述有源层、所述源极和所述漏极上的钝化层
    在所述钝化层上的像素电极，所述钝化层中具有暴露出所述漏极的过孔，所述像素电极通过所述过孔与所述漏极连接。
  6. 根据权利要求5所述的阵列基板，其中，所述栅极绝缘层的表面被进行平整化处理的具体方法包括：所述栅极绝缘层的表面被质量百分比为0.5％～2％的氢氟酸处理30s～120s。
  7. 根据权利要求5所述的阵列基板，其中，所述栅极绝缘层的表面被20PPM～30PPM的臭氧水处理60s～90s，以形成在所述栅极绝缘层上的富氧层。
  8. 根据权利要求5所述的阵列基板，其中，所述有源层由铟镓锌氧化物制成。
  9. 一种薄膜晶体管的制作方法，其中，包括：
    在基板上制作形成栅极；
    在所述基板和所述栅极上制作形成栅极绝缘层，并对所述栅极绝缘层的表面进行平整化处理；
    在所述栅极绝缘层上制作形成富氧层；
    在所述富氧层上制作形成有源层；
    在所述有源层上制作形成源极和漏极；
    在所述有源层、所述源极和所述漏极上制作形成钝化层。
  10. 根据权利要求9所述的薄膜晶体管的制作方法，其中，对所述栅极绝缘层的表面进行平整化处理的具体方法包括：利用质量百分比为0.5％～2％的氢氟酸对所述栅极绝缘层的表面处理30s～120s。
  11. 根据权利要求9所述的薄膜晶体管的制作方法，其中，在所述栅极绝缘层上制作形成富氧层的具体方法包括：利用20PPM～30PPM的臭氧水对所述栅极绝缘层的表面处理60s～90s。
  12. 根据权利要求9所述的薄膜晶体管的制作方法，其中，在所述富氧层上制作形成有源层的具体方法包括：在所述富氧层上沉积形成铟镓锌氧化物层，并对所述铟镓锌氧化物层进行图案化处理。
PCT/CN2017/088394 2017-04-05 2017-06-15 薄膜晶体管及其制作方法、阵列基板 Ceased WO2018184294A1 (zh)

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