WO2018184288A1 - 基于多孔DBR的GaN基VCSEL芯片及制备方法 - Google Patents

基于多孔DBR的GaN基VCSEL芯片及制备方法 Download PDF

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WO2018184288A1
WO2018184288A1 PCT/CN2017/086855 CN2017086855W WO2018184288A1 WO 2018184288 A1 WO2018184288 A1 WO 2018184288A1 CN 2017086855 W CN2017086855 W CN 2017086855W WO 2018184288 A1 WO2018184288 A1 WO 2018184288A1
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layer
dbr
porous
gan
doped gan
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French (fr)
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赵丽霞
杨超
刘磊
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中国科学院半导体研究所
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Priority to US16/500,035 priority Critical patent/US11258231B2/en
Publication of WO2018184288A1 publication Critical patent/WO2018184288A1/zh

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Definitions

  • the present disclosure relates to the field of laser light sources, and in particular to a GaN-based VCSEL (vertical cavity surface emitting laser), and more particularly to a GaN-based VCSEL chip based on a porous DBR (Bragd mirror) bottom mirror and a preparation method thereof.
  • a GaN-based VCSEL vertical cavity surface emitting laser
  • a GaN-based VCSEL chip based on a porous DBR (Bragd mirror) bottom mirror and a preparation method thereof.
  • GaN semiconductor-based lasers have shown great application prospects and market demands in high-density optical storage, laser illumination, laser display, visible light communication, etc. In recent years, they have attracted much attention in international research and industry. At present, GaN-based edge-emitting lasers have been commercialized, and vertical cavity surface emitting lasers (VCSELs) with superior performance have not yet reached a practical level. Compared with traditional edge-emitting lasers, GaN-based VCSELs have good dynamic single-mode and space-emission models, low operating threshold, small beam divergence angle, low manufacturing cost, high temperature stability, and high performance. Two-dimensional array integration of density and higher power light output. Therefore, the application prospect of GaN-based VCSELs is broader.
  • the difficulty is to obtain an optical cavity of high quality factor, especially the realization of a highly reflective bottom mirror constituting the cavity.
  • the top mirror can be a well-processed dielectric DBR, such as a SiO 2 /TiO 2 system DBR, while the bottom mirror needs to be directly embedded on the substrate side in the epitaxial structure of the VCSEL, such as an epitaxial AlN/GaN system.
  • Another alternative is to peel off the epitaxial layer from the substrate by laser lift-off and then The GaN surface deposition medium DBR layer or metal mirror is peeled off and then thermobonded or plated with other substrates.
  • the method avoids the problem of the epitaxial nitride DBR, and can realize a high reflectivity bottom mirror, which is favorable for obtaining a high quality factor resonant microcavity.
  • the method of laser stripping is costly, and the bottom of the epitaxial layer after peeling is very uneven, and it needs to be chemically polished to achieve flattening of the peeling surface, thereby reducing scattering loss.
  • the method of re-depositing the substrate DBR bottom mirror by stripping the substrate has a complicated device process and is expensive, and is not ideal for practical GaN-based VCSELs.
  • the layer is converted into a DBR structure in which the porous layer and the non-porous layer are alternately stacked by lateral electrochemical etching, thereby realizing high-quality embedding of the VCSEL bottom mirror.
  • the dielectric DBR layer is used as the top mirror, and the device preparation is completed by the VCSEL conventional process.
  • the present disclosure provides a porous DBR-based GaN-based VCSEL chip, comprising:
  • a substrate the material of which is sapphire, silicon or silicon carbide;
  • An n-type doped GaN layer is formed on an upper surface of the bottom porous DBR layer, and a periphery of the n-type doped GaN layer is etched downward to form a mesa having a depth smaller than the n-type doped GaN a thickness of the layer, wherein the middle of the n-type doped GaN layer is a convex portion;
  • An electron blocking layer formed on an upper surface of the active layer
  • a current limiting layer which is an insulating medium, is formed on an upper surface and a side surface of the p-type doped GaN layer, a current window is formed at a center of the current confinement layer, and the current confinement layer covers the active layer and the electron blocking layer And n-type doping the sidewalls of the raised portion of the GaN layer and covering a portion of the mesa;
  • a p-electrode formed on the periphery of the transparent electrode with a recess formed therein;
  • a dielectric DBR layer is formed on the upper surface of the transparent electrode in the p-electrode recess.
  • the present disclosure also provides a method for preparing a GaN-based VCSEL chip based on a porous DBR, comprising the following steps:
  • Step 1 sequentially growing a buffer layer, alternately stacked lightly doped layers and heavily doped layers, an n-type doped GaN layer, an active layer, an electron blocking layer, and a p-doped GaN layer on a substrate,
  • the material of the substrate is sapphire, silicon or silicon carbide;
  • Step 2 performing lateral etching on the alternately stacked lightly doped layer and the heavily doped layer by electrochemical etching, and converting it into a bottom porous DBR layer in which the porous layer and the non-porous layer are alternately stacked;
  • Step 3 etching down the periphery of the p-doped GaN layer, the etching depth reaches the n-type doped GaN layer, and the mesa is formed around the n-doped GaN layer;
  • Step 4 preparing a current limiting layer on the sidewalls of the p-doped GaN layer, the mesa, the active layer, and the electron blocking layer;
  • Step 5 using a photolithography and etching technique to open a current window on the current confinement layer and remove a portion of the current confinement layer on the mesa;
  • Step 6 preparing a transparent electrode at a current window on the p-doped GaN layer
  • Step 7 preparing an n-electrode and a p-electrode on a mesa surface on which a part of the current confinement layer is removed and a periphery of the transparent electrode, wherein a recess is formed in the middle of the p-electrode;
  • Step 8 Prepare a dielectric DBR layer on the upper surface of the transparent electrode in the recess of the p-electrode to complete device preparation.
  • the beneficial effect of the present disclosure is that since the porous DBR only needs epitaxial doping concentration period modulation
  • the GaN layer is prepared by electrochemical etching, and there is no lattice mismatch problem, and the implementation process is simple and reproducible, and can be directly embedded in the bottom of the chip, which is beneficial to practical applications.
  • the highly reflective porous DBR is used as the bottom mirror, and the mature medium DBR is used as the top mirror to form the optical resonant cavity, which is beneficial to obtain high quality factor GaN-based electrically pumped VCSEL devices, thereby satisfying optical storage and optical communication.
  • display and other fields for high-power output, high-density integrated light source requirements are examples of the GaN layer.
  • Figure 1 is a schematic structural view of an embodiment of the present disclosure
  • Figure 3 is a bottom porous DBR scanning electron microscope image of Figure 1;
  • the present disclosure provides a porous DBR-based GaN-based VCSEL chip, including:
  • the substrate 10 may be a planar or patterned substrate, the material of the substrate 10 may be sapphire, silicon or silicon carbide;
  • a buffer layer 11 is formed on the upper surface of the substrate 10.
  • the buffer layer 11 is composed of a low-temperature GaN nucleation layer and an unintentionally doped GaN layer, and can be used as a nitrogen source, trimethylgallium or triethylamine.
  • a Ga source gallium firstly grows a GaN nucleation layer at a low temperature, and then thermally grows an unintentionally doped GaN layer.
  • Materials useful as nucleation layers also include AlN, ZnO or graphene;
  • the material of the bottom porous DBR layer 12 is GaN, AlGaN, InGaN or AlInGaN, or a combination of a porous layer and a non-porous layer of the above material combination Multi-cycle DBR;
  • the bottom porous DBR layer 12 is obtained by electrochemically etching the lightly doped layer and the heavily doped layer which are alternately stacked, wherein the heavily doped layer has a typical doping concentration of 1 ⁇ 10 19 cm -3 , lightly doped layer a typical concentration of 5 ⁇ 10 16 cm -3 , the number of cycles of the bottom porous DBR layer 12 may be 12;
  • n-type GaN layer is further grown between the bottom porous DBR layer 12 and the buffer layer 11 as a current spreading layer dedicated to electrochemical etching to form the bottom porous DBR layer 12;
  • An active layer 14 is formed on the convex portion 13" of the n-type doped GaN layer 13.
  • the active layer 14 is an InGaN/GaN multiple quantum well structure, and its luminescence peak is located near 520 nm, and is porous at the bottom.
  • the high reverse band of the DBR layer 12 corresponds to achieve a matching of the emission wavelength and the resonant wavelength;
  • An electron blocking layer 15 is formed on the upper surface of the active layer 14, the electron blocking layer 15 is an AlGaN material, and can be p-type doped, the dopant is ferrocene;
  • a p-type doped GaN layer 16 which is formed on the upper surface of the electron blocking layer 15;
  • a typical current window is a circular hole pattern having a diameter of 10-30 ⁇ m; the current confinement layer 17 covers the active layer 14, the electron blocking layer 15, and the n-type doped GaN layer 13 convex The sidewall of the portion 13" and covering a portion of the mesa 13' to achieve sidewall passivation, reducing leakage paths of the device;
  • the material of the current confinement layer 17 is SiO 2 , SiN x , HfO 2 or Al 2 O 3 ;
  • a transparent electrode 18 is formed on the current confinement layer 17 and the current window 17' above the p-doped GaN layer 16.
  • the material used as the transparent electrode comprises indium-doped tin oxide ITO, graphene, ZnO thin film. , transparent metal or nano silver wire, or a composite film material;
  • a p-electrode 21 formed on the periphery of the transparent electrode 18 with a recess formed therein;
  • the metal material used for the n electrode 20 and the p electrode 21 is Cr/Al/Ti/Au, Cr/Pt/Au, Ni/Au, Ni/Ag/Pt/Au, Ti/Au or Ti/Pt/Au;
  • a dielectric DBR layer 19 is formed on the upper surface of the transparent electrode 18 in the recess of the p-electrode 21 as a top mirror, and the dielectric DBR layer 19 may be multi-period SiO 2 /TiO 2 , SiO 2 /Ta 2 O 5 , TiO 2 /Al 2 O 3 or ZrO 2 /SiO 2 structure; the dielectric layer also includes a phase adjustment layer on the side close to the transparent electrode 18 to adjust the electric field distribution in the VCSEL to minimize the absorption of the transparent electrode 18 loss.
  • the dielectric DBR layer 19 and the bottom porous DBR layer 12 respectively constitute upper and lower mirrors of the VCSEL chip, and the reflectivity of the bottom porous DBR layer 12 near the luminescence peak of the active layer 14 is above 95% and higher than the dielectric DBR layer 19 So that the VCSEL device emits light from the side of the top dielectric DBR layer.
  • the present disclosure provides a method for fabricating a porous DBR-based GaN-based VCSEL chip, including the following steps:
  • Step 1 sequentially growing a buffer layer 11, alternating lightly doped layers, an n-type doped GaN layer 13, an active layer 14, an electron blocking layer 15, and a p-doped GaN layer 16 on a substrate 10.
  • the material of the substrate 10 is sapphire, silicon or silicon carbide
  • the material of the bottom porous DBR layer 12 is a multi-period DBR formed by alternately stacking a nitride porous layer and a non-porous layer, and the constituent material thereof is GaN, AlGaN, InGaN or AlInGaN, or a combination of the above materials, a layer of n-type GaN is further grown between the bottom porous DBR layer 12 and the buffer layer 11. a layer, as a current spreading layer dedicated to electrochemical etching to form a porous DBR;
  • Step 2 performing electrochemical etching on the alternating stacked light and heavy doped layers, and converting them into a bottom porous DBR layer 12 in which the porous layer and the non-porous layer are alternately stacked;
  • Step 3 etching down the periphery of the p-doped GaN layer 16 to etch the depth into the n-doped GaN layer 13, and forming a mesa 13' around the n-doped GaN layer 13;
  • Step 4 Preparing a current confinement layer 17 on the sidewalls of the p-doped GaN layer 16, the mesa 13', the active layer 14, and the electron blocking layer 15 to achieve carrier narrowing and sidewall passivation, and reduce the device a leakage path; wherein the material of the current confinement layer 17 is SiO 2 , SiN x , HfO 2 or Al 2 O 3 ;
  • Step 5 using a photolithography, etching technique to open a current window 17' on the current confinement layer 17 and remove a portion of the current confinement layer 17 on the mesa 13';
  • Step 6 preparing a transparent electrode 18 at the current window 17' on the p-doped GaN layer 16;
  • Step 7 preparing an n-electrode 20 and a p-electrode 21 on the mesa 13' from which the partial current confinement layer 17 is removed and the periphery of the transparent electrode 18, and a recess is formed in the middle of the p-electrode 21;
  • the metal material used for the n electrode 20 and the p electrode 21 is Cr/Al/Ti/Au, Cr/Pt/Au, Ni/Au, Ni/Ag/Pt/Au, Ti/Au or Ti/Pt/Au;
  • Step 8 Prepare a dielectric DBR layer 19 on the upper surface of the transparent electrode 18 in the recess of the p-electrode 21 to complete the device preparation.
  • the dielectric DBR layer 19 is multi-period SiO 2 /TiO 2 , SiO 2 /Ta 2 O 5 , TiO. 2 /Al 2 O 3 or ZrO 2 /SiO 2 structure.
  • the present disclosure provides a scanning electron microscope image of a GaN base porous DBR layer 12 and its corresponding reflection spectrum.
  • the porous layer in FIG. 3 is a heavily doped GaN layer after electrochemical etching, and the unetched GaN layer is a lightly doped layer.
  • the two layers of material have a refractive index difference due to the introduction of the air gap and are alternately stacked to form a bottom porous DBR layer.
  • the abscissa in the reflection spectrum of Fig. 4 is the wavelength, and the ordinate is the reflectance.
  • the bottom porous DBR layer 12 has a very high reflectance near 520 nm and a wide high reflection band, which can satisfy The requirements of GaN-based green VCSELs for high reflectivity bottom mirrors.
  • the resonant cavity can be fundamentally broken.
  • Technical barrier to the bottom mirror of the rate By periodically etching a periodic GaN epitaxial structure in which an undoped layer (or lightly doped layer) and a heavily doped layer are alternately stacked, a lateral air hole can be selectively formed in the heavily doped layer, thereby changing the material of the layer.
  • the effective refractive index, non-doped layer (or lightly doped layer) is not affected by corrosion.
  • the introduction of the air gap will cause a certain refractive index difference between the porous GaN layer and the non-porous layer, thereby forming a DBR composite structure in which the porous GaN layer and the non-porous layer are alternately stacked.
  • a GaN-based VCSEL was prepared using the dielectric DBR layer as a top mirror.

Abstract

一种基于多孔DBR的GaN基VCSEL芯片及其制备方法，其中芯片包括：一衬底(10)；制作在衬底(10)上的缓冲层(11)；制作在缓冲层(11)上的底部多孔DBR层(12)；制作在底部多孔DBR层(12)上的n型掺杂GaN层(13)及外围向下刻蚀形成有台面(13')；制作在n型掺杂GaN层(13)上的有源层(14)；制作在有源层(14)上的电子阻挡层(15)；制作在电子阻挡层(15)上的p型掺杂GaN层(16)；制作在p型掺杂GaN层(16)上的电流限制层(17)，其中心形成有电流窗口(17')，且电流限制层(17)覆盖有源层(14)、电子阻挡层(15)和n型掺杂GaN层(13)凸起部分(13")的侧壁；制作在p型掺杂GaN层(16)上的透明电极(18)；制作在n型掺杂GaN层(13)台面(13')上的n电极(20)；制作在透明电极(18)上的p电极(21)，中间形成有凹缺；制作在p电极(21)凹缺内透明电极(18)上的介质DBR层(19)。

Description

基于多孔DBR的GaN基VCSEL芯片及制备方法 技术领域
本公开属于激光光源领域，具体涉及一种GaN基VCSEL(垂直腔面发射激光器)，特别涉及一种基于多孔DBR(布拉格反射镜)底部反射镜的GaN基VCSEL芯片及制备方法。
背景技术
GaN半导体基激光器在高密度光存储、激光照明、激光显示、可见光通信等领域展现出了巨大的应用前景和市场需求，近年来在国际科研和产业界备受关注。目前，GaN基边发射激光器已实现了商品化，而性能更为优异的垂直腔面发射激光器(VCSEL)尚未达到实用化水平。和传统的边发射激光器相比，GaN基VCSEL具有良好的动态单模特性和空间发射模特性，且工作阈值低、光束发散角小，具有制作成本低、温度稳定性高等优点，还可以实现高密度的二维阵列集成和更高功率的光输出。因此，GaN基VCSEL的应用前景更为广阔。
不过，对于已报道的GaN基VCSEL，其难点是获得高品质因子的光学谐振腔，特别是构成谐振腔的高反射性底部反射镜的实现。通常，其顶部反射镜可采用工艺成熟的介质DBR，如SiO2/TiO2体系DBR，而底部反射镜则需要在VCSEL的外延结构中直接在衬底一侧生长嵌入，如外延AlN/GaN系的氮化物DBR层，且底镜反射率一般要求越高越好。由于AlN/GaN的晶格失配和热膨胀系数差异，实际过程中制备高质量AlN/GaN系DBR困难极大。同时，由于AlN/GaN的折射率差较小，往往需要增加更多DBR的周期数并引入超晶格插入层来实现反射镜的高反射率，这将进一步增加AlN/GaN系DBR的外延难度。因此，以AlN/GaN系为代表的氮化物DBR生长程序复杂，外延条件极为苛刻且重复率不高。
另一种可替代方案是通过激光剥离使外延层从衬底上脱落，然后在 剥离GaN面沉积介质DBR层或金属反射镜再与其它衬底热压键合或电镀铜衬底。该方法规避了外延氮化物DBR的难题，可以实现高反射率的底部反射镜，有利于获得高品质因子的谐振微腔。不过激光剥离的方法成本较高，且剥离后的外延层底部很不平整，需要经过化学磨拋以实现剥离面的平坦化，从而降低散射损耗。此外，为了尽量减轻激光剥离对有源区的影响，往往需要采用较长的谐振腔长使有源区远离剥离面，但这会降低谐振腔的品质因子。因此，通过剥离衬底再沉积介质DBR底部反射镜的方法，其器件工艺复杂且成本昂贵，对于实用化GaN基VCSEL并不理想。
发明内容
本公开的目的在于，提供一种基于多孔DBR的GaN基VCSEL芯片及制备方法，其是以横向多孔DBR作为GaN基VCSEL的底部反射镜，通过在VCSEL外延结构中直接生长交替堆叠的轻重掺杂层，并经横向电化学腐蚀将其转变为多孔层与非多孔层交替堆叠的DBR结构，从而实现VCSEL底部反射镜的高质量嵌入。在此基础上，以介质DBR层作为顶部反射镜，采用VCSEL常规工艺完成器件制备。
为达到上述目的，本公开提供一种基于多孔DBR的GaN基VCSEL芯片，包括：
一衬底，该衬底的材料为蓝宝石、硅或碳化硅；
一缓冲层，其制作在衬底的上表面；
一底部多孔DBR层，其制作在缓冲层的上表面；
一n型掺杂GaN层，其制作在底部多孔DBR层的上表面，所述n型掺杂GaN层的外围向下刻蚀形成有台面，所述台面的深度小于所述n型掺杂GaN层的厚度，所述n型掺杂GaN层的中间为凸起部分；
一有源层，其制作在所述n型掺杂GaN层的凸起部分上；
一电子阻挡层，其制作在所述有源层的上表面；
一p型掺杂GaN层，其制作在所述电子阻挡层的上表面；
一电流限制层，为绝缘介质，其制作在所述p型掺杂GaN层的上表面及侧面，该电流限制层的中心形成有电流窗口，且该电流限制层覆盖有源层、电子阻挡层和n型掺杂GaN层凸起部分的侧壁，并覆盖部分台面；
一透明电极，其制作在所述p型掺杂GaN层上面的电流限制层及电流窗口处；
一n电极，其制作在n型掺杂GaN层的台面上；
一p电极，其制作在所述透明电极上面的四周，中间形成有凹缺；
一介质DBR层，其制作在所述p电极凹缺内透明电极的上表面。
本公开还提供一种基于多孔DBR的GaN基VCSEL芯片的制备方法，包括如下步骤：
步骤1：在一衬底上依次生长缓冲层、交替堆叠的轻掺杂层和重掺杂层、n型掺杂GaN层、有源层、电子阻挡层和p型掺杂GaN层，所述衬底的材料为蓝宝石、硅或碳化硅；
步骤2：采用电化学腐蚀的方法对交替堆叠的轻掺杂层和重掺杂层进行横向腐蚀，将其转变为多孔层和非多孔层交替堆叠的底部多孔DBR层；
步骤3：在p型掺杂GaN层上的四周向下刻蚀，刻蚀深度到达n型掺杂GaN层内，在n型掺杂GaN层的四周形成台面；
步骤4：在p型掺杂GaN层、台面、有源层和电子阻挡层的侧壁制备电流限制层；
步骤5：采用光刻、腐蚀技术在电流限制层上开一电流窗口并去掉台面上的部分电流限制层；
步骤6：在p型掺杂GaN层上的电流窗口处制备一透明电极；
步骤7：在去掉部分电流限制层的台面上和透明电极的四周分别制备n电极和p电极，该p电极的中间形成有凹缺；
步骤8：在p电极的凹缺内透明电极的上表面制备介质DBR层，完成器件制备。
本公开的有益效果是，由于多孔DBR只需外延掺杂浓度周期调制 的GaN层，并采用电化学腐蚀的方法制备，不存在晶格失配问题，且实现过程简单、可重复性高，可以直接嵌入在芯片底部，利于实际应用。同时，以高反射性多孔DBR为底部反射镜，以技术成熟的介质DBR为顶部反射镜构成光学谐振腔，有利于获得高品质因子的GaN基电泵浦VCSEL器件，从而满足光存储、光通信及显示等领域对于高功率输出、高密度集成的光源需求。
附图说明
为使本公开的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图对本公开做进一步详细说明。这里以绿光多孔DBR及其VCSEL作为优选实施例进行说明。其中：
图1为本公开实施例的结构示意图；
图2为本公开实施例的制备流程图；
图3为图1的底部多孔DBR扫描电子显微镜图片；
图4为与图3对应的反射谱图。
具体实施方式
在本公开中，术语“包括”和“含有”及其派生词意为包括而非限制。
需要说明的是，本公开中提到的方向用语，例如“上”、“下”、“前”、“后”、“左”、“右”等，仅是参考附图的方向，并非用来限制本发明的保护范围。贯穿附图，相同的元素由相同或相近的附图标记来表示。在可能导致对本发明的理解造成混淆时，将省略常规结构或构造。并且图中各部件的形状和尺寸不反映真实大小和比例，而仅示意本公开实施例的内容。
请参阅图1，本公开提供一种基于多孔DBR的GaN基VCSEL芯片，包括：
一衬底10，衬底10可以为平面或图形衬底，该衬底10的材料可以为蓝宝石、硅或碳化硅；
一缓冲层11，其制作在衬底10的上表面，该缓冲层11由低温GaN形核层和非故意掺杂GaN层构成，可以高纯纯氨气作为氮源，三甲基镓或三乙基镓作为Ga源，先低温生长GaN形核层，再高温生长非故意掺杂GaN层。可用作形核层的材料还包括AlN、ZnO或石墨烯；
一底部多孔DBR层12，其制作在缓冲层11的上表面，所述底部多孔DBR层12的材料为GaN、AlGaN、InGaN或AlInGaN，或以上材料组合的多孔层和非多孔层交替堆叠构成的多周期DBR；
其中，所述底部多孔DBR层12通过电化学腐蚀交替堆叠的轻掺杂层和重掺杂层获得，其中重掺杂层的典型掺杂浓度为1×1019cm-3，轻掺杂层的典型浓度5×1016cm-3，底部多孔DBR层12的周期数可以为12；
所述底部多孔DBR层12和缓冲层11之间还生长有一层n型GaN层，作为专用于电化学腐蚀形成底部多孔DBR层12的电流扩展层；
一n型掺杂GaN层13，掺杂剂为硅烷，典型掺杂浓度为1×1018cm-3，其制作在底部多孔DBR层12的上表面，所述n型掺杂GaN层13的外围向下刻蚀形成有台面13’，所述台面13’的深度小于所述n型掺杂GaN层13的厚度，所述n型掺杂GaN层13的中间为凸起部分13”；
一有源层14，其制作在所述n型掺杂GaN层13的凸起部分13”上，该有源层14为InGaN/GaN多量子阱结构，其发光峰位于520nm附近，与底部多孔DBR层12的高反带对应，以实现发光波长与谐振波长的匹配；
一电子阻挡层15，其制作在所述有源层14的上表面，该电子阻挡层15为AlGaN材料，可进行p型掺杂，掺杂剂为二茂镁；
一p型掺杂GaN层16，其制作在所述电子阻挡层15的上表面；
一电流限制层17，可以为绝缘介质，其制作在所述p型掺杂GaN层16的上表面及侧面，该电流限制层17的中心形成有电流窗口17’，以实现载流子窄化，典型的电流窗口为直径在10-30μm的圆孔图形；该电流限制层17覆盖有源层14、电子阻挡层15和n型掺杂GaN层13凸 起部分13”的侧壁，并覆盖部分台面13’以实现侧壁钝化，减小器件的漏电通道；
其中所述电流限制层17的材料为SiO2、SiNx、HfO2或Al2O3；
一透明电极18，其制作在所述p型掺杂GaN层16上面的电流限制层17及电流窗口17’处，可用作透明电极的材料包括为掺铟氧化锡ITO，石墨烯、ZnO薄膜、透明金属或纳米银线，或以上复合薄膜材料；
一n电极20，其制作在n型掺杂GaN层13的台面13’上；
一p电极21，其制作在所述透明电极18上面的四周，中间形成有凹缺；
其中所述n电极20和p电极21所用金属材料为Cr/Al/Ti/Au、Cr/Pt/Au、Ni/Au、Ni/Ag/Pt/Au、Ti/Au或Ti/Pt/Au；
一介质DBR层19，其制作在所述p电极21凹缺内的透明电极18的上表面作为顶部反射镜，该介质DBR层19可以为多周期SiO2/TiO2、SiO2/Ta2O5、TiO2/Al2O3或ZrO2/SiO2结构；该介质层中靠近透明电极18一侧还包含一相位调整层，以调整VCSEL中的电场分布，尽可能降低透明电极18的吸收损耗。
其中介质DBR层19和底部多孔DBR层12分别构成VCSEL芯片的上、下反射镜，且底部多孔DBR层12在有源层14发光峰附近的反射率在95％以上并高于介质DBR层19，以使VCSEL器件从顶部介质DBR层一侧出光。
请参阅图2并结合参阅图1所示，本公开提供一种基于多孔DBR的GaN基VCSEL芯片的制备方法，包括如下步骤：
步骤1：在一衬底10上依次生长缓冲层11、交替堆叠的轻重掺杂层、n型掺杂GaN层13、有源层14、电子阻挡层15和p型掺杂GaN层16；
其中所述衬底10的材料为蓝宝石、硅或碳化硅，所述底部多孔DBR层12的材料为氮化物多孔层和非多孔层交替堆叠构成的多周期DBR，其构成材料为GaN、AlGaN、InGaN或AlInGaN，或以上材料的组合材料，所述底部多孔DBR层12和缓冲层11之间还生长有一层n型GaN 层，作为专用于电化学腐蚀形成多孔DBR的电流扩展层；
步骤2：采用电化学腐蚀的方法对交替堆叠的轻重掺杂层进行横向腐蚀，将其转变为多孔层和非多孔层交替堆叠的底部多孔DBR层12；
步骤3：在p型掺杂GaN层16上的四周向下刻蚀，刻蚀深度到达n型掺杂GaN层13内，并在n型掺杂GaN层13的四周形成台面13’；
步骤4：在p型掺杂GaN层16、台面13’、有源层14和电子阻挡层15的侧壁制备电流限制层17，以实现载流子窄化和侧壁钝化，减小器件的漏电通道；其中所述电流限制层17的材料为SiO2、SiNx、HfO2或Al2O3；
步骤5：采用光刻、腐蚀技术在电流限制层17上开一电流窗口17’并去掉台面13’上的部分电流限制层17；
步骤6：在p型掺杂GaN层16上的电流窗口17’处制备一透明电极18；
步骤7：在去掉部分电流限制层17的台面13’上和透明电极18的四周分别制备n电极20和p电极21，该p电极21的中间形成有凹缺；
其中所述n电极20和p电极21所用金属材料为Cr/Al/Ti/Au、Cr/Pt/Au、Ni/Au、Ni/Ag/Pt/Au、Ti/Au或Ti/Pt/Au；
步骤8：在p电极21的凹缺内透明电极18的上表面制备介质DBR层19，完成器件制备，该介质DBR层19为多周期SiO2/TiO2、SiO2/Ta2O5、TiO2/Al2O3或ZrO2/SiO2结构。
请参阅图3并结合参阅图4所示，本公开提供一种GaN基底部多孔DBR层12的扫描电子显微镜图片及其对应的反射谱图。其中，图3内的多孔层为经电化学腐蚀后的重掺杂GaN层，而未腐蚀的GaN层为轻掺杂层。两层材料由于空气隙的引入存在折射率差，并交替堆叠构成底部多孔DBR层。图4反射谱中的横坐标为波长，纵坐标为反射率，从反射谱图可以看出，该底部多孔DBR层12在520nm附近具有极高的反射率以及较宽的高反射带，可以满足GaN基绿光VCSEL对于高反射率底部反射镜的要求。
通过本公开实施例的横向多孔DBR，可以从根本上突破谐振腔高反 射率底部反射镜的技术壁垒。通过电化学腐蚀非掺杂层(或轻掺杂层)和重掺杂层交替堆叠的周期性GaN外延结构，可选择性的在重掺杂层内形成横向空气孔道，从而改变该层材料的有效折射率，而非掺杂层(或轻掺杂层)则不受腐蚀影响。空气隙的引入将使多孔GaN层与非多孔层产生一定的折射率差，从而形成多孔GaN层和非多孔层交替堆叠的DBR复合结构。在此基础上，以介质DBR层作为顶部反射镜，制备GaN基VCSEL。
以上所述的具体实施例，对本公开的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本公开的具体实施例而已，并不用于限制本公开，凡在本公开的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (10)

  1. 一种基于多孔DBR的GaN基VCSEL芯片，包括：
    一衬底，该衬底的材料为蓝宝石、硅或碳化硅；
    一缓冲层，其制作在衬底的上表面；
    一底部多孔DBR层，其制作在缓冲层的上表面；
    一n型掺杂GaN层，其制作在底部多孔DBR层的上表面，所述n型掺杂GaN层的外围向下刻蚀形成有台面，所述台面的深度小于所述n型掺杂GaN层的厚度，所述n型掺杂GaN层的中间为凸起部分；
    一有源层，其制作在所述n型掺杂GaN层的凸起部分上；
    一电子阻挡层，其制作在所述有源层的上表面；
    一p型掺杂GaN层，其制作在所述电子阻挡层的上表面；
    一电流限制层，为绝缘介质，其制作在所述p型掺杂GaN层的上表面及侧面，该电流限制层的中心形成有电流窗口，且该电流限制层覆盖有源层、电子阻挡层和n型掺杂GaN层凸起部分的侧壁，并覆盖部分台面；
    一透明电极，其制作在所述p型掺杂GaN层上面的电流限制层及电流窗口处；
    一n电极，其制作在n型掺杂GaN层的台面上；
    一p电极，其制作在所述透明电极上面的四周，中间形成有凹缺；
    一介质DBR层，其制作在所述p电极凹缺内透明电极的上表面。
  2. 根据权利要求1所述的基于多孔DBR的GaN基VCSEL芯片，其中所述介质DBR层和底部多孔DBR层分别构成VCSEL芯片的上、下反射镜；且底部多孔DBR层在有源层发光峰附近的反射率在95％以上并高于介质DBR层。
  3. 根据权利要求1所述的基于多孔DBR的GaN基VCSEL芯片，其中所述底部多孔DBR层的结构为氮化物多孔层和非多孔层交替堆叠构成的DBR。
  4. 根据权利要求1所述的基于多孔DBR的GaN基VCSEL芯片， 其中所述电流限制层的材料为SiO2、SiNx、HfO2或Al2O3。
  5. 根据权利要求1所述的基于多孔DBR的GaN基VCSEL芯片，其中所述底部多孔DBR层和缓冲层之间还生长有一层n型GaN层，作为专用于电化学腐蚀形成底部多孔DBR层的电流扩展层。
  6. 一种基于多孔DBR的GaN基VCSEL芯片的制备方法，包括如下步骤：
    步骤1：在一衬底上依次生长缓冲层、交替堆叠的轻掺杂层和重掺杂层、n型掺杂GaN层、有源层、电子阻挡层和p型掺杂GaN层，所述衬底的材料为蓝宝石、硅或碳化硅；
    步骤2：采用电化学腐蚀的方法对交替堆叠的轻掺杂层和重掺杂层进行横向腐蚀，将其转变为多孔层和非多孔层交替堆叠的底部多孔DBR层；
    步骤3：在p型掺杂GaN层上的四周向下刻蚀，刻蚀深度到达n型掺杂GaN层内，在n型掺杂GaN层的四周形成台面；
    步骤4：在p型掺杂GaN层、台面、有源层和电子阻挡层的侧壁制备电流限制层；
    步骤5：采用光刻、腐蚀技术在电流限制层上开一电流窗口并去掉台面上的部分电流限制层；
    步骤6：在p型掺杂GaN层上的电流窗口处制备一透明电极；
    步骤7：在去掉部分电流限制层的台面上和透明电极的四周分别制备n电极和p电极，该p电极的中间形成有凹缺；
    步骤8：在p电极的凹缺内透明电极的上表面制备介质DBR层，完成器件制备。
  7. 根据权利要求6所述的基于多孔DBR的GaN基VCSEL芯片的制备方法，其中介质DBR层和底部多孔DBR层分别构成VCSEL芯片的上、下反射镜，且底部多孔DBR层在有源层发光峰附近的反射率在95％以上并高于介质DBR层。
  8. 根据权利要求6所述的基于多孔DBR的GaN基VCSEL芯片的制备方法，其中所述底部多孔DBR层的材料为氮化物多孔层和非多孔 层交替堆叠构成的多周期DBR。
  9. 根据权利要求6所述的基于多孔DBR的GaN基VCSEL芯片的制备方法，其中所述电流限制层的材料为SiO2、SiNx、HfO2或Al2O3。
  10. 根据权利要求6所述的基于多孔DBR的GaN基VCSEL芯片的制备方法，其中所述底部多孔DBR层和缓冲层之间还生长有一层n型GaN层，作为专用于电化学腐蚀形成底部多孔DBR层的电流扩展层。
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