WO2018181921A1 - Réseau d'éléments à résistance variable et procédé pour commander un réseau d'éléments à résistance variable - Google Patents

Réseau d'éléments à résistance variable et procédé pour commander un réseau d'éléments à résistance variable Download PDF

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Publication number
WO2018181921A1
WO2018181921A1 PCT/JP2018/013685 JP2018013685W WO2018181921A1 WO 2018181921 A1 WO2018181921 A1 WO 2018181921A1 JP 2018013685 W JP2018013685 W JP 2018013685W WO 2018181921 A1 WO2018181921 A1 WO 2018181921A1
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Prior art keywords
selection
elements
switching
variable resistance
electrically connected
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PCT/JP2018/013685
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English (en)
Japanese (ja)
Inventor
岡本　浩一郎
宗弘 多田
直樹 伴野
井口　憲幸
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日本電気株式会社
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Publication of WO2018181921A1 publication Critical patent/WO2018181921A1/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • the present invention is based on the priority claim of Japanese patent application: Japanese Patent Application No. 2017-073040 (filed on March 31, 2017), the entire contents of which are incorporated herein by reference. Shall.
  • the present invention relates to a variable resistance element array having a rectifying element and a control method thereof.
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • Examples of the functional element formed inside the copper multilayer wiring structure in the semiconductor device include a resistance variable nonvolatile element (hereinafter referred to as “resistance variable element”) and a capacitor (capacitance element).
  • Examples of capacitors embedded in a logic LSI include an embedded DRAM (Dynamic Random Access Memory) and a decoupling capacitor. By mounting these capacitors on the copper wiring, it is possible to increase the capacity and area of the capacitor.
  • FPGA Field Programmable Gate Array
  • the resistance change element is a generic term for elements that store information according to changes in the resistance state.
  • the resistance change element has a three-layer structure in which a resistance change layer is sandwiched between a lower electrode and an upper electrode, and utilizes a phenomenon in which a resistance change of the resistance change layer occurs when a voltage is applied between both electrodes. is doing.
  • Examples of the resistance change element include ReRAM (Resistive Random Access Memory) using a metal oxide as a resistance change layer, and a solid electrolyte switch element using a solid electrolyte as a resistance change layer. The structure and switching operation of the solid electrolyte switch element will be briefly described below.
  • the solid electrolyte switch element has a structure in which a solid electrolyte layer is sandwiched between two electrodes (a lower electrode and an upper electrode).
  • One of the two electrodes is chemically active, a metal material that can be easily oxidized and reduced by voltage application is used, and the other electrode is a chemically inert metal material .
  • a chemically active electrode is used as the lower electrode.
  • a solid electrolyte switch element in an off state when a lower electrode (chemically active electrode) is grounded and a negative voltage is applied to the upper electrode (chemically inactive electrode), Metal atoms constituting the lower electrode are ionized and eluted into the solid electrolyte layer, and the metal ions are combined with electrons supplied from the upper electrode to form a conductive metal bridge in the solid electrolyte layer.
  • both electrodes are electrically connected by the metal bridge formed in the solid electrolyte layer, the switch is turned on (low resistance state).
  • the operation of changing from the off state to the on state by applying this voltage is called a set.
  • the switch in the ON state, when the lower electrode is grounded again and a positive voltage is applied to the upper electrode, the metal atom of the metal bridge is ionized, and the metal ion is combined with the electrons supplied from the lower electrode to form the lower electrode.
  • the switch By pulling back and electrically isolating both electrodes, the switch changes to a high resistance OFF state.
  • the operation of changing from the on state to the off state by applying a positive voltage is called reset, and the set and reset are collectively called programming.
  • the solid electrolyte switch element is nonvolatile between the on state and the off state, and can be repeatedly programmed. By using this characteristic, it can be applied to a nonvolatile memory or a nonvolatile switch. Become.
  • Patent Document 1 An example of a memory element using a solid electrolyte is disclosed in Patent Document 1.
  • the memory element disclosed in Patent Document 1 has a configuration in which a memory layer in which a resistance change layer and an ion source layer are stacked is provided between a first electrode and a second electrode.
  • the resistance change layer corresponds to a solid electrolyte layer
  • the ion source layer corresponds to an electrode for supplying metal ions.
  • the off state is preferably a lower leakage current, that is, a higher resistance. Therefore, in order to increase the resistance in the OFF state, generally, a higher positive voltage is applied during the reset operation.
  • a high reset voltage higher than a certain voltage is applied, dielectric breakdown occurs in the solid electrolyte layer, and the resistance change does not show any more while transitioning to a lower resistance state than the normal ON state. This voltage is called a dielectric breakdown voltage. Therefore, a high reset voltage can be applied and a higher resistance OFF state can be obtained by designing and manufacturing the element so that the dielectric breakdown voltage becomes high.
  • the ON state has a lower resistance from the viewpoint of suppressing signal delay and improving retention characteristics.
  • a set current (Iset) that flows at the time of setting may be set large.
  • Iset above a certain level flows, a larger reset current is required in the reset operation, and resetting cannot be performed due to restrictions on the amount of current on the circuit, and off defects are likely to occur. Therefore, at the time of setting, appropriate Iset control is required.
  • Patent Literature 2 and Patent Literature 3 disclose a two-terminal switching element provided inside a copper multilayer wiring structure on a CMOS (Complementary Metal Oxide Semiconductor) substrate.
  • CMOS Complementary Metal Oxide Semiconductor
  • the copper wiring itself exposed by opening a part of the insulating layer inside the copper multilayer wiring structure on the CMOS substrate is used as an active electrode for supplying metal ions into the solid electrolyte. Yes.
  • Non-Patent Document 1 includes a complementary resistance change element in which two resistance change elements each having a structure in which two lower electrodes exposed in the same opening are opposed to each other are connected in series. A technique for improving the performance is disclosed.
  • Non-Patent Document 2 in a complementary resistance change element, a write terminal is electrically separated by a rectifier element during signal transmission operation by further connecting a rectifier element to the connection terminal, and a selection transistor is provided for each cell. A method for reducing the cell area without the need for connection is disclosed.
  • Non-Patent Document 3 in a complementary resistance change element, by connecting two rectifying elements to a connection terminal, complementary resistance change elements in the same row or column can be set in a crossbar array. A method for enabling multi-fanout output of a signal is disclosed.
  • Vset set voltage
  • the complementary resistance change elements disclosed in Non-Patent Documents 2 and 3 in the configuration in which one or two rectifier elements are connected to the connection terminal, when one resistance change element is set, the series connection is performed. Since Vset is applied via the rectified element, at the moment when the variable resistance element changes from the OFF state to the ON state at the time of setting, the majority of Vset is applied to the rectifier element, and a large Iset flows, irreversible of the rectifier element May cause serious dielectric breakdown.
  • Vset in the complementary resistance change elements disclosed in Non-Patent Documents 2 and 3, Vset must be set low in order to suppress dielectric breakdown, and it is difficult to obtain a sufficiently low on-resistance, and the set yield is low. There was a possibility that would decrease. Therefore, there is a need for a variable resistance element array that improves the set yield while preventing dielectric breakdown of the rectifying element.
  • the main object of the present invention is to provide a variable resistance element array and a control method therefor that can improve the set yield while preventing the dielectric breakdown of the rectifying element at the time of setting.
  • the variable resistance element array according to the first aspect is a switching cell including two variable resistance elements and two rectifying elements, and includes a first direction and a second direction different from the first direction.
  • the other terminal of one rectifying element of the two rectifying elements in each switching cell on the same line electrically connected to the first selection wiring and arranged in the first direction corresponds to the corresponding first
  • the other terminal of the other resistance change element among the two resistance change elements in each of the switching cells on the same line that is electrically connected to two selection wirings and arranged in the second direction corresponds to the corresponding first
  • the other terminal of the other rectifying element of the two rectifying elements in each of the switching cells of the same column electrically connected to the three selection wirings and arranged in the second direction is a pair It is electrically connected to the fourth selection wiring, the drive current amount of the first and third selection switching element is different from the respective drive current amount of the second and fourth selection switching elements.
  • a resistance change element array control method is the resistance change element array control method according to the first aspect, wherein the two resistance change elements in the selected switching cell are in an OFF state, respectively. At one time, the other terminal of at least one rectifying element of the two rectifying elements in the selected switching cell is connected to ground, and of the two variable resistance elements in the selected switching cell. By applying a negative voltage to the other terminal of at least one of the resistance change elements, the two resistance change elements in the selected switching cell are controlled to be turned on as a whole.
  • FIG. 3 is a circuit diagram schematically showing a configuration of a switching cell in the variable resistance element array according to Embodiment 1.
  • FIG. 3 is a schematic diagram illustrating an example of a configuration of a variable resistance element of a switching cell in the variable resistance element array according to Embodiment 1.
  • FIG. 3 is a circuit diagram schematically showing the configuration of the variable resistance element array according to the first embodiment.
  • 1 is a block diagram schematically showing a configuration of a storage device including a variable resistance element array according to Embodiment 1.
  • FIG. FIG. 5 is a circuit diagram schematically showing a configuration of a variable resistance element array according to Embodiment 2.
  • connection lines between blocks such as drawings referred to in the following description include both bidirectional and unidirectional directions.
  • the unidirectional arrow schematically shows the main signal (data) flow and does not exclude bidirectionality.
  • FIG. 1 is a circuit diagram schematically illustrating a configuration of a switching cell in the variable resistance element array according to the first embodiment.
  • FIG. 2 is a schematic diagram illustrating an example of the configuration of the variable resistance element of the switching cell in the variable resistance element array according to the first embodiment.
  • FIG. 3 is a circuit diagram schematically illustrating the configuration of the variable resistance element array according to the first embodiment.
  • FIG. 4 is a block diagram schematically illustrating a configuration of a storage device including the resistance change element array according to the first embodiment.
  • the switching cell 10 is a basic circuit (cell) including a first resistance change element 11 and a second resistance change element 12, a first rectification element 13, and a second rectification element 14.
  • the first resistance change element 11 and the second resistance change element 12 are elements capable of storing information according to a change in resistance state (see FIG. 1).
  • the first variable resistance element 11 and the second variable resistance element 12 have a three-layer structure in which the variable resistance layer 3 is sandwiched between the first electrode 1 and the second electrode 2 (see FIG. 2).
  • the variable resistance layers 3 of the first variable resistance element 11 and the second variable resistance element 12 are separated from each other and independent.
  • the first variable resistance element 11 can have the same configuration as the second variable resistance element 12.
  • the first variable resistance element 11 and the second variable resistance element 12 can be provided inside a multilayer wiring structure (not shown) formed on a semiconductor substrate (not shown).
  • the first electrode 1 of the first variable resistance element 11 is electrically connected to the first terminal 11a (see FIGS. 1 and 2).
  • the second electrode 2 of the first variable resistance element 11 is electrically connected to the second terminal 11b.
  • the first electrode 1 of the second resistance change element 12 is electrically connected to the first terminal 12a.
  • the second electrode 2 of the second variable resistance element 12 is electrically connected to the second terminal 12b.
  • a resistance change of the resistance change layer 3 occurs when a voltage is applied between the first electrode 1 and the second electrode 2.
  • a ReRAM using a metal oxide as the resistance change layer 3 As the first resistance change element 11 and the second resistance change element 12, a ReRAM using a metal oxide as the resistance change layer 3, a solid electrolyte switch element using a solid electrolyte as the resistance change layer 3, or the like is used. it can.
  • a material serving as a metal ion supply source is used for one of the first electrode 1 and the second electrode 2.
  • a metal material for example, Cu, Ta
  • a metal material for example, Cu, Ta
  • the resistance change layer 3 can be made of a material that can easily elute or collect metal ions by applying a voltage between the first electrode 1 and the second electrode 2 and that has little material deterioration due to a switching cycle. .
  • the resistance change layer 3 is made of, for example, an oxide containing at least one of Al, Co, Fe, Hf, Mn, Nb, Si, Ta, Ti, Zn, and Zr, or chalcogenide, amorphous Si, and SiOCH. Can be used.
  • the first rectifying element 13 and the second rectifying element 14 are elements having a rectifying action for flowing current with the same characteristics in both directions.
  • a two-terminal rectifier is used for the first rectifier 13 and the second rectifier 14.
  • Examples of the first rectifying element 13 and the second rectifying element 14 include a varistor (for example, a-Si / SiN / a-Si), a threshold switch (for example, an ovonic threshold switch, an ion-electron mixed conductor switch), a zet wrap, Zener diodes electrically connected in series or parallel, avalanche diodes electrically connected in series or parallel, diodes (eg silicon diode, germanium diode) electrically connected in series or parallel, etc. Can be used.
  • a varistor for example, a-Si / SiN / a-Si
  • a threshold switch for example, an ovonic threshold switch, an ion-electron mixed conductor switch
  • zet wrap Zen
  • the first terminals 11 a and 12 a having the same polarity of the first variable resistance element 11 and the second variable resistance element 12, and the first terminals 13 a having the same polarity of the first rectifying element 13 and the second rectifying element 14. , 14a are electrically connected in common.
  • the second terminal 11b of the first resistance change element 11 is electrically connected to the corresponding first selection wiring (21 in FIG. 3).
  • the second terminal 13b of the first rectifying element 13 is electrically connected to the corresponding second selection wiring (22 in FIG. 3).
  • the second terminal 12b of the second resistance change element 12 is electrically connected to the corresponding third selection wiring (23 in FIG. 3).
  • the second terminal 14b of the second rectifying element 14 is electrically connected to the corresponding fourth selection wiring (24 in FIG. 3).
  • each 1st terminal 11a, 12a of the resistance change elements 11 and 12 and each 1st terminal 13a, 14a of the rectifier elements 13 and 14 are electrically connected.
  • it can be confirmed with a transmission electron microscope, a scanning electron microscope, or the like).
  • the first resistance change element 11 and the second resistance change element 12 are solid electrolyte switch elements
  • the first electrode 1 is a chemically active electrode
  • the first variable resistance element 11 and the second variable resistance element 12 are each in an off state (high resistance state), at least the second terminal 13b of the first rectifying element 13 and the second terminal 14b of the second rectifying element 14 When one side is connected to ground and a positive voltage (write voltage) is applied to at least one of the second terminal 11b of the first resistance change element 11 and the second terminal 12b of the second resistance change element 12, the first resistance change element 11 And metal atoms constituting the first electrode 1 are ionized and eluted into the resistance change layer 3 in at least one of the second resistance change elements 12, and the metal ions are combined with electrons supplied from the second electrode 2, A conductive metal bridge (not shown) is formed in the resistance change layer 3.
  • the first resistance change element 11 and the second resistance change element 12 are turned on as a whole. (Low resistance state).
  • the voltage application conditions here are determined depending on the form of the resistance change element and the peripheral circuit, a desired ON state, and the like, and may be pulse application or sweep application.
  • the ON state at least one of the second terminal 11b of the first variable resistance element 11 and the second terminal 12b of the second variable resistance element 12 is connected to the ground, and the second terminal 13b of the first rectifying element 13 and the second terminal 12b are connected.
  • a positive voltage erase voltage
  • the metal atoms of the metal bridge relating to at least one of the resistance change elements 11 and 12 in the on state are ionized, and the metal ions are
  • the first resistance change element 11 and the second resistance change element 12 are turned off as a whole by being combined with electrons supplied from the first electrode 1 and pulled back to the first electrode 1 and electrically insulating both electrodes. Return to the state (high resistance state).
  • the switching cell 10 as described above can be used in the variable resistance element array 100 of FIG.
  • the resistance change element array 100 is an array in which switching cells 10 including a plurality of resistance change elements 11 and 12 are arranged.
  • the variable resistance element array 100 includes a switching cell 10, first to fourth selection wirings 21 to 24, a column decoder 30, and a row decoder 40.
  • the switching cell 10 has a configuration as described with reference to FIGS.
  • a plurality of switching cells 10 are arranged in the array region 20 and arranged in a first direction (X direction) and a second direction (Y direction) different from the first direction (X direction). ing.
  • the angle formed between the X direction and the Y direction is a right angle, but the angle formed between the X direction and the Y direction may be an obtuse angle or an acute angle.
  • the second terminal (11b in FIG. 1) of the first resistance change element 11 in each switching cell 10 on the same line arranged in the first direction (X direction) is electrically connected to the corresponding first selection wiring 21.
  • the second terminal (13b in FIG. 1) of the first rectifying element 13 in each switching cell 10 on the same line arranged in the first direction (X direction) is electrically connected to the corresponding second selection wiring 22. It is connected.
  • the second terminal (12b in FIG. 1) of the second variable resistance element 12 in each switching cell 10 on the same line arranged in the second direction (Y direction) is electrically connected to the corresponding third selection wiring 23. It is connected to the.
  • the second terminal (14b in FIG. 1) of the second rectifying element 14 in each switching cell 10 on the same line arranged in the second direction (Y direction) is electrically connected to the corresponding fourth selection wiring 24. ing.
  • the first selection wiring 21 and the second selection wiring 22 are wirings extending in the first direction (X direction) in the array region 20.
  • the first selection wiring 21 and the second selection wiring 22 form a pair.
  • There are a plurality of pairs of the first selection wiring 21 and the second selection wiring 22 (a pair of bit lines BL11 and BL21, a pair of BL12 and BL22,..., A pair of BL1n and BL2n).
  • the third selection wiring 23 and the fourth selection wiring 24 are wirings extending in the second direction (Y direction) in the array region 20.
  • the third selection wiring 23 and the fourth selection wiring 24 make a pair.
  • There are a plurality of pairs of the third selection wiring 23 and the fourth selection wiring 24 in the array region 20 (a pair of word lines WL11 and WL21, a pair of WL12 and WL22,..., A pair of WL1m and WL2m).
  • the parasitic capacitance of the first selection wiring 21 can be made equal to the parasitic capacitance of the third selection wiring 23. Further, the length of the first selection wiring 21 can be made equal to the length of the third selection wiring 23.
  • the parasitic capacitance of the second selection wiring 22 can be made equal to the parasitic capacitance of the fourth selection wiring 24. Further, the length of the second selection wiring 22 can be made equal to the length of the fourth selection wiring 24.
  • the set current flowing through the resistance change element 11 or 12 in the switching cell 10 selected by the first selection wiring 21 and the fourth selection wiring 24 or the second selection wiring 22 and the third selection wiring 23 is 10 ⁇ A or more and 1 mA. The following can be set.
  • the column decoder 30 is a decoder for selecting the first selection wiring 21 and the second selection wiring 22 related to the pair of bit lines BL11 and BL21, the pair of BL12 and BL22,..., BL1n and BL2n.
  • the column decoder 30 functions as a cell selection circuit that selects one switching cell 10 from the array region 20 in cooperation with the row decoder 40.
  • the column decoder 30 includes a plurality of first field effect transistors 31 that are electrically connected to the first selection lines 21 associated with the bit lines BL11 to BL1n, respectively. Further, the column decoder 30 includes a plurality of second field effect transistors 32 electrically connected to the second selection wirings 22 related to the bit lines BL21 to BL2n, respectively.
  • the column decoder 30 is controlled by an array control circuit (51 in FIG. 4) of the control circuit (50 in FIG. 4), a pair of bit lines BL11 and BL21, a pair of BL12 and BL22,..., A pair of BL1n and BL2n.
  • the first selection wiring 21 and the second selection wiring 22 are selected every time.
  • the row decoder 40 is a decoder for selecting the third selection wiring 23 and the fourth selection wiring 24 related to the pair of word lines WL11 and WL21, the pair of WL12 and WL22,..., WL1m and WL2m.
  • the row decoder 40 functions as a cell selection circuit that selects one switching cell 10 from the array region 20 in cooperation with the column decoder 30.
  • the row decoder 40 includes a plurality of third field effect transistors 41 that are electrically connected to the third selection wirings 23 related to the word lines WL11 to WL1m, respectively.
  • the row decoder 40 includes a plurality of fourth field effect transistors 42 electrically connected to each of the fourth selection wirings 24 related to the word lines WL21 to WL2m.
  • the row decoder 40 controls the pair of word lines WL11 and WL21, the pair of WL12 and WL22,..., WL1m and WL2m under the control of the array control circuit (51 in FIG. 4) of the control circuit (50 in FIG. 4).
  • the third selection wiring 23 and the fourth selection wiring 24 are selected every time.
  • the first field effect transistor 31 is a selection switching element electrically connected to the first selection wiring 21 associated with the corresponding bit line BL11 to BL1n.
  • the second field effect transistor 32 is a selection switching element electrically connected to the second selection wiring 22 associated with the corresponding bit line BL21 to BL2n.
  • the third field effect transistor 41 is a selection switching element electrically connected to the third selection wiring 23 associated with the corresponding word lines WL11 to WL1m.
  • the fourth field effect transistor 42 is a selection switching element that is electrically connected to the corresponding fourth selection wiring 24 according to the word lines WL21 to WL2m.
  • the drive current amounts of the first field effect transistor 31 and the third field effect transistor 41 are different from the drive current amounts of the second field effect transistor 32 and the fourth field effect transistor 42.
  • the drive current amounts of the first field effect transistor 31 and the third field effect transistor 41 are larger than the drive current amounts of the second field effect transistor 32 and the fourth field effect transistor 42.
  • one field effect transistor 31, 32, 41, 42 is provided for each of the selection wirings 21 to 24.
  • the present invention is not limited to this, and the field effect transistor 31, A plurality of 32, 41, and 42 can be connected in series or in parallel.
  • the gate widths of the first field effect transistor 31 and the third field effect transistor 41 can be set to be larger than the gate widths of the second field effect transistor 32 and the fourth field effect transistor 42.
  • first field effect transistor 31 and the third field effect transistor 41 are configured such that two or more field effect transistors are electrically connected in parallel, and are included in the first field effect transistor 31 and the third field effect transistor 41.
  • the number of parallel field effect transistors can be set to be larger than the number of parallel field effect transistors included in the second field effect transistor 32 and the fourth field effect transistor 42.
  • the channel lengths of the field effect transistors included in the first field effect transistor 31 and the third field effect transistor 41 are set to be larger than the channel lengths of the field effect transistors included in the second field effect transistor 32 and the fourth field effect transistor 42. It can be set to be smaller.
  • the field effect transistors 31, 32, 41, and 42 are used as the selective switching elements.
  • the present invention is not limited to this, and a bipolar transistor may be used as the selective switching element.
  • the storage device 200 includes a control circuit 50 for controlling the array region 20, the column decoder 30 and the row decoder 40.
  • the control circuit 50 includes an array control circuit 51, a write circuit 52, and a read circuit 53.
  • the array control circuit 51 selects at least one of the first resistance change element 11 and the second resistance change element 12 in one switching cell 10 from the array region 20 by controlling the column decoder 30 and the row decoder 40. It is a control circuit that can.
  • the write circuit 52 can apply a write voltage or an erase voltage to at least one of the selected first resistance change element 11 and second resistance change element 12 via the corresponding selection wirings 21 to 24. It is.
  • the read circuit 53 is a circuit that can apply a read voltage to at least one of the selected first resistance change element 11 and second resistance change element 12 via the corresponding selection wirings 21 to 24.
  • the variable resistance element array 100 includes memory circuits such as DRAM, SRAM (Static RAM), flash memory, FRAM (Ferro-Electric RAM) (registered trademark), capacitors, bipolar transistors, and the like.
  • the present invention can also be applied to a semiconductor product having a logic circuit such as a microprocessor, a board having a logic circuit such as a microprocessor, or a board or package on which these are simultaneously mounted.
  • the variable resistance element array 100 according to the first embodiment can also be applied to electronic circuit devices, optical circuit devices, quantum circuit devices, micromachines, MEMS (Micro-Electro-Mechanical Systems), and the like.
  • the drive current amounts of the first field effect transistor 31 and the third field effect transistor 41 are set to be different from the drive current amounts of the second field effect transistor 32 and the fourth field effect transistor 42.
  • a sufficient voltage can be applied to at least one of the resistance change elements 11 and 12, and the resistance change elements 11 and 12 Since the current that flows immediately after setting at least one of them can be limited, the set yield can be improved while preventing dielectric breakdown of the rectifying elements 13 and 14.
  • FIG. 5 is a circuit diagram schematically showing the configuration of the variable resistance element array according to the second embodiment.
  • the resistance change element array 100 is an array in which switching cells 10 including a plurality of resistance change elements 11 and 12 are arranged.
  • the resistance change element array 100 includes a switching cell 10, first to fourth selection wirings 21 to 24, and first to fourth selection switching elements 61, 62, 71, and 72.
  • the switching cell 10 includes a first resistance change element 11 and a second resistance change element 12, a first rectification element 13 and a second rectification element 14.
  • a plurality of switching cells 10 are arranged in the array region 20 and arranged in a first direction (X direction) and a second direction (Y direction) different from the first direction (X direction). ing.
  • one terminal of the same polarity of the first resistance change element 11 and the second resistance change element 12 and one terminal of the same polarity of the first rectification element 13 and the second rectification element 14 are Commonly connected electrically.
  • the other terminal of the first resistance change element 11 in each switching cell 10 on the same line arranged in the first direction (X direction) is electrically connected to the corresponding first selection wiring 21.
  • the other terminal of the first rectifying element 13 in each switching cell 10 on the same line arranged in the first direction (X direction) is electrically connected to the corresponding second selection wiring 22.
  • the other terminal of the second variable resistance element 12 in each switching cell 10 on the same line arranged in the second direction (Y direction) is electrically connected to the corresponding third selection wiring 23.
  • the other terminal of the second rectifying element 14 in each switching cell 10 on the same line arranged in the second direction (Y direction) is electrically connected to the corresponding fourth selection wiring 24.
  • the first selection wiring 21 and the second selection wiring 22 are wirings extending in the first direction (X direction) in the array region 20.
  • the first selection wiring 21 and the second selection wiring 22 form a pair. There are a plurality of pairs of the first selection wiring 21 and the second selection wiring 22 in the array region 20.
  • the third selection wiring 23 and the fourth selection wiring 24 are wirings extending in the second direction (Y direction) in the array region 20.
  • the third selection wiring 23 and the fourth selection wiring 24 make a pair. There are a plurality of pairs of the third selection wiring 23 and the fourth selection wiring 24 in the array region 20.
  • the first selection switching element 61 is at least one selection switching element electrically connected to the corresponding first selection wiring 21.
  • the second selection switching element 62 is at least one selection switching element electrically connected to the corresponding second selection wiring 22.
  • the third selection switching element 71 is at least one selection switching element electrically connected to the corresponding third selection wiring 23.
  • the fourth selection switching element 72 is at least one selection switching element electrically connected to the corresponding fourth selection wiring 24.
  • the drive current amounts of the first selection switching element 61 and the third selection switching element 71 are different from the drive current amounts of the second selection switching element 62 and the fourth selection switching element 72.
  • the drive current amounts of the first selection switching element 61 and the third selection switching element 71 are set to be different from the drive current amounts of the second selection switching element 62 and the fourth selection switching element 72.
  • a sufficient voltage can be applied to at least one of the resistance change elements 11 and 12, and the resistance change elements 11 and 12 Since the current that flows immediately after setting at least one of them can be limited, the set yield can be improved while preventing dielectric breakdown of the rectifying elements 13 and 14.
  • variable resistance element array In the present invention, the variable resistance element array according to the first aspect is possible.
  • each driving current amount of the first and third selective switching elements is larger than each driving current amount of the second and fourth selective switching elements.
  • At least one of the first, second, third, and fourth selection switching elements is the corresponding first, second, third, and fourth selection. It includes at least one bipolar transistor or field effect transistor electrically connected to at least one of the wirings.
  • the first, second, third, and fourth selection switching elements are electrically connected to the corresponding first, second, third, and fourth selection wirings, respectively.
  • the field effect transistors included in the first and third selective switching elements have a gate width which is included in the second and fourth selective switching elements. It is larger than the gate width of the transistor.
  • the first, second, third, and fourth selection switching elements are electrically connected to the corresponding first, second, third, and fourth selection wirings, respectively.
  • the number of parallel field effect transistors included in the third selection switching element is greater than the number of parallel field effect transistors included in the second and fourth selection switching elements.
  • the first, second, third, and fourth selection switching elements are electrically connected to the corresponding first, second, third, and fourth selection wirings, respectively.
  • the field effect transistors included in the first and third selective switching elements have a channel length included in the second and fourth selective switching elements. It is smaller than the channel length of the transistor.
  • the resistance change element array according to the first aspect further includes at least one fifth and sixth selection switching elements electrically connected to the corresponding second and fourth selection wirings, respectively.
  • the parasitic capacitance of the second selection wiring is equal to the parasitic capacitance of the fourth selection wiring.
  • the length of the second selection wiring is equal to the length of the fourth selection wiring.
  • a set current flowing through the variable resistance element in the switching cell selected by the first and fourth selection wirings or the second and third selection wirings is It is set to 10 ⁇ A or more and 1 mA or less.
  • variable resistance element array control method according to the second aspect is possible.
  • the two rectifications in the selected switching cell when the two variable resistance elements in the selected switching cell are in an ON state as a whole.
  • the other terminal of at least one rectifying element among the elements is connected to the ground, and a positive voltage is applied to the other terminal of at least one of the two variable resistance elements in the selected switching cell.
  • the memory device includes the resistance change element array according to the first viewpoint and a control circuit that controls the resistance change element array.
  • control circuit controls the first, second, third, and fourth selection switching elements to control the 2 in one switching cell from the array region.
  • An array control circuit for selecting at least one of the two resistance change elements, and at least one of the two resistance change elements in the switching cell selected by the array control circuit.
  • a writing circuit for applying a writing voltage or an erasing voltage via four selection wirings.
  • control circuit includes first, second, third, and third corresponding to at least one of the two resistance change elements in the switching cell selected by the array control circuit.
  • a readout circuit for applying a readout voltage via the fourth selection wiring is further provided.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)

Abstract

La présente invention permet d'améliorer un rendement de formation d'ensemble tout en empêchant une rupture d'isolation d'un élément de redressement lorsqu'il est mis en place. Dans une pluralité de cellules de commutation, des bornes sur un côté de deux éléments de résistance variable sont électriquement connectées à des bornes respectives sur un côté de deux éléments de redressement. Dans les cellules de commutation disposées dans une première direction, l'un des éléments de résistance variable et l'un des éléments de redressement sont respectivement connectés électriquement à une première ligne de câblage de sélection et à une seconde ligne de câblage de sélection. Dans les cellules de commutation disposées dans une seconde direction, l'autre des éléments de résistance variable et l'autre des éléments de redressement sont respectivement connectés électriquement à une troisième ligne de câblage de sélection et à une quatrième ligne de câblage de sélection. Les quantités de courant d'attaque des premier et troisième éléments de commutation de sélection connectés électriquement aux première et troisième lignes de câblage de sélection sont différentes de celles des seconde et quatrième éléments de commutation de sélection connectés électriquement aux second et quatrième lignes de câblage de sélection.
PCT/JP2018/013685 2017-03-31 2018-03-30 Réseau d'éléments à résistance variable et procédé pour commander un réseau d'éléments à résistance variable WO2018181921A1 (fr)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2018190241A1 (ja) * 2017-04-11 2020-05-14 日本電気株式会社 スイッチ回路とこれを用いた半導体装置およびスイッチ方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004186553A (ja) * 2002-12-05 2004-07-02 Sharp Corp 不揮発性メモリセル及び不揮発性半導体記憶装置
WO2010143414A1 (fr) * 2009-06-08 2010-12-16 パナソニック株式会社 Procédé d'écriture pour un élément de mémoire non volatile à variation de résistance et dispositif de mémoire non volatile à variation de résistance
WO2016163120A1 (fr) * 2015-04-06 2016-10-13 日本電気株式会社 Élément de commutation et dispositif à semi-conducteurs et procédé de production de dispositif à semi-conducteurs
WO2016203751A1 (fr) * 2015-06-18 2016-12-22 日本電気株式会社 Élément de redressement, élément de commutation, et procédé de fabrication d'élément de redressement

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004186553A (ja) * 2002-12-05 2004-07-02 Sharp Corp 不揮発性メモリセル及び不揮発性半導体記憶装置
WO2010143414A1 (fr) * 2009-06-08 2010-12-16 パナソニック株式会社 Procédé d'écriture pour un élément de mémoire non volatile à variation de résistance et dispositif de mémoire non volatile à variation de résistance
WO2016163120A1 (fr) * 2015-04-06 2016-10-13 日本電気株式会社 Élément de commutation et dispositif à semi-conducteurs et procédé de production de dispositif à semi-conducteurs
WO2016203751A1 (fr) * 2015-06-18 2016-12-22 日本電気株式会社 Élément de redressement, élément de commutation, et procédé de fabrication d'élément de redressement

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2018190241A1 (ja) * 2017-04-11 2020-05-14 日本電気株式会社 スイッチ回路とこれを用いた半導体装置およびスイッチ方法

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