WO2018181921A1 - Variable resistance element array and method for controlling variable resistance element array - Google Patents

Variable resistance element array and method for controlling variable resistance element array Download PDF

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Publication number
WO2018181921A1
WO2018181921A1 PCT/JP2018/013685 JP2018013685W WO2018181921A1 WO 2018181921 A1 WO2018181921 A1 WO 2018181921A1 JP 2018013685 W JP2018013685 W JP 2018013685W WO 2018181921 A1 WO2018181921 A1 WO 2018181921A1
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Prior art keywords
selection
elements
switching
variable resistance
electrically connected
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PCT/JP2018/013685
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French (fr)
Japanese (ja)
Inventor
岡本　浩一郎
宗弘 多田
直樹 伴野
井口　憲幸
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日本電気株式会社
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Publication of WO2018181921A1 publication Critical patent/WO2018181921A1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • the present invention is based on the priority claim of Japanese patent application: Japanese Patent Application No. 2017-073040 (filed on March 31, 2017), the entire contents of which are incorporated herein by reference. Shall.
  • the present invention relates to a variable resistance element array having a rectifying element and a control method thereof.
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • Examples of the functional element formed inside the copper multilayer wiring structure in the semiconductor device include a resistance variable nonvolatile element (hereinafter referred to as “resistance variable element”) and a capacitor (capacitance element).
  • Examples of capacitors embedded in a logic LSI include an embedded DRAM (Dynamic Random Access Memory) and a decoupling capacitor. By mounting these capacitors on the copper wiring, it is possible to increase the capacity and area of the capacitor.
  • FPGA Field Programmable Gate Array
  • the resistance change element is a generic term for elements that store information according to changes in the resistance state.
  • the resistance change element has a three-layer structure in which a resistance change layer is sandwiched between a lower electrode and an upper electrode, and utilizes a phenomenon in which a resistance change of the resistance change layer occurs when a voltage is applied between both electrodes. is doing.
  • Examples of the resistance change element include ReRAM (Resistive Random Access Memory) using a metal oxide as a resistance change layer, and a solid electrolyte switch element using a solid electrolyte as a resistance change layer. The structure and switching operation of the solid electrolyte switch element will be briefly described below.
  • the solid electrolyte switch element has a structure in which a solid electrolyte layer is sandwiched between two electrodes (a lower electrode and an upper electrode).
  • One of the two electrodes is chemically active, a metal material that can be easily oxidized and reduced by voltage application is used, and the other electrode is a chemically inert metal material .
  • a chemically active electrode is used as the lower electrode.
  • a solid electrolyte switch element in an off state when a lower electrode (chemically active electrode) is grounded and a negative voltage is applied to the upper electrode (chemically inactive electrode), Metal atoms constituting the lower electrode are ionized and eluted into the solid electrolyte layer, and the metal ions are combined with electrons supplied from the upper electrode to form a conductive metal bridge in the solid electrolyte layer.
  • both electrodes are electrically connected by the metal bridge formed in the solid electrolyte layer, the switch is turned on (low resistance state).
  • the operation of changing from the off state to the on state by applying this voltage is called a set.
  • the switch in the ON state, when the lower electrode is grounded again and a positive voltage is applied to the upper electrode, the metal atom of the metal bridge is ionized, and the metal ion is combined with the electrons supplied from the lower electrode to form the lower electrode.
  • the switch By pulling back and electrically isolating both electrodes, the switch changes to a high resistance OFF state.
  • the operation of changing from the on state to the off state by applying a positive voltage is called reset, and the set and reset are collectively called programming.
  • the solid electrolyte switch element is nonvolatile between the on state and the off state, and can be repeatedly programmed. By using this characteristic, it can be applied to a nonvolatile memory or a nonvolatile switch. Become.
  • Patent Document 1 An example of a memory element using a solid electrolyte is disclosed in Patent Document 1.
  • the memory element disclosed in Patent Document 1 has a configuration in which a memory layer in which a resistance change layer and an ion source layer are stacked is provided between a first electrode and a second electrode.
  • the resistance change layer corresponds to a solid electrolyte layer
  • the ion source layer corresponds to an electrode for supplying metal ions.
  • the off state is preferably a lower leakage current, that is, a higher resistance. Therefore, in order to increase the resistance in the OFF state, generally, a higher positive voltage is applied during the reset operation.
  • a high reset voltage higher than a certain voltage is applied, dielectric breakdown occurs in the solid electrolyte layer, and the resistance change does not show any more while transitioning to a lower resistance state than the normal ON state. This voltage is called a dielectric breakdown voltage. Therefore, a high reset voltage can be applied and a higher resistance OFF state can be obtained by designing and manufacturing the element so that the dielectric breakdown voltage becomes high.
  • the ON state has a lower resistance from the viewpoint of suppressing signal delay and improving retention characteristics.
  • a set current (Iset) that flows at the time of setting may be set large.
  • Iset above a certain level flows, a larger reset current is required in the reset operation, and resetting cannot be performed due to restrictions on the amount of current on the circuit, and off defects are likely to occur. Therefore, at the time of setting, appropriate Iset control is required.
  • Patent Literature 2 and Patent Literature 3 disclose a two-terminal switching element provided inside a copper multilayer wiring structure on a CMOS (Complementary Metal Oxide Semiconductor) substrate.
  • CMOS Complementary Metal Oxide Semiconductor
  • the copper wiring itself exposed by opening a part of the insulating layer inside the copper multilayer wiring structure on the CMOS substrate is used as an active electrode for supplying metal ions into the solid electrolyte. Yes.
  • Non-Patent Document 1 includes a complementary resistance change element in which two resistance change elements each having a structure in which two lower electrodes exposed in the same opening are opposed to each other are connected in series. A technique for improving the performance is disclosed.
  • Non-Patent Document 2 in a complementary resistance change element, a write terminal is electrically separated by a rectifier element during signal transmission operation by further connecting a rectifier element to the connection terminal, and a selection transistor is provided for each cell. A method for reducing the cell area without the need for connection is disclosed.
  • Non-Patent Document 3 in a complementary resistance change element, by connecting two rectifying elements to a connection terminal, complementary resistance change elements in the same row or column can be set in a crossbar array. A method for enabling multi-fanout output of a signal is disclosed.
  • Vset set voltage
  • the complementary resistance change elements disclosed in Non-Patent Documents 2 and 3 in the configuration in which one or two rectifier elements are connected to the connection terminal, when one resistance change element is set, the series connection is performed. Since Vset is applied via the rectified element, at the moment when the variable resistance element changes from the OFF state to the ON state at the time of setting, the majority of Vset is applied to the rectifier element, and a large Iset flows, irreversible of the rectifier element May cause serious dielectric breakdown.
  • Vset in the complementary resistance change elements disclosed in Non-Patent Documents 2 and 3, Vset must be set low in order to suppress dielectric breakdown, and it is difficult to obtain a sufficiently low on-resistance, and the set yield is low. There was a possibility that would decrease. Therefore, there is a need for a variable resistance element array that improves the set yield while preventing dielectric breakdown of the rectifying element.
  • the main object of the present invention is to provide a variable resistance element array and a control method therefor that can improve the set yield while preventing the dielectric breakdown of the rectifying element at the time of setting.
  • the variable resistance element array according to the first aspect is a switching cell including two variable resistance elements and two rectifying elements, and includes a first direction and a second direction different from the first direction.
  • the other terminal of one rectifying element of the two rectifying elements in each switching cell on the same line electrically connected to the first selection wiring and arranged in the first direction corresponds to the corresponding first
  • the other terminal of the other resistance change element among the two resistance change elements in each of the switching cells on the same line that is electrically connected to two selection wirings and arranged in the second direction corresponds to the corresponding first
  • the other terminal of the other rectifying element of the two rectifying elements in each of the switching cells of the same column electrically connected to the three selection wirings and arranged in the second direction is a pair It is electrically connected to the fourth selection wiring, the drive current amount of the first and third selection switching element is different from the respective drive current amount of the second and fourth selection switching elements.
  • a resistance change element array control method is the resistance change element array control method according to the first aspect, wherein the two resistance change elements in the selected switching cell are in an OFF state, respectively. At one time, the other terminal of at least one rectifying element of the two rectifying elements in the selected switching cell is connected to ground, and of the two variable resistance elements in the selected switching cell. By applying a negative voltage to the other terminal of at least one of the resistance change elements, the two resistance change elements in the selected switching cell are controlled to be turned on as a whole.
  • FIG. 3 is a circuit diagram schematically showing a configuration of a switching cell in the variable resistance element array according to Embodiment 1.
  • FIG. 3 is a schematic diagram illustrating an example of a configuration of a variable resistance element of a switching cell in the variable resistance element array according to Embodiment 1.
  • FIG. 3 is a circuit diagram schematically showing the configuration of the variable resistance element array according to the first embodiment.
  • 1 is a block diagram schematically showing a configuration of a storage device including a variable resistance element array according to Embodiment 1.
  • FIG. FIG. 5 is a circuit diagram schematically showing a configuration of a variable resistance element array according to Embodiment 2.
  • connection lines between blocks such as drawings referred to in the following description include both bidirectional and unidirectional directions.
  • the unidirectional arrow schematically shows the main signal (data) flow and does not exclude bidirectionality.
  • FIG. 1 is a circuit diagram schematically illustrating a configuration of a switching cell in the variable resistance element array according to the first embodiment.
  • FIG. 2 is a schematic diagram illustrating an example of the configuration of the variable resistance element of the switching cell in the variable resistance element array according to the first embodiment.
  • FIG. 3 is a circuit diagram schematically illustrating the configuration of the variable resistance element array according to the first embodiment.
  • FIG. 4 is a block diagram schematically illustrating a configuration of a storage device including the resistance change element array according to the first embodiment.
  • the switching cell 10 is a basic circuit (cell) including a first resistance change element 11 and a second resistance change element 12, a first rectification element 13, and a second rectification element 14.
  • the first resistance change element 11 and the second resistance change element 12 are elements capable of storing information according to a change in resistance state (see FIG. 1).
  • the first variable resistance element 11 and the second variable resistance element 12 have a three-layer structure in which the variable resistance layer 3 is sandwiched between the first electrode 1 and the second electrode 2 (see FIG. 2).
  • the variable resistance layers 3 of the first variable resistance element 11 and the second variable resistance element 12 are separated from each other and independent.
  • the first variable resistance element 11 can have the same configuration as the second variable resistance element 12.
  • the first variable resistance element 11 and the second variable resistance element 12 can be provided inside a multilayer wiring structure (not shown) formed on a semiconductor substrate (not shown).
  • the first electrode 1 of the first variable resistance element 11 is electrically connected to the first terminal 11a (see FIGS. 1 and 2).
  • the second electrode 2 of the first variable resistance element 11 is electrically connected to the second terminal 11b.
  • the first electrode 1 of the second resistance change element 12 is electrically connected to the first terminal 12a.
  • the second electrode 2 of the second variable resistance element 12 is electrically connected to the second terminal 12b.
  • a resistance change of the resistance change layer 3 occurs when a voltage is applied between the first electrode 1 and the second electrode 2.
  • a ReRAM using a metal oxide as the resistance change layer 3 As the first resistance change element 11 and the second resistance change element 12, a ReRAM using a metal oxide as the resistance change layer 3, a solid electrolyte switch element using a solid electrolyte as the resistance change layer 3, or the like is used. it can.
  • a material serving as a metal ion supply source is used for one of the first electrode 1 and the second electrode 2.
  • a metal material for example, Cu, Ta
  • a metal material for example, Cu, Ta
  • the resistance change layer 3 can be made of a material that can easily elute or collect metal ions by applying a voltage between the first electrode 1 and the second electrode 2 and that has little material deterioration due to a switching cycle. .
  • the resistance change layer 3 is made of, for example, an oxide containing at least one of Al, Co, Fe, Hf, Mn, Nb, Si, Ta, Ti, Zn, and Zr, or chalcogenide, amorphous Si, and SiOCH. Can be used.
  • the first rectifying element 13 and the second rectifying element 14 are elements having a rectifying action for flowing current with the same characteristics in both directions.
  • a two-terminal rectifier is used for the first rectifier 13 and the second rectifier 14.
  • Examples of the first rectifying element 13 and the second rectifying element 14 include a varistor (for example, a-Si / SiN / a-Si), a threshold switch (for example, an ovonic threshold switch, an ion-electron mixed conductor switch), a zet wrap, Zener diodes electrically connected in series or parallel, avalanche diodes electrically connected in series or parallel, diodes (eg silicon diode, germanium diode) electrically connected in series or parallel, etc. Can be used.
  • a varistor for example, a-Si / SiN / a-Si
  • a threshold switch for example, an ovonic threshold switch, an ion-electron mixed conductor switch
  • zet wrap Zen
  • the first terminals 11 a and 12 a having the same polarity of the first variable resistance element 11 and the second variable resistance element 12, and the first terminals 13 a having the same polarity of the first rectifying element 13 and the second rectifying element 14. , 14a are electrically connected in common.
  • the second terminal 11b of the first resistance change element 11 is electrically connected to the corresponding first selection wiring (21 in FIG. 3).
  • the second terminal 13b of the first rectifying element 13 is electrically connected to the corresponding second selection wiring (22 in FIG. 3).
  • the second terminal 12b of the second resistance change element 12 is electrically connected to the corresponding third selection wiring (23 in FIG. 3).
  • the second terminal 14b of the second rectifying element 14 is electrically connected to the corresponding fourth selection wiring (24 in FIG. 3).
  • each 1st terminal 11a, 12a of the resistance change elements 11 and 12 and each 1st terminal 13a, 14a of the rectifier elements 13 and 14 are electrically connected.
  • it can be confirmed with a transmission electron microscope, a scanning electron microscope, or the like).
  • the first resistance change element 11 and the second resistance change element 12 are solid electrolyte switch elements
  • the first electrode 1 is a chemically active electrode
  • the first variable resistance element 11 and the second variable resistance element 12 are each in an off state (high resistance state), at least the second terminal 13b of the first rectifying element 13 and the second terminal 14b of the second rectifying element 14 When one side is connected to ground and a positive voltage (write voltage) is applied to at least one of the second terminal 11b of the first resistance change element 11 and the second terminal 12b of the second resistance change element 12, the first resistance change element 11 And metal atoms constituting the first electrode 1 are ionized and eluted into the resistance change layer 3 in at least one of the second resistance change elements 12, and the metal ions are combined with electrons supplied from the second electrode 2, A conductive metal bridge (not shown) is formed in the resistance change layer 3.
  • the first resistance change element 11 and the second resistance change element 12 are turned on as a whole. (Low resistance state).
  • the voltage application conditions here are determined depending on the form of the resistance change element and the peripheral circuit, a desired ON state, and the like, and may be pulse application or sweep application.
  • the ON state at least one of the second terminal 11b of the first variable resistance element 11 and the second terminal 12b of the second variable resistance element 12 is connected to the ground, and the second terminal 13b of the first rectifying element 13 and the second terminal 12b are connected.
  • a positive voltage erase voltage
  • the metal atoms of the metal bridge relating to at least one of the resistance change elements 11 and 12 in the on state are ionized, and the metal ions are
  • the first resistance change element 11 and the second resistance change element 12 are turned off as a whole by being combined with electrons supplied from the first electrode 1 and pulled back to the first electrode 1 and electrically insulating both electrodes. Return to the state (high resistance state).
  • the switching cell 10 as described above can be used in the variable resistance element array 100 of FIG.
  • the resistance change element array 100 is an array in which switching cells 10 including a plurality of resistance change elements 11 and 12 are arranged.
  • the variable resistance element array 100 includes a switching cell 10, first to fourth selection wirings 21 to 24, a column decoder 30, and a row decoder 40.
  • the switching cell 10 has a configuration as described with reference to FIGS.
  • a plurality of switching cells 10 are arranged in the array region 20 and arranged in a first direction (X direction) and a second direction (Y direction) different from the first direction (X direction). ing.
  • the angle formed between the X direction and the Y direction is a right angle, but the angle formed between the X direction and the Y direction may be an obtuse angle or an acute angle.
  • the second terminal (11b in FIG. 1) of the first resistance change element 11 in each switching cell 10 on the same line arranged in the first direction (X direction) is electrically connected to the corresponding first selection wiring 21.
  • the second terminal (13b in FIG. 1) of the first rectifying element 13 in each switching cell 10 on the same line arranged in the first direction (X direction) is electrically connected to the corresponding second selection wiring 22. It is connected.
  • the second terminal (12b in FIG. 1) of the second variable resistance element 12 in each switching cell 10 on the same line arranged in the second direction (Y direction) is electrically connected to the corresponding third selection wiring 23. It is connected to the.
  • the second terminal (14b in FIG. 1) of the second rectifying element 14 in each switching cell 10 on the same line arranged in the second direction (Y direction) is electrically connected to the corresponding fourth selection wiring 24. ing.
  • the first selection wiring 21 and the second selection wiring 22 are wirings extending in the first direction (X direction) in the array region 20.
  • the first selection wiring 21 and the second selection wiring 22 form a pair.
  • There are a plurality of pairs of the first selection wiring 21 and the second selection wiring 22 (a pair of bit lines BL11 and BL21, a pair of BL12 and BL22,..., A pair of BL1n and BL2n).
  • the third selection wiring 23 and the fourth selection wiring 24 are wirings extending in the second direction (Y direction) in the array region 20.
  • the third selection wiring 23 and the fourth selection wiring 24 make a pair.
  • There are a plurality of pairs of the third selection wiring 23 and the fourth selection wiring 24 in the array region 20 (a pair of word lines WL11 and WL21, a pair of WL12 and WL22,..., A pair of WL1m and WL2m).
  • the parasitic capacitance of the first selection wiring 21 can be made equal to the parasitic capacitance of the third selection wiring 23. Further, the length of the first selection wiring 21 can be made equal to the length of the third selection wiring 23.
  • the parasitic capacitance of the second selection wiring 22 can be made equal to the parasitic capacitance of the fourth selection wiring 24. Further, the length of the second selection wiring 22 can be made equal to the length of the fourth selection wiring 24.
  • the set current flowing through the resistance change element 11 or 12 in the switching cell 10 selected by the first selection wiring 21 and the fourth selection wiring 24 or the second selection wiring 22 and the third selection wiring 23 is 10 ⁇ A or more and 1 mA. The following can be set.
  • the column decoder 30 is a decoder for selecting the first selection wiring 21 and the second selection wiring 22 related to the pair of bit lines BL11 and BL21, the pair of BL12 and BL22,..., BL1n and BL2n.
  • the column decoder 30 functions as a cell selection circuit that selects one switching cell 10 from the array region 20 in cooperation with the row decoder 40.
  • the column decoder 30 includes a plurality of first field effect transistors 31 that are electrically connected to the first selection lines 21 associated with the bit lines BL11 to BL1n, respectively. Further, the column decoder 30 includes a plurality of second field effect transistors 32 electrically connected to the second selection wirings 22 related to the bit lines BL21 to BL2n, respectively.
  • the column decoder 30 is controlled by an array control circuit (51 in FIG. 4) of the control circuit (50 in FIG. 4), a pair of bit lines BL11 and BL21, a pair of BL12 and BL22,..., A pair of BL1n and BL2n.
  • the first selection wiring 21 and the second selection wiring 22 are selected every time.
  • the row decoder 40 is a decoder for selecting the third selection wiring 23 and the fourth selection wiring 24 related to the pair of word lines WL11 and WL21, the pair of WL12 and WL22,..., WL1m and WL2m.
  • the row decoder 40 functions as a cell selection circuit that selects one switching cell 10 from the array region 20 in cooperation with the column decoder 30.
  • the row decoder 40 includes a plurality of third field effect transistors 41 that are electrically connected to the third selection wirings 23 related to the word lines WL11 to WL1m, respectively.
  • the row decoder 40 includes a plurality of fourth field effect transistors 42 electrically connected to each of the fourth selection wirings 24 related to the word lines WL21 to WL2m.
  • the row decoder 40 controls the pair of word lines WL11 and WL21, the pair of WL12 and WL22,..., WL1m and WL2m under the control of the array control circuit (51 in FIG. 4) of the control circuit (50 in FIG. 4).
  • the third selection wiring 23 and the fourth selection wiring 24 are selected every time.
  • the first field effect transistor 31 is a selection switching element electrically connected to the first selection wiring 21 associated with the corresponding bit line BL11 to BL1n.
  • the second field effect transistor 32 is a selection switching element electrically connected to the second selection wiring 22 associated with the corresponding bit line BL21 to BL2n.
  • the third field effect transistor 41 is a selection switching element electrically connected to the third selection wiring 23 associated with the corresponding word lines WL11 to WL1m.
  • the fourth field effect transistor 42 is a selection switching element that is electrically connected to the corresponding fourth selection wiring 24 according to the word lines WL21 to WL2m.
  • the drive current amounts of the first field effect transistor 31 and the third field effect transistor 41 are different from the drive current amounts of the second field effect transistor 32 and the fourth field effect transistor 42.
  • the drive current amounts of the first field effect transistor 31 and the third field effect transistor 41 are larger than the drive current amounts of the second field effect transistor 32 and the fourth field effect transistor 42.
  • one field effect transistor 31, 32, 41, 42 is provided for each of the selection wirings 21 to 24.
  • the present invention is not limited to this, and the field effect transistor 31, A plurality of 32, 41, and 42 can be connected in series or in parallel.
  • the gate widths of the first field effect transistor 31 and the third field effect transistor 41 can be set to be larger than the gate widths of the second field effect transistor 32 and the fourth field effect transistor 42.
  • first field effect transistor 31 and the third field effect transistor 41 are configured such that two or more field effect transistors are electrically connected in parallel, and are included in the first field effect transistor 31 and the third field effect transistor 41.
  • the number of parallel field effect transistors can be set to be larger than the number of parallel field effect transistors included in the second field effect transistor 32 and the fourth field effect transistor 42.
  • the channel lengths of the field effect transistors included in the first field effect transistor 31 and the third field effect transistor 41 are set to be larger than the channel lengths of the field effect transistors included in the second field effect transistor 32 and the fourth field effect transistor 42. It can be set to be smaller.
  • the field effect transistors 31, 32, 41, and 42 are used as the selective switching elements.
  • the present invention is not limited to this, and a bipolar transistor may be used as the selective switching element.
  • the storage device 200 includes a control circuit 50 for controlling the array region 20, the column decoder 30 and the row decoder 40.
  • the control circuit 50 includes an array control circuit 51, a write circuit 52, and a read circuit 53.
  • the array control circuit 51 selects at least one of the first resistance change element 11 and the second resistance change element 12 in one switching cell 10 from the array region 20 by controlling the column decoder 30 and the row decoder 40. It is a control circuit that can.
  • the write circuit 52 can apply a write voltage or an erase voltage to at least one of the selected first resistance change element 11 and second resistance change element 12 via the corresponding selection wirings 21 to 24. It is.
  • the read circuit 53 is a circuit that can apply a read voltage to at least one of the selected first resistance change element 11 and second resistance change element 12 via the corresponding selection wirings 21 to 24.
  • the variable resistance element array 100 includes memory circuits such as DRAM, SRAM (Static RAM), flash memory, FRAM (Ferro-Electric RAM) (registered trademark), capacitors, bipolar transistors, and the like.
  • the present invention can also be applied to a semiconductor product having a logic circuit such as a microprocessor, a board having a logic circuit such as a microprocessor, or a board or package on which these are simultaneously mounted.
  • the variable resistance element array 100 according to the first embodiment can also be applied to electronic circuit devices, optical circuit devices, quantum circuit devices, micromachines, MEMS (Micro-Electro-Mechanical Systems), and the like.
  • the drive current amounts of the first field effect transistor 31 and the third field effect transistor 41 are set to be different from the drive current amounts of the second field effect transistor 32 and the fourth field effect transistor 42.
  • a sufficient voltage can be applied to at least one of the resistance change elements 11 and 12, and the resistance change elements 11 and 12 Since the current that flows immediately after setting at least one of them can be limited, the set yield can be improved while preventing dielectric breakdown of the rectifying elements 13 and 14.
  • FIG. 5 is a circuit diagram schematically showing the configuration of the variable resistance element array according to the second embodiment.
  • the resistance change element array 100 is an array in which switching cells 10 including a plurality of resistance change elements 11 and 12 are arranged.
  • the resistance change element array 100 includes a switching cell 10, first to fourth selection wirings 21 to 24, and first to fourth selection switching elements 61, 62, 71, and 72.
  • the switching cell 10 includes a first resistance change element 11 and a second resistance change element 12, a first rectification element 13 and a second rectification element 14.
  • a plurality of switching cells 10 are arranged in the array region 20 and arranged in a first direction (X direction) and a second direction (Y direction) different from the first direction (X direction). ing.
  • one terminal of the same polarity of the first resistance change element 11 and the second resistance change element 12 and one terminal of the same polarity of the first rectification element 13 and the second rectification element 14 are Commonly connected electrically.
  • the other terminal of the first resistance change element 11 in each switching cell 10 on the same line arranged in the first direction (X direction) is electrically connected to the corresponding first selection wiring 21.
  • the other terminal of the first rectifying element 13 in each switching cell 10 on the same line arranged in the first direction (X direction) is electrically connected to the corresponding second selection wiring 22.
  • the other terminal of the second variable resistance element 12 in each switching cell 10 on the same line arranged in the second direction (Y direction) is electrically connected to the corresponding third selection wiring 23.
  • the other terminal of the second rectifying element 14 in each switching cell 10 on the same line arranged in the second direction (Y direction) is electrically connected to the corresponding fourth selection wiring 24.
  • the first selection wiring 21 and the second selection wiring 22 are wirings extending in the first direction (X direction) in the array region 20.
  • the first selection wiring 21 and the second selection wiring 22 form a pair. There are a plurality of pairs of the first selection wiring 21 and the second selection wiring 22 in the array region 20.
  • the third selection wiring 23 and the fourth selection wiring 24 are wirings extending in the second direction (Y direction) in the array region 20.
  • the third selection wiring 23 and the fourth selection wiring 24 make a pair. There are a plurality of pairs of the third selection wiring 23 and the fourth selection wiring 24 in the array region 20.
  • the first selection switching element 61 is at least one selection switching element electrically connected to the corresponding first selection wiring 21.
  • the second selection switching element 62 is at least one selection switching element electrically connected to the corresponding second selection wiring 22.
  • the third selection switching element 71 is at least one selection switching element electrically connected to the corresponding third selection wiring 23.
  • the fourth selection switching element 72 is at least one selection switching element electrically connected to the corresponding fourth selection wiring 24.
  • the drive current amounts of the first selection switching element 61 and the third selection switching element 71 are different from the drive current amounts of the second selection switching element 62 and the fourth selection switching element 72.
  • the drive current amounts of the first selection switching element 61 and the third selection switching element 71 are set to be different from the drive current amounts of the second selection switching element 62 and the fourth selection switching element 72.
  • a sufficient voltage can be applied to at least one of the resistance change elements 11 and 12, and the resistance change elements 11 and 12 Since the current that flows immediately after setting at least one of them can be limited, the set yield can be improved while preventing dielectric breakdown of the rectifying elements 13 and 14.
  • variable resistance element array In the present invention, the variable resistance element array according to the first aspect is possible.
  • each driving current amount of the first and third selective switching elements is larger than each driving current amount of the second and fourth selective switching elements.
  • At least one of the first, second, third, and fourth selection switching elements is the corresponding first, second, third, and fourth selection. It includes at least one bipolar transistor or field effect transistor electrically connected to at least one of the wirings.
  • the first, second, third, and fourth selection switching elements are electrically connected to the corresponding first, second, third, and fourth selection wirings, respectively.
  • the field effect transistors included in the first and third selective switching elements have a gate width which is included in the second and fourth selective switching elements. It is larger than the gate width of the transistor.
  • the first, second, third, and fourth selection switching elements are electrically connected to the corresponding first, second, third, and fourth selection wirings, respectively.
  • the number of parallel field effect transistors included in the third selection switching element is greater than the number of parallel field effect transistors included in the second and fourth selection switching elements.
  • the first, second, third, and fourth selection switching elements are electrically connected to the corresponding first, second, third, and fourth selection wirings, respectively.
  • the field effect transistors included in the first and third selective switching elements have a channel length included in the second and fourth selective switching elements. It is smaller than the channel length of the transistor.
  • the resistance change element array according to the first aspect further includes at least one fifth and sixth selection switching elements electrically connected to the corresponding second and fourth selection wirings, respectively.
  • the parasitic capacitance of the second selection wiring is equal to the parasitic capacitance of the fourth selection wiring.
  • the length of the second selection wiring is equal to the length of the fourth selection wiring.
  • a set current flowing through the variable resistance element in the switching cell selected by the first and fourth selection wirings or the second and third selection wirings is It is set to 10 ⁇ A or more and 1 mA or less.
  • variable resistance element array control method according to the second aspect is possible.
  • the two rectifications in the selected switching cell when the two variable resistance elements in the selected switching cell are in an ON state as a whole.
  • the other terminal of at least one rectifying element among the elements is connected to the ground, and a positive voltage is applied to the other terminal of at least one of the two variable resistance elements in the selected switching cell.
  • the memory device includes the resistance change element array according to the first viewpoint and a control circuit that controls the resistance change element array.
  • control circuit controls the first, second, third, and fourth selection switching elements to control the 2 in one switching cell from the array region.
  • An array control circuit for selecting at least one of the two resistance change elements, and at least one of the two resistance change elements in the switching cell selected by the array control circuit.
  • a writing circuit for applying a writing voltage or an erasing voltage via four selection wirings.
  • control circuit includes first, second, third, and third corresponding to at least one of the two resistance change elements in the switching cell selected by the array control circuit.
  • a readout circuit for applying a readout voltage via the fourth selection wiring is further provided.

Abstract

The present invention enables improvement of a set-forming yield while preventing insulation breakdown of a rectifying element when being set. In a plurality of switching cells, terminals on one side of two variable resistance elements are electrically connected to respective terminals on one side of two rectifying elements. In the switching cells arrayed in a first direction, one of the variable resistance elements and one of the rectifying elements are respectively electrically connected to a first selection wiring line and a second selection wiring line. In the switching cells arrayed in a second direction, the other one of the variable resistance elements and the other one of the rectifying elements are respectively electrically connected to a third selection wiring line and a fourth selection wiring line. The driving current amounts of first and third selection switching elements electrically connected to the first and third selection wiring lines are different from those of second and fourth selection switching elements electrically connected to the second and fourth selection wiring lines.

Description

抵抗変化素子アレイ及びその制御方法Variable resistance element array and control method thereof
［関連出願についての記載］
本発明は、日本国特許出願：特願２０１７－０７３０４０号（２０１７年３月３１日出願）の優先権主張に基づくものであり、同出願の全記載内容は引用をもって本書に組み込み記載されているものとする。
　本発明は、整流素子を有する抵抗変化素子アレイ及びその制御方法に関する。 [Description of related applications]
The present invention is based on the priority claim of Japanese patent application: Japanese Patent Application No. 2017-073040 (filed on March 31, 2017), the entire contents of which are incorporated herein by reference. Shall.
The present invention relates to a variable resistance element array having a rectifying element and a control method thereof.
　半導体装置（特に、シリコンデバイス）は、微細化（スケーリング則：Ｍｏｏｒｅの法則）によってデバイスの集積化・低電力化が進められ、３年４倍のペースで開発が進められてきた。近年、ＭＯＳＦＥＴ（Metal Oxide Semiconductor Field Effect Transistor）のゲート長は２０ｎｍ以下となり、リソグラフィプロセスの高騰（装置価格およびマスクセット価格）に加え、デバイス寸法の物理的限界（動作限界・ばらつき限界）により、これまでのスケーリング則とは異なるアプローチでのデバイス性能の改善が求められている。 Semiconductor devices (especially silicon devices) have been developed at a pace of 3 years, with the integration of devices and the reduction of power consumption being promoted by miniaturization (scaling law: Moore's law). In recent years, the gate length of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) has been reduced to 20 nm or less, and due to the soaring lithography process (apparatus price and mask set price), the physical limits of device dimensions (operation limits and dispersion limits) There is a need for improved device performance with a different approach than the scaling law.
　半導体装置における銅多層配線構造の内部に形成される機能素子としては、例えば、抵抗変化型不揮発性素子（以下、「抵抗変化素子」と称する）やキャパシタ（容量素子）等がある。ロジックＬＳＩ（Large Scale Integration）に混載されるキャパシタとしては、エンベデッドＤＲＡＭ（Dynamic Random Access Memory）や、デカップリングキャパシタなどがある。これらのキャパシタを銅配線上に搭載することで、キャパシタの大容量化や小面積化が実現可能になる。 Examples of the functional element formed inside the copper multilayer wiring structure in the semiconductor device include a resistance variable nonvolatile element (hereinafter referred to as “resistance variable element”) and a capacitor (capacitance element). Examples of capacitors embedded in a logic LSI (Large Scale Integration) include an embedded DRAM (Dynamic Random Access Memory) and a decoupling capacitor. By mounting these capacitors on the copper wiring, it is possible to increase the capacity and area of the capacitor.
　ところで、ゲートアレイとスタンダードセルとの中間的な位置づけとしてＦＰＧＡ（Field Programmable Gate Array）と呼ばれるデバイスが開発されている。これは、顧客自身がチップの製造後に任意の回路構成を行うことを可能とするものである。プログラマブル素子では、抵抗変化素子等を配線接続部に介在させ、顧客自身が任意に配線の電気的接続を行うことができる。このようなプログラマブル素子を有する半導体装置を用いることで、回路の自由度を向上させることができる。 By the way, a device called FPGA (Field Programmable Gate Array) has been developed as an intermediate position between the gate array and the standard cell. This makes it possible for the customer himself to perform an arbitrary circuit configuration after manufacturing the chip. In a programmable element, a resistance change element etc. can be interposed in a wiring connection part, and the customer himself / herself can arbitrarily connect the wiring. By using a semiconductor device having such a programmable element, the degree of freedom of the circuit can be improved.
　ここで、抵抗変化素子とは、抵抗状態の変化によって情報を記憶する素子の総称である。抵抗変化素子では、下部電極と上部電極との間に抵抗変化層を挟んだ３層構造を有しており、両電極間に電圧を印加することで抵抗変化層の抵抗変化が生じる現象を利用している。抵抗変化素子としては、抵抗変化層として金属酸化物を用いたＲｅＲＡＭ（Resistive Random Access Memory）や、抵抗変化層として固体電解質を用いた固体電解質型スイッチ素子などがある。以下に、固体電解質型スイッチ素子の構造およびスイッチング動作について簡単に説明する。 Here, the resistance change element is a generic term for elements that store information according to changes in the resistance state. The resistance change element has a three-layer structure in which a resistance change layer is sandwiched between a lower electrode and an upper electrode, and utilizes a phenomenon in which a resistance change of the resistance change layer occurs when a voltage is applied between both electrodes. is doing. Examples of the resistance change element include ReRAM (Resistive Random Access Memory) using a metal oxide as a resistance change layer, and a solid electrolyte switch element using a solid electrolyte as a resistance change layer. The structure and switching operation of the solid electrolyte switch element will be briefly described below.
　固体電解質型スイッチ素子は、固体電解質層を２つの電極（下部電極および上部電極）で挟んだ構造を有している。２つの電極のうち一方の電極は化学的に活性であり、電圧印加により容易に酸化および還元が可能な金属材料が用いられ、他方の電極には、化学的に不活性な金属材料が用いられる。 The solid electrolyte switch element has a structure in which a solid electrolyte layer is sandwiched between two electrodes (a lower electrode and an upper electrode). One of the two electrodes is chemically active, a metal material that can be easily oxidized and reduced by voltage application is used, and the other electrode is a chemically inert metal material .
　次に、固体電解質型スイッチ素子の動作について説明する。ここでは、例として化学的に活性な電極を下部電極とする。例えば、オフ状態（高抵抗状態）にある固体電解質型スイッチ素子において、下部電極（化学的に活性な電極）を接地し、上部電極（化学的に不活性な電極）に負電圧を印加すると、下部電極を構成する金属原子がイオン化して固体電解質層中に溶出し、金属イオンが上部電極から供給される電子と結合して、固体電解質層に導電性を有する金属架橋が形成される。この固体電解質層中に形成された金属架橋により両電極が電気的に接続されることで、スイッチがオン状態（低抵抗状態）に変化する。この電圧印加によってオフ状態からオン状態へ変化させる動作をセットと呼ぶ。 Next, the operation of the solid electrolyte switch element will be described. Here, as an example, a chemically active electrode is used as the lower electrode. For example, in a solid electrolyte switch element in an off state (high resistance state), when a lower electrode (chemically active electrode) is grounded and a negative voltage is applied to the upper electrode (chemically inactive electrode), Metal atoms constituting the lower electrode are ionized and eluted into the solid electrolyte layer, and the metal ions are combined with electrons supplied from the upper electrode to form a conductive metal bridge in the solid electrolyte layer. When both electrodes are electrically connected by the metal bridge formed in the solid electrolyte layer, the switch is turned on (low resistance state). The operation of changing from the off state to the on state by applying this voltage is called a set.
　一方、上記オン状態において、下部電極を再び接地し、上部電極に正電圧を印加すると、上記金属架橋の金属原子がイオン化し、金属イオンが下部電極から供給される電子と結合して下部電極に引き戻され、両電極が電気的に絶縁されることで、スイッチが高抵抗のオフ状態に変化する。この正電圧印加によってオン状態からオフ状態へ変化させる動作をリセットと呼び、セットとリセットを合わせてプログラミングと呼ぶ。 On the other hand, in the ON state, when the lower electrode is grounded again and a positive voltage is applied to the upper electrode, the metal atom of the metal bridge is ionized, and the metal ion is combined with the electrons supplied from the lower electrode to form the lower electrode. By pulling back and electrically isolating both electrodes, the switch changes to a high resistance OFF state. The operation of changing from the on state to the off state by applying a positive voltage is called reset, and the set and reset are collectively called programming.
　このように固体電解質型スイッチ素子はこのオン状態とオフ状態の間を不揮発で、かつ繰り返しプログラミング動作が可能であり、この特性を利用することで不揮発性メモリあるいは不揮発性スイッチへの応用が可能になる。 As described above, the solid electrolyte switch element is nonvolatile between the on state and the off state, and can be repeatedly programmed. By using this characteristic, it can be applied to a nonvolatile memory or a nonvolatile switch. Become.
　固体電解質を利用した記憶素子の一例が特許文献１に開示されている。特許文献１に開示された記憶素子は、第１電極と第２電極との間に、抵抗変化層およびイオン源層が積層された記憶層が設けられた構成となっている。この記憶素子の構成を上記の固体電解質型スイッチ素子の構成と対比すると、抵抗変化層は固体電解質層に相当し、イオン源層は金属イオンを供給する電極に相当する。 An example of a memory element using a solid electrolyte is disclosed in Patent Document 1. The memory element disclosed in Patent Document 1 has a configuration in which a memory layer in which a resistance change layer and an ion source layer are stacked is provided between a first electrode and a second electrode. When the configuration of the memory element is compared with the configuration of the solid electrolyte switch element, the resistance change layer corresponds to a solid electrolyte layer, and the ion source layer corresponds to an electrode for supplying metal ions.
　固体電解質型スイッチ素子の不揮発性メモリおよび不揮発性スイッチへの応用においては、オフ状態は、より低いリーク電流、すなわちより高抵抗であることが好ましい。したがって、オフ状態の高抵抗化を図るためには、一般的に、リセット動作時により高い正電圧を印加することが行われる。しかしながら、ある電圧以上の高いリセット電圧を印加すると固体電解質層内にて絶縁破壊を生じ、正常なオン状態よりも低抵抗の状態に遷移したままそれ以上抵抗変化を示さなくなる。この電圧を絶縁破壊電圧と呼ぶ。したがって、絶縁破壊電圧が高くなるように素子を設計し、製造することで、高いリセット電圧を印加でき、より高抵抗のオフ状態が得られる。 In application of the solid electrolyte switch element to a nonvolatile memory and a nonvolatile switch, the off state is preferably a lower leakage current, that is, a higher resistance. Therefore, in order to increase the resistance in the OFF state, generally, a higher positive voltage is applied during the reset operation. However, when a high reset voltage higher than a certain voltage is applied, dielectric breakdown occurs in the solid electrolyte layer, and the resistance change does not show any more while transitioning to a lower resistance state than the normal ON state. This voltage is called a dielectric breakdown voltage. Therefore, a high reset voltage can be applied and a higher resistance OFF state can be obtained by designing and manufacturing the element so that the dielectric breakdown voltage becomes high.
　一方、オン状態は、信号遅延の抑制や保持特性の向上の観点から、より低抵抗であることが好ましい。オン状態の低抵抗化を図るためには、一般的に、セット時に流れるセット電流（Ｉｓｅｔ）を大きく設定すればよい。しかしながら、一定以上のＩｓｅｔが流れると、リセット動作においてより大きなリセット電流が必要となり、回路上の電流量の制約からリセットできずオフ不良が発生しやすくなる。したがって、セット時においては、適切なＩｓｅｔの制御が求められる。 On the other hand, it is preferable that the ON state has a lower resistance from the viewpoint of suppressing signal delay and improving retention characteristics. In order to reduce the resistance in the ON state, generally, a set current (Iset) that flows at the time of setting may be set large. However, if Iset above a certain level flows, a larger reset current is required in the reset operation, and resetting cannot be performed due to restrictions on the amount of current on the circuit, and off defects are likely to occur. Therefore, at the time of setting, appropriate Iset control is required.
　これらを半導体装置における銅多層配線内部に形成する手法について知られている。例えば、特許文献２および特許文献３には、ＣＭＯＳ（Complementary Metal Oxide Semiconductor）基板上の銅多層配線構造の内部に設けられた２端子スイッチング素子が開示されている。この２端子スイッチング素子では、ＣＭＯＳ基板上の銅多層配線構造の内部において、絶縁層の一部を開口加工して露出した銅配線そのものを、金属イオンを固体電解質中へ供給する活性電極として用いている。 A method for forming these inside a copper multilayer wiring in a semiconductor device is known. For example, Patent Literature 2 and Patent Literature 3 disclose a two-terminal switching element provided inside a copper multilayer wiring structure on a CMOS (Complementary Metal Oxide Semiconductor) substrate. In this two-terminal switching element, the copper wiring itself exposed by opening a part of the insulating layer inside the copper multilayer wiring structure on the CMOS substrate is used as an active electrode for supplying metal ions into the solid electrolyte. Yes.
　また、非特許文献１には、同一の開口部に露出した２つの下部電極を対向させた構造からなる２つの抵抗変化素子を直列に接続した相補型抵抗変化素子を構成し、抵抗状態の信頼性を向上する技術が開示されている。 Further, Non-Patent Document 1 includes a complementary resistance change element in which two resistance change elements each having a structure in which two lower electrodes exposed in the same opening are opposed to each other are connected in series. A technique for improving the performance is disclosed.
　また、非特許文献２には、相補型抵抗変化素子において、接続端子にさらに整流素子を接続することで、信号伝達動作時に書き込み端子が整流素子によって電気的に分離され、セルごとに選択トランジスタを接続する必要がなく、セル面積を低減する方法が開示されている。 In Non-Patent Document 2, in a complementary resistance change element, a write terminal is electrically separated by a rectifier element during signal transmission operation by further connecting a rectifier element to the connection terminal, and a selection transistor is provided for each cell. A method for reducing the cell area without the need for connection is disclosed.
　さらに、非特許文献３には、相補型抵抗変化素子において、接続端子に２つの整流素子を接続することで、クロスバーアレイにて、同一の行あるいは列内の相補型抵抗変化素子をセットでき、信号のマルチファンアウト出力を可能とする方法が開示されている。 Further, in Non-Patent Document 3, in a complementary resistance change element, by connecting two rectifying elements to a connection terminal, complementary resistance change elements in the same row or column can be set in a crossbar array. A method for enabling multi-fanout output of a signal is disclosed.
特開２０１１－１８７９２５号公報JP 2011-187925 A 特開２０１１－０９１３１７号公報JP 2011-091317 A 国際公開第２０１０／０７９８１６号International Publication No. 2010/0779816
　以下の分析は、本願発明者により与えられる。 The following analysis is given by the present inventor.
　十分に低い抵抗変化素子のオン抵抗を得るためには、Ｉｓｅｔを大きくする必要があり、そのためにはセットに要するセット電圧（Ｖｓｅｔ）を高くする必要がある。しかしながら、非特許文献２及び３に開示された相補型抵抗変化素子において、接続端子に１つ又は２つの整流素子が接続された構成においては、一方の抵抗変化素子をセットする際に、直列接続された整流素子を介してＶｓｅｔを印加するため、セット時に抵抗変化素子がオフ状態からオン状態に変化した瞬間、Ｖｓｅｔの大部分が整流素子に印加されるともに大きなＩｓｅｔが流れ、整流素子の不可逆な絶縁破壊が発生する可能性がある。したがって、非特許文献２及び３に開示された相補型抵抗変化素子では、絶縁破壊を抑制するためにＶｓｅｔを低く設定せざるをえず、十分に低いオン抵抗を得るのが困難で、セット歩留まりが低下してしまうという可能性があった。したがって、整流素子の絶縁破壊を防止しながら、セット歩留まりを改善した抵抗変化素子アレイが求められる。 In order to obtain a sufficiently low on-resistance of the variable resistance element, it is necessary to increase Iset, and for this purpose, it is necessary to increase the set voltage (Vset) required for setting. However, in the complementary resistance change elements disclosed in Non-Patent Documents 2 and 3, in the configuration in which one or two rectifier elements are connected to the connection terminal, when one resistance change element is set, the series connection is performed. Since Vset is applied via the rectified element, at the moment when the variable resistance element changes from the OFF state to the ON state at the time of setting, the majority of Vset is applied to the rectifier element, and a large Iset flows, irreversible of the rectifier element May cause serious dielectric breakdown. Therefore, in the complementary resistance change elements disclosed in Non-Patent Documents 2 and 3, Vset must be set low in order to suppress dielectric breakdown, and it is difficult to obtain a sufficiently low on-resistance, and the set yield is low. There was a possibility that would decrease. Therefore, there is a need for a variable resistance element array that improves the set yield while preventing dielectric breakdown of the rectifying element.
　本発明の主な課題は、セット時の整流素子の絶縁破壊を防止しつつ、セット歩留まりを改善することができる抵抗変化素子アレイ及びその制御方法を提供することである。 The main object of the present invention is to provide a variable resistance element array and a control method therefor that can improve the set yield while preventing the dielectric breakdown of the rectifying element at the time of setting.
　第１の視点に係る抵抗変化素子アレイは、２つの抵抗変化素子と２つの整流素子とを含むスイッチングセルであって、第１の方向、及び、前記第１の方向とは異なる第２の方向に配列して配置された複数のスイッチングセルと、前記複数のスイッチングセルが配置されたアレイ領域において前記第１の方向に延在した複数対の第１及び第２選択配線と、前記アレイ領域において前記第２の方向に延在した複数対の第３及び第４選択配線と、対応する前記第１、第２、第３及び第４選択配線に、それぞれ、電気的に接続された少なくとも１つの第１、第２、第３及び第４選択スイッチング素子と、を備え、前記スイッチングセルにおいて、２つの前記抵抗変化素子の同一極性の一方の端子同士と、２つの前記整流素子の同一極性の一方の端子同士とは、共通に電気的に接続され、前記第１の方向に配列した同じライン上の各前記スイッチングセルにおける前記２つの抵抗変化素子のうち一方の抵抗変化素子の他方の端子は、対応する前記第１選択配線に電気的に接続され、前記第１の方向に配列した同じライン上の各前記スイッチングセルにおける前記２つの整流素子のうち一方の整流素子の他方の端子は、対応する前記第２選択配線に電気的に接続され、前記第２の方向に配列した同じライン上の各前記スイッチングセルにおける前記２つの抵抗変化素子のうち他方の抵抗変化素子の他方の端子は、対応する前記第３選択配線に電気的に接続され、前記第２の方向に配列した同じ列の各前記スイッチングセルにおける前記２つの整流素子のうち他方の整流素子の他方の端子は、対応する前記第４選択配線に電気的に接続され、前記第１及び第３選択スイッチング素子の各駆動電流量は、前記第２及び第４選択スイッチング素子の各駆動電流量と異なる。 The variable resistance element array according to the first aspect is a switching cell including two variable resistance elements and two rectifying elements, and includes a first direction and a second direction different from the first direction. A plurality of switching cells arranged in an array, a plurality of pairs of first and second selection wirings extending in the first direction in the array region in which the plurality of switching cells are disposed, and in the array region At least one of the plurality of pairs of third and fourth selection wirings extending in the second direction and the corresponding first, second, third, and fourth selection wirings are electrically connected to each other. First, second, third and fourth selective switching elements, and in the switching cell, one terminal of the same polarity of the two variable resistance elements and one of the same polarity of the two rectifying elements Terminal And the other terminal of one of the variable resistance elements of the two variable resistance elements in each of the switching cells on the same line arranged in the first direction is electrically connected in common. The other terminal of one rectifying element of the two rectifying elements in each switching cell on the same line electrically connected to the first selection wiring and arranged in the first direction corresponds to the corresponding first The other terminal of the other resistance change element among the two resistance change elements in each of the switching cells on the same line that is electrically connected to two selection wirings and arranged in the second direction corresponds to the corresponding first The other terminal of the other rectifying element of the two rectifying elements in each of the switching cells of the same column electrically connected to the three selection wirings and arranged in the second direction is a pair It is electrically connected to the fourth selection wiring, the drive current amount of the first and third selection switching element is different from the respective drive current amount of the second and fourth selection switching elements.
　第２の視点に係る抵抗変化素子アレイの制御方法は、第１の視点に係る抵抗変化素子アレイの制御方法であって、選択された前記スイッチングセルにおける前記２つの抵抗変化素子がそれぞれオフ状態にあるときに、選択された前記スイッチングセルにおける前記２つの整流素子のうち少なくとも一方の整流素子の他方の端子を接地に接続し、かつ、選択された前記スイッチングセルにおける前記２つの抵抗変化素子のうち少なくとも一方の抵抗変化素子の他方の端子に負電圧を印加することによって、選択された前記スイッチングセルにおける前記２つの抵抗変化素子が全体としてオン状態に変化するように制御する。 A resistance change element array control method according to a second aspect is the resistance change element array control method according to the first aspect, wherein the two resistance change elements in the selected switching cell are in an OFF state, respectively. At one time, the other terminal of at least one rectifying element of the two rectifying elements in the selected switching cell is connected to ground, and of the two variable resistance elements in the selected switching cell. By applying a negative voltage to the other terminal of at least one of the resistance change elements, the two resistance change elements in the selected switching cell are controlled to be turned on as a whole.
　前記第１～第２の視点によれば、セット時の整流素子の絶縁破壊を防止しつつ、セット歩留まりを改善することができる。 According to the first and second viewpoints, it is possible to improve the set yield while preventing dielectric breakdown of the rectifying element during setting.
実施形態１に係る抵抗変化素子アレイにおけるスイッチングセルの構成を模式的に示した回路図である。3 is a circuit diagram schematically showing a configuration of a switching cell in the variable resistance element array according to Embodiment 1. FIG. 実施形態１に係る抵抗変化素子アレイにおけるスイッチングセルの抵抗変化素子の構成の一例を示した模式図である。3 is a schematic diagram illustrating an example of a configuration of a variable resistance element of a switching cell in the variable resistance element array according to Embodiment 1. FIG. 実施形態１に係る抵抗変化素子アレイの構成を模式的に示した回路図である。FIG. 3 is a circuit diagram schematically showing the configuration of the variable resistance element array according to the first embodiment. 実施形態１に係る抵抗変化素子アレイを含む記憶装置の構成を模式的に示したブロック図である。1 is a block diagram schematically showing a configuration of a storage device including a variable resistance element array according to Embodiment 1. FIG. 実施形態２に係る抵抗変化素子アレイの構成を模式的に示した回路図である。FIG. 5 is a circuit diagram schematically showing a configuration of a variable resistance element array according to Embodiment 2.
　以下、実施形態について図面を参照しつつ説明する。なお、本出願において図面参照符号を付している場合は、それらは、専ら理解を助けるためのものであり、図示の態様に限定することを意図するものではない。なお、下記の実施形態は、あくまで例示であり、本発明を限定するものではない。また、以降の説明で参照する図面等のブロック間の接続線は、双方向及び単方向の双方を含む。一方向矢印については、主たる信号（データ）の流れを模式的に示すものであり、双方向性を排除するものではない。 Hereinafter, embodiments will be described with reference to the drawings. Note that, in the present application, where reference numerals are attached to the drawings, these are only for the purpose of helping understanding, and are not intended to be limited to the illustrated embodiments. In addition, the following embodiment is an illustration to the last and does not limit this invention. In addition, connection lines between blocks such as drawings referred to in the following description include both bidirectional and unidirectional directions. The unidirectional arrow schematically shows the main signal (data) flow and does not exclude bidirectionality.
［実施形態１］
　実施形態１に係る抵抗変化素子アレイにおけるスイッチングセルについて図面を用いて説明する。図１は、実施形態１に係る抵抗変化素子アレイにおけるスイッチングセルの構成を模式的に示した回路図である。図２は、実施形態１に係る抵抗変化素子アレイにおけるスイッチングセルの抵抗変化素子の構成の一例を示した模式図である。図３は、実施形態１に係る抵抗変化素子アレイの構成を模式的に示した回路図である。図４は、実施形態１に係る抵抗変化素子アレイを含む記憶装置の構成を模式的に示したブロック図である。 [Embodiment 1]
A switching cell in the variable resistance element array according to Embodiment 1 will be described with reference to the drawings. FIG. 1 is a circuit diagram schematically illustrating a configuration of a switching cell in the variable resistance element array according to the first embodiment. FIG. 2 is a schematic diagram illustrating an example of the configuration of the variable resistance element of the switching cell in the variable resistance element array according to the first embodiment. FIG. 3 is a circuit diagram schematically illustrating the configuration of the variable resistance element array according to the first embodiment. FIG. 4 is a block diagram schematically illustrating a configuration of a storage device including the resistance change element array according to the first embodiment.
　図１を参照すると、スイッチングセル１０は、第１抵抗変化素子１１及び第２抵抗変化素子１２と第１整流素子１３及び第２整流素子１４とを含む基本回路（セル）である。 Referring to FIG. 1, the switching cell 10 is a basic circuit (cell) including a first resistance change element 11 and a second resistance change element 12, a first rectification element 13, and a second rectification element 14.
　第１抵抗変化素子１１及び第２抵抗変化素子１２は、抵抗状態の変化によって情報を記憶することが可能な素子である（図１参照）。第１抵抗変化素子１１及び第２抵抗変化素子１２には、２端子型の抵抗変化素子が用いられる。第１抵抗変化素子１１及び第２抵抗変化素子１２は、第１電極１と第２電極２との間に抵抗変化層３を挟んだ３層構造を有している（図２参照）。第１抵抗変化素子１１及び第２抵抗変化素子１２の各抵抗変化層３は、互いに分離して独立している。第１抵抗変化素子１１は、第２抵抗変化素子１２と同じ構成とすることができる。第１抵抗変化素子１１及び第２抵抗変化素子１２は、半導体基板（図示せず）上に形成された多層配線構造（図示せず）の内部に設けることができる。第１抵抗変化素子１１の第１電極１は、第１端子１１ａに電気的に接続されている（図１、図２参照）。第１抵抗変化素子１１の第２電極２は、第２端子１１ｂに電気的に接続されている。第２抵抗変化素子１２の第１電極１は、第１端子１２ａに電気的に接続されている。第２抵抗変化素子１２の第２電極２は、第２端子１２ｂに電気的に接続されている。第１抵抗変化素子１１及び第２抵抗変化素子１２は、第１電極１と第２電極２との間に電圧を印加することで抵抗変化層３の抵抗変化が生じる。 The first resistance change element 11 and the second resistance change element 12 are elements capable of storing information according to a change in resistance state (see FIG. 1). As the first resistance change element 11 and the second resistance change element 12, a two-terminal resistance change element is used. The first variable resistance element 11 and the second variable resistance element 12 have a three-layer structure in which the variable resistance layer 3 is sandwiched between the first electrode 1 and the second electrode 2 (see FIG. 2). The variable resistance layers 3 of the first variable resistance element 11 and the second variable resistance element 12 are separated from each other and independent. The first variable resistance element 11 can have the same configuration as the second variable resistance element 12. The first variable resistance element 11 and the second variable resistance element 12 can be provided inside a multilayer wiring structure (not shown) formed on a semiconductor substrate (not shown). The first electrode 1 of the first variable resistance element 11 is electrically connected to the first terminal 11a (see FIGS. 1 and 2). The second electrode 2 of the first variable resistance element 11 is electrically connected to the second terminal 11b. The first electrode 1 of the second resistance change element 12 is electrically connected to the first terminal 12a. The second electrode 2 of the second variable resistance element 12 is electrically connected to the second terminal 12b. In the first resistance change element 11 and the second resistance change element 12, a resistance change of the resistance change layer 3 occurs when a voltage is applied between the first electrode 1 and the second electrode 2.
　第１抵抗変化素子１１及び第２抵抗変化素子１２としては、抵抗変化層３として金属酸化物を用いたＲｅＲＡＭや、抵抗変化層３として固体電解質を用いた固体電解質型スイッチ素子などを用いることができる。第１抵抗変化素子１１及び第２抵抗変化素子１２が固体電解質型スイッチ素子の場合、第１電極１及び第２電極２のうち一方の電極には、金属イオンの供給源となる材料が用いられ、化学的に活性であり（イオン化しやすく）、かつ、電圧印加により容易に酸化および還元が可能な金属材料（例えば、Ｃｕ、Ｔａ）を用いることができる。同じく他方の電極には、化学的に不活性な（イオン化しにくい）金属材料（例えば、Ｒｕ、Ｔｉ）を用いることができる。抵抗変化層３は、第１電極１と第２電極２との間の電圧印加により金属イオンを容易に溶出もしくは回収することができ、かつ、スイッチングサイクルによる材料劣化が小さい材料を用いることができる。抵抗変化層３には、例えば、Ａｌ、Ｃｏ、Ｆｅ、Ｈｆ、Ｍｎ、Ｎｂ、Ｓｉ、Ｔａ、Ｔｉ、Ｚｎ、Ｚｒのうち、すくなくとも１つを含む酸化物、あるいはカルコゲナイド、アモルファスＳｉ、ＳｉＯＣＨ等を用いることができる。 As the first resistance change element 11 and the second resistance change element 12, a ReRAM using a metal oxide as the resistance change layer 3, a solid electrolyte switch element using a solid electrolyte as the resistance change layer 3, or the like is used. it can. In the case where the first resistance change element 11 and the second resistance change element 12 are solid electrolyte type switch elements, a material serving as a metal ion supply source is used for one of the first electrode 1 and the second electrode 2. A metal material (for example, Cu, Ta) that is chemically active (easily ionized) and that can be easily oxidized and reduced by applying a voltage can be used. Similarly, a metal material (for example, Ru, Ti) that is chemically inert (not easily ionized) can be used for the other electrode. The resistance change layer 3 can be made of a material that can easily elute or collect metal ions by applying a voltage between the first electrode 1 and the second electrode 2 and that has little material deterioration due to a switching cycle. . The resistance change layer 3 is made of, for example, an oxide containing at least one of Al, Co, Fe, Hf, Mn, Nb, Si, Ta, Ti, Zn, and Zr, or chalcogenide, amorphous Si, and SiOCH. Can be used.
　第１整流素子１３及び第２整流素子１４は、両方向に同じ特性で電流を流す整流作用を有する素子である。第１整流素子１３及び第２整流素子１４には、２端子型の整流素子が用いられる。第１整流素子１３及び第２整流素子１４として、例えば、バリスタ（例えば、ａ－Ｓｉ／ＳｉＮ／ａ－Ｓｉ）、閾値スイッチ（例えば、オボニック閾値スイッチ、イオン電子混合伝導体スイッチ）、ゼットラップ、ツェナーダイオードを直列又は並列に電気的に接続したもの、アバランシェダイオードを直列又は並列に電気的に接続したもの、ダイオード（例えば、シリコンダイオード、ゲルマニウムダイオード）を直列又は並列に電気的に接続したもの等を用いることができる。 The first rectifying element 13 and the second rectifying element 14 are elements having a rectifying action for flowing current with the same characteristics in both directions. A two-terminal rectifier is used for the first rectifier 13 and the second rectifier 14. Examples of the first rectifying element 13 and the second rectifying element 14 include a varistor (for example, a-Si / SiN / a-Si), a threshold switch (for example, an ovonic threshold switch, an ion-electron mixed conductor switch), a zet wrap, Zener diodes electrically connected in series or parallel, avalanche diodes electrically connected in series or parallel, diodes (eg silicon diode, germanium diode) electrically connected in series or parallel, etc. Can be used.
　スイッチングセル１０において、第１抵抗変化素子１１及び第２抵抗変化素子１２の同一極性の第１端子１１ａ、１２ａ同士と、第１整流素子１３及び第２整流素子１４の同一極性の第１端子１３ａ、１４ａ同士とは、共通に電気的に接続されている。第１抵抗変化素子１１の第２端子１１ｂは、対応する第１選択配線（図３の２１）に電気的に接続される。第１整流素子１３の第２端子１３ｂは、対応する第２選択配線（図３の２２）に電気的に接続される。第２抵抗変化素子１２の第２端子１２ｂは、対応する第３選択配線（図３の２３）に電気的に接続される。第２整流素子１４の第２端子１４ｂは、対応する第４選択配線（図３の２４）に電気的に接続される。 In the switching cell 10, the first terminals 11 a and 12 a having the same polarity of the first variable resistance element 11 and the second variable resistance element 12, and the first terminals 13 a having the same polarity of the first rectifying element 13 and the second rectifying element 14. , 14a are electrically connected in common. The second terminal 11b of the first resistance change element 11 is electrically connected to the corresponding first selection wiring (21 in FIG. 3). The second terminal 13b of the first rectifying element 13 is electrically connected to the corresponding second selection wiring (22 in FIG. 3). The second terminal 12b of the second resistance change element 12 is electrically connected to the corresponding third selection wiring (23 in FIG. 3). The second terminal 14b of the second rectifying element 14 is electrically connected to the corresponding fourth selection wiring (24 in FIG. 3).
　なお、抵抗変化素子１１、１２の各第１端子１１ａ、１２ａと、整流素子１３、１４の各第１端子１３ａ、１４ａと、が電気的に接続された構成であることは、種々の測定器（例えば、透過型電子線顕微鏡、走査型電子顕微鏡等）で確認することが可能である。 In addition, it is various measuring instruments that each 1st terminal 11a, 12a of the resistance change elements 11 and 12 and each 1st terminal 13a, 14a of the rectifier elements 13 and 14 are electrically connected. (For example, it can be confirmed with a transmission electron microscope, a scanning electron microscope, or the like).
　以上のようなスイッチングセル１０では、例えば、第１抵抗変化素子１１及び第２抵抗変化素子１２が固体電解質型スイッチ素子であって、第１電極１が化学的に活性な電極であり、第２電極２が化学的に不活性な電極とすると、以下のような動作を行う。 In the switching cell 10 as described above, for example, the first resistance change element 11 and the second resistance change element 12 are solid electrolyte switch elements, the first electrode 1 is a chemically active electrode, and the second If the electrode 2 is a chemically inert electrode, the following operation is performed.
　第１抵抗変化素子１１及び第２抵抗変化素子１２がそれぞれオフ状態（高抵抗状態）にあるときに、第１整流素子１３の第２端子１３ｂ及び第２整流素子１４の第２端子１４ｂの少なくとも一方を接地に接続し、第１抵抗変化素子１１の第２端子１１ｂ及び第２抵抗変化素子１２の第２端子１２ｂの少なくとも一方に正電圧（書き込み電圧）を印加すると、第１抵抗変化素子１１及び第２抵抗変化素子１２の少なくとも一方において第１電極１を構成する金属原子がイオン化して抵抗変化層３中に溶出し、金属イオンが第２電極２から供給される電子と結合して、抵抗変化層３に、導電性を有する金属架橋（図示せず）が形成される。この抵抗変化層３中に形成された金属架橋により第１電極１と第２電極２が電気的に接続されることで、第１抵抗変化素子１１及び第２抵抗変化素子１２が全体としてオン状態（低抵抗状態）に変化する。なお、ここでの電圧の印加条件は、抵抗変化素子や周辺回路の形態、所望するオン状態などに依存して決まり、パルス印加でもスイープ印加でもよい。 When the first variable resistance element 11 and the second variable resistance element 12 are each in an off state (high resistance state), at least the second terminal 13b of the first rectifying element 13 and the second terminal 14b of the second rectifying element 14 When one side is connected to ground and a positive voltage (write voltage) is applied to at least one of the second terminal 11b of the first resistance change element 11 and the second terminal 12b of the second resistance change element 12, the first resistance change element 11 And metal atoms constituting the first electrode 1 are ionized and eluted into the resistance change layer 3 in at least one of the second resistance change elements 12, and the metal ions are combined with electrons supplied from the second electrode 2, A conductive metal bridge (not shown) is formed in the resistance change layer 3. Since the first electrode 1 and the second electrode 2 are electrically connected by the metal bridge formed in the resistance change layer 3, the first resistance change element 11 and the second resistance change element 12 are turned on as a whole. (Low resistance state). Note that the voltage application conditions here are determined depending on the form of the resistance change element and the peripheral circuit, a desired ON state, and the like, and may be pulse application or sweep application.
　一方、オン状態において、第１抵抗変化素子１１の第２端子１１ｂ及び第２抵抗変化素子１２の第２端子１２ｂの少なくとも一方を接地に接続し、第１整流素子１３の第２端子１３ｂ及び第２整流素子１４の第２端子１４ｂの少なくとも一方に正電圧（消去電圧）を印加すると、オン状態である抵抗変化素子１１、１２の少なくとも一方に係る金属架橋の金属原子がイオン化し、金属イオンが第１電極１から供給される電子と結合して第１電極１に引き戻され、両電極が電気的に絶縁されることで、第１抵抗変化素子１１及び第２抵抗変化素子１２が全体としてオフ状態（高抵抗状態）に戻る。 On the other hand, in the ON state, at least one of the second terminal 11b of the first variable resistance element 11 and the second terminal 12b of the second variable resistance element 12 is connected to the ground, and the second terminal 13b of the first rectifying element 13 and the second terminal 12b are connected. When a positive voltage (erase voltage) is applied to at least one of the second terminals 14b of the two rectifying elements 14, the metal atoms of the metal bridge relating to at least one of the resistance change elements 11 and 12 in the on state are ionized, and the metal ions are The first resistance change element 11 and the second resistance change element 12 are turned off as a whole by being combined with electrons supplied from the first electrode 1 and pulled back to the first electrode 1 and electrically insulating both electrodes. Return to the state (high resistance state).
　以上のようなスイッチングセル１０は、図３の抵抗変化素子アレイ１００に用いることができる。抵抗変化素子アレイ１００は、複数の抵抗変化素子１１、１２を含むスイッチングセル１０が配列したアレイである。抵抗変化素子アレイ１００は、スイッチングセル１０と、第１～第４選択配線２１～２４と、カラムデコーダ３０と、ロウデコーダ４０と、を有する。 The switching cell 10 as described above can be used in the variable resistance element array 100 of FIG. The resistance change element array 100 is an array in which switching cells 10 including a plurality of resistance change elements 11 and 12 are arranged. The variable resistance element array 100 includes a switching cell 10, first to fourth selection wirings 21 to 24, a column decoder 30, and a row decoder 40.
　スイッチングセル１０は、図１及び図２で説明した通りの構成である。スイッチングセル１０は、アレイ領域２０において、複数配置され、第１の方向（Ｘ方向）、及び、第１の方向（Ｘ方向）とは異なる第２の方向（Ｙ方向）に配列して配置されている。なお、図３ではＸ方向とＹ方向との成す角度は直角であるが、Ｘ方向とＹ方向との成す角度が鈍角又は鋭角であってもよい。 The switching cell 10 has a configuration as described with reference to FIGS. A plurality of switching cells 10 are arranged in the array region 20 and arranged in a first direction (X direction) and a second direction (Y direction) different from the first direction (X direction). ing. In FIG. 3, the angle formed between the X direction and the Y direction is a right angle, but the angle formed between the X direction and the Y direction may be an obtuse angle or an acute angle.
　第１の方向（Ｘ方向）に配列した同じライン上の各スイッチングセル１０における第１抵抗変化素子１１の第２端子（図１の１１ｂ）は、対応する第１選択配線２１に電気的に接続されている。また、第１の方向（Ｘ方向）に配列した同じライン上の各スイッチングセル１０における第１整流素子１３の第２端子（図１の１３ｂ）は、対応する第２選択配線２２に電気的に接続されている。また、第２の方向（Ｙ方向）に配列した同じライン上の各スイッチングセル１０における第２抵抗変化素子１２の第２端子（図１の１２ｂ）は、対応する第３選択配線２３に電気的に接続されている。第２の方向（Ｙ方向）に配列した同じライン上の各スイッチングセル１０における第２整流素子１４の第２端子（図１の１４ｂ）は、対応する第４選択配線２４に電気的に接続されている。 The second terminal (11b in FIG. 1) of the first resistance change element 11 in each switching cell 10 on the same line arranged in the first direction (X direction) is electrically connected to the corresponding first selection wiring 21. Has been. Further, the second terminal (13b in FIG. 1) of the first rectifying element 13 in each switching cell 10 on the same line arranged in the first direction (X direction) is electrically connected to the corresponding second selection wiring 22. It is connected. Further, the second terminal (12b in FIG. 1) of the second variable resistance element 12 in each switching cell 10 on the same line arranged in the second direction (Y direction) is electrically connected to the corresponding third selection wiring 23. It is connected to the. The second terminal (14b in FIG. 1) of the second rectifying element 14 in each switching cell 10 on the same line arranged in the second direction (Y direction) is electrically connected to the corresponding fourth selection wiring 24. ing.
　第１選択配線２１及び第２選択配線２２は、アレイ領域２０において第１の方向（Ｘ方向）に延在した配線である。第１選択配線２１及び第２選択配線２２は、対を成す。第１選択配線２１及び第２選択配線２２の対は、アレイ領域２０において複数（ビット線ＢＬ１１及びＢＬ２１の対、ＢＬ１２及びＢＬ２２の対、・・・、ＢＬ１ｎ及びＢＬ２ｎの対）ある。 The first selection wiring 21 and the second selection wiring 22 are wirings extending in the first direction (X direction) in the array region 20. The first selection wiring 21 and the second selection wiring 22 form a pair. There are a plurality of pairs of the first selection wiring 21 and the second selection wiring 22 (a pair of bit lines BL11 and BL21, a pair of BL12 and BL22,..., A pair of BL1n and BL2n).
　第３選択配線２３及び第４選択配線２４は、アレイ領域２０において第２の方向（Ｙ方向）に延在した配線である。第３選択配線２３及び第４選択配線２４は、対を成す。第３選択配線２３及び第４選択配線２４の対は、アレイ領域２０において複数（ワード線ＷＬ１１及びＷＬ２１の対、ＷＬ１２及びＷＬ２２の対、・・・、ＷＬ１ｍ及びＷＬ２ｍの対）ある。 The third selection wiring 23 and the fourth selection wiring 24 are wirings extending in the second direction (Y direction) in the array region 20. The third selection wiring 23 and the fourth selection wiring 24 make a pair. There are a plurality of pairs of the third selection wiring 23 and the fourth selection wiring 24 in the array region 20 (a pair of word lines WL11 and WL21, a pair of WL12 and WL22,..., A pair of WL1m and WL2m).
　第１選択配線２１の寄生電気容量は、第３選択配線２３の寄生電気容量と等しくすることができる。また、第１選択配線２１の長さは、第３選択配線２３の長さと等しくすることができる。第２選択配線２２の寄生電気容量は、第４選択配線２４の寄生電気容量と等しくすることができる。また、第２選択配線２２の長さは、第４選択配線２４の長さと等しくすることができる。 The parasitic capacitance of the first selection wiring 21 can be made equal to the parasitic capacitance of the third selection wiring 23. Further, the length of the first selection wiring 21 can be made equal to the length of the third selection wiring 23. The parasitic capacitance of the second selection wiring 22 can be made equal to the parasitic capacitance of the fourth selection wiring 24. Further, the length of the second selection wiring 22 can be made equal to the length of the fourth selection wiring 24.
　第１選択配線２１及び第４選択配線２４、又は、第２選択配線２２及び第３選択配線２３にて選択されるスイッチングセル１０における抵抗変化素子１１又は１２に流れるセット電流は、１０μＡ以上かつ１ｍＡ以下に設定することができる。 The set current flowing through the resistance change element 11 or 12 in the switching cell 10 selected by the first selection wiring 21 and the fourth selection wiring 24 or the second selection wiring 22 and the third selection wiring 23 is 10 μA or more and 1 mA. The following can be set.
　カラムデコーダ３０は、ビット線ＢＬ１１及びＢＬ２１の対、ＢＬ１２及びＢＬ２２の対、・・・、ＢＬ１ｎ及びＢＬ２ｎの対に係る第１選択配線２１及び第２選択配線２２を選択するためのデコーダである。カラムデコーダ３０は、ロウデコーダ４０との協働により、アレイ領域２０の中から１つのスイッチングセル１０を選択するセル選択回路として機能する。カラムデコーダ３０は、ビット線ＢＬ１１～ＢＬ１ｎに係る各第１選択配線２１に、それぞれ、電気的に接続された複数の第１電界効果トランジスタ３１を有する。また、カラムデコーダ３０は、ビット線ＢＬ２１～ＢＬ２ｎに係る各第２選択配線２２に、それぞれ、電気的に接続された複数の第２電界効果トランジスタ３２を有する。カラムデコーダ３０は、制御回路（図４の５０）のアレイ制御回路（図４の５１）の制御により、ビット線ＢＬ１１及びＢＬ２１の対、ＢＬ１２及びＢＬ２２の対、・・・、ＢＬ１ｎ及びＢＬ２ｎの対ごとに第１選択配線２１及び第２選択配線２２を選択する。 The column decoder 30 is a decoder for selecting the first selection wiring 21 and the second selection wiring 22 related to the pair of bit lines BL11 and BL21, the pair of BL12 and BL22,..., BL1n and BL2n. The column decoder 30 functions as a cell selection circuit that selects one switching cell 10 from the array region 20 in cooperation with the row decoder 40. The column decoder 30 includes a plurality of first field effect transistors 31 that are electrically connected to the first selection lines 21 associated with the bit lines BL11 to BL1n, respectively. Further, the column decoder 30 includes a plurality of second field effect transistors 32 electrically connected to the second selection wirings 22 related to the bit lines BL21 to BL2n, respectively. The column decoder 30 is controlled by an array control circuit (51 in FIG. 4) of the control circuit (50 in FIG. 4), a pair of bit lines BL11 and BL21, a pair of BL12 and BL22,..., A pair of BL1n and BL2n. The first selection wiring 21 and the second selection wiring 22 are selected every time.
　ロウデコーダ４０は、ワード線ＷＬ１１及びＷＬ２１の対、ＷＬ１２及びＷＬ２２の対、・・・、ＷＬ１ｍ及びＷＬ２ｍの対に係る第３選択配線２３及び第４選択配線２４を選択するためのデコーダである。ロウデコーダ４０は、カラムデコーダ３０との協働により、アレイ領域２０の中から１つのスイッチングセル１０を選択するセル選択回路として機能する。ロウデコーダ４０は、ワード線ＷＬ１１～ＷＬ１ｍに係る各第３選択配線２３に、それぞれ、電気的に接続された複数の第３電界効果トランジスタ４１を有する。また、ロウデコーダ４０は、ワード線ＷＬ２１～ＷＬ２ｍに係る各第４選択配線２４に、それぞれ、電気的に接続された複数の第４電界効果トランジスタ４２を有する。ロウデコーダ４０は、制御回路（図４の５０）のアレイ制御回路（図４の５１）の制御により、ワード線ＷＬ１１及びＷＬ２１の対、ＷＬ１２及びＷＬ２２の対、・・・、ＷＬ１ｍ及びＷＬ２ｍの対ごとに第３選択配線２３及び第４選択配線２４を選択する。 The row decoder 40 is a decoder for selecting the third selection wiring 23 and the fourth selection wiring 24 related to the pair of word lines WL11 and WL21, the pair of WL12 and WL22,..., WL1m and WL2m. The row decoder 40 functions as a cell selection circuit that selects one switching cell 10 from the array region 20 in cooperation with the column decoder 30. The row decoder 40 includes a plurality of third field effect transistors 41 that are electrically connected to the third selection wirings 23 related to the word lines WL11 to WL1m, respectively. In addition, the row decoder 40 includes a plurality of fourth field effect transistors 42 electrically connected to each of the fourth selection wirings 24 related to the word lines WL21 to WL2m. The row decoder 40 controls the pair of word lines WL11 and WL21, the pair of WL12 and WL22,..., WL1m and WL2m under the control of the array control circuit (51 in FIG. 4) of the control circuit (50 in FIG. 4). The third selection wiring 23 and the fourth selection wiring 24 are selected every time.
　第１電界効果トランジスタ３１は、対応するビット線ＢＬ１１～ＢＬ１ｎに係る第１選択配線２１に電気的に接続された選択スイッチング素子である。第２電界効果トランジスタ３２は、対応するビット線ＢＬ２１～ＢＬ２ｎに係る第２選択配線２２に電気的に接続された選択スイッチング素子である。第３電界効果トランジスタ４１は、対応するワード線ＷＬ１１～ＷＬ１ｍに係る第３選択配線２３に電気的に接続された選択スイッチング素子である。第４電界効果トランジスタ４２は、対応する第４選択配線２４にワード線ＷＬ２１～ＷＬ２ｍに係る電気的に接続された選択スイッチング素子である。 The first field effect transistor 31 is a selection switching element electrically connected to the first selection wiring 21 associated with the corresponding bit line BL11 to BL1n. The second field effect transistor 32 is a selection switching element electrically connected to the second selection wiring 22 associated with the corresponding bit line BL21 to BL2n. The third field effect transistor 41 is a selection switching element electrically connected to the third selection wiring 23 associated with the corresponding word lines WL11 to WL1m. The fourth field effect transistor 42 is a selection switching element that is electrically connected to the corresponding fourth selection wiring 24 according to the word lines WL21 to WL2m.
　第１電界効果トランジスタ３１及び第３電界効果トランジスタ４１の各駆動電流量は、第２電界効果トランジスタ３２及び第４電界効果トランジスタ４２の各駆動電流量と異なる。第１電界効果トランジスタ３１及び第３電界効果トランジスタ４１の各駆動電流量は、第２電界効果トランジスタ３２及び第４電界効果トランジスタ４２の各駆動電流量よりも大きい。なお、図３では電界効果トランジスタ３１、３２、４１、４２は選択配線２１～２４ごとに１つ設けられているが、これに限るものではなく、選択配線２１～２４ごとに電界効果トランジスタ３１、３２、４１、４２を直列又は並列に接続して複数設けることができる。また、第１電界効果トランジスタ３１及び第３電界効果トランジスタ４１のゲート幅は、第２電界効果トランジスタ３２及び第４電界効果トランジスタ４２のゲート幅よりも大きくなるように設定することができる。また、第１電界効果トランジスタ３１及び第３電界効果トランジスタ４１を２つ以上の電界効果トランジスタが並列に電気的に接続された構成とし、第１電界効果トランジスタ３１及び第３電界効果トランジスタ４１に含まれる電界効果トランジスタの並列数を、第２電界効果トランジスタ３２及び第４電界効果トランジスタ４２に含まれる電界効果トランジスタの並列数よりも多くなるように設定することができる。さらに、第１電界効果トランジスタ３１及び第３電界効果トランジスタ４１に含まれる電界効果トランジスタのチャネル長を、第２電界効果トランジスタ３２及び第４電界効果トランジスタ４２に含まれる電界効果トランジスタのチャネル長よりも小さくするように設定することができる。 The drive current amounts of the first field effect transistor 31 and the third field effect transistor 41 are different from the drive current amounts of the second field effect transistor 32 and the fourth field effect transistor 42. The drive current amounts of the first field effect transistor 31 and the third field effect transistor 41 are larger than the drive current amounts of the second field effect transistor 32 and the fourth field effect transistor 42. In FIG. 3, one field effect transistor 31, 32, 41, 42 is provided for each of the selection wirings 21 to 24. However, the present invention is not limited to this, and the field effect transistor 31, A plurality of 32, 41, and 42 can be connected in series or in parallel. The gate widths of the first field effect transistor 31 and the third field effect transistor 41 can be set to be larger than the gate widths of the second field effect transistor 32 and the fourth field effect transistor 42. Further, the first field effect transistor 31 and the third field effect transistor 41 are configured such that two or more field effect transistors are electrically connected in parallel, and are included in the first field effect transistor 31 and the third field effect transistor 41. The number of parallel field effect transistors can be set to be larger than the number of parallel field effect transistors included in the second field effect transistor 32 and the fourth field effect transistor 42. Further, the channel lengths of the field effect transistors included in the first field effect transistor 31 and the third field effect transistor 41 are set to be larger than the channel lengths of the field effect transistors included in the second field effect transistor 32 and the fourth field effect transistor 42. It can be set to be smaller.
　なお、図３では、選択スイッチング素子として電界効果トランジスタ３１、３２、４１、４２を用いているが、これに限るものではなく、選択スイッチング素子としてバイポーラトランジスタを用いてもよい。 In FIG. 3, the field effect transistors 31, 32, 41, and 42 are used as the selective switching elements. However, the present invention is not limited to this, and a bipolar transistor may be used as the selective switching element.
　図３の抵抗変化素子アレイ１００（アレイ領域２０、カラムデコーダ３０及びロウデコーダ４０）は、図４のような記憶装置２００に用いることができる。記憶装置２００は、アレイ領域２０、カラムデコーダ３０及びロウデコーダ４０を制御するための制御回路５０を有する。制御回路５０は、アレイ制御回路５１と、書き込み回路５２と、読み出し回路５３と、を備える。 3 can be used in the storage device 200 as shown in FIG. 4. The storage device 200 includes a control circuit 50 for controlling the array region 20, the column decoder 30 and the row decoder 40. The control circuit 50 includes an array control circuit 51, a write circuit 52, and a read circuit 53.
　アレイ制御回路５１は、カラムデコーダ３０及びロウデコーダ４０を制御することにより、アレイ領域２０の中から１つのスイッチングセル１０における第１抵抗変化素子１１及び第２抵抗変化素子１２の少なくとも一方を選択することが可能な制御回路である。書き込み回路５２は、選択された第１抵抗変化素子１１及び第２抵抗変化素子１２の少なくとも一方へ、対応する選択配線２１～２４を介して、書き込み電圧又は消去電圧を印加することが可能な回路である。読み出し回路５３は、選択された第１抵抗変化素子１１及び第２抵抗変化素子１２の少なくとも一方へ、対応する選択配線２１～２４を介して、読み出し電圧を印加することが可能な回路である。 The array control circuit 51 selects at least one of the first resistance change element 11 and the second resistance change element 12 in one switching cell 10 from the array region 20 by controlling the column decoder 30 and the row decoder 40. It is a control circuit that can. The write circuit 52 can apply a write voltage or an erase voltage to at least one of the selected first resistance change element 11 and second resistance change element 12 via the corresponding selection wirings 21 to 24. It is. The read circuit 53 is a circuit that can apply a read voltage to at least one of the selected first resistance change element 11 and second resistance change element 12 via the corresponding selection wirings 21 to 24.
　なお、実施形態１に係る抵抗変化素子アレイ１００は、例えば、ＤＲＡＭ、ＳＲＡＭ（Static RAM）、フラッシュメモリ、ＦＲＡＭ（Ferro-Electric RAM）（登録商標）、キャパシタ、バイポーラトランジスタ等のようなメモリ回路を有する半導体製品、マイクロプロセッサなどの論理回路を有する半導体製品、またはそれらを同時に搭載したボードやパッケージにも適用することができる。また、実施形態１に係る抵抗変化素子アレイ１００は、電子回路装置、光回路装置、量子回路装置、マイクロマシン、ＭＥＭＳ（Micro-Electro-Mechanical Systems）等にも適用することができる。 The variable resistance element array 100 according to the first embodiment includes memory circuits such as DRAM, SRAM (Static RAM), flash memory, FRAM (Ferro-Electric RAM) (registered trademark), capacitors, bipolar transistors, and the like. The present invention can also be applied to a semiconductor product having a logic circuit such as a microprocessor, a board having a logic circuit such as a microprocessor, or a board or package on which these are simultaneously mounted. The variable resistance element array 100 according to the first embodiment can also be applied to electronic circuit devices, optical circuit devices, quantum circuit devices, micromachines, MEMS (Micro-Electro-Mechanical Systems), and the like.
　実施形態１によれば、第１電界効果トランジスタ３１及び第３電界効果トランジスタ４１の各駆動電流量を、第２電界効果トランジスタ３２及び第４電界効果トランジスタ４２の各駆動電流量と異なるように設定することで、選択した抵抗変化素子１１、１２の少なくとも一方をセットする際に、抵抗変化素子１１、１２の少なくとも一方に十分な電圧を印加することができ、かつ、抵抗変化素子１１、１２の少なくとも一方をセットした直後に流れる電流を制限することができるので、整流素子１３、１４の絶縁破壊を防止しながら、セット歩留まりを改善することができる。 According to the first embodiment, the drive current amounts of the first field effect transistor 31 and the third field effect transistor 41 are set to be different from the drive current amounts of the second field effect transistor 32 and the fourth field effect transistor 42. Thus, when setting at least one of the selected resistance change elements 11 and 12, a sufficient voltage can be applied to at least one of the resistance change elements 11 and 12, and the resistance change elements 11 and 12 Since the current that flows immediately after setting at least one of them can be limited, the set yield can be improved while preventing dielectric breakdown of the rectifying elements 13 and 14.
［実施形態２］
　実施形態２に係る抵抗変化素子アレイについて図面を用いて説明する。図５は、実施形態２に係る抵抗変化素子アレイの構成を模式的に示した回路図である。 [Embodiment 2]
A variable resistance element array according to Embodiment 2 will be described with reference to the drawings. FIG. 5 is a circuit diagram schematically showing the configuration of the variable resistance element array according to the second embodiment.
　抵抗変化素子アレイ１００は、複数の抵抗変化素子１１、１２を含むスイッチングセル１０が配列したアレイである。抵抗変化素子アレイ１００は、スイッチングセル１０と、第１～第４選択配線２１～２４と、第１～第４選択スイッチング素子６１、６２、７１、７２と、を有する。 The resistance change element array 100 is an array in which switching cells 10 including a plurality of resistance change elements 11 and 12 are arranged. The resistance change element array 100 includes a switching cell 10, first to fourth selection wirings 21 to 24, and first to fourth selection switching elements 61, 62, 71, and 72.
　スイッチングセル１０は、第１抵抗変化素子１１及び第２抵抗変化素子１２と第１整流素子１３及び第２整流素子１４とを含む。スイッチングセル１０は、アレイ領域２０において、複数配置され、第１の方向（Ｘ方向）、及び、第１の方向（Ｘ方向）とは異なる第２の方向（Ｙ方向）に配列して配置されている。スイッチングセル１０において、第１抵抗変化素子１１及び第２抵抗変化素子１２の同一極性の一方の端子同士と、第１整流素子１３及び第２整流素子１４の同一極性の一方の端子同士とは、共通に電気的に接続されている。 The switching cell 10 includes a first resistance change element 11 and a second resistance change element 12, a first rectification element 13 and a second rectification element 14. A plurality of switching cells 10 are arranged in the array region 20 and arranged in a first direction (X direction) and a second direction (Y direction) different from the first direction (X direction). ing. In the switching cell 10, one terminal of the same polarity of the first resistance change element 11 and the second resistance change element 12 and one terminal of the same polarity of the first rectification element 13 and the second rectification element 14 are Commonly connected electrically.
　第１の方向（Ｘ方向）に配列した同じライン上の各スイッチングセル１０における第１抵抗変化素子１１の他方の端子は、対応する第１選択配線２１に電気的に接続されている。また、第１の方向（Ｘ方向）に配列した同じライン上の各スイッチングセル１０における第１整流素子１３の他方の端子は、対応する第２選択配線２２に電気的に接続されている。また、第２の方向（Ｙ方向）に配列した同じライン上の各スイッチングセル１０における第２抵抗変化素子１２の他方の端子は、対応する第３選択配線２３に電気的に接続されている。第２の方向（Ｙ方向）に配列した同じライン上の各スイッチングセル１０における第２整流素子１４の他方の端子は、対応する第４選択配線２４に電気的に接続されている。 The other terminal of the first resistance change element 11 in each switching cell 10 on the same line arranged in the first direction (X direction) is electrically connected to the corresponding first selection wiring 21. The other terminal of the first rectifying element 13 in each switching cell 10 on the same line arranged in the first direction (X direction) is electrically connected to the corresponding second selection wiring 22. The other terminal of the second variable resistance element 12 in each switching cell 10 on the same line arranged in the second direction (Y direction) is electrically connected to the corresponding third selection wiring 23. The other terminal of the second rectifying element 14 in each switching cell 10 on the same line arranged in the second direction (Y direction) is electrically connected to the corresponding fourth selection wiring 24.
　第１選択配線２１及び第２選択配線２２は、アレイ領域２０において第１の方向（Ｘ方向）に延在した配線である。第１選択配線２１及び第２選択配線２２は、対を成す。第１選択配線２１及び第２選択配線２２の対は、アレイ領域２０において複数ある。 The first selection wiring 21 and the second selection wiring 22 are wirings extending in the first direction (X direction) in the array region 20. The first selection wiring 21 and the second selection wiring 22 form a pair. There are a plurality of pairs of the first selection wiring 21 and the second selection wiring 22 in the array region 20.
　第３選択配線２３及び第４選択配線２４は、アレイ領域２０において第２の方向（Ｙ方向）に延在した配線である。第３選択配線２３及び第４選択配線２４は、対を成す。第３選択配線２３及び第４選択配線２４の対は、アレイ領域２０において複数ある。 The third selection wiring 23 and the fourth selection wiring 24 are wirings extending in the second direction (Y direction) in the array region 20. The third selection wiring 23 and the fourth selection wiring 24 make a pair. There are a plurality of pairs of the third selection wiring 23 and the fourth selection wiring 24 in the array region 20.
　第１選択スイッチング素子６１は、対応する第１選択配線２１に電気的に接続された少なくとも１つの選択スイッチング素子である。第２選択スイッチング素子６２は、対応する第２選択配線２２に電気的に接続された少なくとも１つの選択スイッチング素子である。第３選択スイッチング素子７１は、対応する第３選択配線２３に電気的に接続された少なくとも１つの選択スイッチング素子である。第４選択スイッチング素子７２は、対応する第４選択配線２４に電気的に接続された少なくとも１つの選択スイッチング素子である。第１選択スイッチング素子６１及び第３選択スイッチング素子７１の各駆動電流量は、第２選択スイッチング素子６２及び第４選択スイッチング素子７２の各駆動電流量と異なる。 The first selection switching element 61 is at least one selection switching element electrically connected to the corresponding first selection wiring 21. The second selection switching element 62 is at least one selection switching element electrically connected to the corresponding second selection wiring 22. The third selection switching element 71 is at least one selection switching element electrically connected to the corresponding third selection wiring 23. The fourth selection switching element 72 is at least one selection switching element electrically connected to the corresponding fourth selection wiring 24. The drive current amounts of the first selection switching element 61 and the third selection switching element 71 are different from the drive current amounts of the second selection switching element 62 and the fourth selection switching element 72.
　実施形態２によれば、第１選択スイッチング素子６１及び第３選択スイッチング素子７１の各駆動電流量を、第２選択スイッチング素子６２及び第４選択スイッチング素子７２の各駆動電流量と異なるように設定することで、選択した抵抗変化素子１１、１２の少なくとも一方をセットする際に、抵抗変化素子１１、１２の少なくとも一方に十分な電圧を印加することができ、かつ、抵抗変化素子１１、１２の少なくとも一方をセットした直後に流れる電流を制限することができるので、整流素子１３、１４の絶縁破壊を防止しながら、セット歩留まりを改善することができる。 According to the second embodiment, the drive current amounts of the first selection switching element 61 and the third selection switching element 71 are set to be different from the drive current amounts of the second selection switching element 62 and the fourth selection switching element 72. Thus, when setting at least one of the selected resistance change elements 11 and 12, a sufficient voltage can be applied to at least one of the resistance change elements 11 and 12, and the resistance change elements 11 and 12 Since the current that flows immediately after setting at least one of them can be limited, the set yield can be improved while preventing dielectric breakdown of the rectifying elements 13 and 14.
（付記）
　本発明では、前記第１の視点に係る抵抗変化素子アレイの形態が可能である。 (Appendix)
In the present invention, the variable resistance element array according to the first aspect is possible.
　前記第１の視点に係る抵抗変化素子アレイにおいて、前記第１及び第３選択スイッチング素子の各駆動電流量は、前記第２及び第４選択スイッチング素子の各駆動電流量よりも大きい。 In the variable resistance element array according to the first aspect, each driving current amount of the first and third selective switching elements is larger than each driving current amount of the second and fourth selective switching elements.
　前記第１の視点に係る抵抗変化素子アレイにおいて、前記第１、第２、第３及び第４選択スイッチング素子のうち少なくとも１つは、対応する前記第１、第２、第３及び第４選択配線のうち少なくとも１つに電気的に接続された少なくとも１つのバイポーラトランジスタ又は電界効果トランジスタを含む。 In the variable resistance element array according to the first aspect, at least one of the first, second, third, and fourth selection switching elements is the corresponding first, second, third, and fourth selection. It includes at least one bipolar transistor or field effect transistor electrically connected to at least one of the wirings.
　前記第１の視点に係る抵抗変化素子アレイにおいて、前記第１、第２、第３及び第４選択スイッチング素子は、それぞれ、対応する前記第１、第２、第３及び第４選択配線に電気的に接続された少なくとも１つの電界効果トランジスタを含み、前記第１及び第３選択スイッチング素子に含まれる前記電界効果トランジスタのゲート幅は、前記第２及び第４選択スイッチング素子に含まれる前記電界効果トランジスタのゲート幅よりも大きい。 In the variable resistance element array according to the first aspect, the first, second, third, and fourth selection switching elements are electrically connected to the corresponding first, second, third, and fourth selection wirings, respectively. The field effect transistors included in the first and third selective switching elements have a gate width which is included in the second and fourth selective switching elements. It is larger than the gate width of the transistor.
　前記第１の視点に係る抵抗変化素子アレイにおいて、前記第１、第２、第３及び第４選択スイッチング素子は、それぞれ、対応する前記第１、第２、第３及び第４選択配線に電気的に接続された少なくとも１つの電界効果トランジスタを含み、前記第１及び第３選択スイッチング素子は、２つ以上の前記電界効果トランジスタが並列に電気的に接続された構成であり、前記第１及び第３選択スイッチング素子に含まれる前記電界効果トランジスタの並列数は、前記第２及び第４選択スイッチング素子に含まれる前記電界効果トランジスタの並列数よりも多い。 In the variable resistance element array according to the first aspect, the first, second, third, and fourth selection switching elements are electrically connected to the corresponding first, second, third, and fourth selection wirings, respectively. At least one field effect transistor connected to each other, wherein the first and third selective switching elements are configured such that two or more field effect transistors are electrically connected in parallel; The number of parallel field effect transistors included in the third selection switching element is greater than the number of parallel field effect transistors included in the second and fourth selection switching elements.
　前記第１の視点に係る抵抗変化素子アレイにおいて、前記第１、第２、第３及び第４選択スイッチング素子は、それぞれ、対応する前記第１、第２、第３及び第４選択配線に電気的に接続された少なくとも１つの電界効果トランジスタを含み、前記第１及び第３選択スイッチング素子に含まれる前記電界効果トランジスタのチャネル長は、前記第２及び第４選択スイッチング素子に含まれる前記電界効果トランジスタのチャネル長よりも小さい。 In the variable resistance element array according to the first aspect, the first, second, third, and fourth selection switching elements are electrically connected to the corresponding first, second, third, and fourth selection wirings, respectively. The field effect transistors included in the first and third selective switching elements have a channel length included in the second and fourth selective switching elements. It is smaller than the channel length of the transistor.
　前記第１の視点に係る抵抗変化素子アレイにおいて、対応する前記第２及び第４選択配線に、それぞれ、電気的に接続された少なくとも１つの第５及び第６選択スイッチング素子をさらに備える。 The resistance change element array according to the first aspect further includes at least one fifth and sixth selection switching elements electrically connected to the corresponding second and fourth selection wirings, respectively.
　前記第１の視点に係る抵抗変化素子アレイにおいて、前記第２選択配線の寄生電気容量は、前記第４選択配線の寄生電気容量と等しい。 In the variable resistance element array according to the first aspect, the parasitic capacitance of the second selection wiring is equal to the parasitic capacitance of the fourth selection wiring.
　前記第１の視点に係る抵抗変化素子アレイにおいて、前記第２選択配線の長さは、前記第４選択配線の長さと等しい。 In the variable resistance element array according to the first aspect, the length of the second selection wiring is equal to the length of the fourth selection wiring.
　前記第１の視点に係る抵抗変化素子アレイにおいて、前記第１及び第４選択配線、又は、前記第２及び第３選択配線にて選択される前記スイッチングセルにおける前記抵抗変化素子に流れるセット電流は、１０μＡ以上かつ１ｍＡ以下に設定される。 In the variable resistance element array according to the first aspect, a set current flowing through the variable resistance element in the switching cell selected by the first and fourth selection wirings or the second and third selection wirings is It is set to 10 μA or more and 1 mA or less.
　本発明では、前記第２の視点に係る抵抗変化素子アレイの制御方法の形態が可能である。 In the present invention, the variable resistance element array control method according to the second aspect is possible.
　前記第２の視点に係る抵抗変化素子アレイの制御方法において、選択された前記スイッチングセルにおける前記２つの抵抗変化素子が全体としてオン状態にあるときに、選択された前記スイッチングセルにおける前記２つの整流素子のうち少なくとも一方の整流素子の他方の端子を接地に接続し、かつ、選択された前記スイッチングセルにおける前記２つの抵抗変化素子のうち少なくとも一方の抵抗変化素子の他方の端子に正電圧を印加することによって、選択された前記スイッチングセルにおける前記２つの抵抗変化素子が全体としてオフ状態に変化するように制御する。 In the control method of the variable resistance element array according to the second aspect, the two rectifications in the selected switching cell when the two variable resistance elements in the selected switching cell are in an ON state as a whole. The other terminal of at least one rectifying element among the elements is connected to the ground, and a positive voltage is applied to the other terminal of at least one of the two variable resistance elements in the selected switching cell. By doing so, the two variable resistance elements in the selected switching cell are controlled to change to the OFF state as a whole.
　第３の視点に係る記憶装置は、前記第１の視点に係る抵抗変化素子アレイと、前記抵抗変化素子アレイを制御する制御回路と、を備える。 The memory device according to the third aspect includes the resistance change element array according to the first viewpoint and a control circuit that controls the resistance change element array.
　前記第３の視点に係る記憶装置において、前記制御回路は、前記第１、第２、第３及び第４選択スイッチング素子を制御することにより前記アレイ領域の中から１つの前記スイッチングセルにおける前記２つの抵抗変化素子の少なくとも一方を選択するアレイ制御回路と、前記アレイ制御回路によって選択された前記スイッチングセルにおける前記２つの抵抗変化素子の少なくとも一方に、対応する第１、第２、第３及び第４選択配線を介して、書き込み電圧又は消去電圧を印加する書き込み回路と、を備える。 In the storage device according to the third aspect, the control circuit controls the first, second, third, and fourth selection switching elements to control the 2 in one switching cell from the array region. An array control circuit for selecting at least one of the two resistance change elements, and at least one of the two resistance change elements in the switching cell selected by the array control circuit. And a writing circuit for applying a writing voltage or an erasing voltage via four selection wirings.
　前記第３の視点に係る記憶装置において、前記制御回路は、前記アレイ制御回路によって選択された前記スイッチングセルにおける前記２つの抵抗変化素子の少なくとも一方に、対応する第１、第２、第３及び第４選択配線を介して、読み出し電圧を印加する読み出し回路をさらに備える。 In the memory device according to the third aspect, the control circuit includes first, second, third, and third corresponding to at least one of the two resistance change elements in the switching cell selected by the array control circuit. A readout circuit for applying a readout voltage via the fourth selection wiring is further provided.
　なお、上記の特許文献、非特許文献の各開示を、本書に引用をもって繰り込むものとする。本発明の全開示（特許請求の範囲及び図面を含む）の枠内において、さらにその基本的技術思想に基づいて、実施形態ないし実施例の変更・調整が可能である。また、本発明の全開示の枠内において種々の開示要素（各請求項の各要素、各実施形態ないし実施例の各要素、各図面の各要素等を含む）の多様な組み合わせないし選択（必要により不選択）が可能である。すなわち、本発明は、請求の範囲及び図面を含む全開示、技術的思想にしたがって当業者であればなし得るであろう各種変形、修正を含むことは勿論である。また、本願に記載の数値及び数値範囲については、明記がなくともその任意の中間値、下位数値、及び、小範囲が記載されているものとみなされる。 It should be noted that the disclosures of the above patent documents and non-patent documents are incorporated herein by reference. Within the scope of the entire disclosure (including claims and drawings) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various combinations or selections of various disclosed elements (including each element of each claim, each element of each embodiment or example, each element of each drawing, etc.) within the framework of the entire disclosure of the present invention (necessary) Can be selected). That is, the present invention naturally includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the drawings, and the technical idea. Further, regarding numerical values and numerical ranges described in the present application, it is considered that any intermediate value, lower numerical value, and small range are described even if not specified.
　１　第１電極
　２　抵抗変化層
　３　第２電極
　１０　スイッチングセル
　１１　第１抵抗変化素子（一方の抵抗変化素子）
　１２　第２抵抗変化素子（他方の抵抗変化素子）
　１１ａ、１２ａ　第１端子（一方の端子）
　１１ｂ、１２ｂ　第２端子（他方の端子）
　１３　第１整流素子（一方の整流素子）
　１４　第２整流素子（他方の整流素子）
　１３ａ、１４ａ　第１端子（一方の端子）
　１３ｂ、１４ｂ　第２端子（他方の端子）
　２０　アレイ領域
　２１　第１選択配線
　２２　第２選択配線
　２３　第３選択配線
　２４　第４選択配線
　３０　カラムデコーダ
　３１　第１電界効果トランジスタ
　３２　第２電界効果トランジスタ
　４０　ロウデコーダ
　４１　第３電界効果トランジスタ
　４２　第４電界効果トランジスタ
　５０　制御回路
　５１　アレイ制御回路
　５２　書き込み回路
　５３　読み出し回路
　６１　第１選択スイッチング素子
　６２　第２選択スイッチング素子
　７１　第３選択スイッチング素子
　７２　第４選択スイッチング素子
　１００　抵抗変化素子アレイ
　２００　記憶装置 DESCRIPTION OF SYMBOLS 1 1st electrode 2 Resistance change layer 3 2nd electrode 10 Switching cell 11 1st resistance change element (one resistance change element)
12 Second variable resistance element (the other variable resistance element)
11a, 12a First terminal (one terminal)
11b, 12b Second terminal (the other terminal)
13 First rectifier element (one rectifier element)
14 Second rectifier (the other rectifier)
13a, 14a First terminal (one terminal)
13b, 14b Second terminal (the other terminal)
20 array region 21 first selection wiring 22 second selection wiring 23 third selection wiring 24 fourth selection wiring 30 column decoder 31 first field effect transistor 32 second field effect transistor 40 row decoder 41 third field effect transistor 42 fourth Field effect transistor 50 Control circuit 51 Array control circuit 52 Write circuit 53 Read circuit 61 First selection switching element 62 Second selection switching element 71 Third selection switching element 72 Fourth selection switching element 100 Resistance change element array 200 Storage device

Claims (10)

  1. 　２つの抵抗変化素子と２つの整流素子とを含むスイッチングセルであって、第１の方向、及び、前記第１の方向とは異なる第２の方向に配列して配置された複数のスイッチングセルと、
    　前記複数のスイッチングセルが配置されたアレイ領域において前記第１の方向に延在した複数対の第１及び第２選択配線と、
    　前記アレイ領域において前記第２の方向に延在した複数対の第３及び第４選択配線と、
    　対応する前記第１、第２、第３及び第４選択配線に、それぞれ、電気的に接続された少なくとも１つの第１、第２、第３及び第４選択スイッチング素子と、
    を備え、
    　前記スイッチングセルにおいて、２つの前記抵抗変化素子の同一極性の一方の端子同士と、２つの前記整流素子の同一極性の一方の端子同士とは、共通に電気的に接続され、
    　前記第１の方向に配列した同じライン上の各前記スイッチングセルにおける前記２つの抵抗変化素子のうち一方の抵抗変化素子の他方の端子は、対応する前記第１選択配線に電気的に接続され、
    　前記第１の方向に配列した同じライン上の各前記スイッチングセルにおける前記２つの整流素子のうち一方の整流素子の他方の端子は、対応する前記第２選択配線に電気的に接続され、
    　前記第２の方向に配列した同じライン上の各前記スイッチングセルにおける前記２つの抵抗変化素子のうち他方の抵抗変化素子の他方の端子は、対応する前記第３選択配線に電気的に接続され、
    　前記第２の方向に配列した同じ列の各前記スイッチングセルにおける前記２つの整流素子のうち他方の整流素子の他方の端子は、対応する前記第４選択配線に電気的に接続され、
    　前記第１及び第３選択スイッチング素子の各駆動電流量は、前記第２及び第４選択スイッチング素子の各駆動電流量と異なる、
    抵抗変化素子アレイ。     A switching cell including two resistance change elements and two rectifying elements, and a plurality of switching cells arranged in a first direction and a second direction different from the first direction; ,
    A plurality of pairs of first and second selection wirings extending in the first direction in an array region in which the plurality of switching cells are disposed;
    A plurality of pairs of third and fourth selection wirings extending in the second direction in the array region;
    At least one first, second, third and fourth selection switching element electrically connected to the corresponding first, second, third and fourth selection wiring, respectively;
    With
    In the switching cell, one terminal of the same polarity of the two variable resistance elements and one terminal of the same polarity of the two rectifying elements are electrically connected in common,
    The other terminal of one of the two resistance change elements in each of the switching cells on the same line arranged in the first direction is electrically connected to the corresponding first selection wiring,
    The other terminal of one of the two rectifying elements in each of the switching cells on the same line arranged in the first direction is electrically connected to the corresponding second selection wiring,
    The other terminal of the other resistance change element among the two resistance change elements in each of the switching cells on the same line arranged in the second direction is electrically connected to the corresponding third selection wiring,
    The other terminal of the other rectifying element among the two rectifying elements in each of the switching cells in the same column arranged in the second direction is electrically connected to the corresponding fourth selection wiring,
    The drive current amounts of the first and third selective switching elements are different from the drive current amounts of the second and fourth selective switching elements,
    Variable resistance element array.
  2. 　前記第１及び第３選択スイッチング素子の各駆動電流量は、前記第２及び第４選択スイッチング素子の各駆動電流量よりも大きい、
    請求項１に記載の抵抗変化素子アレイ。     Each drive current amount of the first and third selection switching elements is larger than each drive current amount of the second and fourth selection switching elements,
    The variable resistance element array according to claim 1.
  3. 　前記第１、第２、第３及び第４選択スイッチング素子のうち少なくとも１つは、対応する前記第１、第２、第３及び第４選択配線のうち少なくとも１つに電気的に接続された少なくとも１つのバイポーラトランジスタ又は電界効果トランジスタを含む、
    請求項１又は２記載の抵抗変化素子アレイ。     At least one of the first, second, third, and fourth selection switching elements is electrically connected to at least one of the corresponding first, second, third, and fourth selection wirings. Including at least one bipolar transistor or field effect transistor,
    The variable resistance element array according to claim 1 or 2.
  4. 　前記第１、第２、第３及び第４選択スイッチング素子は、それぞれ、対応する前記第１、第２、第３及び第４選択配線に電気的に接続された少なくとも１つの電界効果トランジスタを含み、
    　前記第１及び第３選択スイッチング素子に含まれる前記電界効果トランジスタのゲート幅は、前記第２及び第４選択スイッチング素子に含まれる前記電界効果トランジスタのゲート幅よりも大きい、
    請求項１乃至３のいずれか一に記載の抵抗変化素子アレイ。     Each of the first, second, third, and fourth selection switching elements includes at least one field effect transistor electrically connected to the corresponding first, second, third, and fourth selection wiring. ,
    A gate width of the field effect transistor included in the first and third selection switching elements is larger than a gate width of the field effect transistor included in the second and fourth selection switching elements;
    The variable resistance element array according to any one of claims 1 to 3.
  5. 　前記第１、第２、第３及び第４選択スイッチング素子は、それぞれ、対応する前記第１、第２、第３及び第４選択配線に電気的に接続された少なくとも１つの電界効果トランジスタを含み、
    　前記第１及び第３選択スイッチング素子は、２つ以上の前記電界効果トランジスタが並列に電気的に接続された構成であり、
    　前記第１及び第３選択スイッチング素子に含まれる前記電界効果トランジスタの並列数は、前記第２及び第４選択スイッチング素子に含まれる前記電界効果トランジスタの並列数よりも多い、
    請求項１乃至３のいずれか一に記載の抵抗変化素子アレイ。     Each of the first, second, third, and fourth selection switching elements includes at least one field effect transistor electrically connected to the corresponding first, second, third, and fourth selection wiring. ,
    The first and third selection switching elements have a configuration in which two or more field effect transistors are electrically connected in parallel.
    The parallel number of the field effect transistors included in the first and third selective switching elements is greater than the parallel number of the field effect transistors included in the second and fourth selective switching elements.
    The variable resistance element array according to any one of claims 1 to 3.
  6. 　前記第１、第２、第３及び第４選択スイッチング素子は、それぞれ、対応する前記第１、第２、第３及び第４選択配線に電気的に接続された少なくとも１つの電界効果トランジスタを含み、
    　前記第１及び第３選択スイッチング素子に含まれる前記電界効果トランジスタのチャネル長は、前記第２及び第４選択スイッチング素子に含まれる前記電界効果トランジスタのチャネル長よりも小さい、
    請求項１乃至３のいずれか一に記載の抵抗変化素子アレイ。     Each of the first, second, third, and fourth selection switching elements includes at least one field effect transistor electrically connected to the corresponding first, second, third, and fourth selection wiring. ,
    The channel length of the field effect transistor included in the first and third selection switching elements is smaller than the channel length of the field effect transistor included in the second and fourth selection switching elements.
    The variable resistance element array according to any one of claims 1 to 3.
  7. 　前記第２選択配線の寄生電気容量は、前記第４選択配線の寄生電気容量と等しい、
    請求項１乃至３のいずれか一に記載の抵抗変化素子アレイ。     The parasitic capacitance of the second selection wiring is equal to the parasitic capacitance of the fourth selection wiring.
    The variable resistance element array according to any one of claims 1 to 3.
  8. 　前記第２選択配線の長さは、前記第４選択配線の長さと等しい、
    請求項１乃至３及び７のいずれか一に記載の抵抗変化素子アレイ。     A length of the second selection wiring is equal to a length of the fourth selection wiring;
    The resistance change element array according to any one of claims 1 to 3 and 7.
  9. 　前記第１及び第４選択配線、又は、前記第２及び第３選択配線にて選択される前記スイッチングセルにおける前記抵抗変化素子に流れるセット電流は、１０μＡ以上かつ１ｍＡ以下に設定される、
    請求項１乃至３のいずれか一に記載の抵抗変化素子アレイ。     A set current flowing through the resistance change element in the switching cell selected by the first and fourth selection wirings or the second and third selection wirings is set to 10 μA or more and 1 mA or less.
    The variable resistance element array according to any one of claims 1 to 3.
  10. 　請求項１乃至９のいずれか一に記載の抵抗変化素子アレイの制御方法であって、
    　選択された前記スイッチングセルにおける前記２つの抵抗変化素子がそれぞれオフ状態にあるときに、選択された前記スイッチングセルにおける前記２つの整流素子のうち少なくとも一方の整流素子の他方の端子を接地に接続し、かつ、選択された前記スイッチングセルにおける前記２つの抵抗変化素子のうち少なくとも一方の抵抗変化素子の他方の端子に負電圧を印加することによって、選択された前記スイッチングセルにおける前記２つの抵抗変化素子が全体としてオン状態に変化するように制御する、
    抵抗変化素子アレイの制御方法。     A method for controlling a variable resistance element array according to any one of claims 1 to 9,
    When the two variable resistance elements in the selected switching cell are each in an off state, the other terminal of at least one of the two rectifying elements in the selected switching cell is connected to the ground. And applying a negative voltage to the other terminal of at least one of the two variable resistance elements in the selected switching cell to thereby select the two variable resistance elements in the selected switching cell. Control to turn on as a whole,
    Control method of resistance change element array.
PCT/JP2018/013685 2017-03-31 2018-03-30 Variable resistance element array and method for controlling variable resistance element array WO2018181921A1 (en)

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