WO2018177152A1 - 编码方法、解码方法、装置和系统 - Google Patents

编码方法、解码方法、装置和系统 Download PDF

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Publication number
WO2018177152A1
WO2018177152A1 PCT/CN2018/079511 CN2018079511W WO2018177152A1 WO 2018177152 A1 WO2018177152 A1 WO 2018177152A1 CN 2018079511 W CN2018079511 W CN 2018079511W WO 2018177152 A1 WO2018177152 A1 WO 2018177152A1
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code
data
codeword
frame
codewords
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PCT/CN2018/079511
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English (en)
French (fr)
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陆玉春
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华为技术有限公司
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Priority to EP18776473.3A priority Critical patent/EP3595208A4/en
Publication of WO2018177152A1 publication Critical patent/WO2018177152A1/zh
Priority to US16/579,264 priority patent/US11043975B2/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0064—Concatenated codes
    • H04L1/0065—Serial concatenated codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0059—Convolutional codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/1515—Reed-Solomon codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/3761—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35 using code combining, i.e. using combining of codeword portions which may have been transmitted separately, e.g. Digital Fountain codes, Raptor codes or Luby Transform [LT] codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes

Definitions

  • the present application relates to the field of codec technology and, more particularly, to an encoding method, a decoding method, an apparatus and a system.
  • FEC Forward Error Correction
  • the application provides an encoding method, a decoding method, an apparatus and a system to improve the efficiency of codec.
  • an encoding method comprising: determining a frame of an outer code of data to be encoded, the frame of the outer code comprising a data information code and a check code of the data information code, the frame of the outer code Divided into Q data blocks, each of the Q data blocks includes W bits, where W and Q are respectively integers greater than zero; encoding the Q data blocks to obtain Q codewords of the code, wherein the Q data blocks are in one-to-one correspondence with Q codewords of the inner code, and the first codeword of the Q codewords of the inner code includes a first data block and a check code of the first data block, where the first codeword is any one of Q codewords of the inner code, and the first data block is data corresponding to the first codeword Piece.
  • the frame of the outer code is divided into Q data blocks of length W bits, and the Q data blocks are encoded to obtain Q codewords of the inner code, where the Q codes of the inner code
  • the first codeword in the word contains a check code that only includes the check code of the first data block, thereby reducing the complexity of the encoding.
  • the first codeword included in the Q codewords of the inner code only includes the check code of the first data block, so in the process of encoding, the codeword of the outer code may be
  • the pipeline is input to the inner code encoder for encoding, thereby reducing the delay in the encoding process.
  • encoding the coded data by means of concatenated coding can reduce the bit error rate and improve the error correction performance.
  • the cascading coding is performed by means of a pipeline, and the coding delay and complexity can be reduced with respect to the coding method of the same error correction performance.
  • the coded data is encoded by means of concatenated coding
  • the data to be encoded may be encoded by a lower gain only by an outer code encoder, or the data to be encoded may be coded by means of concatenation coding.
  • Higher gain coding which improves codec compatibility.
  • the method further includes: adding at least one blank bit in each of the Q codewords of the inner code, where the at least one blank bit is used to adjust the coded codeword rate.
  • At least one blank bit is filled in the inner code to adjust the rate of the codec, thereby improving the efficiency of the codec.
  • the method further includes: performing precoding on the Q codewords of the inner code to obtain precoded data.
  • the determining a frame of the outer code of the data to be encoded includes: acquiring data to be encoded; and encoding the data to be encoded to obtain a frame of the outer code.
  • the outer code is a Reed Solomon RS code.
  • the inner code includes any one of the following: an RS code, a BCH code, and a convolutional code.
  • W takes the value of any of the following values: 160, 320, 480, and 640.
  • a second aspect provides a decoding method, including: acquiring Q codewords of an inner code of data to be decoded, where Q codewords of the inner code are in one-to-one correspondence with Q data blocks included in a frame of an outer code,
  • the first codeword of the Q codewords of the inner code includes a first data block and a check code of the first data block, where the first codeword is in the Q codewords of the inner code Any one of the codewords, the first data block is a data block corresponding to the first codeword; and the Q codewords of the inner code are decoded to obtain a frame of the outer code, wherein the outer code
  • the frame of the code is divided into the Q data blocks, each of the Q data blocks includes W bits, and W and Q are respectively integers greater than zero; and the frame of the outer code is decoded, To get the decoded data.
  • the Q codewords based on the inner code are decoded to obtain the frame of the outer code, and the decoded data is obtained according to the frame of the outer code.
  • the Q codewords of the inner code are in one-to-one correspondence with the Q data blocks included in the frame of the outer code.
  • the check code included in the first codeword of the Q codewords of the inner code includes only the check code of the first data block, thereby reducing the complexity of decoding.
  • the speed of decoding the inner code is improved. After decoding the inner code to obtain one frame of the outer code, it can be input to the outer code encoder for decoding in a pipeline manner, thereby reducing the delay in the encoding process.
  • encoding the coded data by means of concatenated coding can reduce the bit error rate and improve the error correction performance.
  • the cascading coding is performed by means of a pipeline, and the coding delay and complexity can be reduced with respect to the coding method of the same error correction performance.
  • the decoded data is decoded by means of cascading decoding, and the data to be decoded may be decoded by a lower gain only by the outer code decoder, or the data to be decoded may be performed by means of cascade decoding. Higher gain decoding enables improved codec compatibility.
  • the Q codewords of the inner code further include at least one blank bit, where the at least one blank bit is used to adjust the encoded codeword rate.
  • At least one blank bit is filled in the inner code to adjust the codeword rate of the codec, thereby improving the efficiency of the codec.
  • the method before the acquiring the Q codewords of the inner code of the data to be decoded, the method further includes: acquiring data to be decoded; performing decoding processing on precoding the data to be decoded, to Obtaining Q codewords of the inner code.
  • the outer code is a Reed Solomon RS code.
  • the inner code includes any one of the following: an RS code, a BCH code, and a convolutional code.
  • W takes the value of any of the following values: 160, 320, 480, and 640.
  • an encoding apparatus comprising means for performing the method of the first aspect or various implementations thereof.
  • a decoding apparatus comprising means for performing the method of the second aspect or various implementations thereof.
  • a communication system comprising the encoding device of the third aspect and the decoding device of the fourth aspect.
  • an encoding apparatus including a nonvolatile storage medium, and a central processing unit, the nonvolatile storage medium storing an executable program, the central processing unit and the nonvolatile storage The medium is connected and the executable program is executed to implement the method of the first aspect.
  • a decoding apparatus including a nonvolatile storage medium, and a central processing unit, the nonvolatile storage medium storing an executable program, the central processing unit and the nonvolatile storage The medium is connected and the executable program is executed to implement the method of the second aspect.
  • a communication system comprising the encoding device of the sixth aspect and the decoding device of the seventh aspect.
  • a computer readable medium storing program code for device execution, the program code comprising instructions for performing the method of the first aspect.
  • a computer readable medium storing program code for device execution, the program code comprising instructions for performing the method of the second aspect.
  • a communication system comprising the encoding device of the ninth aspect and the decoding device of the tenth aspect.
  • FIG. 1 is a schematic structural diagram of a codec system according to an embodiment of the present application.
  • FIG. 2 is a schematic flowchart of an encoding method in an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a frame structure of a concatenated code according to an embodiment of the present application.
  • FIG. 4 is a schematic flowchart of a decoding method according to an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a frame of a concatenated code according to still another embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a frame of a concatenated code according to still another embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a frame of a concatenated code according to still another embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a frame of a concatenated code according to still another embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a frame of a concatenated code according to still another embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a frame of a concatenated code according to still another embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a frame of a concatenated code according to still another embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of a frame of a concatenated code according to still another embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of a frame of a concatenated code according to still another embodiment of the present application.
  • FIG. 14 is a schematic structural diagram of a frame of a concatenated code according to still another embodiment of the present application.
  • FIG. 15 is a schematic diagram of a codec system according to still another embodiment of the present application.
  • 16 is a schematic diagram of a codec system according to still another embodiment of the present application.
  • 17 is a schematic diagram of a codec system according to still another embodiment of the present application.
  • FIG. 18 is a schematic diagram of a codec system according to still another embodiment of the present application.
  • FIG. 19 is a schematic diagram of an encoding apparatus according to an embodiment of the present application.
  • FIG. 20 is a schematic diagram of a decoding apparatus according to an embodiment of the present application.
  • 21 is a schematic diagram of an encoding apparatus according to still another embodiment of the present application.
  • FIG. 22 is a schematic diagram of a decoding apparatus according to still another embodiment of the present application.
  • the embodiment of the present application proposes an encoding method, a decoding method, an apparatus and a system.
  • GSM Global System of Mobile communication
  • CDMA Code Division Multiple Access
  • WCDMA Wideband Code Division Multiple Access
  • GPRS General Packet Radio Service
  • LTE Long Term Evolution
  • FDD Frequency Division Duplex
  • TDD Time Division Duplex
  • UMTS Universal Mobile Telecommunication System
  • WiMAX Worldwide Interoperability for Microwave Access
  • the method for jointly coding the outer code and the inner code in the embodiment of the present application may also be referred to as concatenated coding.
  • the code obtained by means of concatenated coding may also be referred to as a concatenated code, or the concatenated code may include the above outer code and the above inner code.
  • FIG. 1 is a schematic structural diagram of a codec system 100 according to an embodiment of the present application. It should be understood that the codec system and the scenario described in the embodiments of the present invention are for the purpose of more clearly illustrating the technical solutions of the embodiments of the present invention, and do not constitute a limitation of the technical solutions provided by the embodiments of the present invention. With the evolution and development of the codec system, the technical solutions provided by the embodiments of the present invention are equally applicable to similar technical problems.
  • the encoding module of the codec system 100 of FIG. 1 includes an outer code encoder and an inner code encoder
  • the decoding module of the codec system 100 of FIG. 1 includes an outer code decoder and an inner code decoder.
  • 1 shows the structure of a codec system including an outer code encoder and an outer code decoder. It is to be understood by those skilled in the art that the codec system 100 of FIG. 1 may further include a plurality of outer code encoders and a plurality of outer code decoders, which are not limited in this embodiment of the present application.
  • the data stream to be encoded is sequentially encoded by an outer code encoder and an inner code encoder, wherein the output of the outer code encoder is used as an input of the inner code encoder.
  • the encoding of the outer and inner codes can be done in a pipelined manner. Or the encoding of the inner and outer codes can be performed at the same time, and the inner code encoding is not required after the outer code encoding is completed.
  • the inner code decoder first performs inner code decoding after receiving the data stream to be decoded, and when the number of errors in the inner code decoding exceeds the error correction capability of the inner code decoder, the inner code decoder will The received original data after removing the inner code check code is transmitted to the outer code decoder. After receiving the data transmitted by the inner code decoder, the outer code decoder starts decoding error correction to obtain the decoded data.
  • FIG. 2 shows a schematic flowchart of an encoding method 200 of an embodiment of the present application. As shown in FIG. 2, the method 200 includes:
  • S201 Determine a frame of an outer code of the data to be encoded, where the frame of the outer code includes a data information code and a check code of the data information code, where the frame of the outer code is divided into Q data blocks, where the Q Each of the data blocks includes W bits, where W and Q are respectively integers greater than zero.
  • the frame of the outer code may be a directly acquired frame of the outer code that has been encoded.
  • the data to be encoded may be acquired, and the data to be encoded is encoded to obtain a frame of the outer code.
  • the outer code may be a Reed Solomon (RS) code.
  • RS Reed Solomon
  • Other types of error correction codes are also not limited in this embodiment of the present application.
  • the outer code may include a data information code and a check code, where the check code is used to check the data information code.
  • the Q data blocks Encode the Q data blocks to obtain Q codewords of the inner code, where the Q data blocks are in one-to-one correspondence with the Q codewords of the inner code, and the Q of the inner code
  • the first codeword of the codewords includes a first data block and a check code of the first data block, and the first codeword is any one of Q codewords of the inner code,
  • the first data block is a data block corresponding to the first codeword.
  • the check code of the first codeword of the inner code includes only the check code of the first data block. Therefore, the encoding order of the Q inner codes does not affect the encoding result of the inner code.
  • the Q codewords of the inner code may be synchronous coding, sequential coding, or other asynchronous methods. In other words, before the frame of the outer code is completely output to the inner code encoder, the inner code encoder can be encoded in synchronization with the outer code encoder, thereby reducing the delay in the encoding process.
  • the outer code encoder may output the codeword of the outer code that has been encoded in a pipelined manner, and the inner code encoder may receive the codeword of the outer code in a pipelined manner. And encoding Q data blocks to obtain Q code words of the inner code.
  • the frame of the outer code may include 1 frame of the outer code.
  • One frame of the outer code may include one codeword of the outer code, and may also include multiple codewords of the outer code.
  • the outer code may be divided into Q data blocks by using multiple division manners.
  • a bit or a symbol sequence composed of a plurality of code words of the outer code may be arbitrarily placed, for example, a code word sequence of a plurality of outer codes may be sequentially arranged, or a code word of a plurality of outer codes may be interposed.
  • the arrangement of the present application is not limited thereto.
  • FIG. 3 is a schematic diagram of a frame structure of a concatenated code according to an embodiment of the present application.
  • 1 frame of the outer code in FIG. 3 includes L code words of the outer code, and code character numbers or bits included in the L code words of the outer code are divided into Q data blocks, and each of the Q data blocks
  • the data blocks can be encoded as data information codes of the inner code, and the generated check codes can be attached to the code words of the inner code after the data information codes.
  • L is an integer greater than zero.
  • D denotes a data information code
  • P1 denotes a check code of the outer code
  • P2 denotes a check code of the inner code.
  • the frame of the outer code is divided into Q data blocks of length W bits, and the Q data blocks are encoded to obtain Q codewords of the inner code, where the Q codes of the inner code
  • the first codeword in the word contains a check code that only includes the check code of the first data block, thereby reducing the complexity of the encoding.
  • the first codeword included in the Q codewords of the inner code only includes the check code of the first data block, so in the process of encoding, the codeword of the outer code may be
  • the pipeline is input to the inner code encoder for encoding, thereby reducing the delay in the encoding process.
  • encoding the coded data by means of concatenated coding can reduce the bit error rate and improve the error correction performance.
  • the cascading coding is performed by means of a pipeline, and the coding delay and complexity can be reduced with respect to the coding method of the same error correction performance.
  • the coded data is encoded by means of concatenated coding
  • the data to be encoded may be encoded by a lower gain only by an outer code encoder, or the data to be encoded may be coded by means of concatenation coding.
  • Higher gain coding which improves codec compatibility.
  • the codec method provided by the embodiment of the present application can reduce the delay and complexity of the codec and improve the compatibility of the codec while ensuring the codec gain.
  • At least one blank bit may be filled in the inner code.
  • the at least one blank bit can be used to fill in invalid data, and can also be used to fill in valid information.
  • the at least one blank bit can be used for channel management.
  • the number of blank bits contained in the inner code can be selected according to the rate of the actual link.
  • the criterion for selecting the number of blank bits may be: obtaining the ratio of the length of the codeword of the inner code after adding the blank bit to the bit length of the data information, and the number of blank bits should be such that the minimum and the denominator of the ratio are as large as possible small. In order to simplify the clock used in the codec process, adapt to the rate of the actual link.
  • At least one blank bit is filled in the inner code to adjust the rate of the codec, thereby improving the efficiency of the codec.
  • the method 200 further includes: generating a signal to be transmitted based on the Q codewords of the inner code.
  • the foregoing Q codewords based on the inner code generate a signal to be transmitted, and may include multiple processing manners.
  • This embodiment of the present application does not limit this.
  • the Q codewords of the inner code may be subjected to interleaving, channel coding, and mapping processing to generate a signal to be transmitted.
  • the method 200 further includes performing precoding on the Q codewords of the inner code to obtain precoded data, and generating a signal to be sent based on the precoded data.
  • the Q codewords of the inner code may be pre-coded, and then the signal to be transmitted is generated based on the pre-coded data, which can improve the error of the concatenated coding. performance.
  • Q codewords of the inner code may be input to a 1/(1+D) MOD X precoder for precoding processing.
  • D represents the delay of one symbol unit of the digital filter
  • MOD represents the modular division operation
  • N is the number of code character numbers of the RS code
  • K is an RS (N, K) code.
  • the number of information symbols, M is the number of bits included in each code character number of the RS code
  • Y, M, and N are integers greater than zero, respectively.
  • the above RS code can be expressed as RS (N, K).
  • the outer code can include RS (544, 514), RS (528, 514), or RS (271, 257).
  • the value of W is any one of the following values: 160, 320, 480, and 640.
  • the number of bits of the data information code of the inner code may be 160, 320, 480, and 640.
  • the selection of the inner code can be found in the contents listed in Tables 1 to 8 below.
  • FIG. 4 is a schematic flowchart of a decoding method according to an embodiment of the present application.
  • the decoding method 400 includes:
  • S401 Obtain Q codewords of the inner code of the data to be decoded, where the Q codewords of the inner code are in one-to-one correspondence with the Q data blocks included in the frame of the outer code, and the Q codewords of the inner code are
  • the first codeword includes a first data block and a check code of the first data block, the first codeword being any one of Q codewords of the inner code, the first data block And is a data block corresponding to the first codeword.
  • the outer code is an RS code.
  • the Q codewords based on the inner code are decoded to obtain the frame of the outer code, and the decoded data is obtained according to the frame of the outer code.
  • the Q codewords of the inner code are in one-to-one correspondence with the Q data blocks included in the frame of the outer code.
  • the check code included in the first codeword of the Q codewords of the inner code includes only the check code of the first data block, thereby reducing the complexity of decoding.
  • the speed of decoding the inner code is improved. After decoding the inner code to obtain one frame of the outer code, it can be input to the outer code encoder for decoding in a pipeline manner, thereby reducing the delay in the encoding process.
  • encoding the coded data by means of concatenated coding can reduce the bit error rate and improve the error correction performance.
  • the cascading coding is performed by means of a pipeline, and the coding delay and complexity can be reduced with respect to the coding method of the same error correction performance.
  • the decoded data is decoded by means of cascading decoding, and the data to be decoded may be decoded by a lower gain only by the outer code decoder, or the data to be decoded may be performed by means of cascade decoding. Higher gain decoding enables improved codec compatibility.
  • the codec method provided by the embodiment of the present application can reduce the delay and complexity of the codec and improve the compatibility of the codec while ensuring the codec gain.
  • the Q codewords of the inner code further include at least one blank bit, and the at least one blank bit is used to adjust the coded codeword rate after the concatenation.
  • the method before the acquiring the Q codewords of the internal code of the data to be decoded, the method further includes: acquiring data to be decoded; performing decoding processing on precoding the data to be decoded, to Obtaining Q codewords of the inner code.
  • the inner code includes any one of the following: an RS code, a BCH code, and a convolutional code.
  • the value of W is any one of the following values: 160, 320, 480, and 640.
  • the value of W may also be any other value, which is not limited by the embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a frame of a concatenated code according to an embodiment of the present application.
  • D represents the data information code of the outer code
  • P1 represents the check code of the outer code
  • P2 represents the check code of the inner code.
  • the outer code in the figure is an RS (N, K) code.
  • the P RS codewords are divided into Q data blocks of length W bits in the frame of the concatenated code.
  • P*N*M Q*W
  • M is the number of bits included in each code character number of the RS code.
  • Each data block is encoded as a data information code of the inner code to generate a check code, which can be attached after each data block to form a code word of the inner code.
  • the codeword of the inner code may include any one of the following: a BCH code, an RS code, and a convolutional code.
  • one frame of the outer code in FIG. 5 may be composed of one RS codeword, or may be composed of multiple RS codewords.
  • the frame of the outer code may be composed of L RS code words, and L is a positive integer greater than or equal to 1.
  • the bit or code character number composed of L RS code words may be randomly arranged in the frame of the outer code, and may be arranged in order or interleaved.
  • FIGS. 6 to 8 are schematic structural diagrams of frames of a concatenated code according to still another embodiment of the present application.
  • D represents the data information code of the outer code
  • P1 represents the check code of the outer code
  • P2 represents the check code of the inner code.
  • the number of data information codes of each codeword of the inner code of FIGS. 6 to 8 is 320 bits.
  • One frame of the outer code of Fig. 6 includes one code word of the RS (544, 514) code.
  • One frame of the outer code of Fig. 7 includes two code words of the RS (528, 514) code.
  • One frame of the outer code of Fig. 8 includes two code words of the RS (544, 514) code.
  • the inner code in the examples of FIGS. 6 to 8 may be the BCH (n, x, t, m) code shown in Table 1, or the RS (N, K, T, M shown in Table 2). )code.
  • the length of the digital information code of each codeword of the BCH code in Table 1 and the RS code in Table 2 is 320 bits.
  • n represents the codeword length of each codeword
  • x represents the number of bits of the data information code in each codeword
  • t is the number of bits that can be corrected for each codeword
  • m represents the code.
  • the dimension of the finite field of the word N represents the number of code character numbers of each code
  • K represents the number of code character numbers of the data information code of each codeword
  • T is the number of code character numbers that can be corrected for each codeword
  • OH indicates the ratio of the check code or overhead.
  • the number of blank bits included in the inner code may be selected according to the rate of the actual link.
  • the criterion for selecting the number of blank bits may be: obtaining the ratio of the length of the codeword of the inner code after adding the blank bit to the bit length of the data information, and the number of blank bits should be such that the minimum and the denominator of the ratio are as large as possible small.
  • adapt to the rate of the actual link For example, when the BCH (356, 320, 4) code is selected as the inner code, a 4-bit blank bit can be added after each BCH code, and the entire BCH data frame is complemented into 360 bits, at which time the codeword length and data of the inner code.
  • FIG. 9 to FIG. 10 is a schematic structural diagram of a frame of a concatenated code according to another embodiment of the present application.
  • D denotes a data information code of an outer code
  • P1 denotes a check code of an outer code
  • P2 denotes a check code of an inner code.
  • the number of data information codes of each codeword of the inner code of FIG. 9 or FIG. 10 is 480 bits.
  • One frame of the outer code of Fig. 9 includes three code words of the RS (544, 514) code.
  • One frame of the outer code of Fig. 10 includes one code word of the RS (528, 514) code.
  • the inner code in the example of FIG. 9 or FIG. 10 may be the BCH (n, x, t, m) code shown in Table 2, or the RS (N, K, T, M shown in Table 3). )code.
  • the length of the digital information code of each codeword of the BCH code in Table 3 and the RS code in Table 4 is 480 bits.
  • n represents the codeword length of each codeword
  • x represents the number of bits of the data information code in each codeword
  • t is the number of bits that can be corrected for each codeword
  • m represents the code.
  • the dimension of the finite field of the word N represents the number of code character numbers of each code
  • K represents the number of code character numbers of the data information code of each codeword
  • T is the number of code character numbers that can be corrected for each codeword
  • OH indicates the ratio of the check code or overhead.
  • FIG. 11 or FIG. 12 is a schematic structural diagram of a frame of a concatenated code according to still another embodiment of the present application.
  • D denotes a data information code of an outer code
  • P1 denotes a check code of an outer code
  • P2 denotes a check code of an inner code.
  • the number of data information codes of each codeword of the inner code of FIG. 11 or FIG. 12 is 640 bits.
  • One frame of the outer code of Fig. 11 includes two code words of an RS (544, 514) code.
  • One frame of the outer code of Fig. 12 includes four code words of the RS (528, 514) code.
  • the inner code in the example of FIG. 11 or FIG. 12 may be the BCH (n, x, t, m) code shown in Table 5, or the RS (N, K, T, M shown in Table 6). )code.
  • the length of the digital information code of each codeword of the BCH code in Table 5 and the RS code in Table 6 is 640 bits.
  • n represents the codeword length of each codeword
  • x represents the number of bits of the data information code in each codeword
  • t is the number of bits that can be corrected for each codeword
  • m represents the code.
  • the dimension of the finite field of the word N represents the number of code character numbers of each code
  • K represents the number of code character numbers of the data information code of each codeword
  • T is the number of code character numbers that can be corrected for each codeword
  • OH indicates the ratio of the check code or overhead.
  • FIG. 13 or FIG. 14 is a schematic structural diagram of a frame of a concatenated code according to still another embodiment of the present application.
  • D denotes a data information code of an outer code
  • P1 denotes a check code of an outer code
  • P2 denotes a check code of an inner code.
  • the number of data information codes of each codeword of the inner code in FIG. 13 or FIG. 14 is 160 bits.
  • One frame of the outer code of Fig. 13 includes one code word of the RS (544, 514) code.
  • One frame of the outer code of Fig. 14 includes one code word of the RS (528, 514) code.
  • the inner code in the example of FIG. 13 or FIG. 14 may be the BCH (n, x, t, m) code shown in Table 7, or the RS (N, K, T, M shown in Table 8). )code.
  • the length of the digital information code of each codeword of the BCH code in Table 7 and the RS code in Table 8 is 160 bits.
  • n represents the codeword length of each codeword
  • x represents the number of bits of the data information code in each codeword
  • t is the number of bits that can be corrected for each codeword
  • m represents the code.
  • the dimension of the finite field of the word N represents the number of code character numbers of each code
  • K represents the number of code character numbers of the data information code of each codeword
  • T is the number of code character numbers that can be corrected for each codeword
  • OH indicates the ratio of the check code or overhead.
  • FIG. 15 is a schematic diagram of a codec system according to still another embodiment of the present application.
  • Figure 15 can be applied to a Dense Wavelength Division Multiplexing system that is capable of providing a direct link between routers and routers. For example, a 400 Gbps link with single carrier coherent demodulation can be used in this link.
  • the codec system of FIG. 15 can provide a FEC algorithm with stronger error correction capability for the direct link, and has lower complexity, so that the codec device can be put into the optical module.
  • the example of FIG. 15 includes a first module and a second module, wherein the first module may be an interface chip on the line card, the second module may be a chip in the optical module, and communication between the first module and the second module
  • the interface can be called 400GAUI-X.
  • the first module supports RS (544, 514) codec.
  • the second module supports RS (544, 514) + BCH cascade codec.
  • the first module sends the encoded RS (544, 514) codeword to the second module, and after receiving the RS (544, 514) code, the decoding device in the second module may After the RS (544, 514) codeword is decoded, the check digit is removed to obtain the source data. The source data is then re-concatenated by the encoding device of RS (544, 514) + BCH.
  • the process of transmitting signals to other devices is as follows, and the following process may be performed by a module inside the second module.
  • the second module includes a physical medium attachment (PMA) module, a first processing module, and a second processing module.
  • the second module may include a PMA module, a first processing module, and a second processing module.
  • the first processing module can include at least one of the following modules: an alignment word module, a reordering + de-interleaving module, and an RS (544, 514) decoding module.
  • the second processing module may include: an RS check code removal module, an RS+BCH cascade coding module, an interleave module, a channel coding module, a symbol mapping module, and a filtering module.
  • the second processing module further includes at least one of the following modules: a coherent detection module, a symbol demapping module, a channel decoding module, a deinterleaving module, an RS+BCH decoding module, and an RS+BCH check code removal module.
  • the first processing module may also include at least one of the following modules: an RS (544, 514) encoding module, a distribution and interleaving module.
  • the S1501.400GAUI-X communication interface receives the data stream and inputs the data stream to the PMA layer to obtain N physical coding sublayer (PCS) data streams.
  • PCS physical coding sublayer
  • S1505.RS (544, 514) removes the check code data and sends it to the RS+BCH concatenated code encoder for encoding processing.
  • the data encoded by the S1506.RS+BCH concatenated code is subjected to interleaving, channel coding, and symbol mapping processing to generate a signal to be transmitted.
  • the filtered signal to be sent is sent to the transmitter, and is modulated and sent to the channel for transmission.
  • the second module may transmit and encode the received data to the first module.
  • the specific process is as follows, and the following process can be executed by modules inside the second module.
  • the receiver receives the signal from the channel and performs coherent detection on the signal.
  • the received data stream is decoded by the RS+BCH concatenated code to generate a decoded data stream.
  • the decoded data stream is sent to the RS (544, 514) encoder after the RS+BCH check data is removed.
  • the S1515.RS (544, 514) encoder re-encodes the data.
  • the data generated by the S1516.RS (544, 514) encoder is distributed and interleaved by the PMA layer and sent to the communication interface for data transmission.
  • FIG. 16 is a schematic diagram of a codec system according to still another embodiment of the present application.
  • the application scenario of Figure 16 is similar to that of Figure 15, and is not described here.
  • the first module and the second module are included in the example of FIG. 16.
  • the communication interface between the first module and the second module may be referred to as 400GAUI-X.
  • the first module supports RS (544, 514) codec.
  • the second module supports RS (544, 514) + BCH cascade codec.
  • FIG. 15 is different from the example of FIG. 16 in that the encoding method of FIG. 16 can directly reuse the RS (544, 514) decoded codeword and directly generate the concatenated codeword by BCH encoding.
  • the codewords generated by the two schemes shown in Figures 15 and 16 can be identical.
  • the second module may include a PMA module, a first processing module, and a second processing module.
  • the first processing module can include at least one of the following modules: an alignment word module, a reordering + de-interleaving module, and an RS (544, 514) decoding module.
  • the second processing module may include: an RS check code removal module (optional), a BCH coding module, an interleaving module, a channel coding module, a symbol mapping module, and a filtering module.
  • the second processing module further includes at least one of the following modules: a coherent detection module, a symbol demapping module, a channel decoding module, a deinterleave module, a BCH decoding module, and a BCH check code removal module.
  • the first processing module may also include at least one of the following modules: an RS (544, 514) encoding module (optional), a distribution and interleaving module.
  • the communication interface receives the data stream transmitted by the first module, and inputs the data stream to a physical medium attachment (PMA) layer to obtain N physical coding sublayer (PCS) data streams.
  • PMA physical medium attachment
  • PCS physical coding sublayer
  • S1603 Perform channel reordering and deinterleaving on the aligned data, and then input the processed data to an RS (544, 514) decoder for decoding.
  • the RS (544, 514) decoded data retains the check code.
  • S1605.RS (544, 514)
  • the data of the reserved check code is sent to the BCH encoder for concatenated coding processing.
  • the data encoded by the S1606.RS+BCH concatenated code is subjected to interleaving, channel coding, and symbol mapping processing to generate a signal to be transmitted.
  • the signal to be transmitted is subjected to Nyquist filtering.
  • the filtered signal to be sent is sent to the transmitter, and is modulated and sent to the channel for transmission.
  • the second module may send and receive the received data to the first module.
  • the specific process is as follows, and the following process can be executed by modules inside the second module.
  • the receiver receives signals from the channel and performs coherent detection on the signals.
  • the received data stream is decoded by BCH to obtain a data stream after the first decoding.
  • the first decoded data stream is removed from the BCH check code, and then RS (544, 514) is decoded to obtain a second decoded data stream.
  • the second decoded data stream retains the RS (544, 514) check code, and the RS (544, 514) encoder is not required to re-encode the data.
  • FIG. 17 is a schematic diagram of a codec system of still another embodiment.
  • the codec system includes a processing module, a PMA module, and two communication interfaces.
  • the processing module includes an encoding module and a decoding module.
  • the encoding module may include at least one of the following modules: encoding and rate matching module, 256B/257B transcoding module, scrambling module, insertion alignment module, Pre-FEC distribution module, RS+BCH concatenated encoding module, distribution, and Rate conversion module.
  • the decoding module may include at least one of the following modules: an alignment word module, a reordering + deinterleaving module, an RS+BCH cascading decoding module, a post-FEC (Post-FEC) deinterleaving module, and an alignment word removal.
  • Module descrambling code module, 256B/257B transcoding decoding module, decoding and rate matching module.
  • the above two communication interfaces may be referred to as a 400GMII interface and a 400GAUI-X interface, respectively.
  • RS (544, 514) is selected as the FEC codeword in 400GE Ethernet, and the next generation 400GE and the future 800GE and 1.6TbE require higher performance FEC algorithm.
  • the codec method of FIG. 17 can be applied to 400GE, 800GE, 1.6TbE (ie, 400G Ethernet, 800G Ethernet, 1.6Tb Ethernet).
  • the S1701.64B (B represents a bit) data block is encoded by 64B66B to generate a 66B code block.
  • S1702.4 66B code blocks are generated by the 256B257B transcoding encoder to generate 257B code blocks.
  • the S1703.257B code block stream is scrambled by the scrambling module.
  • the scrambled 257B code block stream is inserted into the AM alignment word to form N PCS channel data streams.
  • N PCS channel streams are distributed to M RS+BCH encoders through the Pre-FEC distribution module for concatenated coding.
  • a total of 5140B blocks of 20 257B code blocks form the data portion of the codeword.
  • N FEC data streams are formed.
  • the S1706.FEC data stream is sent to the communication interface for transmission after being distributed and rate converted.
  • the S1711.400GAUI-X interface input data stream passes through the PMA layer and becomes N PCS bit streams.
  • the aligned data is channel-reordered, deinterleaved, and sent to M RS+BCH decoders for decoding. After decoding, N FEC data streams are formed.
  • the N FEC data streams are deinterleaved by the Post-FEC deinterleaving module to be restored into N PCS data streams.
  • the N PCS data streams are descrambled after removing the AM alignment word to generate a 257B data block stream.
  • the S1716.257B data block stream is restored to four 66B data blocks by the 256B257B transcoding decoder.
  • the S1717.66B data block is decoded by 64B66B to generate a 64B data block.
  • the codec system of Figure 18 can be applied to a backplane link.
  • the codec system includes a Media Access Control (MAC) module and a Physical Media Dependent (PMD) module, the codec system including at least one of the following modules: a 64B66B encoding and rate matching module, 256B/257B transcoding coding module, scrambling code module, alignment word module, Pre-FEC distribution module, RS+BCH cascade coding module, and interleaving module.
  • MAC Media Access Control
  • PMD Physical Media Dependent
  • the codec system may further include at least one of the following modules: an alignment word module, a deinterleaving module, an RS+BCH cascade decoding module, a Post-FEC deinterleaving module, an alignment word removal module, and a descrambling code module. , transcoding decoding module, 64B66B decoding and rate matching module.
  • the 64B data block stream input by the S1801.MAC is encoded by the 64B66B encoding module to generate a 66B data block.
  • S1802.4 66B data blocks are encoded by 256B/257B transcoding module to generate 257B data blocks.
  • the S1803.257B data block stream passes through the scrambling code module to generate a scrambled 257B data block stream.
  • the scrambled 257B data block stream is synchronously aligned.
  • M RS+BCH encoders encode large blocks of 20 257B data blocks.
  • the 257B data block stream is restored to four 66B data block streams by the 256B/257B decoding module.
  • the 66B data block stream is input to the 64B66B decoding module to be restored to the 64B data block and sent to the MAC module.
  • FIG. 19 is a schematic block diagram of an encoding apparatus according to an embodiment of the present application.
  • the encoding device 1900 of FIG. 19 includes a determining unit 1910 and a processing unit 1920,
  • the determining unit 1910 is configured to determine a frame of an outer code of the data to be encoded, where the frame of the outer code includes a data information code and a check code of the data information code, and the frame of the outer code is divided into Q data. a block, each of the Q data blocks includes W bits, where W and Q are respectively integers greater than zero;
  • the processing unit 1920 is configured to encode the Q data blocks to obtain Q codewords of the inner code, where the Q data blocks are in one-to-one correspondence with the Q codewords of the inner code.
  • the first codeword of the Q codewords of the inner code includes a first data block and a check code of the first data block, and the first codeword is any one of Q codewords of the inner code a codeword, the first data block being a data block corresponding to the first codeword.
  • FIG. 20 is a schematic structural diagram of a decoding apparatus 2000 according to an embodiment of the present application.
  • the decoding device of FIG. 20 includes: an obtaining unit 2010 and a processing unit 2020,
  • the acquiring unit 2010 is configured to acquire Q codewords of the inner code of the data to be decoded, where the Q codewords of the inner code are in one-to-one correspondence with the Q data blocks included in the frame of the outer code, and the Q of the inner code
  • the first codeword of the codewords includes a first data block and a check code of the first data block, and the first codeword is any one of Q codewords of the inner code,
  • the first data block is a data block corresponding to the first codeword;
  • the processing unit 2020 is configured to decode Q codewords of the inner code to obtain a frame of the outer code, where a frame of the outer code is divided into the Q data blocks, where the Q Each of the data blocks includes W bits, W and Q are respectively integers greater than zero; and the frame of the outer code is decoded to obtain decoded data.
  • FIG. 21 is a schematic block diagram of an encoding apparatus 2100 according to an embodiment of the present invention. It should be understood that the encoding device 2100 is capable of performing the various steps of the encoding method described above, and to avoid repetition, it will not be described in detail herein.
  • the encoding device 2100 includes:
  • a memory 2110 configured to store a program
  • a communication interface 2120 configured to communicate with other devices
  • the processor 2130 is configured to execute a program in the memory 2110. When the program is executed, the processor 2130 is configured to determine a frame of an outer code of data to be encoded, where the frame of the outer code includes a data information code and a a check code of the data information code, the frame of the outer code is divided into Q data blocks, each of the Q data blocks includes W bits, where W and Q are respectively greater than zero
  • the processor 2130 is further configured to encode the Q data blocks to obtain Q codewords of the inner code, where the Q data blocks and the Q codewords of the inner code are one by one
  • the first codeword of the Q codewords of the inner code includes a first data block and a check code of the first data block, where the first codeword is Q codewords of the inner code Any one of the code words, the first data block is a data block corresponding to the first code word.
  • FIG. 22 is a schematic block diagram of a decoding device 2200 according to an embodiment of the present invention. It should be understood that the decoding device 2200 is capable of performing the various steps of the decoding method described above, and to avoid repetition, it will not be described in detail herein.
  • the decoding device 2200 includes:
  • a memory 2210 configured to store a program
  • a communication interface 2220 configured to communicate with other devices
  • the processor 2230 is configured to execute a program in the memory 2210. When the program is executed, the processor 2230 is configured to acquire Q code words of an inner code of data to be decoded, and Q code words of the inner code.
  • the first codeword of the Q codewords of the inner code includes a first data block and a check code of the first data block, where a codeword is any one of Q codewords of the inner code, the first data block is a data block corresponding to the first codeword; and Q codes for the inner code Decoding a word to obtain a frame of the outer code, wherein a frame of the outer code is divided into the Q data blocks, and each of the Q data blocks includes W bits, Q is an integer greater than zero; and decoding the frame of the outer code to obtain decoded data.
  • the disclosed systems, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the functions may be stored in a computer readable storage medium if implemented in the form of a software functional unit and sold or used as a standalone product.
  • the technical solution of the present application which is essential or contributes to the prior art, or a part of the technical solution, may be embodied in the form of a software product, which is stored in a storage medium, including
  • the instructions are used to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present application.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like, which can store program codes. .

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Abstract

本申请提供了一种编码方法、解码方法、装置和系统，以提高编解码的效率。该方法包括：确定待编码数据的外码的帧，外码的帧包括数据信息码和数据信息码的校验码，外码的帧被划分为Q个数据块，Q个数据块中的每个数据块包括W个比特，其中，W、Q分别为大于零的整数；对Q个数据块进行编码，以获取内码的Q个码字，其中，Q个数据块与内码的Q个码字一一对应，内码的Q个码字中的第一码字包括第一数据块和第一数据块的校验码，第一码字为内码的Q个码字中的任意一个码字，第一数据块为第一码字对应的数据块。

Description

编码方法、解码方法、装置和系统
本申请要求于2017年03月29日提交中国专利局、申请号为201710195399.7、发明名称为“编码方法、解码方法、装置和系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及编解码技术领域，并且更具体地，涉及编码方法、解码方法、装置和系统。
背景技术
随着高速通信链路速率的不断上升，信道的各种损伤效应逐渐加强，导致信噪比下降，为了改善低信噪比条件下的误码性能，前向纠错(Forward Error Correction，FEC)编解码技术已逐渐成为高速通信链路的必选技术。FEC编解码技术的要求主要体现在高增益、低延迟、低复杂度、以及高兼容性。
为了适应更高速率的通信链路，如何能够在综合地考虑FEC编解码的增益、延迟、复杂度以及高兼容性的情况下，获取高性能的FEC编解码技术，是业界亟待解决的问题。
发明内容
本申请提供一种编码方法、解码方法、装置和系统，以提高编解码的效率。
第一方面，提供了一种编码方法，包括：确定待编码数据的外码的帧，所述外码的帧包括数据信息码和所述数据信息码的校验码，所述外码的帧被划分为Q个数据块，所述Q个数据块中的每个数据块包括W个比特，其中，W、Q分别为大于零的整数；对所述Q个数据块进行编码，以获取内码的Q个码字，其中，所述Q个数据块与所述内码的Q个码字一一对应，所述内码的Q个码字中的第一码字包括第一数据块和所述第一数据块的校验码，所述第一码字为所述内码的Q个码字中的任意一个码字，所述第一数据块为所述第一码字对应的数据块。
在本申请实施例中，外码的帧被划分为长度为W比特的Q个数据块，并对Q个数据块编码，以获取内码的Q个码字，其中，内码的Q个码字中的第一码字包含的校验码只包括第一数据块的校验码，从而能够减少编码的复杂度。
在本申请实施例中，由于内码的Q个码字中的第一码字包含的校验码只包括第一数据块的校验码，因此在编码的过程中，外码的码字可以采用流水线的方式输入至内码编码器进行编码，从而能够减少编码过程中的延迟。
在本申请实施例中，通过级联编码的方式对待编码数据进行编码，能够减少误码率，提高纠错性能。并且通过流水线的方式进行级联编码，相对于同等纠错性能的编码方式，能够减少编码延迟和复杂度。
在本申请实施例中，通过级联编码的方式对待编码数据进行编码，待编码的数据可以 只通过外码编码器进行较低增益的编码，或者，待编码数据可以通过级联编码的方式进行较高增益的编码，从而能够提高编解码的兼容性。
在一种可能的实现方式中，还包括：在所述内码的Q个码字中的每个帧中添加至少一个空白比特，所述至少一个空白比特用于调整编码的码字速率。
在本申请实施例中，通过在内码中填充至少一个空白比特，以调整编解码的速率，从而提高了编解码的效率
在一种可能的实现方式中，还包括：基于所述内码的Q个码字进行预编码，以得到预编码后的数据。
在一种可能的实现方式中，所述确定待编码数据的外码的帧，包括：获取待编码数据；对所述待编码数据进行编码，以获取所述外码的帧。
在一种可能的实现方式中，所述外码为里德所罗门RS码。
在一种可能的实现方式中，所述外码的帧包括Y个RS码的码字，且Y*N*M＝Q*W，N为RS码的码字符号数量，K为RS(N,K)码的信息符号数量，M为RS码的每个码字符号包括的比特数量，Y、M、N分别为大于零的整数。
在一种可能的实现方式中，N＝544,K＝514；或，N＝528,K＝514；或，N＝271，K＝257。
在一种可能的实现方式中，所述内码包括以下任意一种：RS码、BCH码和卷积码。
在一种可能的实现方式中，W的取值为以下数值中的任一项：160、320、480和640。
第二方面，提供了一种解码方法，包括：获取待解码数据的内码的Q个码字，所述内码的Q个码字与外码的帧包括的Q个数据块一一对应，所述内码的Q个码字中的第一码字包括第一数据块和所述第一数据块的校验码，所述第一码字为所述内码的Q个码字中的任意一个码字，所述第一数据块为所述第一码字对应的数据块；对所述内码的Q个码字进行解码，以获取所述外码的帧，其中，所述外码的帧被划分为所述Q个数据块，所述Q个数据块中的每个数据块包括W个比特，W、Q分别为大于零的整数；对所述外码的帧进行解码，以获取解码后的数据。
在本申请实施例中，基于内码的Q个码字进行解码获取外码的帧，并根据外码的帧获取解码后的数据。内码的Q个码字与外码的帧包括的Q个数据块一一对应。其中，内码的Q个码字中的第一码字包含的校验码只包括第一数据块的校验码，从而能够减少解码的复杂度。
在本申请实施例中，由于内码的Q个码字中的第一码字包含的校验码只包括第一数据块的校验码，因此提高了对内码进行解码的速度。在对内码解码得到外码的1个帧后可以以流水线的方式输入至外码编码器进行解码，从而能够减少编码过程中的延迟。
在本申请实施例中，通过级联编码的方式对待编码数据进行编码，能够减少误码率，提高纠错性能。并且通过流水线的方式进行级联编码，相对于同等纠错性能的编码方式，能够减少编码延迟和复杂度。
在本申请实施例中，通过级联解码的方式对待解码数据进行解码，待解码的数据可以只通过外码解码器进行较低增益的解码，或者，待解码数据可以通过级联解码的方式进行较高增益的解码，从而能够提高编解码的兼容性。
在一种可能的实现方式中，所述内码的Q个码字中还包括至少一个空白比特，所述至少一个空白比特用于调整编码的码字速率。
在本申请实施例中，通过在内码中填充至少一个空白比特，以调整编解码的码字速率，从而提高了编解码的效率
在一种可能的实现方式中，在所述获取所述待解码数据的内码的Q个码字之前，还包括：获取待解码数据；对所述待解码数据进行预编码的解码处理，以获取所述内码的Q个码字。
在一种可能的实现方式中，所述外码为里德所罗门RS码。
在一种可能的实现方式中，所述外码的帧包括Y个RS码的码字，且Y*N*M＝Q*W，其中，N为RS码的每个码字包括的码字符号数量，M为RS码的每个码字符号包括的比特数量，Y、M、N分别为大于零的整数。
在一种可能的实现方式中，N＝544,K＝514；或，N＝528,K＝514；或，N＝271，K＝257。
在一种可能的实现方式中，所述内码包括以下任意一种：RS码、BCH码和卷积码。
在一种可能的实现方式中，W的取值为以下数值中的任一项：160、320、480和640。
第三方面，提供了一种编码装置，所述编码装置包括用于执行所述第一方面或其各种实现方式中的方法的模块。
第四方面，提供了一种解码装置，所述解码装置包括用于执行所述第二方面或其各种实现方式中的方法的模块。
第五方面，提供一种通信系统，包括第三方面所述的编码装置和第四方面所述的解码装置。
第六方面，提供一种编码装置，包括非易失性存储介质，以及中央处理器，所述非易失性存储介质存储有可执行程序，所述中央处理器与所述非易失性存储介质连接，并执行所述可执行程序以实现所述第一方面中的方法。
第七方面，提供一种解码装置，包括非易失性存储介质，以及中央处理器，所述非易失性存储介质存储有可执行程序，所述中央处理器与所述非易失性存储介质连接，并执行所述可执行程序以实现所述第二方面中的方法。
第八方面，提供一种通信系统，包括第六方面所述的编码装置和第七方面所述的解码装置。
第九方面，提供一种计算机可读介质，所述计算机可读介质存储用于设备执行的程序代码，所述程序代码包括用于执行第一方面中的方法的指令。
第十方面，提供一种计算机可读介质，所述计算机可读介质存储用于设备执行的程序代码，所述程序代码包括用于执行第二方面中的方法的指令。
第十一方面，提供一种通信系统，包括第九方面所述的编码装置和第十方面所述的解码装置。
附图说明
图1是本申请实施例的编解码系统的示意性结构。
图2是本申请实施例的编码方法的示意性流程图。
图3是本申请实施例的级联码的帧结构示意图。
图4是本申请实施例的解码方法的示意性流程图。
图5是本申请又一实施例的级联码的帧的示意性结构图。
图6是本申请又一实施例的级联码的帧的示意性结构图。
图7是本申请又一实施例的级联码的帧的示意性结构图。
图8是本申请又一实施例的级联码的帧的示意性结构图。
图9是本申请又一实施例的级联码的帧的示意性结构图。
图10是本申请又一实施例的级联码的帧的示意性结构图。
图11是本申请又一实施例的级联码的帧的示意性结构图。
图12是本申请又一实施例的级联码的帧的示意性结构图。
图13是本申请又一实施例的级联码的帧的示意性结构图。
图14是本申请又一实施例的级联码的帧的示意性结构图。
图15是本申请又一实施例的编解码系统的示意图。
图16是本申请又一实施例的编解码系统的示意图。
图17是本申请又一实施例的编解码系统的示意图。
图18是本申请又一实施例的编解码系统的示意图。
图19是本申请实施例的编码装置的示意图。
图20是本申请实施例的解码装置的示意图。
图21是本申请又一实施例的编码装置的示意图。
图22是本申请又一实施例的解码装置的示意图。
具体实施方式
下面将结合附图，对本申请中的技术方案进行描述。
本申请实施例提出了一种编码方法、解码方法、装置和系统。
应理解，本发明实施例的技术方案可以应用于各种通信系统，例如：全球移动通讯(Global System of Mobile communication，GSM)系统、码分多址(Code Division Multiple Access，CDMA)系统、宽带码分多址(Wideband Code Division Multiple Access，WCDMA)系统、通用分组无线业务(General Packet Radio Service，GPRS)、长期演进(Long Term Evolution，LTE)系统、LTE频分双工(Frequency Division Duplex，FDD)系统、LTE时分双工(Time Division Duplex，TDD)、通用移动通信系统(Universal Mobile Telecommunication System，UMTS)或全球互联微波接入(Worldwide Interoperability for Microwave Access，WiMAX)通信系统等。
需要说明的是，本申请实施例中的将外码和内码进行联合编码的方法也可以称作级联编码。采用级联编码的方式获得的编码也可以称作级联码，或者说，级联码包括上述外码和上述内码。
图1是本申请实施例的编解码系统100的示意性结构图。应理解，本发明实施例描述的编解码系统及场景是为了更加清楚的说明本发明实施例的技术方案，并不构成对本发明实施例提供的技术方案的限定，本领域普通技术人员可知，随着编解码系统的演变和发展，本发明实施例提供的技术方案对于类似的技术问题，同样适用。
图1的编解码系统100的编码模块包括外码编码器和内码编码器，图1的编解码系统100的解码模块包括外码解码器和内码解码器。其中，图1示出了包括一个外码编码器和一个外码解码器的编解码系统的结构。本领域技术人员可以理解，图1的编解码系统100 还可以包括多个外码编码器和多个外码解码器，本申请实施例对此不作限定。
如图1所示，在编码部分，待编码的数据流依次通过外码编码器和内码编码器进行编码，其中外码编码器的输出作为内码编码器的输入。外码和内码的编码可以通过流水线方式完成。或者说内、外码的编码可以同时进行，不需要等外码编码完成后再进行内码编码。
可选地，在解码部分，内码解码器在接收到待解码的数据流后先进行内码解码，当内码解码的错误数量超过该内码解码器纠错能力时，内码解码器将接收到的去除内码校验码后的原始数据传输至外码解码器。外码解码器接收到内码解码器传递过来的数据后开始进行译码纠错，以获取解码后的数据。
图2示出了本申请实施例的编码方法200的示意性流程图。如图2所示，该方法200包括：
S201，确定待编码数据的外码的帧，所述外码的帧包括数据信息码和所述数据信息码的校验码，所述外码的帧被划分为Q个数据块，所述Q个数据块中的每个数据块包括W个比特，其中，W、Q分别为大于零的整数。
可选地，所述外码的帧可以是直接获取的已经编码完成的外码的帧。或者，也可以是获取待编码数据，对所述待编码数据进行编码，以得到所述外码的帧。
可选地，所述外码可以是里德所罗门(Reed Solomon,RS)码。也可以是其他类型的纠错码，本申请实施例对此不作限定。
可选地，所述外码可以包括数据信息码和校验码，所述校验码用于校验所述数据信息码。
S202，对所述Q个数据块进行编码，以获取内码的Q个码字，其中，所述Q个数据块与所述内码的Q个码字一一对应，所述内码的Q个码字中的第一码字包括第一数据块和所述第一数据块的校验码，所述第一码字为所述内码的Q个码字中的任意一个码字，所述第一数据块为所述第一码字对应的数据块。
需要说明的是，上述内码的第一码字的校验码只包括第一数据块的校验码。因此，Q个内码的编码顺序不影响内码的编码结果。或者说，内码的Q个码字可以是同步编码，也可以是顺序编码，或者采用其他不同步的方式。换句话说，在外码的帧完整输出到内码编码器之前，内码编码器可以与外码编码器同步进行编码，因此，减少了编码过程中的延迟。
作为一个示例，在外码编码的过程中，外码编码器可以以流水线的方式输出已经编码完成的外码的码字，内码编码器可以以流水线的方式接收外码的码字。并对对Q个数据块进行编码，以获取内码的Q个码字。
可选地，所述外码的帧可以包括外码的1个帧。所述外码的1个帧可以包括外码的一个码字，也可以包括外码的多个码字。
可选地，可以采用多种划分方式将所述外码划分为Q个数据块。例如，所述外码的多个码字组成的比特或符号顺序可以任意摆放，例如，可以是多个外码的码字顺序排列，也可以是多个外码的码字之间间插排列，本申请实施例对此不作限定。
作为一个具体示例，图3是本申请实施例的级联码的帧结构示意图。图3中的外码的1个帧包括外码的L个码字，外码的L个码字包括的码字符号或比特被划分为Q个数据块，所述Q个数据块中的每个数据块可以作为内码的数据信息码进行编码，生成的校验码可以附在数据信息码之后形成内码的码字。L为大于0的整数。在图3的例子中，D表示数据 信息码，P1表示外码的校验码，P2表示内码的校验码。
在本申请实施例中，外码的帧被划分为长度为W比特的Q个数据块，并对Q个数据块编码，以获取内码的Q个码字，其中，内码的Q个码字中的第一码字包含的校验码只包括第一数据块的校验码，从而能够减少编码的复杂度。
在本申请实施例中，由于内码的Q个码字中的第一码字包含的校验码只包括第一数据块的校验码，因此在编码的过程中，外码的码字可以采用流水线的方式输入至内码编码器进行编码，从而能够减少编码过程中的延迟。
在本申请实施例中，通过级联编码的方式对待编码数据进行编码，能够减少误码率，提高纠错性能。并且通过流水线的方式进行级联编码，相对于同等纠错性能的编码方式，能够减少编码延迟和复杂度。
在本申请实施例中，通过级联编码的方式对待编码数据进行编码，待编码的数据可以只通过外码编码器进行较低增益的编码，或者，待编码数据可以通过级联编码的方式进行较高增益的编码，从而能够提高编解码的兼容性。
因此，本申请实施例提供的编解码方法可以在保证编解码增益的同时，降低编解码的延迟和复杂度，提高编解码的兼容性。
可选地，为了调整编码后数据流的速率，可以在内码中填充至少一个空白比特。该至少一个空白比特可以用于填充无效数据，也可以用于填充有效信息。例如，该至少一个空白比特可以用于通道管理。
作为一个示例，内码包含的空白比特的数量可以根据实际链路的速率选取。选取空白比特的数量的标准可以是：获取添加空白比特后的内码的码字长度与数据信息比特长度的比值，空白比特的数量应使得该比值的最小约数的分子值和分母值尽可能小。以便于简化编解码过程中使用的时钟，适应实际链路的速率。
在本申请实施例中，通过在内码中填充至少一个空白比特，以调整编解码的速率，从而提高了编解码的效率。
可选地，在获取内码的Q个码字之后，方法200还包括：基于内码的Q个码字生成待发送的信号。
具体地，上述基于内码的Q个码字生成待发送的信号，可以包括多种处理方式。本申请实施例对此不作限制。例如，可以将内码的Q个码字经过交织、信道编码、映射处理，以生成待发送的信号。
可选地，所述方法200还包括：基于内码的Q个码字进行预编码，得到预编码后的数据，基于预编码后的数据生成待发送的信号。
在本申请实施例中，在存在突发信道的情况下，可以对内码的Q个码字进行预编码，然后基于预编码后的数据生成待发送的信号，能够改善级联编码的误码性能。
作为一个具体示例，可以将内码的Q个码字输入至1/(1+D)MOD X预编码器，以进行预编码处理。其中，D表示数字滤波器一个符号单位的延迟，MOD表示模除运算，X表示模除运算的阶数，比如采用PAM-4调制的时候X＝4。
可选地，所述外码的帧可以包括Y个RS码的码字，且Y*N*M＝Q*W，N为RS码的码字符号数量，K为RS(N,K)码的信息符号数量，M为RS码的每个码字符号包括的比特数量，Y、M、N分别为大于零的整数。上述RS码可以表示为RS(N,K)。
可选地，在外码RS(N,K)中，N＝544,K＝514；或，N＝528,K＝514；或，N＝271，K＝257。例如，外码可以包括RS(544，514)、RS(528，514)或RS(271，257)。
可选地，W的取值为以下数值中的任一项：160、320、480和640。或者说，内码的数据信息码的比特数量可以是160、320、480和640。例如，内码的选取可以参见下文中的表1至表8所列举的内容。
上文介绍了本申请实施例中的编码方法，下文介绍本申请实施例中的解码方法400。图4是本申请实施例的解码方法的示意性流程图。为了简洁，图4的方法中与前文中相同或相似的内容，此处不再赘述。该解码方法400包括：
S401，获取待解码数据的内码的Q个码字，所述内码的Q个码字与外码的帧包括的Q个数据块一一对应，所述内码的Q个码字中的第一码字包括第一数据块和所述第一数据块的校验码，所述第一码字为所述内码的Q个码字中的任意一个码字，所述第一数据块为所述第一码字对应的数据块。
S402，对所述内码的Q个码字进行解码，以获取所述外码的帧，其中，所述外码的帧被划分为所述Q个数据块，所述Q个数据块中的每个数据块包括W个比特，W、Q分别为大于零的整数。
可选地，所述外码为RS码。
S403，对所述外码的帧进行解码，以获取解码后的数据。
在本申请实施例中，基于内码的Q个码字进行解码获取外码的帧，并根据外码的帧获取解码后的数据。内码的Q个码字与外码的帧包括的Q个数据块一一对应。其中，内码的Q个码字中的第一码字包含的校验码只包括第一数据块的校验码，从而能够减少解码的复杂度。
在本申请实施例中，由于内码的Q个码字中的第一码字包含的校验码只包括第一数据块的校验码，因此提高了对内码进行解码的速度。在对内码解码得到外码的1个帧后可以以流水线的方式输入至外码编码器进行解码，从而能够减少编码过程中的延迟。
在本申请实施例中，通过级联编码的方式对待编码数据进行编码，能够减少误码率，提高纠错性能。并且通过流水线的方式进行级联编码，相对于同等纠错性能的编码方式，能够减少编码延迟和复杂度。
在本申请实施例中，通过级联解码的方式对待解码数据进行解码，待解码的数据可以只通过外码解码器进行较低增益的解码，或者，待解码数据可以通过级联解码的方式进行较高增益的解码，从而能够提高编解码的兼容性。
因此，本申请实施例提供的编解码方法可以在保证编解码增益的同时，降低编解码的延迟和复杂度，提高编解码的兼容性。
可选地，在方法400中，所述内码的Q个码字还包括至少一个空白比特，所述至少一个空白比特用于调整级联编码后的码字速率。
可选地，在方法400中，在所述获取所述待解码数据的内码的Q个码字之前，还包括：获取待解码数据；对所述待解码数据进行预编码的解码处理，以获取所述内码的Q个码字。
可选地，在方法400中，所述外码的帧包括Y个RS码的码字，且Y*N*M＝Q*W，其中，N为RS码的每个码字包括的码字符号数量，M为RS码的每个码字符号包括的比特数量，Y、M、N分别为大于零的整数。
可选地，在方法400中，N＝544,K＝514；或，N＝528,K＝514；或，N＝271，K＝257。
可选地，在方法400中，所述内码包括以下任意一种：RS码、BCH码和卷积码。
可选地，在方法400中，W的取值为以下数值中的任一项：160、320、480和640。
在本申请实施例中，W的取值也可以是其他任意数值，本申请实施例对此不作限定。
下文将结合附图，描述本申请实施例的编码方法和解码方法的具体实施例。
图5是本申请实施例的级联码的帧的示意性结构图。图5中，D表示外码的数据信息码、P1表示外码的校验码，P2表示内码的校验码。如图5所示，图中的外码为RS(N,K)码。该级联码的帧中将P个RS码字划分为Q个长度为W比特的数据块。P*N*M＝Q*W，M是RS码的每个码字符号包括的比特数量。每个数据块作为内码的数据信息码进行编码，以生成校验码，校验码可以附在每个数据块之后，形成内码的码字。可选地，为了调整编码后数据流的速率，可以在内码的码字的后面添加适当的空白比特。该空白比特可以固定填充无效数据，也可以填充有效信息。例如，该有效信息以用于通道管理。可选地，内码的码字可以包括以下任意一种：BCH码，RS码，卷积码。
可选地，图5中的外码的1个帧可以由一个RS码字组成，也可以由多个RS码字组成。例如，外码的帧可以由L个RS码字组成，L为大于等于1的正整数。L个RS码字组成的比特或者码字符号顺序在外码的帧中可以任意摆放，可以顺序排列，也可以间插排列。
图6至图8是本申请又一实施例的级联码的帧的示意性结构图。图6至图8中，D表示外码的数据信息码、P1表示外码的校验码，P2表示内码的校验码。其中，图6至图8的内码的每个码字的数据信息码的数量为320比特。
图6的外码的1个帧包括RS(544,514)码的1个码字。RS(544,514)码字以W＝320比特为粒度进行切分，RS(544,514)码的1个帧正好切分成Q＝17个长度为W＝320比特的数据块。
图7的外码的1个帧包括RS(528,514)码的2个码字。RS(528,514)码的1个帧正好切分成Q＝33个长度为W＝320比特的数据块。
图8的外码的1个帧包括RS(544,514)码的2个码字。RS(544,514)码的1个帧正好切分成Q＝34个长度为W＝320比特的数据块。
作为一个具体示例，图6至图8的例子中的内码可以是表1所示的BCH(n,x,t,m)码，或者表2所示的RS(N,K,T,M)码。表1中的BCH码和表2中的RS码的每个码字的数字信息码的长度为320比特。
其中，在本申请实施例中，n表示每个码字的码字长度，x表示每个码字中的数据信息码的比特数量，t为每个码字可以纠正的比特数量，m表示码字的有限域的维数，N表示每个码子的码字符号数量，K表示每个码字的数据信息码的码字符号数量，T为每个码字可以纠正的码字符号数量；M为每个码字的码字符号的比特数量。OH表示校验码或开销的比例。
可选地，内码包含的空白比特的数量可以根据实际链路的速率选取。选取空白比特的数量的标准可以是：获取添加空白比特后的内码的码字长度与数据信息比特长度的比值，空白比特的数量应使得该比值的最小约数的分子值和分母值尽可能小。以便于简化编解码过程中使用的时钟，适应实际链路的速率。例如，当选择BCH(356,320,4)码作为内码时， 可以在每个BCH码后添加4比特空白比特，将整个BCH数据帧补齐为360比特，此时内码的码字长度和数据信息比特的长度之比为360/320＝9/8。
表1
Figure PCTCN2018079511-appb-000001
表2
Figure PCTCN2018079511-appb-000002
Figure PCTCN2018079511-appb-000003
图9至或图10是本申请又一申请实施例的的级联码的帧的示意性结构图。图9或图10中，D表示外码的数据信息码、P1表示外码的校验码，P2表示内码的校验码。其中，图9或图10的内码的每个码字的数据信息码的数量为480比特。
图9的外码的1个帧包括RS(544,514)码的3个码字。RS(544,514)码字以W＝480比特为粒度进行切分，RS(544,514)码的1个帧正好切分成Q＝34个长度为W＝480比特的数据块。
图10的外码的1个帧包括RS(528,514)码的1个码字。RS(528,514)码的1个帧正好切分成Q＝11个长度为W＝480比特的数据块。
作为一个具体示例，图9或图10的例子中的内码可以是表2所示的BCH(n,x,t,m)码，或者表3所示的RS(N,K,T,M)码。表3中的BCH码和表4中的RS码的每个码字的数字信息码的长度为480比特。
其中，在本申请实施例中，n表示每个码字的码字长度，x表示每个码字中的数据信息码的比特数量，t为每个码字可以纠正的比特数量，m表示码字的有限域的维数，N表示每个码子的码字符号数量，K表示每个码字的数据信息码的码字符号数量，T为每个码字可以纠正的码字符号数量；M为每个码字的码字符号的比特数量。OH表示校验码或开销的比例。
作为一个示例，内码包含的空白比特的数量可以根据实际链路的速率选取，例如，当选择BCH(540,480,6)码作为内码时，可以在每个BCH码后添加0个比特空白比特，此时内码的码字长度和数据信息比特的长度之比为360/320＝9/8。
表3
Figure PCTCN2018079511-appb-000004
Figure PCTCN2018079511-appb-000005
表4
Figure PCTCN2018079511-appb-000006
Figure PCTCN2018079511-appb-000007
图11或图12是本申请又一实施例的级联码的帧的示意性结构图。图11或图12中，D表示外码的数据信息码、P1表示外码的校验码，P2表示内码的校验码。其中，图11或图12的内码的每个码字的数据信息码的数量为640比特。
图11的外码的1个帧包括RS(544,514)码的2个码字。RS(544,514)码字以W＝640比特为粒度进行切分，RS(544,514)码的1个帧正好切分成Q＝17个长度为W＝640比特的数据块。
图12的外码的1个帧包括RS(528,514)码的4个码字。RS(528,514)码的1个帧正好切分成Q＝33个长度为W＝640比特的数据块。
作为一个具体示例，图11或图12的例子中的内码可以是表5所示的BCH(n,x,t,m)码，或者表6所示的RS(N,K,T,M)码。表5中的BCH码和表6中的RS码的每个码字的数字信息码的长度为640比特。
其中，在本申请实施例中，n表示每个码字的码字长度，x表示每个码字中的数据信息码的比特数量，t为每个码字可以纠正的比特数量，m表示码字的有限域的维数，N表示每个码子的码字符号数量，K表示每个码字的数据信息码的码字符号数量，T为每个码字可以纠正的码字符号数量；M为每个码字的码字符号的比特数量。OH表示校验码或开销的比例。
作为一个示例，内码包含的空白比特的数量可以根据实际链路的速率选取，例如，当选择BCH(720,640,8)码作为内码时，可以在每个BCH码后添加0个比特空白比特，此时内码的码字长度和数据信息比特的长度之比为720/640＝9/8。
表5
Figure PCTCN2018079511-appb-000008
Figure PCTCN2018079511-appb-000009
表6
Figure PCTCN2018079511-appb-000010
Figure PCTCN2018079511-appb-000011
图13或图14是本申请又一实施例的级联码的帧的示意性结构图。图13或图14中，D表示外码的数据信息码、P1表示外码的校验码，P2表示内码的校验码。其中，图13或图14中的内码的每个码字的数据信息码的数量为160比特。
图13的外码的1个帧包括RS(544,514)码的1个码字。RS(544,514)码字以W＝160比特为粒度进行切分，RS(544,514)码的1个帧正好切分成Q＝34个长度为W＝160比特的数据块。
图14的外码的1个帧包括RS(528,514)码的1个码字。RS(528,514)码的1个帧正好切分成Q＝33个长度为W＝160比特的数据块。
作为一个具体示例，图13或图14的例子中的内码可以是表7所示的BCH(n,x,t,m)码，或者表8所示的RS(N,K,T,M)码。表7中的BCH码和表8中的RS码的每个码字的数字信息码的长度为160比特。
其中，在本申请实施例中，n表示每个码字的码字长度，x表示每个码字中的数据信息码的比特数量，t为每个码字可以纠正的比特数量，m表示码字的有限域的维数，N表示每个码子的码字符号数量，K表示每个码字的数据信息码的码字符号数量，T为每个码 字可以纠正的码字符号数量；M为每个码字的码字符号的比特数量。OH表示校验码或开销的比例。
作为一个示例，内码包括的空白比特的数量可以根据实际链路的速率选取。例如，当选择BCH(176,160,2)码作为内码时，可以在每个BCH码后添加4比特空白比特，将BCH码的码字长度补齐为180比特，此时内码的码字长度和数据信息比特的长度之比为为180/160＝9/8。
表7
Figure PCTCN2018079511-appb-000012
表8
Figure PCTCN2018079511-appb-000013
Figure PCTCN2018079511-appb-000014
作为一个具体示例，图15是本申请又一实施例的编解码系统的示意图。图15可以应用于密集波分复用系统，其能够提供路由器到路由器的之间的直连链路。例如，该链路中可以采用单载波相干解调的400Gbps链路。图15的编解码系统能够为该直连链路提供纠错能力更强的FEC算法，并且具有较低的复杂度，从而能够将编解码的装置放进光模块中。
图15的示例中包括第一模块和第二模块，其中，第一模块可以是线卡上的接口芯片，第二模块可以是光模块内的芯片，第一模块和第二模块之间的通信接口可以称为400GAUI-X。第一模块支持RS(544,514)编解码。第二模块支持RS(544,514)+BCH级联编解码。
在图15所示的第一链路方向，第一模块将编码后的RS(544,514)码字发送至第二模块，第二模块中的解码装置在接收到RS(544,514)码后，可以将RS(544,514)码字解码后去掉校验位，以得到源数据。然后将该源数据重新通过RS(544,514)+BCH的编码装置重新进行级联编码。
图15的第一链路方向中，第二模块中从第一模块接收数据，进行解码和编码之后，向其他设备发送信号的流程如下所示，下述流程可以由第二模块内部的模块执行。第二模块包括物理媒介附加(physical medium attachment,PMA)模块、第一处理模块和第二处理模块。第二模块可以包括PMA模块、第一处理模块、第二处理模块。该第一处理模块可以包括以下模块中的至少一个：对齐字模块、重排序+解交织模块、RS(544,514)解码模块。第二处理模块可以包括：RS校验码去除模块、RS+BCH级联编码模块、交织模块、信道编码模块、符号映射模块、滤波模块。第二处理模块还包括以下模块中的至少一个：相干检测模块、符号解映射模块、信道解码模块、解交织模块、RS+BCH解码模块、RS+BCH校验码去除模块。第一处理模块还可以包括以下模块中的至少一个：RS(544,514)编码模块、分发和交织模块。
S1501.400GAUI-X通信接口接收数据流，并将该数据流输入至PMA层，以获取N个物理编码子层(physical coding sublayer,PCS)数据流。
S1502.根据内部的对齐字标识(Alignment Marxer，AM)，将N个PCS数据流进行同步对齐。
S1503.对该对齐后的数据进行通道重排序、解交织，然后将处理后的数据输入至RS(544,514)解码器解码。
S1504.将对RS(544,514)码进行解码后获取的数据去除校验码。
S1505.RS(544,514)去除校验码的数据送入RS+BCH级联码编码器进行编码处理。
S1506.RS+BCH级联码编码后的数据经过交织、信道编码、符号映射处理，生成待发送的信号。
S1507.可选地，将待发送的信号进行奈奎斯特(Nyquist)滤波；
S1508.将滤波后的待发送信号送入发送器,并在调制后送往信道中传输。
图15的第二链路方向中，第二模块可以对接收到的数据进行解码和编码之后，向第一模块发送。其具体流程如下所示，下述流程可以由第二模块内部的模块执行。
S1511.接收器从信道中接收信号，并对信号进行相干检测。
S1512.对相干检测得到的通信信号进行符号解映射、信道解码，解交织，生成接收数据流。
S1513.接收的数据流经过RS+BCH级联码解码，生成解码后的数据流。
S1514.解码后的数据流去除RS+BCH校验数据后送入RS(544,514)编码器。
S1515.RS(544,514)编码器对数据进行再次编码。
S1516.RS(544,514)编码器生成的数据经过PMA层分发和交织以后发往通信接口进行数据传输。
图16是本申请又一实施例的编解码系统的示意图。图16的应用场景与图15类似，此处不再赘述。图16的示例中包括第一模块和第二模块。第一模块和第二模块之间的通信接口可以称为400GAUI-X。第一模块支持RS(544,514)编解码。第二模块支持RS(544,514)+BCH级联编解码。
其中，图15与图16的例子不同之处在于，图16的编码方法可以直接重用RS(544,514)解码后的码字，直接通过BCH编码后生成级联后的码字。图15和图16给出的两种方案生成的码字可以完全相同。
图16的第一链路方向，第二模块中从第一模块接收数据，进行解码和编码之后，向其他设备发送信号的流程如下所示，下述流程可以由第二模块内部的模块执行。第二模块可以包括PMA模块、第一处理模块、第二处理模块。该第一处理模块可以包括以下模块中的至少一个：对齐字模块、重排序+解交织模块、RS(544,514)解码模块。第二处理模块可以包括：RS校验码去除模块(可不选)、BCH编码模块、交织模块、信道编码模块、符号映射模块、滤波模块。第二处理模块还包括以下模块中的至少一个：相干检测模块、符号解映射模块、信道解码模块、解交织模块、BCH解码模块、BCH校验码去除模块。第一处理模块还可以包括以下模块中的至少一个：RS(544,514)编码模块(可不选)、分发和交织模块。
S1601.通信接口接收第一模块传输的数据流，并将该数据流输入至物理媒介附加(physical medium attachment,PMA)层，以获取N个物理编码子层(physical coding sublayer,PCS)数据流。
S1602.根据内部的对齐字标识(Alignment Marxer，AM)，将N个PCS数据流进行同步对齐。
S1603.对该对齐后的数据进行通道重排序、解交织，然后将处理后的数据输入至RS(544,514)解码器解码。
S1604.可选地，RS(544,514)解码后的数据保留校验码。
S1605.RS(544,514)保留校验码的数据送入BCH编码器进行级联编码处理。
S1606.RS+BCH级联码编码后的数据经过交织、信道编码、符号映射处理，生成待发送的信号。
S1607.可选地，将待发送的信号进行奈奎斯特(Nyquist)滤波后。
S1608.将滤波后的待发送信号送入发送器,并在调制后送往信道中传输。
图16的第二链路方向，第二模块可以对接收到的数据进行解码和编码之后，向第一模块发送。其具体流程如下所示，下述流程可以由第二模块内部的模块执行。
S1611.接收器从信道中接收信号，并对信号进行相干检测。
S1612.对相干检测得到的通信信号进行符号解映射、信道解码，解交织，以生成接收数据流。
S1613.接收的数据流经过BCH解码，得到第一次解码后的数据流。
S1614.第一次解码后的数据流去除BCH校验码，然后进行RS(544，514)的解码，得到第二次解码后的数据流。
S1615.可选地，第二次解码后的数据流保留RS(544,514)的校验码，无需RS(544,514)编码器对数据进行再次编码。
S1616.将保留校验码的RS(544,514)码形成的数据进行分发和交织以后发往通信接口进行数据传输。
作为一个具体示例，图17是又一实施例的编解码系统的示意图。该编解码系统包括处理模块、PMA模块和两个通信接口。该处理模块包括编码模块和解码模块。编码模块可以包括以下模块中的至少一个：编码和速率匹配模块、256B/257B转码编码模块、扰码模块、插入对齐字模块、Pre-FEC分发模块、RS+BCH级联编码模块、分发和速率变换模块。可选地，该解码模块可以包括以下模块中的至少一个：对齐字模块、重排序+解交织模块、RS+BCH级联解码模块、后-FEC(Post-FEC)解交织模块、对齐字去除模块、解扰码模块、256B/257B转码解码模块、解码和速率匹配模块。上述两个通信接口可以分别称为400GMII接口和400GAUI-X接口。当前400GE以太网中选用RS(544,514)作为FEC码字，下一代400GE以及未来的800GE和1.6TbE需要更高性能的FEC算法。图17的编解码方法可以应用于400GE、800GE、1.6TbE(即400G以太网、800G以太网、1.6Tb以太网)。
图17中的编码方法的数据处理的流程如下：
S1701.64B(B表示比特)数据块经过64B66B编码后生成66B码块。
S1702.4个66B码块经过256B257B转码编码器后生成257B码块。
S1703.257B码块流经过扰码模块进行扰码。
S1704.经过扰码后的257B码块流插入AM对齐字形成N个PCS通道数据流。
S1705.N个PCS通道流经过Pre-FEC分发模块分发到M个RS+BCH编码器中进行级联编码。20个257B码块共5140B形成码字的数据部分。编码后形成N个FEC数据流。
S1706.FEC数据流经过分发和速率变换后发往通信接口进行传输。
图17中的解码方法的数据处理的流程如下：
S1711.400GAUI-X接口输入数据流经过PMA层后变成N个PCS比特流。
S1712.根据内部的AM对齐字对N个PCS比特流进行同步对齐。
S1713.对齐后的数据经过通道重排序、解交织后送入M个RS+BCH解码器解码。解码后形成N个FEC数据流。
S1714.N个FEC数据流经过Post-FEC解交织模块进行解交织恢复成N个PCS数据流。
S1715.N个PCS数据流去除AM对齐字后解扰，生成257B数据块流。
S1716.257B数据块流经过256B257B转码解码器恢复成4个66B数据块。
S1717.66B数据块经过64B66B解码后生成64B数据块。
图18是本申请又一实施例的编解码系统的示意图。图18的编解码系统可以应用于背板链路中。该编解码系统包括媒体介入控制层(Media Access Control,MAC)模块和物理介质关联层(Physical Media Dependent,PMD)模块，该编解码系统包括以下模块中的至少一个：64B66B编码和速率匹配模块、256B/257B转码编码模块、扰码模块、对齐字模块、Pre-FEC分发模块、RS+BCH级联编码模块、交织模块。可选地，该编解码系统还可以包括以下模块中的至少一个：对齐字模块、解交织模块、RS+BCH级联解码模块、Post-FEC解交织模块、对齐字去除模块、解扰码模块、转码解码模块、64B66B解码和速率匹配模块。
在图18中，编码方法的处理流程如下：
S1801.MAC输入的64B数据块流经过64B66B编码模块编码后生成66B数据块。
S1802.4个66B数据块经过256B/257B转码编码模块编码生成257B数据块。
S1803.257B数据块流经过扰码模块后生成扰码后的257B数据块流。
S1804.可选地，扰码后的257B数据块流进行同步对齐。
S1805.可选地，257B数据块流进行码字交织分散到M个RS+BCH编码器中，M>＝1。
S1806.M个RS+BCH编码器对20个257B数据块组成的大数据块进行编码。
S1807.可选地，编码后的数据分发到N个数据通道(PMD)中传输，N>＝1。
在图18中，解码方法的处理流程如下：
S1811.通过N个数据通道(PMD)中接收数据，对数据进行通道对齐N>＝1。该步骤在N>1时必选，N＝1时可选。
S1812.对对齐后的N个数据通道执行解交织，然后将数据送入M个RS+BCH解码器进行解码。该步骤在N>1时必选，N＝1时可选。
S1813.对经过M个RS+BCH解码器解码后的数据进行Post-FEC解交织，生成N个数据通道。该步骤在N>1时必选，N＝1时可选。
S1814.对N个数据通道进行去除AM对齐字。该步骤在N>1时必选，N＝1时可选。
S1815.对去除AM对齐字后的N个数据通道进行解扰恢复，得到257B数据块流。
S1816.对257B数据块流经过256B/257B解码模块恢复成4个66B数据块流。
S1817.将66B数据块流输入至64B66B解码模块，以恢复成64B数据块，并发往MAC模块。
下文结合附图，介绍本申请实施例的编解码装置。
图19是本申请实施例的编码装置的示意性框图。图19的编码装置1900包括：确定单元1910和处理单元1920，
所述确定单元1910用于确定待编码数据的外码的帧，所述外码的帧包括数据信息码和所述数据信息码的校验码，所述外码的帧被划分为Q个数据块，所述Q个数据块中的每个数据块包括W个比特，其中，W、Q分别为大于零的整数；
所述处理单元1920用于对所述Q个数据块进行编码，以获取内码的Q个码字，其中，所述Q个数据块与所述内码的Q个码字一一对应，所述内码的Q个码字中的第一码字包括第一数据块和所述第一数据块的校验码，所述第一码字为所述内码的Q个码字中的任意 一个码字，所述第一数据块为所述第一码字对应的数据块。
图20是本申请实施例的解码装置2000的示意性结构图。图20的解码装置包括：获取单元2010和处理单元2020，
所述获取单元2010用于获取待解码数据的内码的Q个码字，所述内码的Q个码字与外码的帧包括的Q个数据块一一对应，所述内码的Q个码字中的第一码字包括第一数据块和所述第一数据块的校验码，所述第一码字为所述内码的Q个码字中的任意一个码字，所述第一数据块为所述第一码字对应的数据块；
所述处理单元2020用于对所述内码的Q个码字进行解码，以获取所述外码的帧，其中，所述外码的帧被划分为所述Q个数据块，所述Q个数据块中的每个数据块包括W个比特，W、Q分别为大于零的整数；以及对所述外码的帧进行解码，以获取解码后的数据。
图21是本发明实施例的编码装置2100的示意性框图。应理解，编码装置2100能够执行上文所述的编码方法的各个步骤，为了避免重复，此处不再详述。编码装置2100包括：
存储器2110，用于存储程序；
通信接口2120，用于和其他设备进行通信；
处理器2130，用于执行存储器2110中的程序，当所述程序被执行时，所述处理器2130用于确定待编码数据的外码的帧，所述外码的帧包括数据信息码和所述数据信息码的校验码，所述外码的帧被划分为Q个数据块，所述Q个数据块中的每个数据块包括W个比特，其中，W、Q分别为大于零的整数；所述处理器2130还用于对所述Q个数据块进行编码，以获取内码的Q个码字，其中，所述Q个数据块与所述内码的Q个码字一一对应，所述内码的Q个码字中的第一码字包括第一数据块和所述第一数据块的校验码，所述第一码字为所述内码的Q个码字中的任意一个码字，所述第一数据块为所述第一码字对应的数据块。
图22是本发明实施例的解码装置2200的示意性框图。应理解，解码装置2200能够执行上文所述的解码方法的各个步骤，为了避免重复，此处不再详述。解码装置2200包括：
存储器2210，用于存储程序；
通信接口2220，用于和其他设备进行通信；
处理器2230，用于执行存储器2210中的程序，当所述程序被执行时，所述处理器2230用于获取待解码数据的内码的Q个码字，所述内码的Q个码字与外码的帧包括的Q个数据块一一对应，所述内码的Q个码字中的第一码字包括第一数据块和所述第一数据块的校验码，所述第一码字为所述内码的Q个码字中的任意一个码字，所述第一数据块为所述第一码字对应的数据块；以及用于对所述内码的Q个码字进行解码，以获取所述外码的帧，其中，所述外码的帧被划分为所述Q个数据块，所述Q个数据块中的每个数据块包括W个比特，W、Q分别为大于零的整数；以及对所述外码的帧进行解码，以获取解码后的数据。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可 以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (34)

  1. 一种编码方法，其特征在于，包括：
    确定待编码数据的外码的帧，所述外码的帧包括数据信息码和所述数据信息码的校验码，所述外码的帧被划分为Q个数据块，所述Q个数据块中的每个数据块包括W个比特，其中，W、Q分别为大于零的整数；
    对所述Q个数据块进行编码，以获取内码的Q个码字，其中，所述Q个数据块与所述内码的Q个码字一一对应，所述内码的Q个码字中的第一码字包括第一数据块和所述第一数据块的校验码，所述第一码字为所述内码的Q个码字中的任意一个码字，所述第一数据块为所述第一码字对应的数据块。
  2. 如权利要求1所述的方法，其特征在于，所述方法还包括：
    在所述内码的Q个码字中的每个帧中添加至少一个空白比特，所述至少一个空白比特用于调整编码的码字速率。
  3. 如权利要求1或2所述的方法，其特征在于，所述方法还包括：基于所述内码的Q个码字进行预编码，以得到预编码后的数据。
  4. 如权利要求1至3中任一项所述的方法，其特征在于，所述确定待编码数据的外码的帧，包括：
    获取待编码数据；
    对所述待编码数据进行编码，以获取所述外码的帧。
  5. 如权利要求1至4中任一项所述的方法，其特征在于，所述外码为里德所罗门RS码。
  6. 如权利要求5所述的方法，其特征在于，所述外码的帧包括Y个RS码的码字，且Y*N*M＝Q*W，N为RS码的码字符号数量，K为RS(N,K)码的信息符号数量，M为RS码的每个码字符号包括的比特数量，Y、M、N分别为大于零的整数。
  7. 如权利要求6所述的方法，其特征在于，N＝544,K＝514；或，N＝528,K＝514；或，N＝271，K＝257。
  8. 如权利要求1至7中任一项所述的方法，其特征在于，所述内码包括以下任意一种：RS码、BCH码和卷积码。
  9. 如权利要求1至8中任一项所述的方法，其特征在于，W的取值为以下数值中的任一项：160、320、480和640。
  10. 一种解码方法，其特征在于，包括：
    获取待解码数据的内码的Q个码字，所述内码的Q个码字与外码的帧包括的Q个数据块一一对应，所述内码的Q个码字中的第一码字包括第一数据块和所述第一数据块的校验码，所述第一码字为所述内码的Q个码字中的任意一个码字，所述第一数据块为所述第一码字对应的数据块；
    对所述内码的Q个码字进行解码，以获取所述外码的帧，其中，所述外码的帧被划分为所述Q个数据块，所述Q个数据块中的每个数据块包括W个比特，W、Q分别为大于零的整数；
    对所述外码的帧进行解码，以获取解码后的数据。
  11. 如权利要求10所述的方法，其特征在于，所述内码的Q个码字中还包括至少一个空白比特，所述至少一个空白比特用于调整编码的码字速率。
  12. 如权利要求10或11所述的方法，其特征在于，在所述获取所述待解码数据的内码的Q个码字之前，所述方法还包括：
    获取待解码数据；
    对所述待解码数据进行预编码的解码处理，以获取所述内码的Q个码字。
  13. 如权利要求10至12中任一项所述的方法，其特征在于，所述外码为里德所罗门RS码。
  14. 如权利要求13所述的方法，其特征在于，所述外码的帧包括Y个RS码的码字，且Y*N*M＝Q*W，其中，N为RS码的每个码字包括的码字符号数量，M为RS码的每个码字符号包括的比特数量，Y、M、N分别为大于零的整数。
  15. 如权利要求14所述的方法，其特征在于，N＝544,K＝514；或，N＝528,K＝514；或，N＝271，K＝257。
  16. 如权利要求10至15中任一项所述的方法，其特征在于，所述内码包括以下任意一种：RS码、BCH码和卷积码。
  17. 如权利要求10至16中任一项所述的方法，其特征在于，W的取值为以下数值中的任一项：160、320、480和640。
  18. 一种编码装置，其特征在于，包括：确定单元和处理单元，
    所述确定单元用于确定待编码数据的外码的帧，所述外码的帧包括数据信息码和所述数据信息码的校验码，所述外码的帧被划分为Q个数据块，所述Q个数据块中的每个数据块包括W个比特，其中，W、Q分别为大于零的整数；
    所述处理单元用于对所述Q个数据块进行编码，以获取内码的Q个码字，其中，所述Q个数据块与所述内码的Q个码字一一对应，所述内码的Q个码字中的第一码字包括第一数据块和所述第一数据块的校验码，所述第一码字为所述内码的Q个码字中的任意一个码字，所述第一数据块为所述第一码字对应的数据块。
  19. 如权利要求18所述的装置，其特征在于，所述处理单元还用于在所述内码的Q个码字中的每个帧中添加至少一个空白比特，所述至少一个空白比特用于调整编码的码字速率。
  20. 如权利要求18或19所述的装置，其特征在于，所述处理单元还用于基于所述内码的Q个码字进行预编码，以得到预编码后的数据。
  21. 如权利要求18至20中任一项所述的装置，其特征在于，在所述确定待编码数据的外码的帧方面，所述确定单元具体用于获取待编码数据；以及对所述待编码数据进行编码，以获取所述外码的帧。
  22. 如权利要求18至21中任一项所述的装置，其特征在于，所述外码为里德所罗门RS码。
  23. 如权利要求22所述的装置，其特征在于，所述外码的帧包括Y个RS码的码字，且Y*N*M＝Q*W，N为RS码的码字符号数量，K为RS(N,K)码的信息符号数量，M为RS码的每个码字符号包括的比特数量，Y、M、N分别为大于零的整数。
  24. 如权利要求23所述的装置，其特征在于，N＝544,K＝514；或，N＝528,K＝514；或，N＝271，K＝257。
  25. 如权利要求18至24中任一项所述的装置，其特征在于，所述内码包括以下任意一种：RS码、BCH码和卷积码。
  26. 如权利要求18至25中任一项所述的装置，其特征在于，W的取值为以下数值中的任一项：160、320、480和640。
  27. 一种解码装置，其特征在于，包括：获取单元和处理单元，
    所述获取单元用于获取待解码数据的内码的Q个码字，所述内码的Q个码字与外码的帧包括的Q个数据块一一对应，所述内码的Q个码字中的第一码字包括第一数据块和所述第一数据块的校验码，所述第一码字为所述内码的Q个码字中的任意一个码字，所述第一数据块为所述第一码字对应的数据块；
    所述处理单元用于对所述内码的Q个码字进行解码，以获取所述外码的帧，其中，所述外码的帧被划分为所述Q个数据块，所述Q个数据块中的每个数据块包括W个比特，W、Q分别为大于零的整数；以及对所述外码的帧进行解码，以获取解码后的数据。
  28. 如权利要求27所述的装置，其特征在于，所述内码的Q个码字中还包括至少一个空白比特，所述至少一个空白比特用于调整编码的码字速率。
  29. 如权利要求27或28所述的装置，其特征在于，在所述获取所述待解码数据的内码的Q个码字之前，所述获取单元还用于获取待解码数据；以及对所述待解码数据进行预编码的解码处理，以获取所述内码的Q个码字。
  30. 如权利要求27至29中任一项所述的装置，其特征在于，所述外码为里德所罗门RS码。
  31. 如权利要求30所述的装置，其特征在于，所述外码的帧包括Y个RS码的码字，且Y*N*M＝Q*W，其中，N为RS码的每个码字包括的码字符号数量，M为RS码的每个码字符号包括的比特数量，Y、M、N分别为大于零的整数。
  32. 如权利要求31所述的装置，其特征在于，N＝544,K＝514；或，N＝528,K＝514；或，N＝271，K＝257。
  33. 如权利要求27至32中任一项所述的装置，其特征在于，所述内码包括以下任意一种：RS码、BCH码和卷积码。
  34. 如权利要求27至33中任一项所述的装置，其特征在于，W的取值为以下数值中的任一项：160、320、480和640。
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