WO2018176934A1 - 一种数据流控方法及装置 - Google Patents

一种数据流控方法及装置 Download PDF

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Publication number
WO2018176934A1
WO2018176934A1 PCT/CN2017/117513 CN2017117513W WO2018176934A1 WO 2018176934 A1 WO2018176934 A1 WO 2018176934A1 CN 2017117513 W CN2017117513 W CN 2017117513W WO 2018176934 A1 WO2018176934 A1 WO 2018176934A1
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WIPO (PCT)
Prior art keywords
tmds
buffer
clock signal
characters
character
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PCT/CN2017/117513
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English (en)
French (fr)
Inventor
张波
Original Assignee
华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP17904245.2A priority Critical patent/EP3595321A1/en
Publication of WO2018176934A1 publication Critical patent/WO2018176934A1/zh
Priority to US16/585,889 priority patent/US11082739B2/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
    • H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
    • H04N21/238—Interfacing the downstream path of the transmission network, e.g. adapting the transmission rate of a video stream to network bandwidth; Processing of multiplex streams
    • H04N21/2389—Multiplex stream processing, e.g. multiplex stream encrypting
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/436—Interfacing a local distribution network, e.g. communicating with another STB or one or more peripheral devices inside the home
    • H04N21/4363—Adapting the video or multiplex stream to a specific local network, e.g. a IEEE 1394 or Bluetooth® network
    • H04N21/43632—Adapting the video or multiplex stream to a specific local network, e.g. a IEEE 1394 or Bluetooth® network involving a wired protocol, e.g. IEEE 1394
    • H04N21/43635—HDMI
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G06F5/12—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
    • G06F5/14—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations for overflow or underflow handling, e.g. full or empty flags
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/434—Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream
    • H04N21/4342—Demultiplexing isochronously with video sync, e.g. according to bit-parallel or bit-serial interface formats, as SDI
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/438—Interfacing the downstream path of the transmission network originating from a server, e.g. retrieving MPEG packets from an IP network
    • H04N21/4385—Multiplex stream processing, e.g. multiplex stream decrypting
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream, rendering scenes according to MPEG-4 scene graphs
    • H04N21/44004—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream, rendering scenes according to MPEG-4 scene graphs involving video buffer management, e.g. video decoder buffer or video display buffer
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/12—Use of DVI or HDMI protocol in interfaces along the display data pipeline

Definitions

  • the present application relates to the field of communications technologies, and in particular, to a data flow control method and apparatus.
  • High Definition Multimedia Interface is a digital video/audio interface technology, a dedicated digital interface for image transmission, which can simultaneously transmit audio and video signals in the existing public HDMI standard protocol 2.0.
  • video display data, display control signals, audio data, and the like are converted into Transition Minimized Differential Signaling (TMDS) characters for transmission in an HDMI cable.
  • TMDS Transition Minimized Differential Signaling
  • the HDMI standard version 2.1 has a fixed rate link (FRL) transmission mode compared to the original version 2.0, which is used to support the higher display data transmission rate of the 2.1 version compared to the 2.0 version, thereby supporting more.
  • FRL fixed rate link
  • GAP null packet
  • the related art in order to perform rate matching of TMDS characters, the related art has proposed to set a buffer in the FRL transmission mode, which can be used to store TMDS characters input into the FRL; then according to the FRL link The clock cycle, the TMDS character in the output buffer or the GAP packet is transmitted to the FRL link.
  • the storage capacity of the buffer in the FRL is limited, if the clock signal in the FRL arrives.
  • the buffer may overflow.
  • the overflow means that the number of input TMDS characters exceeds the storage capacity of the buffer.
  • the clock signal arrives, continuously output the TMDS character in the buffer to the FRL transmission channel. Since the rate of inputting the TMDS character in the FRL is smaller than the transmission rate of the TMDS character required by the FRL, the buffer may be caused at this time.
  • Underflow the underflow means that when the entire buffer has no TMDS characters, it is also required to output the TMDS characters from the buffer; and the overflow and underflow of the buffer will destroy the display timing inherent to the original TMDS characters.
  • the present application provides a data flow control method and apparatus such that a buffer in an FRL neither overflows nor underflows, and the display timing inherent to the TMDS character is guaranteed.
  • the present application provides a data flow control method, including: when a clock signal arrives, calculating, by a device, a quantity of a currently stored minimized transmission differential signal TMDS character in a buffer of the device, where a clock signal period is Set according to a rate at which the fixed rate link FRL transmits the TMDS character; the device outputs the TMDS character in the buffer when the number of currently stored TMDS characters in the buffer reaches a preset value; otherwise, the output is empty a data packet; wherein the preset value is less than or equal to a capacity of the buffer to store a TMDS character.
  • the device calculates, when the clock signal arrives, the number of currently stored TMDS characters in the buffer of the device, including: the device acquires when the clock signal arrives a first total number of TMDS characters currently input into the buffer and a second total number of TMDS characters currently output from the buffer; the device to the first total number and the second total number The difference, as the number of TMDS characters currently stored by the buffer.
  • the device outputs the TMDS in the buffer when the number of currently stored TMDS characters in the buffer reaches a preset value Characters, including:
  • the device outputs a TMDS character stored in the buffer when the number of currently stored TMDS characters in the buffer reaches the preset value.
  • the buffer can theoretically store only one TMDS character.
  • the buffer capacity can be designed to be small, the buffer requirement is low, and the implementation is easy.
  • the clock signal is a first clock signal; the device currently stores the number of TMDS characters in the buffer to a preset value. Outputting the TMDS character in the buffer, the device outputting a TMDS character stored in the buffer when the number of currently stored TMDS characters in the buffer reaches a preset value; Outputting, when the second clock signal to the first clock signal subsequent to the first clock signal arrives, a TMDS character stored in the buffer; wherein the I is greater than or equal to 2, less than or equal to M, the M For the number of TMDS characters currently stored in the buffer, the I and M are integers.
  • the device calculates, when the clock signal arrives, the number of currently stored TMDS characters in the buffer of the device, including: the device acquires when the clock signal arrives a third total number and a fourth total number of TMDS characters input to the buffer, the third total number being input to the buffer in the last TMDS character stored by the buffer a total number of characters, the fourth total number being the total number of TMDS characters input to the buffer at a current time; the device as the difference between the fourth total number and the third total number
  • the buffer currently stores the number of TMDS characters.
  • the clock signal is a first clock signal
  • the buffer currently stores the number of TMDS characters as M
  • the M is an integer
  • the device Outputting the TMDS character in the buffer when the number of currently stored TMDS characters in the buffer reaches a preset value, comprising: the device outputting the buffer when the M reaches the preset value a stored TMDS character; the device outputs a TMDS character stored in the buffer when the second clock signal to the Mth clock signal subsequent to the first clock signal arrive.
  • a data flow control apparatus including: a buffer unit configured to store a minimized transmission differential signal TMDS character; and a calculation unit configured to calculate a current storage TMDS character in the buffer unit when the clock signal arrives a quantity; the period of the clock signal is set according to a rate at which the TMDS character is transmitted according to the fixed rate link FRL; and an output unit, when the number of currently stored TMDS characters in the buffer unit reaches a preset value, outputting the The TMDS character in the buffer unit; otherwise, the null data packet is output; the preset value is less than or equal to the capacity of the buffer unit to store the TMDS character.
  • the calculating unit is specifically configured to: when the clock signal arrives, acquire a first total number of TMDS characters currently input into the buffer unit and currently from the The second total number of TMDS characters is outputted in the buffer unit; the difference between the first total number and the second total number is used as the number of TMDS characters currently stored by the buffer unit.
  • the output unit is specifically configured to: when the number of currently stored TMDS characters in the buffer unit reaches the preset value, A TMDS character stored by the buffer unit is output.
  • the clock signal is a first clock signal
  • the output unit is specifically configured to: currently store a TMDS character in the buffer unit Outputting a TMDS character stored in the buffer unit when the number reaches a preset value; and outputting the buffer unit to store when the second clock signal to the first clock signal subsequent to the first clock signal arrives A TMDS character; wherein, the I is greater than or equal to 2, less than or equal to M, and the M is the number of currently stored TMDS characters in the buffer unit, and the I and M are integers.
  • the calculating unit is specifically configured to: when the clock signal arrives, acquire a third total quantity and a fourth total quantity of the TMDS characters input into the buffer unit,
  • the third total number is the total number of TMDS characters input to the buffer unit when the buffer unit last outputs the last stored TMDS character, and the fourth total number is input to the buffer unit at the current time.
  • the total number of TMDS characters; the difference between the fourth total number and the third total number is used as the number of TMDS characters currently stored by the buffer unit.
  • the clock signal is a first clock signal
  • the buffer unit currently stores the number of TMDS characters as M, and the M is an integer
  • the output unit Specifically for:
  • the present application provides a data flow control device including a processor, a memory, and a communication interface; the processor, the memory, and the communication interface are each connected by a bus; the memory is configured to store a computer execution instruction; a processor, the computer-executable instructions for executing the memory storage to perform calculating, when a clock signal arrives, a quantity of a currently stored minimized transmission differential signal TMDS character in a buffer of the device and present in the buffer When the number of stored TMDS characters reaches a preset value, the TMDS character in the buffer is output, otherwise the empty data packet is output; wherein the preset value is less than or equal to the capacity of the buffer to store the TMDS character.
  • the processor calculates, when the clock signal arrives, the number of currently stored TMDS characters in the buffer of the device, including: acquiring the current input when the clock signal arrives a first total number of TMDS characters in the buffer and a second total number of TMDS characters currently output from the buffer; a difference between the first total number and the second total number as a The buffer currently stores the number of TMDS characters.
  • the processor outputs the buffer in the buffer when the number of currently stored TMDS characters in the buffer reaches a preset value.
  • the TMDS character is specifically used to output a TMDS character stored in the buffer when the number of currently stored TMDS characters in the buffer reaches the preset value.
  • the processor outputs the buffer in the buffer when the number of currently stored TMDS characters in the buffer reaches a preset value.
  • the TMDS character includes: outputting a TMDS character stored in the buffer when the number of currently stored TMDS characters in the buffer reaches the preset value.
  • the processor when the clock signal arrives, calculates the number of currently stored TMDS characters in the buffer of the device, including: acquiring the input when the clock signal arrives a third total number and a fourth total number of TMDS characters in the buffer, the third total number being the TMDS character input to the buffer when the buffer last output the last stored TMDS character
  • the total number of the fourth total number is the total number of TMDS characters input to the buffer at the current time; the difference between the fourth total number and the third total number is used as the current buffer Stores the number of TMDS characters.
  • the clock signal is a first clock signal
  • the processor outputs when the number of currently stored TMDS characters in the buffer reaches a preset value.
  • the TMDS character in the buffer is specifically configured to: when the number of currently stored TMDS characters in the buffer reaches a preset value, output a TMDS character stored in the buffer; at the first clock And outputting, by the second clock signal to the first clock signal, a TMDS character stored in the buffer, wherein the I is greater than or equal to 2, less than or equal to M, and the M is in the buffer.
  • the number of TMDS characters currently stored, and both I and M are integers.
  • the present application further provides a data flow control device, including a buffer, a TMDS character counter, a controller, a data selector, and an empty packet generator; wherein the buffer is configured to store a minimized transmission difference a TMDS character; the TMDS character counter for recording the number of TMDS characters input or/and outputting the buffer, and transmitting the recorded number of TMDS characters to the controller; the controller for clocking When the signal arrives, calculating the number of currently stored TMDS characters in the buffer according to the number of TMDS characters recorded by the TMDS character counter, and transmitting the first when the number of currently stored TMDS characters in the buffer reaches a preset value Controlling a signal to the data selector, otherwise transmitting a second control signal to the data selector; the period of the clock signal being set according to a rate at which a fixed rate link FRL transmits a TMDS character; the data selector And for outputting a TMDS character in the buffer when receiving the first control signal of the
  • the TMDS character counter includes: an input TMDS character counter and an output TMDS character counter; the controller calculates a current storage TMDS in the buffer when a clock signal arrives When the number of characters is used, the controller is configured to: when the clock signal arrives, acquire a first count value recorded by the current input TMDS character counter and a second count value recorded by the output TMDS character counter; The first count value is used to indicate the number of TMDS characters input to the buffer currently recorded by the input TMDS character counter, and the second count value is used to indicate the output of the current output TMDS character counter record. The number of TMDS characters; the controller uses the difference between the first count value and the second count value as the number of TMDS characters currently stored by the buffer.
  • the data selector when the data selector receives the first control signal of the controller and outputs the TMDS character in the buffer, Specifically, the data selector outputs a TMDS character in the buffer when receiving the first control signal of the controller.
  • the clock signal is a first clock signal
  • the controller is currently stored in the buffer
  • sending the first control signal to the data selector includes: the controller sending the first control when the number of currently stored TMDS characters in the buffer reaches a preset value Signaling to the data selector; the controller respectively transmitting a first control signal to the data selector when the subsequent second clock signal to the first clock signal of the first clock signal arrive, the I being greater than or equal to 2 Is less than or equal to M, and the M is the number of currently stored TMDS characters in the buffer.
  • the TMDS character counter includes an input TMDS character counter; when the controller arrives, the controller calculates the number of currently stored TMDS characters in the buffer, specifically For: the controller acquires a third count value and a fourth count value recorded by the input TMDS character counter when a clock signal arrives; wherein the third count value is used to indicate that the buffer is last output The last TMDS character stored, the input TMDS character counter records the number of TMDS characters input to the buffer, and the fourth count value is used to indicate that the input of the input TMDS character counter is input to the buffer The number of TMDS characters; the controller uses the difference between the fourth count value and the third count value as the number of TMDS characters currently stored by the buffer.
  • the clock signal is a first clock signal
  • the buffer currently stores the number of TMDS characters as M
  • the M is an integer
  • the controller Sending the first control signal to the data selector when the number of currently stored TMDS characters in the buffer reaches a preset value, comprising: the controller currently storing the number of TMDS characters in the buffer to reach a preset When the value is set, the first control signal is sent to the data selector; the controller sends the first control signal to the data selection when the second clock signal to the Mth clock signal subsequent to the first clock signal arrive Device.
  • the present application further provides a readable storage medium for storing software instructions for performing the functions of any of the above first aspect and the first aspect of the present invention, which are included for performing the present invention.
  • the program designed by the method of any of the above aspects, the first aspect, or any one of the first aspects.
  • FIG. 1 is a schematic diagram of an FRL data packet provided by the present application.
  • FIG. 2 is a schematic diagram of a transmission mode provided by the HDMI standard protocol version 2.1 provided by the present application;
  • 3a-3c are schematic diagrams showing the logical structure of a data flow control device provided by the present application.
  • FIG. 4 is a schematic diagram of a processing flow of a TMDS character type detector provided by the present application.
  • FIG. 5 is a schematic flowchart of a data flow control method provided by the present application.
  • FIG. 6 is another schematic flowchart of a data flow control method provided by the present application.
  • FIG. 7 is still another schematic flowchart of a data flow control method provided by the present application.
  • FIG. 8 is a schematic structural diagram of a data flow control apparatus provided by the present application.
  • FIG. 9 is another schematic structural diagram of a data flow control device provided by the present application.
  • High Definition Multimedia Interface A digital video/audio interface technology that is a dedicated digital interface suitable for image transmission. It can transmit audio and video signals simultaneously and can be used between various terminals. Transmitting video/audio signals, such as transmitting video/audio signals between a set-top box and a television, and transmitting video/audio signals between a television and a computer.
  • TMDS Transition Minimized Differential Signaling
  • FTL Fixed Rate Link
  • FRL data packet a data packet transmitted in an FRL transmission channel, the format of the FRL data packet, as shown in FIG. 1, one FRL data packet is composed of a plurality of FRL characters, wherein each FRL character occupies 16 bits
  • the upper 6 bits of the first FRL character of the FRL packet indicate the type of the entire FRL character, and the lower 6 bits indicate the length of the entire FRL character, and all the FRL characters from the second FRL character to the latter are used for carrying TMDS characters, and one FRL character can carry at least 2 TMDS characters, each TMDS character occupies 8 bits; usually the same type of TMDS characters are packaged in the same FRL data packet.
  • GAP Packet In the HDMI Standard Protocol version 2.1, a proposed FRL packet for rate matching;
  • Buffer It is mainly divided into input buffer and output buffer.
  • the function of the input buffer is to temporarily store the data sent by the peripheral, so that the processor can take it away.
  • the output buffer is used to temporarily store the processor.
  • Data to peripherals; the buffers utilized in this application are primarily input buffers.
  • Data selector (multiplexer, MUX): In the process of multi-channel data transmission, one of the circuits can be selected as needed; common specifications are 4 select 1MUX, 8 select 1MUX, and 16 select 1MUX; this application applies 2 Select 1 data selector, that is, from 2 channels of input data, select 1 channel for output.
  • the transmission mode specified in the 2.1 version of the HDMI standard protocol is first introduced.
  • the transmission mode can be used as an application scenario of the present application, but should not be used as the application.
  • a video signal, an audio signal, and a display control signal are first input to a TMDS character generation module, and the TMDS character generation module can input an input video signal, an audio signal, and a display.
  • the control signal is converted into a TMDS character, and then the TMDS character is input to the encryption module for encryption; finally, the encrypted TMDS character is divided into two paths, one input to the TMDS transmission link and the other input to the FRL transmission link;
  • TMDS transmission link the input encrypted TMDS character will be transmitted to the TMDS transmission channel after being subjected to the scrambling coding module;
  • FRL transmission link the input encrypted TMDS character is transmitted to the FRL transmission channel for transmission after the data flow control module, the FRL packaging module, the FRL data packet to the character block mapping module, and the scrambling coding module, wherein FRL is transmitted.
  • the transmission channel is usually 3 channels or 4 channels.
  • the TMDS transmission link is compatible with the HDMI standard protocol version 2.0
  • the FRL transmission link is a newly proposed transmission link of the HDMI standard protocol version 2.1, and the rate at which the TMDS character is transmitted will be greater than the input of the TMDS character in the link.
  • the rate so for rate matching, a data flow control module is added between the cryptographic module and the FRL packaging module.
  • the application scenario shown in FIG. 2 is only used as an application scenario of the present application. In practical applications, the application has other application scenarios. For example, a scenario may be used, and the scenario shown in FIG. 2 may be used.
  • the TMDS characters generated by the TMDS character generation module are directly input into the TMDS transmission link and the FRL transmission link in two ways, and are no longer processed by the encryption module.
  • the present application provides a data flow control method and apparatus.
  • the solution of the present application will be described in detail by way of embodiments. For the sake of clarity, the following table lists various embodiments of the present application and corresponding Figure.
  • the present application provides a data flow control device, which may be a chip in an actual application, and the device shown in FIG. 3a mainly implements the functions of the data flow control module shown in FIG. 2, and mainly includes: TMDS.
  • the character type detector 31, the buffer 32, the TMDS character counter 33, the controller 34, the MUX 35, and the GAP packet generator 36 are composed.
  • the TMDS character type detector 31 is mainly used for detecting the type of the TMDS character input into the FRL link.
  • the type of the TMDS character mainly includes the video data type of the blanking area and the valid video data type.
  • the TMDS character type detection mainly includes The TMDS character input to the FRL link is detected as a blanking area video data type or a valid video data type; in the present application, the TMDS character type detection may mark the blanking area video data type as Type 2 and will be valid.
  • Video data type labeled Type3.
  • Buffer32 is mainly used to store TMDS characters; the capacity of buffer storage TMDS characters is usually represented by depth d; for example, buffer can store up to 10 TMDS characters, then the depth of the buffer is 10.
  • a TMDS character counter 33 for recording the number of TMDS characters in the input or/and output buffer 32, and transmitting the recorded number of TMDS characters to the controller 34;
  • the TMDS character counter 33 can input one TMDS character, the count value is increased by 1, and each of the two TMDS characters can be input, and the count value is incremented by one.
  • the user can set it according to the requirement.
  • the controller 34 is mainly used to calculate the number of currently stored TMDS characters in the buffer 32 according to the number of TMDS characters recorded by the TMDS character counter 33 when the clock signal arrives, and the number of currently stored TMDS characters in the buffer 32 reaches the preset
  • the first control signal is sent to the MUX 35, otherwise, the second control signal is sent to the MUX 35;
  • the period of the clock signal is set according to the rate at which the fixed rate link FRL transmits the TMDS character; for example, the HDML standard protocol 2.1
  • the version specifies that 8 TMDS characters are transmitted per second in the FRL transmission link.
  • the clock control signal can be specific. Generated by the central processing unit of the entire transmission device, the entire transmission terminal may be specifically a terminal that performs video/audio transmission, for example, to transmit video, audio and video, and display control signals from the set top box to the television,
  • the entire transmission terminal can be specifically a set top box, and the HDML interface is used between the set top box and the television to transmit data, then the set top box can
  • the video, audio and display control signals received through the cable television network are finally divided into two transmission links, TMDS and FRL, into the television through the processing shown in FIG. 2; and the output clock cycle of the FRL link can be specifically determined by The central processor of the set top box is produced.
  • the MUX 35 is configured to output a TMDS character in the buffer 32 when receiving the first control signal of the controller 34, or output the GAP data packet when receiving the second control signal of the controller 34.
  • the MUX 35 when the controller 34 issues the selection signal 1, the MUX 35 outputs a TMDS character from the buffer 32 to the FRL packing module, and when the controller 34 issues the selection signal 0, the MUX 35 outputs a GAP packet from the GAP packet generator 36.
  • the FRL packaging module To the FRL packaging module;
  • a GAP data packet generator 36 configured to generate a GAP data packet
  • the TMDS character type detector 31 is further configured to output the type Type of the TMDS word class to the FRL packaging module, and the FRL packaging module will package the output TMDS character according to the Type and L of the TMDS character, and finally package the TMDS character into the FRL data.
  • the package, the format of the FRL data packet can be specifically seen in Figure 1.
  • TMDS character generated by the TMDS character generation module in FIG. 2 can be directly input into the FRL link, or the encrypted TMDS character can be input into the FRL link after passing through the encryption module shown in FIG. 2,
  • Figure 3a is only an example of the present application and is not intended to limit the application;
  • the controller 34 whenever the clock signal of the FRL link arrives, the controller 34 outputs a TMDS character or a GAP packet to the FRL packaging module, which satisfies the requirement of the FRL link transmission rate.
  • the TMDS character counter 33 in Figure 3a may specifically include an input TMDS character counter 331 and an output TMDS character counter 332;
  • the TMDS character type detector 31 is mainly used for detecting the type of the TMDS character input into the FRL link.
  • the type of the TMDS character mainly includes the blanking area video data type and the valid video data type, TMDS.
  • the character type detection mainly detects whether the TMDS character input into the FRL link is a blanking area video data type or a valid video data type; in the present application, the TMDS character type detection can mark the blanking area video data type as Type2, and the valid video data type, marked as Type3.
  • Buffer32 is mainly used to store TMDS characters; the capacity of buffer storage TMDS characters is usually represented by depth d; for example, buffer can store up to 10 TMDS characters, then the depth of the buffer is 10.
  • the TMDS character counter 331 is input, and is mainly used for recording the number of TMDS characters input into the buffer 32;
  • the controller 34 is configured to acquire, when the clock signal arrives, a first count value recorded by the current input TMDS character counter 331 and a second count value recorded by the output TMDS character counter 332; a count value for indicating the number of TMDS characters input to the buffer currently recorded by the input TMDS character counter, the second count value being used to indicate the TMDS of the output buffer of the current output TMDS character counter record
  • the number of characters, and the difference between the first count value and the second count value is used as the number of TMDS characters currently stored by the buffer.
  • the controller uses the difference between the first count value and the second count value as the number of TMDS characters currently stored by the buffer. And outputting the first control signal to the MUX 35 when the buffer currently stores the number of TMDS characters reaches a preset value, and otherwise outputs the second control signal to the MUX 35;
  • the MUX 35 is mainly configured to output a TMDS character in the buffer 32 when receiving the first control signal, and output an empty packet when receiving the second control signal.
  • the GAP data packet generator 36 is mainly used to generate a GAP data packet
  • the controller 34 calculates the number of currently stored TMDS characters in the current buffer 32 when the first clock signal arrives. For the calculation manner, refer to the foregoing; and then store the TMDS characters in the buffer 32.
  • the first control signal is sent to the MUX 35; and the MUX 35 outputs one TMDS character in the buffer 32; and the controller 34 arrives at the second clock signal to the first clock signal subsequent to the first clock signal.
  • the first control signal is directly sent to the MUX 35, and the step of calculating the buffer 32 storage capacity and determining whether the buffer 32 storage capacity reaches a preset value is not performed; the I is greater than or equal to 2, less than or equal to M, and the M is current in the buffer 32.
  • the number of TMDS characters is stored. For example, when the clock signal 1 arrives, the controller 34 calculates that the number of currently stored TMDS characters in the buffer 32 is 5; then, the controller 34 continues to determine whether the number of currently stored TMDS characters in the buffer 32 reaches The preset value is assumed to be 3, and it can be seen that the number of currently stored TMDS characters in buffer 32 has reached the preset value of 3, Then the controller 34 will send a first control signal to the MUX 35, and the MUX 35 will output a TMDS character in the buffer 32 upon receiving the first control signal; thereafter, the controller 34 arrives at a plurality of clock signals subsequent to the clock signal 1 The first control signal will be directly output to the MUX 35, and the MUX 35 will continue to output the TMDS character; of course, the size of the plurality of clock signal values subsequent to the clock signal 1 can be set by the user, but the value needs to be smaller than the current stored TMDS character in the buffer 32.
  • the TMDS character counter 33 in Figure 3a may specifically include an input TMDS character counter 333;
  • the TMDS character type detector 31 is mainly used for detecting the type of the TMDS character input into the FRL link.
  • the type of the TMDS character mainly includes the video data type of the blanking area and the valid video data type.
  • the TMDS character type detection mainly includes The TMDS character input to the FRL link is detected as a blanking area video data type or a valid video data type; in the present application, the TMDS character type detection may mark the blanking area video data type as Type 2 and will be valid.
  • Video data type labeled Type3.
  • Buffer32 is mainly used to store TMDS characters; the capacity of buffer storage TMDS characters is usually represented by depth d; for example, buffer can store up to 10 TMDS characters, then the depth of the buffer is 10.
  • the TMDS character counter 333 is input, and is mainly used for recording the number of TMDS characters input into the buffer 32;
  • the controller 34 is configured to acquire a third count value and a fourth count value recorded by the input TMDS character counter 333 when the clock signal arrives, where the third count value is used to indicate that the buffer 32 is last stored and stored.
  • the last TMDS character is input to the TMDS character counter 333 to record the number of TMDS characters input to the buffer, and the fourth count value is used to indicate the TMDS character input to the buffer currently recorded by the input TMDS character counter 333
  • the quantity, and the difference between the fourth count value and the third count value, as the number of TMDS characters currently stored by the buffer is configured to acquire a third count value and a fourth count value recorded by the input TMDS character counter 333 when the clock signal arrives, where the third count value is used to indicate that the buffer 32 is last stored and stored.
  • the last TMDS character is input to the TMDS character counter 333 to record the number of TMDS characters input to the buffer, and the fourth count value is used to indicate the TMDS character input to the buffer currently recorded by
  • the controller 34 calculates the number of TMDS characters in the buffer 32 when the first clock signal arrives, and the number of currently stored TMDS characters in the buffer 32 reaches a preset value.
  • the first control signal is sent to the MUX 35; and the controller 34 sends the first control signal to the MUX 35 when the second clock signal to the Mth clock signal subsequent to the first clock signal arrive.
  • the MUX 35 is mainly configured to output a TMDS character in the buffer 32 when receiving the first control signal, and output an empty packet when receiving the second control signal.
  • the GAP packet generator 36 is mainly used to generate GAP packets.
  • Step S41 analyzing the type of the currently input TMDS character
  • Step S42 determining whether the type of the currently input TMDS character is the same as the type of the last input TMDS character; if the same, step S43 is performed; otherwise, step S44 is performed;
  • Step S43 adding 3 to the value of the temporary variable tmp_L of the TMDS character length
  • each TMDS character occupies 3 bytes, so each time a TMDS character is input, the value of tmp_L is increased by 3;
  • Step S44 outputting the initialization length L0 of the TMDS character type Type and the TMDS character to the FRL packaging module;
  • the FRL character in each FRL packet occupies 2 TMDS characters. Therefore, when the initial length L0 of the FRL data is output, the length tmp_L of the TMDS is divided by 2 as The length of the FRL character in the FRL packet.
  • Step S45 The value of the temporary variable tmp_L of the TMDS character length is cleared.
  • controller 34 In the present application, the operation of the controller 34 in Fig. 3a, Fig. 3b or Fig. 3c will be described in detail, since the controller 34 outputs a TMDS character or a GAP empty packet from the buffer 32 whenever the output signal arrives. To the FRL packaging module; at the same time, the storage capacity of the entire buffer32 is limited.
  • the GAP empty packet is continuously output when the clock signal arrives, it may cause overflow of the buffer32, which means that the number of input TMDS characters exceeds The storage capacity of buffer32, resulting in the loss of TMDS characters; if the TMDS character is continuously output when the clock signal arrives, and the input rate of the TMDS character is smaller than the transmission rate of the TMDS character in the FRL link, it is possible It will cause underflow of buffer32.
  • the entire buffer32 has no TMDS characters, it also requires the output of TMDS characters from buffer32. The overflow and underflow of buffer32 will destroy the display timing inherent in the original TMDS characters.
  • the present application provides a data flow control method, which can ensure that the buffer 32 neither overflows nor underflows, and ensures the inherent display timing of the TMDS character, as shown in FIG. 5. As shown, the method is as follows:
  • Step S51 Calculate the number of currently stored TMDS characters in the buffer 32 when the clock signal arrives;
  • Step S52 output the TMDS character in the buffer when the number of currently stored TMDS characters in the buffer 32 reaches a preset value; otherwise, output a GAP data packet; the preset value is to store the TMDS according to the buffer.
  • the capacity of the character is set and the preset value is less than or equal to the capacity of the buffer to store the TMDS character.
  • the first total number of TMDS characters currently input into the buffer 32 and the second total number of TMDS characters currently output from the buffer are obtained; a difference between the total number and the second total number as the number of TMDS characters currently stored by the buffer; and when the number of currently stored TMDS characters in the buffer reaches a preset value, outputting the buffer A stored TMDS character.
  • the buffer when the first clock signal arrives, obtaining a first total number of TMDS characters currently input into the buffer 32 and a second total number of TMDS characters currently outputting from the buffer; a difference between the first total number and the second total number as the number of TMDS characters currently stored by the buffer; when the number of currently stored TMDS characters in the buffer reaches a preset value, the buffer is output a stored TMDS character; when the second clock signal to the first clock signal subsequent to the first clock signal arrives, respectively outputting one TMDS character stored in the buffer 32; wherein the I is greater than or equal to 2, less than or equal to M, the M is the number of currently stored TMDS characters in the buffer, and the I and M are integers.
  • the third total number and the fourth total number of TMDS characters input to the buffer 32 are obtained, where the third total quantity is stored by the buffer 32 last output.
  • the last TMDS character is input to the total number of TMDS characters in the buffer 32, and the fourth total number is the total number of TMDS characters input to the buffer 32 at the current time; the fourth total number and the first a difference between the total number of three, as the number of TMDS characters currently stored in the buffer 32; and when the number of currently stored TMDS characters in the buffer 32 reaches a preset value, a TMDS character in the buffer 32 is output; and the first clock signal is When the subsequent second clock signal to the Mth clock signal arrive, one TMDS character stored in the buffer 32 is respectively output; wherein M is the number of TMDS characters stored in the buffer 32.
  • the number of TMDS characters stored in the buffer 32 is calculated, and when the number of stored TMDS characters reaches a preset value, the storage capacity of the buffer 32 is full.
  • the TMDS character is output from the buffer 32; otherwise, the GAP packet is output; by the above method, it is ensured that neither overflow nor underflow occurs in the buffer 32, thereby ensuring the display timing inherent to the TMDS character.
  • the present application provides a specific implementation manner of the data flow control method, which may be implemented based on the data flow control device shown in FIG. 3b.
  • the principle of the method is: the terminal obtains the current input to the current when each clock signal arrives. a first total number of TMDS characters in the buffer 32 and a second total number of TMDS characters currently outputted from the buffer 32, and the difference between the first total quantity and the second total quantity is stored as the buffer 32
  • the number of TMDS characters when the number of currently stored TMDS characters in the buffer 32 reaches a preset value, the terminal outputs one TMDS character in the buffer 32, otherwise outputs a GAP packet.
  • Step S61 determining whether the current count value n of the buffer 32 input character counter is greater than or equal to a preset value; the preset value may be specifically a depth d-threshold value a of the buffer 32, the threshold value a user may set according to the requirement; if greater than If the value is equal to the preset value, go to step S62; otherwise, continue to step S61, and wait until n is greater than or equal to the preset value;
  • the buffer 32 continuously inputs the TMDS character, and the above step S61 is adopted, mainly to ensure that there is a certain TMDS character in the buffer 32, and then the output is executed.
  • Step S62 Clearing the intermediate variable E that has outputted a certain type of TMDS character to zero;
  • Step S63 Clear the intermediate variable F of the currently outputted TMDS character to zero;
  • Step S64 output selection signal 1 to MUX 35, F plus 1, E plus 1, and when the output selection signal is 1, MUX 35 will output TMDS characters from buffer 32;
  • Step S65 determining whether the difference between n and m is greater than a preset value, n is the number of TMDS characters input into the buffer 32 from the start of inputting the TMDS character to the current time, and m is the value from the start of outputting the TMDS character to the current time. All the number of TMDS characters are output from the buffer 32; the preset value may be specifically the difference between the depth d of the buffer 32 and the threshold d, and the user may set the size of the threshold d according to the requirement; if the difference between n and m is greater than Preset value, step S66 is performed, otherwise, step S67 is performed;
  • the difference between n and m represents the number of TMDS characters currently stored in buffer 32, and if the difference between n and m is greater than a preset value, it indicates that more buffers are stored in the buffer 32 memory.
  • the TMDS character can continue to be output from buffer32, otherwise, the GAP packet is output.
  • Step S66 determining whether E is equal to L0; if yes, executing step S68; otherwise, proceeding to step S64;
  • L0 represents the number of TMDS characters of a certain type input into the buffer 32. If E is equal to L0, the TMDS character of the type is completely output from the buffer 32, and step S68 is performed; otherwise, the TMDS character is continuously outputted from the buffer 32;
  • Step S69 outputting the selection signal 0 to the MUX 35, and the MUX 35 outputs the GAP data packet to the FRL packaging module when the output selection signal is 0;
  • Step S610 determining whether the difference between n and m is greater than a preset value, where the preset value may be specifically the difference between the buffer 32 depth and the threshold c, and the user may set the size of the threshold c; if the difference between the two is greater than The preset value is continued to perform step S63; otherwise, step S69 is executed to continue outputting the GAP data packet to the FRL packaging module;
  • each TMDS character and the GAP packet are taken from the buffer 32 to determine whether the difference between n and m is greater than a preset value, and in the background, the input TMDS in the FRL transmission link is proposed.
  • the rate of characters is less than the rate of outputting TMDS characters, so the number of TMDS characters stored in buffer32 at each time is very small, so in this application, the buffer 32 depth d can be designed very small; it can be seen that the above data method is utilized.
  • the buffer32 with less storage capacity can be realized, and the requirements for hardware devices are lower.
  • the present application provides another specific implementation manner of the data flow control method, which may be implemented based on the data flow control method shown in FIG. 3c.
  • the principle of the method is as follows: the number of currently stored TMDS characters in the buffer 32 is assumed to be M. When M is an integer, the terminal acquires the third total number of TMDS characters input to the buffer 32 at the current time when the first clock signal arrives, and the buffer 32 when the last TMDS character stored last time is output. The fourth total number of TMDS characters is input in the buffer 32; the terminal uses the difference between the fourth total number and the third total number as the number of TMDS characters currently stored in the buffer 32; the terminal currently stores the TMDS in the buffer 32.
  • a TMDS character is output from the M TMDS characters to the FRL packing module; and when the second clock signal to the Mth clock signal subsequent to the first clock signal arrives, the output is sequentially output from the buffer 32.
  • TMDS character to FRL packing module that is, assuming that there are M TMDS characters stored in buffer32, then when the first clock signal arrives, judge buffer3 Whether the number of currently stored TMDS characters in 2 is greater than a preset value; if greater than the preset value, a TMDS character is selected among the M TMDS characters and output to the FRL packaging module; then, when the second clock signal arrives, Select another TMDS character from the M TMDS characters to the FRL packing module, and then type the MTMs characters until the MMS characters are completely output. After that, when the clock signal arrives, it is judged again whether the number of currently stored TMDS characters in the buffer32 is greater than The preset value, if it is greater than, executes the above process again, otherwise it outputs the GAP packet.
  • Step S72 determining whether the current count value n of the buffer 32 input character counter is greater than or equal to a preset value; the preset value may be specifically a depth d-threshold value a of the buffer 32, the threshold value a user may set according to the requirement; if greater than If the value is equal to the preset value, go to step S73; otherwise, continue to step S71, and wait until n is greater than or equal to the preset value;
  • Step S73 Clearing the intermediate variable E that has outputted a certain type of TMDS character to zero;
  • F represents the current time buffer32 stores the number of TMDS characters
  • E represents the cumulative output of the number of TMDS characters
  • Step S75 determining whether E is equal to or greater than L0; wherein, L0 represents the length of inputting a certain type of TMDS character; if so, executing step S76; otherwise, executing step S77;
  • E Since E is cleared, after executing the GAP packet and executing step S74, E may be greater than L0; in this case, the length of a certain type of TMDS character needs to be recalculated, and the specific calculation is performed.
  • the formula please refer to step S76;
  • Step S76 Modify F to F-(E-L0);
  • the number of TMDS characters of a certain type in the input FRL transmission link is eight, but since the storage capacity of the buffer 32 is limited, only five TMDS characters are stored in the buffer 32, then Through the step S77, the five TMDS characters can be simultaneously output and packaged into a FRL data packet, and the TMDS characters are continuously input in the buffer 32. At this time, the steps S78 and S79 are continued; if the S79 satisfies the condition, the process returns to continue execution. S74; in S74, F is set to the number of currently stored TMDS characters in buffer32.
  • E is set as the TMDS character input to buffer32 last time.
  • the sum of the TMDS characters currently input to buffer32, the TMDS characters currently input to buffer32 include the last 3 TMDS characters of the same type and other types of TMDS characters, and L0 represents the 8 TMDS characters of the last input buffer32.
  • E-L0 represents the other types of TMDS characters currently input, and F-(E-L0) is the last 3 remaining TMDS characters; and the remaining 3 TMDS words can be subsequently passed through step S77.
  • the packet is packed into a data packet; that is, in the present application, if the number of TMDS characters of a certain type initially input is larger than the storage capacity of the buffer 32, the TMDS character of the certain type may be packaged into multiple FRL data packets, and GAP empty packets can be inserted between different FRL packets.
  • Step S78 note that the buffer 32 inputs the count value n2 of the character counter at the time of outputting the last TMDS character buffer32;
  • Step S79 determining whether n2-n1 ⁇ (d - threshold a) is established, if yes, proceeding to step S74; otherwise performing step S710;
  • Step S710 Output selection signal 0, at which time MUX 35 outputs a GAP packet.
  • a plurality of TMDS characters are outputted from the buffer 32 at a time for output, and after the plurality of TMDS characters are output, the process of determining whether to output the TMDS character or output the GAP data packet is performed, then Compared with the method provided in the fourth embodiment, a judgment process is performed every time a TMDS character is output, and the present application outputs a plurality of TMDS characters to perform a judgment process, and then displaying the method of the present application can reduce the execution of the judgment process and reduce Power consumption.
  • the present application further provides a data flow control device, which may be implemented by hardware, software or a combination of software and hardware.
  • the device may be a terminal, such as a set top box, a television, a computer or a smart phone. .
  • FIG. 8 is a schematic structural diagram of a data flow control apparatus provided by some embodiments of the present application. As shown in FIG. 8, the data flow control device 80 includes:
  • a buffer unit 81 configured to store a minimum transmission differential signal TMDS character
  • the calculating unit 82 is configured to calculate, when the clock signal arrives, the number of currently stored TMDS characters in the buffer unit; the period of the clock signal is set according to a rate at which the TMDS character is transmitted according to the fixed rate link FRL;
  • the output unit 83 is configured to output a TMDS character in the buffer unit when the number of currently stored TMDS characters in the buffer unit reaches a preset value; otherwise, output a null data packet; the preset value is less than or equal to the
  • the buffer unit stores the capacity of the TMDS character.
  • the calculating unit 82 is configured to: when the clock signal arrives, acquire a first total number of TMDS characters currently input into the buffer unit and a current output of the TMDS character from the buffer unit a total number; a difference between the first total number and the second total number as the number of TMDS characters currently stored by the buffer unit.
  • the output unit 83 is configured to: when the number of currently stored TMDS characters in the buffer unit reaches the preset value, output a TMDS character stored by the buffer unit.
  • the clock signal is a first clock signal
  • the output unit 83 is configured to: when the number of currently stored TMDS characters in the buffer unit reaches a preset value, output a TMDS character stored by the buffer unit; Outputting, when the second clock signal to the first clock signal subsequent to the first clock signal arrives, one TMDS character stored by the buffer unit; wherein the I is greater than or equal to 2, less than or equal to M, the M For the number of TMDS characters currently stored in the buffer unit, the I and M are integers.
  • the calculating unit 82 is configured to: when the clock signal arrives, acquire a third total quantity and a fourth total quantity of the TMDS characters input into the buffer unit, where the third total quantity is a total number of TMDS characters input to the buffer unit when the buffer unit last outputs the last TMDS character stored, and the fourth total number is the total number of TMDS characters input to the buffer unit at the current time; a difference between the fourth total number and the third total number as the number of TMDS characters currently stored by the buffer unit.
  • the clock signal is a first clock signal
  • the buffer unit currently stores the number of TMDS characters as M, and the M is an integer
  • the output unit 83 is specifically configured to: when the M reaches the preset value, output a TMDS character stored by the buffer unit; and outputting a TMDS character stored by the buffer unit when the second clock signal to the Mth clock signal subsequent to the first clock signal arrive.
  • each functional unit in each embodiment of the present application may be Integrated in one processor, it can be physically separate, or two or more modules can be integrated into one module.
  • the above integrated modules can be implemented in the form of hardware or in the form of software functional modules.
  • the present application further provides a data flow control device 90, including a processor 901, a memory 902, and a communication interface 903; the processor 901, the memory 902, and the communication interface 903 all pass through the bus.
  • a memory 902 for storing computer execution instructions may be a non-volatile memory such as a hard disk drive (HDD) or a solid state drive (English: solid-state drive, abbreviation: SSD) And so on, it can also be a volatile memory (English: volatile memory), such as random access memory (English: random-access memory, abbreviation: RAM).
  • Memory 902 is any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited thereto.
  • the processor 901 is configured to execute the computer-executed instructions stored in the memory 902 to perform the data flow control method described in any one of the first embodiment to the fifth embodiment.
  • the description is not repeated herein; the processor 901 may be a Central processing unit (English: central processing unit, referred to as CPU), or digital processing module and so on.
  • connection medium between the above communication interface 903, the processor 901, and the memory 902 is not limited in the application embodiment.
  • the memory 902, the processor 901, and the communication interface 903 are connected by a bus in FIG. 9, and the bus is indicated by a thick line in FIG. 9, and the connection manner between other components is only schematically illustrated. , not limited to.
  • the bus can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, only one thick line is shown in Figure 9, but it does not mean that there is only one bus or one type of bus.
  • the application further provides a computer readable storage medium having instructions stored therein, when executed on a computer, causing the computer to execute the second embodiment, the third embodiment, the fourth embodiment or the embodiment The data flow control method described in 5.
  • embodiments of the present application can be provided as a method, system, or computer program product.
  • the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment in combination of software and hardware.
  • the application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) including computer usable program code.
  • the program instructions may also be stored in a readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the readable memory produce an article of manufacture comprising the instruction device, the Flowchart A process or a plurality of processes and/or block diagrams of functions specified in a block or blocks.
  • program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the steps are provided to implement the functions specified in one or more blocks of the flowchart or in a block or blocks of the flowchart.

Abstract

本申请公开了一种数据流控方法及装置，其中，该方法包括：设备在时钟信号到达时，计算所述设备的缓冲器中当前存储最小化传输差分信号TMDS字符的数量；所述设备在所述缓冲器中当前存储TMDS字符的数量达到预设值时，输出所述缓冲器中的TMDS字符；否则，输出空数据包；其中，所述预设值小于等于所述缓冲器存储TMDS字符的容量；采用本申请的方法及装置，可保证TMDS字符固有的显示时序。

Description

一种数据流控方法及装置
本申请要求在2017年3月29日提交中国专利局、申请号为201710197328.0、发明名称为“一种数据流控方法及装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信技术领域，尤其涉及一种数据流控方法及装置。
背景技术
高清晰度多媒体接口(High Definition Multimedia Interface，HDMI)是一种数字化视频/音频接口技术，适合影像传输的专用型数字化接口，其可同时传送音频和影像信号，在现有公开的HDMI标准协议2.0版本中，将视频显示数据、显示控制信号以及音频数据等转换为最小化传输差分信号(Transition Minimized Differential Signaling，TMDS)字符，用于在HDMI线缆中传输。
目前，HDMI标准2.1版本相对原来的2.0版本新增了固定速率链路(Fix Rate Link，FRL)传输模式，用于支持2.1版本相对于2.0版本来说更高的显示数据传输速率，从而支持更高分辨率和更高帧率视频制式的传输；其中，在大多数应用场景中，FRL传输模式中输入TMDS字符的速率要低于该链路所要求传输TMDS字符的速率；同时，在HDMI标准2.1版中，提出了一种名为空包(GAP)的数据包，该数据包主要用于在FRL传输模式中进行TMDS字符的匹配。在现有技术中，为了进行TMDS字符的速率匹配，相关技术人员提出了在FRL传输模式中设置一缓冲器(buffer)，该buffer可用于存储输入至FRL中的TMDS字符；然后按照FRL链路的时钟周期，输出buffer中的TMDS字符或GAP数据包至FRL链路中传输。
而在HDML标准2.1版本中，关于TMDS字符的输出和GAP数据包的输出并没有相关规定，由于在实际应用中，FRL中所预设buffer的存储容量是有限的，如果在FRL的时钟信号到达时，连续输出GAP数据包，而TMDS字符又是不断输入至FRL中的buffer的，这时可能会造成buffer的上溢，所述上溢是指输入的TMDS字符的数量超过了buffer的存储容量；而如果时钟信号到达时，连续输出buffer中的TMDS字符至FRL传输通道，由于在FRL中输入TMDS字符的速率又小于FRL所要求的TMDS字符的传输速率，因此此时又可能会造成buffer的下溢，所述下溢是指当整个buffer已经没有TMDS字符时，还要求从buffer中输出TMDS字符；而buffer的上溢和下溢均会破坏原来TMDS字符固有的显示时序。
发明内容
本申请提供一种数据流控方法及装置，以使得FRL中的缓冲器既不上溢也不下溢，保证TMDS字符固有的显示时序。
第一方面，本申请提供一种数据流控方法，包括：设备在时钟信号到达时，计算所述设备的缓冲器中当前存储最小化传输差分信号TMDS字符的数量，所述时钟信号的周期为 根据固定速率链路FRL传输TMDS字符的速率所设置的；所述设备在所述缓冲器中当前存储TMDS字符的数量达到预设值时，输出所述缓冲器中的TMDS字符；否则，输出空数据包；其中，所述预设值小于等于所述缓冲器存储TMDS字符的容量。
可以看出，通过上述数据流控方法，可保证缓冲器的既不上溢，也不下溢，从而保证TMDS字符固有的显示时序。
结合第一方面，在第一种可能实现方式中，所述设备在时钟信号到达时，计算所述设备的缓冲器中当前存储TMDS字符的数量，包括：所述设备在时钟信号到达时，获取当前输入至所述缓冲器中TMDS字符的第一总数量和当前从所述缓冲器中输出TMDS字符的第二总数量；所述设备将所述第一总数量和所述第二总数量的差值，作为所述缓冲器当前存储TMDS字符的数量。
结合第一方面或第一种可能实现方式，在第二种可能实现方式中，所述设备在所述缓冲器中当前存储TMDS字符的数量达到预设值时，输出所述缓冲器中的TMDS字符，包括：
所述设备在所述缓冲器中当前存储TMDS字符的数量达到所述预设值时，输出所述缓冲器所存储的一个TMDS字符。
可以看出，在本可能实现方式中，理论上缓冲器可仅存储一个TMDS字符即可，那么具体实现中可将缓冲器的容量设计的很小，对缓冲器的要求较低，易于实现。
结合第一方面或第一种可能实现方式，在第三种可能实现方式中，所述时钟信号为第一时钟信号；所述设备在所述缓冲器中当前存储TMDS字符的数量达到预设值时，输出所述缓冲器中的TMDS字符，包括：所述设备在所述缓冲器中当前存储TMDS字符的数量达到预设值时，输出所述缓冲器所存储的一个TMDS字符；所述设备在所述第一时钟信号后续的第二时钟信号至第I时钟信号到达时，分别输出所述缓冲器所存储的一个TMDS字符；其中，所述I大于等于2，小于等于M，所述M为所述缓冲器中当前存储TMDS字符的数量，所述I和M均为整数。
可以看出，在本可能实现方式中，至少输出2个TMDS字符时，才执行一次判断过程，可节约设备的功耗。
结合第一方面，在第四种可能实现方式中，所述设备在时钟信号到达时，计算所述设备的缓冲器中当前存储TMDS字符的数量，包括：所述设备在时钟信号到达时，获取输入至所述缓冲器中TMDS字符的第三总数量和第四总数量，所述第三总数量为所述缓冲器上次输出所存储的最后一个TMDS字符时输入至所述缓冲器中TMDS字符的总数量，所述第四总数量为当前时刻输入至所述缓冲器中TMDS字符的总数量；所述设备将所述第四总数量和所述第三总数量的差值，作为所述缓冲器当前存储TMDS字符的数量。
结合第四种可能实现方式中，在第五种可能实现方式中，所述时钟信号为第一时钟信号，所述缓冲器当前存储TMDS字符的数量为M，所述M为整数；所述设备在所述缓冲器中当前存储TMDS字符的数量达到预设值时，输出所述缓冲器中的TMDS字符，包括：所述设备在所述M达到所述预设值时，输出所述缓冲器所存储的一个TMDS字符；所述设备在所述第一时钟信号后续的第二时钟信号至第M时钟信号到达时，分别输出所述缓冲器所存储的一个TMDS字符。
可以看出，在输出缓冲器中所有的TMDS字符时，才执行一次判断过程，可节约设备的功能。
第二方面，提供一种数据流控装置，包括：缓冲单元，用于存储最小化传输差分信号TMDS字符；计算单元，用于在时钟信号到达时，计算所述缓冲单元中当前存储TMDS字符的数量；所述时钟信号的周期为根据固定速率链路FRL传输TMDS字符的速率所设置的；输出单元，用于在所述缓冲单元中当前存储TMDS字符的数量达到预设值时，输出所述缓冲单元中的TMDS字符；否则，输出空数据包；所述预设值小于等于所述缓冲单元存储TMDS字符的容量。
结合第二方面，在第一种可能实现方式中，所述计算单元，具体用于：在时钟信号到达时，获取当前输入至所述缓冲单元中TMDS字符的第一总数量和当前从所述缓冲单元中输出TMDS字符的第二总数量；将所述第一总数量和所述第二总数量的差值，作为所述缓冲单元当前存储TMDS字符的数量。
结合第二方面或第一种可能实现方式，在第二种可能实现方式中，所述输出单元，具体用于：在所述缓冲单元中当前存储TMDS字符的数量达到所述预设值时，输出所述缓冲单元所存储的一个TMDS字符。
结合第二方面或第一种可能实现方式，在第二种可能实现方式中，所述时钟信号为第一时钟信号；所述输出单元，具体用于：在所述缓冲单元中当前存储TMDS字符的数量达到预设值时，输出所述缓冲单元所存储的一个TMDS字符；在所述第一时钟信号后续的第二时钟信号至第I时钟信号到达时，分别输出所述缓冲单元所存储的一个TMDS字符；其中，所述I大于等于2，小于等于M，所述M为所述缓冲单元中当前存储TMDS字符的数量，所述I和M均为整数。
结合第二方面，在第三种可能实现方式中，所述计算单元，具体用于：在时钟信号到达时，获取输入至所述缓冲单元中TMDS字符的第三总数量和第四总数量，所述第三总数量为所述缓冲单元上次输出所存储的最后一个TMDS字符时输入至所述缓冲单元中TMDS字符的总数量，所述第四总数量为当前时刻输入至所述缓冲单元中TMDS字符的总数量；将所述第四总数量和所述第三总数量的差值，作为所述缓冲单元当前存储TMDS字符的数量。
结合第三种可能实现方式，在第四种可能实现方式中，所述时钟信号为第一时钟信号，所述缓冲单元当前存储TMDS字符的数量为M，所述M为整数；所述输出单元，具体用于：
在所述M达到所述预设值时，输出所述缓冲单元所存储的一个TMDS字符；在所述第一时钟信号后续的第二时钟信号至第M时钟信号到达时，分别输出所述缓冲单元所存储的一个TMDS字符。
本申请上述第二方面或第二方面的任一种实现所述装置的实施以及有益效果可与本发明上述第一方面或第一方面的任一种实现所述方法的实施以及有益效果可以相互参见，重复之处不再赘述。
第三方面，本申请提供一种数据流控设备，包括处理器、存储器和通信接口；所述处理器、存储器和通信接口均通过总线连接；所述存储器，用于存储计算机执行指令；所述处理器，用于执行所述存储器存储的计算机执行指令，以执行在时钟信号到达时，计算所述设备的缓冲器中当前存储最小化传输差分信号TMDS字符的数量以及在所述缓冲器中当前存储TMDS字符的数量达到预设值时，输出所述缓冲器中的TMDS字符，否则输出空数据包；其中，所述预设值小于等于所述缓冲器存储TMDS字符的容量。
结合第三方面，在第一种可能实现方式中，所述处理器在时钟信号到达时，计算所述设备的缓冲器中当前存储TMDS字符的数量，包括：在时钟信号到达时，获取当前输入至所述缓冲器中TMDS字符的第一总数量和当前从所述缓冲器中输出TMDS字符的第二总数量；将所述第一总数量和所述第二总数量的差值，作为所述缓冲器当前存储TMDS字符的数量。
结合第三方面或第一种可能实现方式，在第二种可能实现方式中，所述处理器在所述缓冲器中当前存储TMDS字符的数量达到预设值时，输出所述缓冲器中的TMDS字符时，具体用于：在所述缓冲器中当前存储TMDS字符的数量达到所述预设值时，输出所述缓冲器所存储的一个TMDS字符。
结合第一方面或第一种可能实现方式，在第三种可能实现方式中，所述处理器在所述缓冲器中当前存储TMDS字符的数量达到预设值时，输出所述缓冲器中的TMDS字符，包括：在所述缓冲器中当前存储TMDS字符的数量达到所述预设值时，输出所述缓冲器所存储的一个TMDS字符。
结合第三方面，在第四种可能实现方式中，所述处理器在时钟信号到达时，计算所述设备的缓冲器中当前存储TMDS字符的数量时，包括：在时钟信号到达时，获取输入至所述缓冲器中TMDS字符的第三总数量和第四总数量，所述第三总数量为所述缓冲器上次输出所存储的最后一个TMDS字符时输入至所述缓冲器中TMDS字符的总数量，所述第四总数量为当前时刻输入至所述缓冲器中TMDS字符的总数量；将所述第四总数量和所述第三总数量的差值，作为所述缓冲器当前存储TMDS字符的数量。
结合第四种可能实现方式，在第五种可能实现方式中，所述时钟信号为第一时钟信号；所述处理器在所述缓冲器中当前存储TMDS字符的数量达到预设值时，输出所述缓冲器中的TMDS字符时，具体用于：在所述缓冲器中当前存储TMDS字符的数量达到预设值时，输出所述缓冲器所存储的一个TMDS字符；在所述第一时钟信号后续的第二时钟信号至第I时钟信号到达时，分别输出所述缓冲器所存储的一个TMDS字符；其中，所述I大于等于2，小于等于M，所述M为所述缓冲器中当前存储TMDS字符的数量，所述I和M均为整数。
本申请上述第三方面或第三方面的任一种实现所述装置的实施以及有益效果可与本申请上述第一方面或第一方面的任一种实现所述方法的实施以及有益效果可以相互参见，重复之处不再赘述。
第四方面，本申请还提供一种数据流控设备，包括缓冲器、TMDS字符计数器、控制器、数据选择器和空数据包产生器；其中，所述缓冲器，用于存储最小化传输差分信号TMDS字符；所述TMDS字符计数器，用于记录输入或/和输出所述缓冲器的TMDS字符数量，且将记录的TMDS字符数量发送给所述控制器；所述控制器，用于在时钟信号到达时，根据所述TMDS字符计数器记录的TMDS字符数量计算所述缓冲器中当前存储TMDS字符的数量，以及在所述缓冲器中当前存储TMDS字符的数量达到预设值时，发送第一控制信号至所述数据选择器，否则，发送第二控制信号至所述数据选择器；所述时钟信号的周期为根据固定速率链路FRL传输TMDS字符的速率所设置的；所述数据选择器，用于在接收到所述控制器的第一控制信号时，输出所述缓冲器中的TMDS字符，或者，在接收到所述控制器的第二控制信号时，输出所述空数包产生器所产生的空数据包。
结合第四方面，在第一种可能实现方式中，所述TMDS字符计数器包括：输入TMDS 字符计数器和输出TMDS字符计数器；所述控制器在时钟信号到达时，计算所述缓冲器中当前存储TMDS字符的数量时，具体用于：所述控制器在时钟信号到达时，获取当前所述输入TMDS字符计数器记录的第一计数值和所述输出TMDS字符计数器记录的第二计数值；其中，所述第一计数值用于指示当前所述输入TMDS字符计数器记录的输入所述缓冲器的TMDS字符数量，所述第二计数值用于指示当前所述输出TMDS字符计数器记录的输出所述缓冲器的TMDS字符数量；所述控制器将所述第一计数值和第二计数值的差值，作为所述缓冲器当前存储TMDS字符的数量。
结合第四方面或第一种可能实现方式，在第二种可能实现方式中，所述数据选择器在接收到所述控制器的第一控制信号，输出所述缓冲器中的TMDS字符时，具体用于：所述数据选择器在接收到所述控制器的第一控制信号时，输出所述缓冲器中的一个TMDS字符。
结合第四方面、第一种可能实现方式或第二种可能实现方式，在第三种可能实现方式中，所述时钟信号为第一时钟信号；所述控制器在所述缓冲器中当前存储TMDS字符的数量达到预设值时，发送第一控制信号至所述数据选择器，包括：所述控制器在所述缓冲器中当前存储TMDS字符的数量达到预设值时，发送第一控制信号至所述数据选择器；所述控制器在第一时钟信号后续的第二时钟信号至第I时钟信号到达时，分别发送第一控制信号至所述数据选择器，所述I大于等于2，小于等于M，所述M为所述缓冲器中当前存储TMDS字符的数量。
结合第四方面，在第四种可能实现方式中，所述TMDS字符计数器包括输入TMDS字符计数器；所述控制器在时钟信号到达时，计算所述缓冲器中当前存储TMDS字符的数量时，具体用于：所述控制器在时钟信号到达时，获取所述输入TMDS字符计数器记录的第三计数值和第四计数值；其中，所述第三计数值用于指示所述缓冲器上次输出所存储的最后一个TMDS字符时所述输入TMDS字符计数器记录的输入所述缓冲器的TMDS字符数量，所述第四计数值用于指示当前所述输入TMDS字符计数器记录的输入所述缓冲器的TMDS字符数量；所述控制器将所述第四计数值和所述第三计数值的差值，作为所述缓冲器当前存储TMDS字符的数量。
结合第四种可能实现方式，在第五种可能实现方式中，所述时钟信号为第一时钟信号，所述缓冲器当前存储TMDS字符的数量为M，所述M为整数；所述控制器在所述缓冲器中当前存储TMDS字符的数量达到预设值时，发送第一控制信号至所述数据选择器，包括：所述控制器在所述缓冲器中当前存储TMDS字符的数量达到预设值时，发送第一控制信号至所述数据选择器；所述控制器在第一时钟信号后续的第二时钟信号至第M时钟信号到达时，分别发送第一控制信号至所述数据选择器。
本申请上述第四方面或第四方面的任一种实现所述装置的实施以及有益效果可与本发明上述第一方面或第一方面的任一种实现所述方法的实施以及有益效果可以相互参见，重复之处不再赘述。
第五方面，本申请还提供了一种可读存储介质，用于存储为执行本发明上述第一方面、第一方面的任意一种实现的功能所用的软件指令，其包含用于执行本发明上述第一方面、第一方面的任意一种实现的方法所设计的程序。
由上可见，在本申请中，终端中当到达一个时钟信号时，即计算一下buffer中存储TMDS字符的数量，而当所存储TMDS字符的数量达到预设值时，说明此时buffer的存储 容量将满，从buffer中输出TMDS字符；否则，则输出GAP数据包；采用上述方法，可保证buffer中既不会出现上溢，也不会出现下溢，从而保证TMDS字符固有的显示时序。
附图说明
图1为本申请提供的FRL数据包的一示意图；
图2为本申请提供的HDMI标准协议2.1版本所提供的传输模式的一示意图；
图3a—图3c为本申请提供的数据流控设备的逻辑结构示意图；
图4为本申请提供的TMDS字符类型检测器的一处理流程示意图；
图5为本申请提供的数据流控方法的一流程示意图；
图6为本申请提供的数据流控方法的另一流程示意图；
图7为本申请提供的数据流控方法的又一流程示意图；
图8为本申请提供的数据流控装置的一结构示意图；
图9为本申请提供的数据流控设备的另一结构示意图。
具体实施方式
为了便于理解，首先对本申请所涉及的一些技术名词进行解释，具体如下：
高清晰度多媒体接口(High Definition Multimedia Interface，HDMI)：一种数字化视频/音频接口技术，是适合影像传输的专用型数字化接口，其可同时传送音频和影像信号，可利用其在各种终端间传输视频/音频信号，比如在机顶盒和电视间传输视频/音频信号、以及在电视和计算机间传输视频/音频信号。
最小化传输差分信号(Transition Minimized Differential Signaling，TMDS)：在HDMI标准协议2.0版本中，所规定的传输视频以及音频数据的一种格式；主要由两种类型，分别为消隐区视频数据类型和有效视频数据数据类型；在HDMI标准协议2.0版本中，将输入的视频显示数据、显示控制信号以及音频数据等转换为TMDS格式的数据，在HDMI线缆中传输。
固定速率链路(Fix Rate Link，FRL)：在HDMI标准协议2.1版本中所提出，为了支持相对于2.0版本更高速率的传输。
FRL数据包：在FRL传输通道中所传输的数据包，所述FRL数据包的格式，如图1所示，1个FRL数据包由多个FRL字符组成，其中，每个FRL字符占用16比特，而FRL数据包的第一个FRL字符的高6比特表示整个FRL字符的类型，低6比特表示整个FRL字符的长度，而从第二个FRL字符开始至后面所有的FRL字符均用于承载TMDS字符，且一个FRL字符可承载至少2个TMDS字符，每个TMDS字符占用8比特；通常将同一类型的TMDS字符，打包在同一个FRL数据包中。
空包(GAP)数据包：在HDMI标准协议2.1版本中，为了进行速率匹配，所提出的一种FRL数据包；
缓冲器(buffer)：主要分为输入buffer和输出buffer，输入buffer的作用是将外设送来的数据暂时存放，以便处理器将它取走；输出buffer的作用是用来暂时存放处理器送往外设的数据；在本申请中所利用的buffer主要为输入buffer。
数据选择器(multiplexer,MUX)：在多路数据传送过程中，能够根据需要将其中一路选 出来的电路；常见的规格为4选1MUX、8选1MUX以及16选1MUX；本申请应用的是2选1数据选择器，即从2路输入数据中，选择1路进行输出。
为了更清楚的介绍本申请的技术方案，如图2所示，首先介绍一下HDMI标准协议2.1版本所规定的传输方式，该传输方式可作为本申请的一种应用场景，但不应当作为对本申请应用场景的限制：
如图2所示，在HDMI标准协议2.1版本中规定，首先将视频信号、音频信号以及显示控制信号输入至TMDS字符产生模块，所述TMDS字符产生模块可将输入的视频信号、音频信号以及显示控制信号转换为TMDS字符，然后，将TMDS字符输入至加密模块，进行加密；最后，将加密的TMDS字符分为两路，一路输入至TMDS传输链路，另一路输入至FRL传输链路；
TMDS传输链路：将输入的加密TMDS字符，将经过加扰编码模块后，输入至TMDS传输通道进行传输；
FRL传输链路：将输入的加密TMDS字符，经过数据流控模块、FRL打包模块、FRL数据包到字符块的映射模块以及加扰编码模块后，输入至FRL传输通道中进行传输，其中，FRL传输通道一般为3通道或4通道。
其中，TMDS传输链路是为了与HDMI标准协议2.0版本相兼容，而FRL传输链路是HDMI标准协议2.1版本新提出的传输链路，其传输TMDS字符的速率将大于输入该链路中TMDS字符的速率，因此为了进行速率匹配，在加密模块与FRL打包模块之间加入了数据流控模块。
应当指出，上述图2所示的应用场景仅仅作为本申请的一种应用场景，在实际应用中，本申请还有其它应用场景，比如，一种应场景可为，可将图2所示的TMDS字符产生模块产生的TMDS字符直接分两路分别输入至TMDS传输链路和FRL传输链路，而不再经过加密模块的处理。
基于以上应用场景，本申请提供一种数据流控方法及装置，下面将以实施例的方式，详细介绍本申请的方案，为了清楚起见，下表列出了本申请各个实施例及对应的附图。
Figure PCTCN2017117513-appb-000001
实施例一
如图3a所示，本申请提供一种数据流控设备，该设备在实际应用中可以为芯片，图3a所示的设备主要实现图2所示的数据流控模块的功能，主要包括：TMDS字符类型检测器31、buffer32、TMDS字符计数器33、控制器34、MUX35以及GAP数据包产生器36 组成。
其中，TMDS字符类型检测器31，主要用于检测输入到FRL链路中TMDS字符的类型，TMDS字符的类型主要有消隐区视频数据类型和有效视频数据类型两种，TMDS字符类型检测主要有于检测输入至FRL链路中的TMDS字符为消隐区视频数据类型，还是有效视频数据类型；在本申请中，TMDS字符类型检测可将消隐区视频数据类型，标记为Type2，而将有效视频数据类型，标记为Type3。
buffer32，主要用于存储TMDS字符；buffer存储TMDS字符的容量通常为深度d代表；例如，buffer最多能存储10个TMDS字符，那么该buffer的深度为10。
TMDS字符计数器33，用于记录输入或/和输出buffer32中的TMDS字符数量，且将记录的TMDS字符数量发送给所述控制器34；
在本申请中，TMDS字符计数器33可每输入一个TMDS字符，计数值加1，而可每输入两个TMDS字符，计数值加1，关于计数规则，用户可根据需求自行设定。
控制器34，主要用于时钟信号到达时，根据所述TMDS字符计数器33记录的TMDS字符数量计算所述buffer32中当前存储TMDS字符的数量，以及在所述buffer32中当前存储TMDS字符的数量达到预设值时，发送第一控制信号至MUX35，否则，发送第二控制信号至MUX35；所述时钟信号的周期为根据固定速率链路FRL传输TMDS字符的速率所设置的；比如，HDML标准协议2.1版本中规定在FRL传输链路中每秒传输8个TMDS字符，那么，时钟信号的周期可具体为1/8＝0.125S，即每隔0.125秒输出一个钟控制信号，该时钟控制信号可具体由整个传输设备的中央处理器所产生的，所述整个传输终端可具体为执行视频/音频传输的终端，比如，以从机顶盒中向电视中传输视频、音视以及显示控制信号为例，那么整个传输终端可具体为机顶盒，而机顶盒和电视之间采用HDML接口进行传输数据，那么，机顶盒可将通过有线电视网络接收的视频、音频以及显示控制信号，经过图2所示的处理过程，最终分TMDS和FRL两种传输链路，输入至电视中；而FRL链路的输出时钟周期可具体由机顶盒的中央处理器所产生。
MUX35，用于在接收到所述控制器34的第一控制信号时，输出buffer32中的TMDS字符，或者，在接收到所述控制器34的第二控制信号时，输出所述GAP数据包产生器36所产生的空数据包。
比如，当控制器34发出选择信号1时，MUX35从buffer32中输出一个TMDS字符至FRL打包模块，而当控制器34发出选择信号0时，MUX35从GAP数据包产生器36中输出一个GAP数据包至FRL打包模块；
GAP数据包产生器36，用于产生GAP数据包；
应当指出，控制器34，还用于输出FRL数据包的长度L给FRL打包模块；其中，FRL数据包的长度L＝L0/2，L0为输入的某一Type的TMDS字符的长度。TMDS字符类型检测器31，还用于输出TMDS字类的类型Type给FRL打包模块，而FRL打包模块将根据TMDS字符的Type以及L对输出的TMDS字符进行打包，最终将TMDS字符打包成FRL数据包，关于FRL数据包的格式可具体参见图1所示。
还应当指出，可将图2中TMDS字符产生模块产生的TMDS字符直接输入至到FRL链路中，也可经过图2所示的加密模块后，再输入加密的TMDS字符至FRL链路中，图3a仅是本申请的一种示例，并不能作为对本申请的限制；
可以得到，在本申请中，每当FRL链路的时钟信号到达时，控制器34即输出一个TMDS 字符或一个GAP数据包至FRL打包模块，那么可满足FRL链路传输速率的需求。
如图3b所示，在一种示例中，图3a中的TMDS字符计数器33可具体包括输入TMDS字符计数器331和输出TMDS字符计数器332；
可选的一种方式，TMDS字符类型检测器31，主要用于检测输入到FRL链路中TMDS字符的类型，TMDS字符的类型主要有消隐区视频数据类型和有效视频数据类型两种，TMDS字符类型检测主要有于检测输入至FRL链路中的TMDS字符为消隐区视频数据类型，还是有效视频数据类型；在本申请中，TMDS字符类型检测可将消隐区视频数据类型，标记为Type2，而将有效视频数据类型，标记为Type3。
buffer32，主要用于存储TMDS字符；buffer存储TMDS字符的容量通常为深度d代表；例如，buffer最多能存储10个TMDS字符，那么该buffer的深度为10。
输入TMDS字符计数器331，主要用于记录输入至所述buffer32中的TMDS字符的数量；
输出TMDS字符计数器332，主要用于记录从buffer32中输出TMDS字符的数量；
所述控制器34，主要用于在时钟信号到达时，获取当前所述输入TMDS字符计数器331记录的第一计数值和所述输出TMDS字符计数器332记录的第二计数值；其中，所述第一计数值用于指示当前所述输入TMDS字符计数器记录的输入所述缓冲器的TMDS字符数量，所述第二计数值用于指示当前所述输出TMDS字符计数器记录的输出所述缓冲器的TMDS字符数量，以及，将所述第一计数值和第二计数值的差值，作为所述缓冲器当前存储TMDS字符的数量。所述控制器将所述第一计数值和第二计数值的差值，作为所述缓冲器当前存储TMDS字符的数量。且在所述缓冲器当前存储TMDS字符的数量达到预设值时，输出第一控制信号至MUX35，否则，输出第二控制信号至MUX35；
MUX35，主要用于在接收到第一控制信号时，将输出buffer32中的一个TMDS字符，在接收到第二控制信号时，输出空包。
GAP数据包产生器36，主要用于产生GAP数据包；
可选的一种方式，所述控制器34在第一时钟信号到达时，计算当前buffer32中当前存储TMDS字符的数量，关于计算方式，可参见上述；然后在所述buffer32中当前存储TMDS字符的数量达到预设值时，发送第一控制信号至MUX35；而MUX35输出buffer32中的一个TMDS字符；而所述控制器34在第一时钟信号后续的第二时钟信号至第I时钟信号到达时，将直接发送第一控制信号至MUX35，而不再经过上述计算buffer32存储容量和判断buffer32存储容量是否达到预设值的步骤；所述I大于等于2，小于等于M，所述M为buffer32中当前存储TMDS字符的数量；比如，控制器34在时钟信号1到达时，经过计算得到buffer32中当前存储TMDS字符的数量为5；那么，控制器34将继续判断buffer32中当前存储TMDS字符的数量是否达到预设值，假设，所述预设值为3，可以看到buffer32中当前存储TMDS字符数量5已经达到预设值3，那么控制器34将发送第一控制信号至MUX35，而MUX35在接收到第一控制信号时，将输出buffer32中的一个TMDS字符；此后，控制器34在时钟信号1后续的多个时钟信号到达时，将直接输出第一控制信号至MUX35，而MUX35将继续输出TMDS字符；当然，时钟信号1后续的多个时钟信号值的大小用户可自行设设置，但该值需小于buffer32中当前存储TMDS字符的数量；而在多个时钟信号后的又一时钟信号到达时，此时可认为时钟信号1再次到达，控制器34将继续执行上述过程。如图3c所示，在一种示例中，图3a中的TMDS字符计数器33可具体包 括输入TMDS字符计数器333；
其中，TMDS字符类型检测器31，主要用于检测输入到FRL链路中TMDS字符的类型，TMDS字符的类型主要有消隐区视频数据类型和有效视频数据类型两种，TMDS字符类型检测主要有于检测输入至FRL链路中的TMDS字符为消隐区视频数据类型，还是有效视频数据类型；在本申请中，TMDS字符类型检测可将消隐区视频数据类型，标记为Type2，而将有效视频数据类型，标记为Type3。
buffer32，主要用于存储TMDS字符；buffer存储TMDS字符的容量通常为深度d代表；例如，buffer最多能存储10个TMDS字符，那么该buffer的深度为10。
输入TMDS字符计数器333，主要用于记录输入至所述buffer32中的TMDS字符的数量；
控制器34，主要用于在时钟信号到达时，获取所述输入TMDS字符计数器333记录的第三计数值和第四计数值，所述第三计数值用于指示所述buffer32上次输出所存储的最后一个TMDS字符时所述输入TMDS字符计数器333记录的输入所述buffer的TMDS字符数量，所述第四计数值用于指示当前所述输入TMDS字符计数器333记录的输入所述buffer的TMDS字符数量，以及将所述第四计数值和所述第三计数值的差值，作为所述buffer当前存储TMDS字符的数量。
具体的，在一种可选的实施方式中，所述控制器34在第一时钟信号到达时，计算buffer32中TMDS字符的数量，而在所述buffer32中当前存储TMDS字符的数量达到预设值时，发送第一控制信号至MUX35；而控制器34在第一时钟信号后续的第二时钟信号至第M时钟信号到达时，分别发送第一控制信号至MUX35。
MUX35，主要用于在接收到第一控制信号时，将输出buffer32中的一个TMDS字符，在接收到第二控制信号时，输出空包。
GAP数据包产生器36，主要用于产生GAP数据包。
实施例二
在本申请实施例中，将详细论述图3a、图3b或图3c中的TMDS字符类型检测器31的工作过程，如图4所示，具体如下：
步骤S41：分析当前输入的TMDS字符的类型；
步骤S42：判断当前输入的TMDS字符的类型与上一个输入的TMDS字符的类型是否相同；如果相同，执行步骤S43；否则，执行步骤S44；
步骤S43：将TMDS字符长度的临时变量tmp_L的值加3；
在实际应用中，每个TMDS字符占3个字节，因此，每输入一个TMDS字符，tmp_L的值加3；
步骤S44：输出TMDS字符类型Type和TMDS字符的初始化长度L0给FRL打包模块；
在本申请中，TMDS字类的Type主要有两种，分别为消隐区视频数据类型和有效视频数据类型；具体的，对于消隐区视频数据类型的为Type标识为2，有效视频数据类型的Type标识3；而L0＝tmp_L/2；
通过图1中FRL数据包的示例可以看出，每个FRL数据包中FRL字符占2个TMDS字符，因此，在输出FRL数据的初始长度L0时，需将TMDS的长度tmp_L除以2，作为 FRL数据包中FRL字符的长度。
步骤S45：将TMDS字符长度的临时变量tmp_L的数值清零。
可以看出，采用上述方法，可保证一个FRL数据包中的TMDS字符的类型相一致。
实施例三
在本申请中，将详细介绍图3a、图3b或图3c中的控制器34的工作过程，由于控制器34在每当输出信号到达时，即从buffer32中输出一个TMDS字符或一个GAP空包至FRL打包模块；同时整个buffer32的存储容量是有限的，如果当时钟信号到达时，连续输出GAP空包，那么可能会导致buffer32的上溢，所述上溢是指输入的TMDS字符的数量超过了buffer32的存储容量，从而导致TMDS字符的丢失；而如果在时钟信号到达时，连续输出TMDS字符，而TMDS字符的输入速率又是小于FRL链路中TMDS字符的传输速率的，此时又可能会造成buffer32的下溢，所述下溢是指当整个buffer32已经没有TMDS字符时，还要求从buffer32中输出TMDS字符；而buffer32的上溢和下溢均会破坏原来TMDS字符固有的显示时序。
为了解决破坏TMDS字符固有的显示时序的问题，本申请提供了一种数据流控方法，利用该方法可保证buffer32的既不上溢，也不下溢，保证TMDS字符固有的显示时序，如图5所示，该方法具体如下：
步骤S51：在时钟信号到达时，计算buffer32中当前存储TMDS字符的数量；
步骤S52：在所述buffer32中当前存储TMDS字符的数量达到预设值时，输出所述缓冲器中的TMDS字符；否则，输出GAP数据包；所述预设值为根据所述缓冲器存储TMDS字符的容量所设置的、且所述预设值小于等于所述缓冲器存储TMDS字符的容量。
在一种实现方式中，在时钟信号到达时，获取当前输入至所述buffer32中TMDS字符的第一总数量和当前从所述缓冲器中输出TMDS字符的第二总数量；将所述第一总数量和所述第二总数量的差值，作为所述缓冲器当前存储TMDS字符的数量；而在所述缓冲器中当前存储TMDS字符的数量达到预设值时，输出所述缓冲器中所存储的一个TMDS字符。
在一种实现方式中，在第一时钟信号到达时，获取当前输入至所述buffer32中TMDS字符的第一总数量和当前从所述缓冲器中输出TMDS字符的第二总数量；将所述第一总数量和所述第二总数量的差值，作为所述缓冲器当前存储TMDS字符的数量；在所述缓冲器中当前存储TMDS字符的数量达到预设值时，输出所述缓冲器所存储的一个TMDS字符；在所述第一时钟信号后续的第二时钟信号至第I时钟信号到达时，分别输出buffer32中所存储的一个TMDS字符；其中，所述I大于等于2，小于等于M，所述M为所述缓冲器中当前存储TMDS字符的数量，所述I和M均为整数。
在一种实现方式中，在第一时钟信号到达时，获取输入至所述buffer32中TMDS字符的第三总数量和第四总数量，所述第三总数量为所述buffer32上次输出所存储的最后一个TMDS字符时输入至所述buffer32中TMDS字符的总数量，所述第四总数量为当前时刻输入至所述buffer32中TMDS字符的总数量；将所述第四总数量和所述第三总数量的差值，作为所述buffer32当前存储TMDS字符的数量；而在buffer32中当前存储TMDS字符的数量达到预设值时，输出buffer32中的一个TMDS字符；而在所述第一时钟信号后续的第二时钟信号至第M时钟信号到达时，分别输出所述buffer32所存储的一个TMDS字符；其中，M为buffer32中存储TMDS字符数量。由上可见，在本申请中，当到达一个时钟信号 时，即计算一下buffer32中存储TMDS字符的数量，而当所存储TMDS字符的数量达到预设值时，说明此时buffer32的存储容量将满，从buffer32中输出TMDS字符；否则，则输出GAP数据包；采用上述方法，可保证buffer32中既不会出现上溢，也不会出现下溢，从而保证TMDS字符固有的显示时序。
实施例四
本申请提供数据流控方法的一种具体实施方式，该方法可具体基于图3b所示的数据流控设备实现，该方法的原理为：终端在每个时钟信号到达时，获取当前输入至所述buffer32中TMDS字符的第一总数量和当前从所述buffer32中输出TMDS字符的第二总数量，将所述第一总数量和所述第二总数量的差值，作为所述buffer32当前存储TMDS字符的数量；所述终端在buffer32中当前存储TMDS字符的数量达到预设值时，输出buffer32中的一个TMDS字符，否则输出GAP数据包。
如图6所示，本申请提供的数据流控方法的具体实施过程，如下：
步骤S61：判断buffer32输入字符计数器当前的计数值n是否大于等于预设值；所述预设值可具体为buffer32的深度d-阈值a，所述阈值a用户可根据需求，自行设置；如果大于等于预设值，执行步骤S62；否则，继续执行步骤S61，一直等待n大于等于预设值为止；
由于在实际应用中，buffer32中不断输入TMDS字符的，采用上述步骤S61，主要是为了保证buffer32中有一定的TMDS字符后，再执行输出。
步骤S62：将当前已输出某类型TMDS字符的中间变量E清零；
步骤S63：将当前已输出TMDS字符的中间变量F清零；
步骤S64：输出选择信号1至MUX35，F加1，E加1，而在输出选择信号为1时，MUX35将从buffer32中输出TMDS字符；
步骤S65：判断n与m的差值是否大于预设值，n为从开始输入TMDS字符至当前时刻为上，所有输入到buffer32中TMDS字符的数量，m为从开始输出TMDS字符至当前时刻为止，所有从buffer32中输出TMDS字符的数量；所述预设值可具体为buffer32的深度d与阈值d的差，而用户可根据需求，自行设置阈值d的大小；如果n与m的差值大于预设值，执行步骤S66，否则，执行步骤S67；
在本申请中，n与m的差值代表buffer32中当前存储TMDS字符的数量，而如果n与m的差值大于预设值，说明此时buffer32存储器中还存储有较多的TMDS字符，此时可从buffer32中继续输出TMDS字符，否则，输出GAP数据包。
步骤S66：判断E是否等于L0；如果是，执行步骤S68；否则，继续执行步骤S64；
在本申请中，L0代表输入至buffer32中某一类型的TMDS字符的数量，如果E等于L0代表该类型的TMDS字符完全从buffer32中输出，执行步骤S68；否则，继续从buffer32中输出TMDS字符；
步骤S68：输出L＝F给FRL打包模块，而FRL打包模块将根据TMDS字符的类型以及长度L，对输出的TMDS字符进行打包。
步骤S67：输出L＝F给FRL打包模块，而FRL打包模块将对当前输出的该类型的TMDS字符进行打包；
步骤S69：输出选择信号0至MUX35，而MUX35在输出选择信号为0时，将输出 GAP数据包给FRL打包模块；
步骤S610：判断n与m的差值是否大于预设值，所述预设值可具体为buffer32深度与阈值c的差值，而用户可自行设置阈值c的大小；如果两者的差值大于预设值，继续执行步骤S63；否则，执行步骤S69，继续输出GAP数据包至FRL打包模块；
由上可见，在本申请实施例中，从buffer32每取出一个TMDS字符和GAP数据包均会判断一下n与m的差值是否大于预设值，且在背景中提出FRL传输链路中输入TMDS字符的速率小于输出TMDS字符的速率，所以每个时刻存储在buffer32中TMDS字符的数量都非常小，所以在本申请中，可将buffer32深度d设计非常小；可见，采用上述数据方法，利用很少存储容量的buffer32即可实现，对硬件设备的要求较低。
实施例五
本申请提供数据流控方法的另一种具体实施方式，该方法可具体基于图3c所示的数据流控方法实现，该方法的原理为：假设buffer32中当前存储TMDS字符的数量为M，所述M为整数，那么终端在第一时钟信号到达时，获取当前时刻输入至所述buffer32中TMDS字符的第三总数量，以及所述buffer32在最近一次输出所存储的最后一个TMDS字符时所述buffer32中输入TMDS字符的第四总数量；终端将所述第四总数量和所述第三总数量的差值，作为所述buffer32当前存储TMDS字符的数量；所述终端在buffer32中当前存储TMDS字符的数量大于预设值时，从M个TMDS字符中输出一个TMDS字符给FRL打包模块；而在第一时钟信号后续的第二时钟信号至第M时钟信号到达时，依次从buffer32中输出一TMDS字符至FRL打包模块；也即，假设buffer32中存储有M个TMDS字符，那么，在第一个时钟信号到达时，判断一下buffer32中当前存储TMDS字符的数量是否大于预设值；如果大于预设值，则在M个TMDS字符中选择一TMDS字符，输出给FRL打包模块；然后，在第二个时钟信号到达时，再从M个TMDS字符中选择另一个TMDS字符给FRL打包模块，依次类型，直至把M个TMDS字符完全输出；此后，再有时钟信号到达时，再次判断一下buffer32中当前存储TMDS字符的数量是否大于预设值，如果大于，再次执行上述过程，否则输出GAP数据包。
如图7所示，本申请提供的数据流控方法的具体实施过程，如下：
步骤S71：初始化n1＝0，n2＝0；其中，n1代表当前时刻输入至buffer32中TMDS字符的总数量，n2代表buffer32在最近一次输出所存储的最后一个TMDS字符时所述buffer32中输入TMDS字符的总数量；
步骤S72：判断buffer32输入字符计数器当前的计数值n是否大于等于预设值；所述预设值可具体为buffer32的深度d-阈值a，所述阈值a用户可根据需求，自行设置；如果大于等于预设值，执行步骤S73；否则，继续执行步骤S71，一直等待n大于等于预设值为止；
步骤S73：将当前已输出某类型TMDS字符的中间变量E清零；
步骤S74：获取当前时刻buffer32输入字符计数器的计数值n1，设置F＝n1-n2，E＝E+F；
其中，F代表当前时刻buffer32存储TMDS字符的数量，E代表累计输出TMDS字符的数量；
步骤S75：判断E大于等于L0是否成立；其中，L0代表输入某类型TMDS字符的长度；如果成立，执行步骤S76；否则，执行步骤S77；
由于E并有进行清零，在输出GAP数据包后，再执行步骤S74时，可能会出现E大于L0的情况；此时这种情况下，需重新计算某类型TMDS字符的长度，具体的计算公式，可具体参见步骤S76；
步骤S76：将F修改为F-(E—L0)；
在本申请中，假设所输入的FRL传输链路中的某类型的TMDS字符的个数为8个，但由于buffer32的存储容量有限，但仅在buffer32中存储了5个TMDS字符，那么此时，通过步骤S77可将这5个TMDS字符同时输出，打包成一FRL数据包，同时buffer32中还是不断输入TMDS字符的，此时，继续执行步骤S78、S79；如果S79满足条件，再返回去继续执行S74；在S74中，将F设置为buffer32中当前存储TMDS字符的数量，此时除了上述剩余的3个TMDS字符外，还有其它的TMDS字符输入，E设置为上次输入至buffer32的TMDS字符和当前输入至buffer32的TMDS字符之和，当前输入至buffer32的TMDS字符包括上次剩余的同类型的3个TMDS字符和其它类型的TMDS字符，而L0代表上次输入buffer32的8个TMDS字符，而E-L0则代表当前输入的其它类型的TMDS字符，而F—(E-L0)，即为上次剩余的3个TMDS字符；而后续通过步骤S77可将这剩余的3个TMDS字符打包成一个数据包；也就是，在本申请中，如果初始输入的某一类型的TMDS字符的数量大于buffer32的存储容量，可将该某型的TMDS字符打包成多个FRL数据包，且不同FRL数据包之间可插入GAP空包。
步骤S77：输出选择信号为1，此时MUX35从buffer32中取F个TMDS字符，输出FRL数据包长度L＝F给FRL打包模块；
步骤S78：记下buffer32在输出最后一个TMDS字符的时刻buffer32输入字符计数器的计数值n2；
步骤S79：判断n2-n1≥(d—阈值a)是否成立，如果成立，继续执行步骤S74；否则执行步骤S710；
步骤S710：输出选择信号0，此时MUX35输出GAP数据包。
由上可见，在本申请实施例中，一次从buffer32中输出多个TMDS字符进行输出，而在这多个TMDS字符均输出后，再执行一次判断输出TMDS字符还是输出GAP数据包的过程，那么，相对于实施例四提供的方法，每输出一个TMDS字符即执行一次判断过程，本申请是输出多个TMDS字符执行一次判断过程，那么显示采用本申请的方法，可减少判断过程的执行，降低功耗。
实施例六
基于同样的发明构思，本申请还提供了一种数据流控装置，该装置具体可通过硬件、软件或软硬件的结合实现，该装置可以是终端，比如机顶盒、电视、计算机或智能手机等终端。
图8示出了本申请一些实施例所提供的数据流控装置的结构示意图。如图8所示，该数据流控装置80包括：
缓冲单元81，用于存储最小化传输差分信号TMDS字符；
计算单元82，用于在时钟信号到达时，计算所述缓冲单元中当前存储TMDS字符的数量；所述时钟信号的周期为根据固定速率链路FRL传输TMDS字符的速率所设置的；
输出单元83，用于在所述缓冲单元中当前存储TMDS字符的数量达到预设值时，输 出所述缓冲单元中的TMDS字符；否则，输出空数据包；所述预设值小于等于所述缓冲单元存储TMDS字符的容量。
在一种实现方式中，计算单元82，具体用于：在时钟信号到达时，获取当前输入至所述缓冲单元中TMDS字符的第一总数量和当前从所述缓冲单元中输出TMDS字符的第二总数量；将所述第一总数量和所述第二总数量的差值，作为所述缓冲单元当前存储TMDS字符的数量。输出单元83，具体用于：在所述缓冲单元中当前存储TMDS字符的数量达到所述预设值时，输出所述缓冲单元所存储的一个TMDS字符。或者，所述时钟信号为第一时钟信号，输出单元83，具体用于：在所述缓冲单元中当前存储TMDS字符的数量达到预设值时，输出所述缓冲单元所存储的一个TMDS字符；在所述第一时钟信号后续的第二时钟信号至第I时钟信号到达时，分别输出所述缓冲单元所存储的一个TMDS字符；其中，所述I大于等于2，小于等于M，所述M为所述缓冲单元中当前存储TMDS字符的数量，所述I和M均为整数。
在一种实现方式中，计算单元82，具体用于：在时钟信号到达时，获取输入至所述缓冲单元中TMDS字符的第三总数量和第四总数量，所述第三总数量为所述缓冲单元上次输出所存储的最后一个TMDS字符时输入至所述缓冲单元中TMDS字符的总数量，所述第四总数量为当前时刻输入至所述缓冲单元中TMDS字符的总数量；将所述第四总数量和所述第三总数量的差值，作为所述缓冲单元当前存储TMDS字符的数量。所述时钟信号为第一时钟信号，所述缓冲单元当前存储TMDS字符的数量为M，所述M为整数；输出单元83，具体用于：在所述M达到所述预设值时，输出所述缓冲单元所存储的一个TMDS字符；在所述第一时钟信号后续的第二时钟信号至第M时钟信号到达时，分别输出所述缓冲单元所存储的一个TMDS字符。
应当指出，由于本申请上述实施例所提供的装置与本发明前述实施例所提供的方法实施例解决问题的原理相似，因而本申请上述实施例所提供的装置的具体实施以及有益效果可与本发明前述实施例所提供的方法的实施以及有益效果可以相互参见，重复之处不再赘述。
还应当指出，本申请实施例中对单元的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，另外，在本申请各个实施例中的各功能单元可以集成在一个处理器中，也可以是单独物理存在，也可以两个或两个以上模块集成在一个模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。
实施例七
基于同样的发明构思，如图9所示，本申请还提供了一种数据流控设备90，包括处理器901、存储器902和通信接口903；处理器901、存储器902和通信接口903均通过总线连接；其中，存储器902，用于存储计算机执行指令；存储器902可以是非易失性存储器，比如硬盘(英文：hard disk drive，缩写：HDD)或固态硬盘(英文：solid-state drive，缩写：SSD)等，还可以是易失性存储器(英文：volatile memory)，例如随机存取存储器(英文：random-access memory，缩写：RAM)。存储器902是能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其他介质，但不限于此。
处理器901，用于执行存储器902存储的计算机执行指令，以执行上述实施例一至实施例五任一实施例所记载的数据流控方法，本申请在此不再赘述；处理器901可以是一个 中央处理模块(英文：central processing unit，简称CPU)，或者为数字处理模块等等。
申请实施例中不限定上述通信接口903、处理器901以及存储器902之间的具体连接介质。本申请实施例在图9中以存储器902、处理器901以及通信接口903之间通过可总线连接，总线在图9中以粗线表示，其它部件之间的连接方式，仅是进行示意性说明，并不引以为限。所述总线可以分为地址总线、数据总线、控制总线等。为便于表示，图9中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
本申请还提供一种计算机可读存储介质，所述计算机可读存储介质中存储有指令，当其在计算机上运行时，使得计算机执行上述实施例二、实施例三、实施例四或实施例五所述的数据流控方法。
本领域内的技术人员应明白，本申请的实施例可提供为方法、系统、或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本申请是参照根据本申请的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的可读存储器中，使得存储在该可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内

Claims (22)

  1. 一种数据流控方法，其特征在于，包括：
    设备在时钟信号到达时，计算所述设备的缓冲器中当前存储最小化传输差分信号TMDS字符的数量；
    所述设备在所述缓冲器中当前存储TMDS字符的数量达到预设值时，输出所述缓冲器中的TMDS字符；否则，输出空数据包；其中，所述预设值小于等于所述缓冲器存储TMDS字符的容量。
  2. 根据权利要求1所述的方法，其特征在于，所述设备在时钟信号到达时，计算所述设备的缓冲器中当前存储TMDS字符的数量，包括：
    所述设备在时钟信号到达时，获取当前输入至所述缓冲器中TMDS字符的第一总数量和当前从所述缓冲器中输出TMDS字符的第二总数量；
    所述设备将所述第一总数量和所述第二总数量的差值，作为所述缓冲器当前存储TMDS字符的数量。
  3. 根据权利要求1或2所述的方法，其特征在于，所述设备在所述缓冲器中当前存储TMDS字符的数量达到预设值时，输出所述缓冲器中的TMDS字符，包括：
    所述设备在所述缓冲器中当前存储TMDS字符的数量达到所述预设值时，输出所述缓冲器所存储的一个TMDS字符。
  4. 根据权利要求1或2所述的方法，其特征在于，所述时钟信号为第一时钟信号；
    所述设备在所述缓冲器中当前存储TMDS字符的数量达到预设值时，输出所述缓冲器中的TMDS字符，包括：
    所述设备在所述缓冲器中当前存储TMDS字符的数量达到预设值时，输出所述缓冲器所存储的一个TMDS字符；
    所述设备在所述第一时钟信号后续的第二时钟信号至第I时钟信号到达时，分别输出所述缓冲器所存储的一个TMDS字符；其中，所述I大于等于2，小于等于M，所述M为所述缓冲器中当前存储TMDS字符的数量，所述I和M均为整数。
  5. 根据权利要求1所述的方法，其特征在于，所述设备在时钟信号到达时，计算所述设备的缓冲器中当前存储TMDS字符的数量，包括：
    所述设备在时钟信号到达时，获取输入至所述缓冲器中TMDS字符的第三总数量和第四总数量，所述第三总数量为所述缓冲器上次输出所存储的最后一个TMDS字符时输入至所述缓冲器中TMDS字符的总数量，所述第四总数量为当前时刻输入至所述缓冲器中TMDS字符的总数量；
    所述设备将所述第四总数量和所述第三总数量的差值，作为所述缓冲器当前存储TMDS字符的数量。
  6. 根据权利要求5所述的方法，其特征在于，所述时钟信号为第一时钟信号，所述缓冲器当前存储TMDS字符的数量为M，所述M为整数；
    所述设备在所述缓冲器中当前存储TMDS字符的数量达到预设值时，输出所述缓冲器中的TMDS字符，包括：
    所述设备在所述M达到所述预设值时，输出所述缓冲器所存储的一个TMDS字符；
    所述设备在所述第一时钟信号后续的第二时钟信号至第M时钟信号到达时，分别输出 所述缓冲器所存储的一个TMDS字符。
  7. 一种数据流控装置，其特征在于，包括：
    缓冲单元，用于存储最小化传输差分信号TMDS字符；
    计算单元，用于在时钟信号到达时，计算所述缓冲单元中当前存储TMDS字符的数量；
    输出单元，用于在所述缓冲单元中当前存储TMDS字符的数量达到预设值时，输出所述缓冲单元中的TMDS字符；否则，输出空数据包；所述预设值小于等于所述缓冲单元存储TMDS字符的容量。
  8. 根据权利要求7所述的装置，其特征在于，所述计算单元，具体用于：
    在时钟信号到达时，获取当前输入至所述缓冲单元中TMDS字符的第一总数量和当前从所述缓冲单元中输出TMDS字符的第二总数量；
    将所述第一总数量和所述第二总数量的差值，作为所述缓冲单元当前存储TMDS字符的数量。
  9. 根据权利要求7或8所述的装置，其特征在于，所述输出单元，具体用于：
    在所述缓冲单元中当前存储TMDS字符的数量达到所述预设值时，输出所述缓冲单元所存储的一个TMDS字符。
  10. 根据权利要求7或8所述的装置，其特征在于，所述时钟信号为第一时钟信号；
    所述输出单元，具体用于：
    在所述缓冲单元中当前存储TMDS字符的数量达到预设值时，输出所述缓冲单元所存储的一个TMDS字符；
    在所述第一时钟信号后续的第二时钟信号至第I时钟信号到达时，分别输出所述缓冲单元所存储的一个TMDS字符；其中，所述I大于等于2，小于等于M，所述M为所述缓冲单元中当前存储TMDS字符的数量，所述I和M均为整数。
  11. 根据权利要求7所述的装置，其特征在于，所述计算单元，具体用于：
    在时钟信号到达时，获取输入至所述缓冲单元中TMDS字符的第三总数量和第四总数量，所述第三总数量为所述缓冲单元上次输出所存储的最后一个TMDS字符时输入至所述缓冲单元中TMDS字符的总数量，所述第四总数量为当前时刻输入至所述缓冲单元中TMDS字符的总数量；
    将所述第四总数量和所述第三总数量的差值，作为所述缓冲单元当前存储TMDS字符的数量。
  12. 根据权利要求11所述的装置，其特征在于，所述时钟信号为第一时钟信号，所述缓冲单元当前存储TMDS字符的数量为M，所述M为整数；
    所述输出单元，具体用于：
    在所述M达到所述预设值时，输出所述缓冲单元所存储的一个TMDS字符；
    在所述第一时钟信号后续的第二时钟信号至第M时钟信号到达时，分别输出所述缓冲单元所存储的一个TMDS字符。
  13. 一种数据流控设备，其特征在于，包括处理器、存储器和通信接口；所述处理器、存储器和通信接口均通过总线连接；
    所述存储器，用于存储计算机执行指令；
    所述处理器，用于执行所述存储器存储的计算机执行指令，以执行在时钟信号到达时，计算所述设备的缓冲器中当前存储最小化传输差分信号TMDS字符的数量以及在所述缓 冲器中当前存储TMDS字符的数量达到预设值时，输出所述缓冲器中的TMDS字符，否则输出空数据包；其中，所述预设值小于等于所述缓冲器存储TMDS字符的容量。
  14. 根据权利要求13所述的设备，其特征在于，所述处理器在所述缓冲器中当前存储TMDS字符的数量达到预设值时，输出所述缓冲器中的TMDS字符时，具体用于：
    在所述缓冲器中当前存储TMDS字符的数量达到所述预设值时，输出所述缓冲器所存储的一个TMDS字符。
  15. 根据权利要求13所述的设备，其特征在于，所述时钟信号为第一时钟信号；所述处理器在所述缓冲器中当前存储TMDS字符的数量达到预设值时，输出所述缓冲器中的TMDS字符时，具体用于：
    在所述缓冲器中当前存储TMDS字符的数量达到预设值时，输出所述缓冲器所存储的一个TMDS字符；
    在所述第一时钟信号后续的第二时钟信号至第I时钟信号到达时，分别输出所述缓冲器所存储的一个TMDS字符；其中，所述I大于等于2，小于等于M，所述M为所述缓冲器中当前存储TMDS字符的数量，所述I和M均为整数。
  16. 一种数据流控设备，其特征在于，包括缓冲器、TMDS字符计数器、控制器、数据选择器和空数据包产生器；
    其中，所述缓冲器，用于存储最小化传输差分信号TMDS字符；
    所述TMDS字符计数器，用于记录输入或/和输出所述缓冲器的TMDS字符数量，且将记录的TMDS字符数量发送给所述控制器；
    所述控制器，用于在时钟信号到达时，根据所述TMDS字符计数器记录的TMDS字符数量计算所述缓冲器中当前存储TMDS字符的数量，以及在所述缓冲器中当前存储TMDS字符的数量达到预设值时，发送第一控制信号至所述数据选择器，否则，发送第二控制信号至所述数据选择器；
    所述数据选择器，用于在接收到所述控制器的第一控制信号时，输出所述缓冲器中的TMDS字符，或者，在接收到所述控制器的第二控制信号时，输出所述空数包产生器所产生的空数据包。
  17. 根据权利要求16所述设备，其特征在于，所述TMDS字符计数器包括：输入TMDS字符计数器和输出TMDS字符计数器；
    所述控制器在时钟信号到达时，计算所述缓冲器中当前存储TMDS字符的数量时，具体用于：
    所述控制器在时钟信号到达时，获取当前所述输入TMDS字符计数器记录的第一计数值和所述输出TMDS字符计数器记录的第二计数值；其中，所述第一计数值用于指示当前所述输入TMDS字符计数器记录的输入所述缓冲器的TMDS字符数量，所述第二计数值用于指示当前所述输出TMDS字符计数器记录的输出所述缓冲器的TMDS字符数量；
    所述控制器将所述第一计数值和第二计数值的差值，作为所述缓冲器当前存储TMDS字符的数量。
  18. 根据权利要求16或17所述设备，其特征在于，所述数据选择器在接收到所述控制器的第一控制信号，输出所述缓冲器中的TMDS字符时，具体用于：
    所述数据选择器在接收到所述控制器的第一控制信号时，输出所述缓冲器中的一个TMDS字符。
  19. 根据权利要求16至18任一项所述设备，其特征在于，所述时钟信号为第一时钟信号；所述控制器在所述缓冲器中当前存储TMDS字符的数量达到预设值时，发送第一控制信号至所述数据选择器，包括：
    所述控制器在所述缓冲器中当前存储TMDS字符的数量达到预设值时，发送第一控制信号至所述数据选择器；
    所述控制器在第一时钟信号后续的第二时钟信号至第I时钟信号到达时，分别发送第一控制信号至所述数据选择器，所述I大于等于2，小于等于M，所述M为所述缓冲器中当前存储TMDS字符的数量。
  20. 根据权利要求16所述设备，其特征在于，所述TMDS字符计数器包括输入TMDS字符计数器；
    所述控制器在时钟信号到达时，计算所述缓冲器中当前存储TMDS字符的数量时，具体用于：
    所述控制器在时钟信号到达时，获取所述输入TMDS字符计数器记录的第三计数值和第四计数值；其中，所述第三计数值用于指示所述缓冲器上次输出所存储的最后一个TMDS字符时所述输入TMDS字符计数器记录的输入所述缓冲器的TMDS字符数量，所述第四计数值用于指示当前所述输入TMDS字符计数器记录的输入所述缓冲器的TMDS字符数量；
    所述控制器将所述第四计数值和所述第三计数值的差值，作为所述缓冲器当前存储TMDS字符的数量。
  21. 根据权利要求20所述设备，其特征在于，所述时钟信号为第一时钟信号，所述缓冲器当前存储TMDS字符的数量为M，所述M为整数；
    所述控制器在所述缓冲器中当前存储TMDS字符的数量达到预设值时，发送第一控制信号至所述数据选择器，包括：
    所述控制器在所述缓冲器中当前存储TMDS字符的数量达到预设值时，发送第一控制信号至所述数据选择器；
    所述控制器在第一时钟信号后续的第二时钟信号至第M时钟信号到达时，分别发送第一控制信号至所述数据选择器。
  22. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质中存储有指令，当其在计算机上运行时，使得计算机执行如权利要求1至6任一项所述的方法。
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