WO2018171393A1 - 一种极化码编译码方法及装置 - Google Patents

一种极化码编译码方法及装置 Download PDF

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WO2018171393A1
WO2018171393A1 PCT/CN2018/077447 CN2018077447W WO2018171393A1 WO 2018171393 A1 WO2018171393 A1 WO 2018171393A1 CN 2018077447 W CN2018077447 W CN 2018077447W WO 2018171393 A1 WO2018171393 A1 WO 2018171393A1
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Prior art keywords
sequence
segment
encoder
hash
codeword
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PCT/CN2018/077447
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English (en)
French (fr)
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陈佩瑶
王加庆
白宝明
孙韶辉
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电信科学技术研究院有限公司
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Publication of WO2018171393A1 publication Critical patent/WO2018171393A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes

Definitions

  • the embodiments of the present invention relate to the field of communications technologies, and in particular, to a method and an apparatus for encoding and decoding a polarization code.
  • the 4G the 4 th Generation mobile communication technology, the fourth generation mobile communication technology
  • the future fifth-generation mobile communications technology 5G 5 th Generation, fifth generation
  • Polar Codes which are 5G eMBB (Enhanced Moblie Broad Band) are a new type of coding that can achieve binary symmetric channel capacity and have excellent decoding performance.
  • the polarization code encoding and decoding method in the prior art includes a CRC (Cyclic Redundancy Check)-assisted polarization code encoding code, a PC (Parity Check)-assisted polarization code encoding code, and a hash. Sequence-assisted polarization code encoding code. 1 is a schematic diagram of a CRC-assisted polarization code encoding and decoding code in the prior art.
  • the CRC-assisted polarization code encoding and decoding process includes: first encoding an information sequence to be encoded by a CRC encoder to generate a corresponding CRC sequence, and then The information sequence and the CRC sequence are sent to the Polar encoder, encoded, modulated by the modulator, and then transmitted to the receiving end through the channel.
  • the bit stream demodulated by the demodulator is translated by the Polar-CRC joint decoder during decoding.
  • the code is mainly a CRC-assisted Successive Cancellation List (SCL) decoding algorithm.
  • SCL Successive Cancellation List
  • the PC-assisted polarization code encoding and decoding process includes: first encoding an information sequence to be encoded by a CRC encoder to generate a corresponding CRC sequence, and then The information sequence and the CRC sequence are sent to the PC-Polar encoder, encoded and modulated by the modulator, and then transmitted to the receiving end through the channel; when decoding, the bit stream demodulated by the modulator is decoded by the Polar decoder.
  • the PC decoder-assisted SCL decoding algorithm is mainly used.
  • the Polar decoder When the decoding result of the final decoding is selected in the decoding, the Polar decoder first restores the candidate codeword to a candidate information sequence containing the PC, and all candidate information sequences are used. The PC decoding process is performed, and the candidate information sequence decoded by the PC and having the highest reliability is used as the final decoding result.
  • the hash-assisted polarization code encoding and decoding process includes: first encoding an information sequence to be encoded by a CRC encoder to generate a corresponding CRC sequence, and the information is obtained.
  • the sequence and the CRC sequence are sent to the Hash encoder to generate a corresponding hash sequence, and then the information sequence, the CRC sequence and the hash sequence are sent to the Polar encoder, encoded, modulated by the modulator, and then transmitted to the receiving end through the channel;
  • the code is used, the bit stream after demodulation of the modulator is decoded by a Polar decoder, mainly by using a hash-assisted SCL decoding algorithm, and when the decoding result of the final decoding is selected in the decoding, Polar-Hash decoding is performed.
  • the candidate codeword is first restored to a candidate information sequence containing an information sequence, a CRC sequence, and a hash sequence, and all candidate information sequences are hash-decoded, and the candidate information sequence with the highest reliability and the highest reliability is finally obtained.
  • the decoding result is first restored to a candidate information sequence containing an information sequence, a CRC sequence, and a hash sequence, and all candidate information sequences are hash-decoded, and the candidate information sequence with the highest reliability and the highest reliability is finally obtained.
  • the low false alarm rate is beneficial to reduce the uplink collision probability of the UE (User Equipment), reduce the power consumption of the UE, and improve the system performance.
  • an SCL list decoding algorithm is generally employed.
  • the last additional N bits are only used for error detection and are not used for auxiliary decoding, so the false alarm rate does not deteriorate, but PC polar requires more parity bit overhead, resulting in BLER performance is degraded.
  • the embodiment of the present application provides a polarization code encoding and decoding method and device, which are used to reduce false alarm rate and error block rate.
  • an embodiment of the present application discloses a polarization code encoding method, including:
  • the first codeword sequences are combined to obtain a second codeword sequence, and the second codeword sequence is subjected to polarization code encoding.
  • the method before the segmentation of the information sequence to be encoded according to the segmentation policy confirmed by the transmitting and receiving parties, the method further includes:
  • segmenting the information sequence to be encoded according to the segmentation policy that has been confirmed by the transmitting and receiving parties including:
  • the segmentation strategy is used to generate one segment sequence m i .
  • the first encoder is a linear encoder or a nonlinear encoder
  • the second encoder is a linear encoder or a nonlinear encoder
  • the linear encoder is a CRC encoder; and the nonlinear encoder is a hash encoder.
  • the first encoder is a hash encoder
  • the segment according to the segment of the sequence m i and m i of the first sequence corresponding to the encoder generates a first check sequence, the segment and the sequence m i are combined into a first check sequence
  • the first codeword sequence including:
  • the series of segments and segment I m m I sequence corresponding Hash value output of the encoder is input to the segment corresponding to the sequence of m I Hash encoder generating a first parity sequence; wherein the segment sequence of m
  • the output value of the Hash encoder corresponding to i is a preset value.
  • the first encoder is a hash encoder
  • the segment according to the segment of the sequence m i and m i of the first sequence corresponding to the encoder generates a first check sequence, the segment and the sequence m i are combined into a first check sequence
  • the first codeword sequence including:
  • the Hash Encoder corresponding to the segment sequence m i and the segment sequence m i-1 Inputting the output value of the Hash Encoder corresponding to the segment sequence m i and the segment sequence m i-1 to the Hash encoder corresponding to the segment sequence m i to generate a first check sequence;
  • the output value of the Hash encoder corresponding to the segment sequence m i-1 is a preset value.
  • the segmentation policy is any one of the following:
  • Equal division strategy non-division strategy, inter-segment overlap strategy, inter-segment non-overlapping strategy, sequential division strategy, out-of-order division strategy, all division strategy and partial division strategy.
  • the embodiment of the present application further discloses a decoding method based on polarization code encoding, including:
  • the demodulated sequence is subjected to continuous deletion list SCL decoding to obtain a codeword sequence C j of the jth segment; 1 ⁇ j ⁇ I and I>1; I is a segmentation strategy The number of corresponding segments;
  • paragraph j corresponding to the first decoder codeword sequence C j check, if the check is not passed, terminating decoding; paragraph j corresponding to a first decoder and The first encoder of the jth segment of the transmitting end corresponds.
  • the method further includes:
  • the demodulated sequence is SCL-decoded to obtain a codeword sequence C j+1 of the j+1th segment;
  • the codeword sequence C j+1 is verified according to the first decoder corresponding to the j+1th segment until the j+1th codeword sequence check fails or the first segment codeword sequence The verification passed.
  • the verifying, by the first decoder corresponding to the j+1th segment, the codeword sequence C j+1 including:
  • the method further includes:
  • the reserved Q is according to the second decoder pair corresponding to the second encoder.
  • the codeword sequence outputted by the path is verified, and the first path sequence that passes the check is used as the decoding output. Otherwise, the sequence in the path with the largest path metric value in the reserved Q path is used as the decoding output.
  • Q ⁇ L and L is a preset number of paths.
  • a polarization code encoding apparatus including:
  • a segmentation module configured to segment the information sequence to be encoded according to the segmentation policy confirmed by the transmitting and receiving parties, to generate a segmentation sequence m i ; 1 ⁇ i ⁇ I and I>1;
  • Combining module configured for any of a series of segments m i, m i, according to the sequence of the segment and the first segment sequence m i corresponding to the encoder generates a first check sequence, the sequence segment and m i of said first composition into a first sequence of parity codeword sequence;
  • an encoding module configured to combine the first codeword sequences to obtain a second codeword sequence, and perform polarization code encoding on the second codeword sequence.
  • the segmentation module is further configured to generate, according to the information sequence to be encoded and the second encoder, before segmenting the information sequence to be encoded according to the segmentation policy that has been confirmed by the transmitting and receiving parties Second check sequence
  • the segmentation module is specifically configured to: after combining the information sequence to be encoded and the second check sequence, use the segmentation strategy to generate one segment sequence m i .
  • the first encoder is a linear encoder or a nonlinear encoder
  • the second encoder is a linear encoder or a nonlinear encoder
  • the linear encoder is a CRC encoder; and the nonlinear encoder is a hash encoder.
  • the first encoder is a hash encoder
  • the composition module is configured to: segment the input sequence the output value m i and m i the series of segments corresponding to segment Hash encoder corresponding to the sequence m i Hash encoder generates a first correction
  • the sequence of the Hash encoder corresponding to the segment sequence m i is a preset value.
  • the first encoder is a hash encoder
  • the combining module is specifically configured to: input an output value of the Hash encoder corresponding to the segment sequence m i and the segment sequence m i-1 to a Hash encoder corresponding to the segment sequence m i to generate a a check sequence; wherein, when the segment sequence m i-1 is the first segment sequence, the output value of the Hash encoder corresponding to the segment sequence m i-1 is a preset value.
  • the segmentation policy is any one of the following:
  • Equal division strategy non-division strategy, inter-segment overlap strategy, inter-segment non-overlapping strategy, sequential division strategy, out-of-order division strategy, all division strategy and partial division strategy.
  • the embodiment of the present application discloses a decoding apparatus based on polarization code encoding, including:
  • a demodulation module configured to demodulate the sequence encoded by the received polarization code
  • Decoding module according to the sender and receiver segment strategy confirmed, the demodulated sequence of consecutive deletions list SCL decoding a codeword sequence obtained in paragraph C j j; 1 ⁇ j ⁇ I and I>1; I is the number of segments corresponding to the segmentation strategy;
  • a first check module configured to perform according to paragraph j corresponding to the first decoder codeword sequence C j check, if the check is not passed, terminating decoding; paragraph j
  • the corresponding first decoder corresponds to the first encoder of the jth segment of the transmitting end.
  • the first verification module is further configured to:
  • the demodulated sequence is SCL-decoded to obtain a codeword sequence C j+1 of the j+1th segment;
  • the codeword sequence C j+1 is verified according to the first decoder corresponding to the j+1th segment until the j+1th codeword sequence check fails or the first segment codeword sequence The verification passed.
  • the first verification module is specifically configured to:
  • the method further includes: a second verification module
  • the second check module is configured to: after the SCL decoding of the demodulated sequence to obtain the last code subsequence, if there are still reserved Q paths, according to the second encoder
  • the second decoder checks the sequence of code words output by the reserved Q path, and outputs the first path sequence that passes the check as a decoding output. Otherwise, the Q path to be reserved has the largest path metric.
  • the sequence in the path of the value is output as a decoding, where Q ⁇ L and L is a predetermined number of paths.
  • the embodiment of the present application further discloses a polarization code encoding apparatus, including a processor, a memory, and a transceiver;
  • a processor that reads a program in memory and performs the following procedures:
  • the processor is further configured to:
  • the processor is specifically configured to:
  • the segmentation strategy is used to generate one segment sequence m i .
  • the first encoder is a linear encoder or a nonlinear encoder
  • the second encoder is a linear encoder or a nonlinear encoder
  • the linear encoder is a CRC encoder; and the nonlinear encoder is a hash encoder.
  • the first encoder is a hash encoder
  • the processor is specifically configured to:
  • the series of segments and segment I m m I sequence corresponding Hash value output of the encoder is input to the segment corresponding to the sequence of m I Hash encoder generating a first parity sequence; wherein the segment sequence of m
  • the output value of the Hash encoder corresponding to i is a preset value.
  • the first encoder is a hash encoder
  • the processor is specifically configured to:
  • the Hash Encoder corresponding to the segment sequence m i and the segment sequence m i-1 Inputting the output value of the Hash Encoder corresponding to the segment sequence m i and the segment sequence m i-1 to the Hash encoder corresponding to the segment sequence m i to generate a first check sequence;
  • the output value of the Hash encoder corresponding to the segment sequence m i-1 is a preset value.
  • the segmentation policy is any one of the following:
  • Equal division strategy non-division strategy, inter-segment overlap strategy, inter-segment non-overlapping strategy, sequential division strategy, out-of-order division strategy, all division strategy and partial division strategy.
  • the embodiment of the present application further discloses a decoding apparatus based on polarization code encoding, including a processor, a memory, and a transceiver;
  • a processor that reads a program in memory and performs the following procedures:
  • the processor is further configured to:
  • the demodulated sequence is SCL-decoded to obtain a codeword sequence Cj+1 of the j+1th segment; and corresponding to the j+1th segment.
  • the first decoder checks the codeword sequence Cj+1 until the j+1th codeword sequence check fails or the first segment codeword sequence check passes.
  • the processor is specifically configured to:
  • the processor is further configured to:
  • the reserved Q is according to the second decoder pair corresponding to the second encoder.
  • the codeword sequence outputted by the path is verified, and the first path sequence that passes the check is used as the decoding output. Otherwise, the sequence in the path with the largest path metric value in the reserved Q path is used as the decoding output.
  • Q ⁇ L and L is a preset number of paths.
  • the embodiment of the present application discloses a readable storage medium, including program code, when the program code is run on a computing device, the program code is used to enable the computing device to perform the first The steps of the method, or the steps of the method of the second aspect.
  • the method and device for encoding a coded code include: segmenting the information sequence to be coded according to the segmentation policy confirmed by the transmitting and receiving parties, and generating one segment sequence m i ; 1 ⁇ i ⁇ I and I>1; for any of a series of segments m i, m i, according to the sequence of the segment and the first segment sequence m i corresponding to the encoder generates a first check sequence, the sequence segment and m i of said first composition into a first sequence of parity codeword sequence; the I th first code word sequence obtained by combining a second codeword sequence, and the second polarization codeword sequence code encoding.
  • the embodiment of the present application divides the information sequence to be encoded into one segment sequence m i , and generates a corresponding check sequence for any segment sequence m i , so that the decoding can be performed according to the segment.
  • segment decoding sections strategy and check on the decoded segment sequence m i obtained according to the check sequence segment corresponding to the sequence m i, in the case where the check does not pass, the decoding is terminated, since At the time of decoding, any segment sequence m i is checked, and if the verification fails, the decoding is terminated instead of being verified after decoding the entire information sequence. If the test fails, the decoding is terminated, so that not only the false alarm rate and the error block rate can be reduced, but also the decoding delay can be reduced.
  • FIG. 1 is a schematic diagram of a CRC-assisted polarization code encoding code in the prior art
  • FIG. 2 is a schematic diagram of a PC-assisted polarization code encoding code in the prior art
  • FIG. 3 is a schematic diagram of a hash-assisted polarization code encoding code in the prior art
  • FIG. 4 is a schematic diagram of a polarization code encoding process according to Embodiment 1 of the present application.
  • FIG. 5A is a schematic diagram of a polarization code encoding according to Embodiment 2 of the present application.
  • FIG. 5B is a schematic diagram of a polarization code decoding according to Embodiment 2 of the present application.
  • FIG. 6A is a schematic diagram of a polarization code encoding according to Embodiment 3 of the present application.
  • FIG. 6B is a schematic diagram of a polarization code decoding according to Embodiment 3 of the present application.
  • FIG. 7 is a schematic diagram of a polarization code encoding according to Embodiment 4 of the present application.
  • FIG. 8A is a schematic diagram of a polarization code encoding according to Embodiment 5 of the present application.
  • FIG. 8B is a schematic diagram of a polarization code decoding according to Embodiment 5 of the present application.
  • FIG. 9A is a schematic diagram of a polarization code encoding according to Embodiment 6 of the present application.
  • FIG. 9B is a schematic diagram of a polarization code decoding according to Embodiment 6 of the present application.
  • FIG. 10 is a schematic diagram of a polarization code encoding according to Embodiment 7 of the present application.
  • FIG. 11 is a schematic flowchart of a polarization code decoding according to an embodiment of the present disclosure.
  • FIG. 12 is a schematic structural diagram of a first polarization code encoding apparatus according to an embodiment of the present disclosure.
  • FIG. 13 is a schematic structural diagram of a first polarization code decoding apparatus according to an embodiment of the present disclosure
  • FIG. 14 is a schematic structural diagram of a second polarization code encoding apparatus according to an embodiment of the present disclosure.
  • FIG. 15 is a schematic structural diagram of a second polarization code decoding apparatus according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic flow chart showing a method for encoding a polarization code provided by an embodiment of the present application. As shown in FIG. 4, the method may include:
  • the segmentation strategy may be an equal division strategy, a non-divisional strategy, an inter-segment overlap strategy, an inter-segment non-overlapping strategy, a sequential division strategy, an out-of-order division strategy, a full division strategy, and a partial division strategy.
  • the I segment sequence m i may be obtained by equally dividing the information sequence.
  • the information sequence may be obtained by unequal division of the information sequence, or may be obtained by dividing the information sequence according to the order, or may be obtained by dividing the information sequence according to the order, that is, the information sequence is obtained by disorderly dividing the information sequence. All the bits of the information sequence are segmented, and some bits of the information sequence may be segmented.
  • the segment sequence m i and the segment sequence m i-1 may or may not overlap, as long as the above is ensured.
  • the segmentation strategy is known to both the sender and the receiver, that is, as long as the segmentation strategy used in the encoding is guaranteed, the segmentation strategy used in the decoding is the same.
  • the information sequence may be randomly generated by the simulation device, and the data sequence carries the data to be transmitted in the process of performing actual data transmission.
  • the length of the information sequence is determined by the code length of the polarization code and the code rate. For example, in the process of performing simulation, when the code length of the polarization code is 256 bits (bits) and the code rate is 1/2, the length of the information sequence is 128 bits, and the simulation device randomly generates a sequence of information having a length of 128 bits.
  • the information sequence is taken as a sequence of information to be encoded.
  • the first encoder i corresponding to the length of the series of segments and segment sequence of m m i generates a first check sequence; may also correspond to the content segments according to sequence segment and a sequence of m i m i a first encoder, generating a first parity sequence; the first encoder may also be a sequence segment length and content of m i and m i corresponding to the series of segments, generating a first parity sequence.
  • generating a first parity sequence may correspond to the segment based on the entire sequence m i and m i in the series of segments a first encoder, generating a first parity sequence; the first encoder may also be part of the series of segments and segment sequence m i m i corresponding to generate a first check sequence.
  • any combination may be used, for example, the segment sequence m i may be preceded, the first check sequence may be followed, or may be A check sequence is in the front, and the segment sequence m i is after, as long as the combination of the transmitting and receiving parties used in the encoding is known.
  • the first codeword sequences may be combined in sequence to obtain a second codeword sequence, or the first codeword sequences may be combined in a non-sequential manner to obtain a second codeword sequence, and other sequences may be used.
  • the method combines the first codeword sequences to obtain the second codeword sequence, as long as the combination mode used in the coding is guaranteed to be the same as the combination adopted in the decoding.
  • the first codeword sequence may be parallel-transformed to obtain a second codeword sequence.
  • the second codeword sequence may be encoded by a polarization code encoder.
  • the transmitting end may store the coding matrix encoded by the polarization code, and when performing the polarization code encoding on the second codeword sequence, the second codeword sequence and the saved coding matrix may be multiplied and added in the binary domain.
  • the sequence coded by the polarization code can be obtained.
  • the process of coding the coded code is a prior art, and the process is not described in the embodiment of the present application.
  • a rate matching algorithm is pre-stored in the transmitting end. After the second codeword sequence is coded by the polarization code, the coded sequence can be rate matched according to a pre-stored rate matching algorithm. When performing rate matching, the rate matching sequence used may be selected by using a Gaussian method or other rate matching sequences that are insensitive to Signal Noise Ratio (SNR).
  • SNR Signal Noise Ratio
  • the encoded sequence can be modulated by the modulator and sent to the receiving end.
  • the first encoder in the above step S402 may be a linear encoder or a nonlinear encoder.
  • the first encoder may be a linear block code encoder, for example, the first encoder adopts a CRC (Cyclic Redundancy Check) encoder; the first encoder is also It may be a linear convolutional encoder, for example, the first encoder is a convolutional code encoder.
  • CRC Cyclic Redundancy Check
  • the first encoder may be a non-linear block code encoder.
  • the first encoder may adopt the output value of the Hash encoder corresponding to each segment sequence mi .
  • Hash encoder set value a first encoder may be a linear convolutional code encoder, e.g., a first segment encoder may be employed for each sequence m i corresponding to the output of the encoder Hash value segment sequence The output value of the Hash encoder corresponding to m i-1 .
  • the method for encoding a polarization code provided by the embodiment of the present application may be applied to a transmitting end, where the sending end may be a base station or a UE.
  • segmentation decoding can be performed according to the segmentation strategy during decoding, thereby reducing the false alarm rate and the block error rate, and also reducing the decoding delay and improving system performance.
  • the first encoder adopts a linear block code CRC encoder, as shown in FIG. 5A, which is a schematic diagram of a polarization code code provided in Embodiment 2 of the present application.
  • FIG. 5A the transmitting end First, the information sequence m to be encoded is divided into I segmentation sequences according to the segmentation strategy confirmed by the transmitting and receiving parties, and the I segment segmentation sequence is ⁇ m 1 , m 2 , . . . , m I ⁇ .
  • the CRC encoder 1 is used according to the segment sequence m 1 to generate a check sequence c 1 (not shown), and the segment sequence m 1 and the check sequence c 1 are combined to generate a code word sequence c′ 1 ;
  • the segmentation sequence m 2 employs a CRC encoder 2, generates a check sequence c 2 (not shown), combines the segment sequence m 2 and the check sequence c 2 to generate a codeword sequence c' 2 ; 3 m 3 using CRC encoder generates a parity sequence c 3 (not shown), the segment sequence and the check sequence c 3 m 3 are combined to generate a codeword sequence c '3; the segment sequence m i Using the CRC encoder i, a check sequence c i (not shown) is generated, and the segment sequence m i and the check sequence c i are combined to generate a code word sequence c' i .
  • the codeword sequence d 1 is sent to the polar code encoder for encoding.
  • the length of the Polar mother code must be an integer power of 2, and the length of the output codeword may be arbitrary, so a rate matching operation is required, that is, a shortening or puncturing operation is performed.
  • the rate matching sequence used in the rate matching operation may be obtained by using a Gaussian approximation method, or another rate matching sequence that is insensitive to SNR, and the polar encoder outputs a code sequence after rate matching.
  • the encoded sequence is modulated by the modulator and sent to the receiver on the channel.
  • the CRC encoder 1, the CRC encoder 2, and the CRC encoder i can adopt the same polynomial such as CRC-8 (the length of the CRC sequence is 8 bits), and the CRC-12 (the length of the CRC sequence is 12 bits). Bit), CRC-16 (the length of the CRC sequence is 16 bits), CRC-24 (the length of the CRC sequence is 24 bits), etc., and different polynomials can also be used.
  • CRC encoder 1 uses CRC-8.
  • the CRC encoder 2 uses CRC-12
  • the CRC encoder i uses CRC-24, as long as the polynomial used in encoding is guaranteed to be the same as the polynomial used in decoding.
  • FIG. 5B a schematic diagram of one polarization present application code decoding according to an embodiment
  • the receiving terminal after receiving a codeword sent by a transmitter 1 d, the codeword need It is sent to the demodulator for demodulation and de-rate matching.
  • the rate matching sequence used can be obtained by Gaussian method or by using Signal Noise Ratio (SNR). Sensitive other rate matching sequences.
  • the de-rate method at the receiving end corresponds to the rate matching method at the transmitting end.
  • the codeword is then fed Polar-CRC decoder in a joint decoding SCL this case, Polar-CRC decoder according to the segment joint strategy shown in FIG. 5A, first translated code sequence c '1, assuming that there are L (L ⁇ 1 and L is a preset value) paths are retained, L codewords can be obtained sequence c '1, At this time, the L code sequence c' of each of yard 1
  • the word sequence c' 1 is checked by the CRC decoder 1 corresponding to the CRC encoder 1, and if the L codeword sequences c' 1 have not passed the check of the CRC decoder 1, the decoding is considered to have failed. And terminate the decoding early. Otherwise, the CRC decoder 1 is reserved to output a path with a checksum of 0, and the decoding is continued based on these paths.
  • the Polar-CRC joint decoder performs the segmentation strategy shown in FIG. 5A and decodes the codeword sequence c' 2 based on the path that has passed the verification, each path at this time is verified. If the check passes, the CRC decoder 2 is left to output a path with a checksum of 0, and the decoding is continued based on these paths.
  • the Polar-CRC joint decoder converts the codeword sequence c' i based on the segmentation strategy shown in FIG. 5A and based on the path that has passed the check, it is assumed that there are Q (Q ⁇ L) paths reserved at this time.
  • Q can be obtained a code sequence c 'i, at this time, the Q-code word sequence c' i of each code sequence c 'i by each CRC coder corresponding to the i i a CRC decoder verify, if the Q code sequence c i in the sequence having the largest path metric value in the path "i did not pass the check, CRC decoder i, the Q output of the codeword sequence c 'as a decoding output . Otherwise, the sequence of the first of the Q codeword sequences c'i that is checked by the CRC decoder 1 is used as the decoded output.
  • the first encoder uses a non-linear block code hash coder, as shown in FIG. 6A, which is a schematic diagram of a polarization code code provided in Embodiment 3 of the present application.
  • the information sequence m to be encoded is first divided into I segmentation sequences according to the segmentation strategy confirmed by the transmitting and receiving parties, and the segmentation sequence of the I segment is ⁇ m 1 , m 2 , . . . , m I ⁇ .
  • the hash sequence h 1 (not shown) is generated by using the hash encoder 1 and the truncation function T1 according to the segment sequence m 1 and the output value S 1 of the hash encoder 1 known by both the transmitting and receiving parties, and then the hash sequence h 1 (not shown) is generated.
  • the segmentation sequence m 1 and the hash sequence h 1 are combined to generate a codeword sequence c' 1 .
  • the segment sequence m 1 is converted into a decimal value input Hash encoder 1 , and on the other hand, the output value S 1 of the Hash encoder 1 known to the transmitting and receiving parties is input into the Hash code. And generating an output value of the Hash Encoder 1, and then converting the output value into a bit stream, and intercepting part or all of the bit stream, so as the hash sequence h 1 corresponding to the information sequence, the segment sequence m 1 is combined with the hash sequence h 1 to generate a codeword sequence c' 1 .
  • the bit stream When part or all of the bit stream is intercepted, it may be intercepted according to a certain method. For example, if the length of the Hash sequence is set, the Hash sequence corresponding to the length may be intercepted in the bit stream, and the interception may be performed from the set position.
  • the fixed position may be the first position, or the first position, and may be intercepted from the first position, or may be intercepted from the end. As long as the interception mode of the hash sequence used in encoding is guaranteed, it is the same as the interception method used in decoding.
  • the length of the hash sequence obtained in the embodiment of the present application is no more than 32 bits.
  • the length of the hash sequence may be, for example, 8 bits, or 32 bits, or the like.
  • the hash encoder 2 and the truncation function T2 are used according to the segment sequence m 2 and the output value S 2 of the Hash encoder 2 known by both the transmitting and receiving parties, thereby generating a hash sequence h 2 (not shown).
  • the segmentation sequence m 2 and the hash sequence h 2 are then combined to generate a codeword sequence c' 2 .
  • the hash sequence 3 and the truncation function T3 are used according to the segment sequence m 3 and the output value S 3 of the Hash encoder 3 known to both the transmitting and receiving parties, thereby generating a hash sequence h 3 (not shown), and then dividing The segment sequence m 3 and the hash sequence h 3 are combined to generate a codeword sequence c' 3 .
  • the hash sequence i and the truncation function Ti are used according to the segment sequence mi and the output value S i of the Hash encoder 3 known to both the transmitting and receiving parties, thereby generating a hash sequence h i (not shown), and then dividing The segment sequence m i and the hash sequence h i are combined to generate a codeword sequence c' i .
  • the codeword sequence d 1 is sent to the polar code encoder for encoding.
  • the length of the Polar mother code must be an integer power of 2, and the length of the output codeword may be arbitrary, so a rate matching operation is required, that is, a shortening or puncturing operation is performed.
  • the rate matching sequence used in the rate matching operation may be obtained by using a Gaussian approximation method, or another rate matching sequence that is insensitive to SNR, and the polar encoder outputs a code sequence after rate matching.
  • the encoded sequence is modulated by the modulator and sent to the receiver on the channel.
  • the Hash coder 1, the Hash coder 2, and the Hash coder i may be the same.
  • the Hash sequence generated by the Hash coder 1, the Hash coder 2, and the Hash coder i is 8 bits long.
  • the hash encoder 1, the hash encoder 2, and the hash encoder i may be different.
  • the hash sequences generated by the hash encoder 1 and the hash encoder 2 are all 8 bits long, and the hash encoder i generates the hash sequence.
  • the length of the Hash sequence is 32 bits, as long as the Hash encoder used in encoding is guaranteed to be the same as the Hash encoder used in decoding.
  • the bit number of the corresponding Hash encoder intercepted by the truncation function T1, the truncation function T2, and the truncation function Ti may be the same or different, as long as both the transmitting and receiving parties are known.
  • the hash coding feature is a change of the v-bit state corresponding to the segment sequence, which causes the v-bit state corresponding to the next segment sequence to be irregular, that is, an avalanche. Effect, so the hash rate can be further reduced by hash coding.
  • 6B the present application diagram of a polarization code decoding according to an embodiment, can be seen from 6B, the receiving terminal after receiving a codeword sent by a transmitter 1 d, the codeword need It is sent to the demodulator for demodulation and de-rate matching.
  • the rate matching sequence used can be obtained by Gaussian method or by using Signal Noise Ratio (SNR). Sensitive other rate matching sequences.
  • the de-rate method at the receiving end corresponds to the rate matching method at the transmitting end.
  • the codeword is then fed Polar-Hash SCL joint decoder for decoding at this time, Polar-Hash combined policies according to the segment decoder shown in FIG. 6A, first translated code sequence c '1, assuming that there are L (L ⁇ 1 and L is a preset value) paths are retained, L codewords can be obtained sequence c '1, At this time, the L code sequence c' of each of yard 1
  • the word sequence c' 1 is checked by the Hash decoder 1 corresponding to the Hash Encoder 1, and if the L codeword sequences c' 1 are not verified by the Hash decoder 1, the decoding is considered to be unsuccessful. And terminate the decoding early. Otherwise, the Hash decoder 1 is reserved for the same path as the original Hash check segment in the sequence, and the decoding is continued based on these paths.
  • the Polar-Hash joint decoder is based on the segmentation strategy shown in FIG. 6A and the codeword sequence c' 2 is decoded based on the path that has passed the verification, each path at this time is verified. If the check passes, the Hash decoder 2 is reserved for the same path as the original Hash check segment in the sequence, and the decoding is continued based on these paths.
  • the first encoder uses a non-linear convolutional code hash encoder.
  • FIG. 7 a schematic diagram of a polarization code encoding provided in Embodiment 4 of the present application is shown in FIG.
  • the transmitting end first divides the information sequence m to be encoded into one segment sequence according to the segmentation strategy confirmed by the transmitting and receiving parties, and records the I segment segment sequence as ⁇ m 1 , m 2 , . . . , m I ⁇ .
  • the hash sequence h 1 (not shown) is generated by using the hash encoder 1 and the truncation function T1 according to the segment sequence m 1 and the output value S 1 of the hash encoder 1 known by both the transmitting and receiving parties, and then the hash sequence h 1 (not shown) is generated.
  • the segmentation sequence m 1 and the hash sequence h 1 are combined to generate a codeword sequence c' 1 .
  • the segment sequence m 1 is converted into a decimal value input Hash encoder 1 , and on the other hand, the output value S 1 of the Hash encoder 1 known to the transmitting and receiving parties is input into the Hash code. 1 , thereby generating the output value S 2 of the Hash Encoder 1, and then converting the output value S 2 into a bit stream, and intercepting part or all of the bit stream, so as the hash sequence h 1 corresponding to the information sequence,
  • the segmentation sequence m 1 and the hash sequence h 1 are combined to generate a codeword sequence c' 1 , thereby further reducing the false alarm rate.
  • the bit stream When part or all of the bit stream is intercepted, it may be intercepted according to a certain method. For example, if the length of the Hash sequence is set, the Hash sequence corresponding to the length may be intercepted in the bit stream, and the interception may be performed from the set position.
  • the fixed position may be the first position, or the first position, and may be intercepted from the first position, or may be intercepted from the end. As long as the interception mode of the hash sequence used in encoding is guaranteed, the interception method used in decoding is the same.
  • the length of the hash sequence obtained in the embodiment of the present application is no more than 32 bits.
  • the length of the hash sequence may be, for example, 8 bits, or 32 bits, or the like.
  • the Hash encoder 2 and the truncation function T2 are employed in accordance with the segmentation sequence m 2 and the output value S 2 of the Hash Encoder 1, thereby generating a hash sequence h 2 (not shown), followed by the segmentation sequence m 2 and the hash sequence. h 2 is combined to generate a codeword sequence c' 2 .
  • the segment sequence m 2 is converted into a decimal value input Hash encoder 2
  • the output value S 2 of the Hash encoder 1 is input to the Hash encoder 2, thereby generating hash 2 encoder output value S 3, S 3 and the output value is converted to a bit stream, the bit stream and intercept some or all of such information as the sequence corresponding to the sequence of hash H 2, the segment sequence m 2 Combined with the hash sequence h 2 , a codeword sequence c' 2 is generated, thereby further reducing the false alarm rate.
  • the Hash encoder 3 and the truncation function T3 are employed according to the segmentation sequence m 3 and the output value S 3 of the Hash Encoder 2, thereby generating a hash sequence h 3 (not shown), after which the segment sequence m 3 and the hash sequence are generated. h 3 is combined to generate a codeword sequence c' 3 .
  • the segment sequence m 3 is converted into a decimal value input Hash encoder 3, and on the other hand, the output value S 3 of the Hash encoder 2 is input to the Hash encoder 3, thereby generating The output value S 4 of the Hash encoder 3 (not shown), and then converting the output value S 4 into a bit stream, and intercepting part or all of the bit stream, so as the hash sequence h 3 corresponding to the information sequence,
  • the segmentation sequence m 3 and the hash sequence h 3 are combined to generate a codeword sequence c' 3 , thereby further reducing the false alarm rate.
  • the hash encoder i and the truncation function Ti are used according to the segment sequence mi and the output value S i of the hash encoder i-1, thereby generating a hash sequence h i (not shown), and then the segment sequence mi Combining with the hash sequence h i generates a codeword sequence c' i , thereby further reducing the false alarm rate.
  • the codeword sequence d 1 is sent to the polar code encoder for encoding.
  • the length of the Polar mother code must be an integer power of 2, and the length of the output codeword may be arbitrary, so a rate matching operation is required, that is, a shortening or puncturing operation is performed.
  • the rate matching sequence used in the rate matching operation may be obtained by using a Gaussian approximation method, or another rate matching sequence that is insensitive to SNR, and the polar encoder outputs a code sequence after rate matching.
  • the encoded sequence is modulated by the modulator and sent to the receiver on the channel.
  • the Hash coder 1, the Hash coder 2, and the Hash coder i may be the same.
  • the Hash sequence generated by the Hash coder 1, the Hash coder 2, and the Hash coder i is 8 bits long.
  • the hash encoder 1, the hash encoder 2, and the hash encoder i may be different.
  • the hash sequences generated by the hash encoder 1 and the hash encoder 2 are all 8 bits long, and the hash encoder i generates the hash sequence.
  • the length of the Hash sequence is 32 bits, as long as the Hash encoder used in encoding is guaranteed to be the same as the Hash encoder used in decoding.
  • the bit number of the corresponding Hash encoder intercepted by the truncation function T1, the truncation function T2, and the truncation function Ti may be the same or different, as long as both the transmitting and receiving parties are known.
  • the hash coding feature is a change of the v-bit state corresponding to the segment sequence, which causes the v-bit state corresponding to the next segment sequence to be irregular, that is, an avalanche. Effect, so the hash rate can be further reduced by hash coding.
  • the decoding process corresponding to the encoding process shown in Fig. 7 is similar to the decoding process shown in Fig. 6B, and will not be described again here.
  • a second encoder may also be included.
  • the second encoder may be a linear encoder or a non-linear encoder.
  • the second encoder may be a linear block code encoder, for example, the second encoder employs a CRC encoder; and the second encoder may also be a linear convolutional encoder, for example, The second encoder is a convolutional code encoder.
  • the second encoder may be a nonlinear block code encoder, and the second encoder may also be a nonlinear convolutional code encoder.
  • the first encoder and the second encoder both use a linear block code CRC encoder, as shown in FIG. 8A, which is a schematic diagram of a polarization code code provided in Embodiment 5 of the present application, and FIG. 8A as can be seen, the information transmitting terminal sequence of m first be encoded after encoding by the encoder to obtain a total CRC codeword sequence e 1, and then the sender and receiver in accordance with the confirmed sequence segment strategy codeword I e 1 be divided into segments The sequence, the segmentation sequence of the I segment is ⁇ m 1 , m 2 , ..., m I ⁇ .
  • the segmentation policy codeword sequence e 1 that has been confirmed by the transmitting and receiving parties is divided into one segment sequence, only the information sequence in the codeword sequence e 1 can be divided according to the segmentation strategy confirmed by both the transmitting and receiving parties.
  • the codeword sequence e 1 may be segmented according to the segmentation policy confirmed by both the transmitting and receiving parties, that is, the information sequence and the check sequence in the codeword sequence e 1 are segmented according to the segmentation strategy confirmed by both the transmitting and receiving parties.
  • the segmentation strategy adopted during encoding is guaranteed, it is the same as the segmentation strategy used in decoding.
  • segmentation of a codeword sequence according to both send and receive e 1 confirmed segment strategy, generates sequence m i I segments, which segments I sequence may be a m i e 1 codeword sequence aliquoted
  • the obtained code sequence e 1 may be obtained by unequal division, or the code word sequence e 1 may be divided according to the order, or the code word sequence e 1 may be divided according to the order.
  • the upcoming codeword sequence scrambled e obtained by dividing a possible codeword sequence all bits e 1 participation segment, also 1 part e codeword sequence bits may be involved in the segment, in addition, the segment sequence m i
  • the segmentation sequence m i-1 may or may not overlap, as long as the segmentation strategy is ensured to be known by both the transmitting and receiving parties, that is, as long as the segmentation strategy used in encoding is guaranteed, and the segmentation used in decoding.
  • the segment strategy is the same.
  • the CRC encoder 1 is used according to the segment sequence m 1 to generate a check sequence c 1 (not shown), and the segment sequence m 1 and the check sequence c 1 are combined to generate a code word sequence c′ 1 ;
  • the segmentation sequence m 2 employs a CRC encoder 2, generates a check sequence c 2 (not shown), combines the segment sequence m 2 and the check sequence c 2 to generate a codeword sequence c' 2 ; 3 m 3 using CRC encoder generates a parity sequence c 3 (not shown), the segment sequence and the check sequence c 3 m 3 are combined to generate a codeword sequence c '3; the segment sequence m i Using the CRC encoder i, a check sequence c i (not shown) is generated, and the segment sequence m i and the check sequence c i are combined to generate a code word sequence c' i .
  • the codeword sequence c' 2 , the codeword sequence c' 2 , the codeword sequence c' 3 and the codeword sequence c' i are combined according to the combination confirmed by the transmitting and receiving parties to obtain the codeword sequence d 1 , and finally The codeword sequence d 1 is sent to the polar code encoder for encoding.
  • the length of the Polar mother code must be an integer power of 2, and the length of the output codeword may be arbitrary, so a rate matching operation is required, that is, a shortening or puncturing operation is performed.
  • the rate matching sequence used in the rate matching operation may be obtained by using a Gaussian approximation method, or another rate matching sequence that is insensitive to SNR, and the polar encoder outputs a code sequence after rate matching.
  • the encoded sequence is modulated by the modulator and sent to the receiver on the channel.
  • the CRC total encoder and the CRC encoder corresponding to each segment sequence may be taken into consideration, and only the CRC total encoder may be considered, or only the CRC encoder may be considered.
  • the CRC encoder corresponding to each segment sequence may also consider only the partial CRC encoder corresponding to the segment sequence.
  • 8B the present application diagram of a polarization code decoding according to an embodiment, can be seen from 8B, the receiving terminal after receiving a codeword sent by a transmitter 1 d, the codeword need The demodulator is sent to demodulate and de-rate matched, and then the codeword is sent to the Polar-CRC joint decoder for SCL decoding. At this time, the Polar-CRC joint decoder is according to FIG. 8A.
  • the codeword sequence c' 1 is first decoded. Assuming that L (L ⁇ 1 and L is the preset value), the path is retained, then L codeword sequences c' 1 can be obtained.
  • sequence of L codewords c ' is a sequence of each codeword c' are 1 1 by the CRC coder decoder corresponding to the CRC data is checked, if the L code sequence c 'by 1 no The check of the CRC decoder 1 considers that the decoding has failed and terminates the decoding early. Otherwise, the CRC decoder 1 is reserved to output a path with a checksum of 0, and the decoding is continued based on these paths.
  • the Polar-CRC joint decoder performs the segmentation strategy shown in FIG. 8A and decodes the codeword sequence c' 2 based on the path that has passed the verification, each path at this time is verified. If the check passes, the CRC decoder 2 is left to output a path with a checksum of 0, and the decoding is continued based on these paths.
  • the Polar-CRC joint decoder converts the codeword sequence c' i based on the segmentation strategy shown in FIG. 8A and based on the path that has passed the check, it is assumed that there are Q (Q ⁇ L) paths reserved at this time.
  • Q can be obtained a code sequence c 'i, at this time, the Q-code word sequence c' i of each code sequence c 'i by each CRC coder corresponding to the i i a CRC decoder verify, if the Q code sequence c i in the sequence having the largest path metric value in the path "i did not pass the check, CRC decoder i, the Q output of the codeword sequence c 'as a decoding output .
  • the CRC decoder i verifies the Q codeword sequence c' i , in order to improve the accuracy of the false alarm rate, it is still necessary to pass the Q codeword sequences c' i through the CRC total encoder. Corresponding CRC total decoder performs verification. If the check passes, the first sequence of the Q codeword sequences c' i is outputted as a decoding output by the CRC total decoder. Otherwise, Q codes are used. word sequence c 'i as a decoding output sequence having the maximum path metric value in the path.
  • the first encoder uses a nonlinear block code Hash encoder
  • the second encoder uses a linear block code CRC encoder, as shown in FIG. 9A, which is a pole provided in Embodiment 6 of the present application.
  • schematic code encoding can be seen from Figures 9A, the transmitting side first m sequence information to be encoded by a codeword sequence segment strategy total CRC encoder for encoding a codeword sequence obtained after e 1, and then transmitted and received in accordance with the two sides have confirmed e 1 will be divided into I segment sequences, and the I segment segment sequence is ⁇ m 1 , m 2 , . . . , m I ⁇ .
  • the segmentation policy codeword sequence e 1 that has been confirmed by the transmitting and receiving parties is divided into one segment sequence, only the information sequence in the codeword sequence e 1 can be divided according to the segmentation strategy confirmed by both the transmitting and receiving parties.
  • the codeword sequence e 1 may be segmented according to the segmentation policy confirmed by both the transmitting and receiving parties, that is, the information sequence and the check sequence in the codeword sequence e 1 are segmented according to the segmentation strategy confirmed by both the transmitting and receiving parties.
  • the segmentation strategy adopted during encoding is guaranteed, it is the same as the segmentation strategy used in decoding.
  • segmentation of a codeword sequence according to both send and receive e 1 confirmed segment strategy, generates sequence m i I segments, which segments I sequence may be a m i e 1 codeword sequence aliquoted
  • the obtained code sequence e 1 may be obtained by unequal division, or the code word sequence e 1 may be divided according to the order, or the code word sequence e 1 may be divided according to the order.
  • the upcoming codeword sequence scrambled e obtained by dividing a possible codeword sequence all bits e 1 participation segment, also 1 part e codeword sequence bits may be involved in the segment, in addition, the segment sequence m i
  • the segmentation sequence m i-1 may or may not overlap, as long as the segmentation strategy is ensured to be known by both the transmitting and receiving parties, that is, as long as the segmentation strategy used in encoding is guaranteed, and the segmentation used in decoding.
  • the segment strategy is the same.
  • the hash sequence h 1 (not shown) is generated by using the hash encoder 1 and the truncation function T1 according to the segment sequence m 1 and the output value S 1 of the hash encoder 1 known by both the transmitting and receiving parties, and then the hash sequence h 1 (not shown) is generated.
  • the segmentation sequence m 1 and the hash sequence h 1 are combined to generate a codeword sequence c' 1 .
  • the segment sequence m 1 is converted into a decimal value input Hash encoder 1 , and on the other hand, the output value S 1 of the Hash encoder 1 known to the transmitting and receiving parties is input into the Hash code. And generating an output value of the Hash Encoder 1, and then converting the output value into a bit stream, and intercepting part or all of the bit stream, so as the hash sequence h 1 corresponding to the information sequence, the segment sequence m 1 is combined with the hash sequence h 1 to generate a codeword sequence c' 1 .
  • the bit stream When part or all of the bit stream is intercepted, it may be intercepted according to a certain method. For example, if the length of the Hash sequence is set, the Hash sequence corresponding to the length may be intercepted in the bit stream, and the interception may be performed from the set position.
  • the fixed position may be the first position, or the first position, and may be intercepted from the first position, or may be intercepted from the end. As long as the interception mode of the hash sequence used in encoding is guaranteed, the interception method used in decoding is the same.
  • the length of the hash sequence obtained in the embodiment of the present application is no more than 32 bits.
  • the length of the hash sequence may be, for example, 8 bits, or 32 bits, or the like.
  • the hash encoder 2 and the truncation function T2 are used according to the segment sequence m 2 and the output value S 2 of the Hash encoder 2 known by both the transmitting and receiving parties, thereby generating a hash sequence h 2 (not shown).
  • the segmentation sequence m 2 and the hash sequence h 2 are then combined to generate a codeword sequence c' 2 .
  • the hash sequence 3 and the truncation function T3 are used according to the segment sequence m 3 and the output value S 3 of the Hash encoder 3 known to both the transmitting and receiving parties, thereby generating a hash sequence h 3 (not shown), and then dividing The segment sequence m 3 and the hash sequence h 3 are combined to generate a codeword sequence c' 3 .
  • the hash sequence i and the truncation function Ti are used according to the segment sequence mi and the output value S i of the Hash encoder 3 known to both the transmitting and receiving parties, thereby generating a hash sequence h i (not shown), and then dividing The segment sequence m i and the hash sequence h i are combined to generate a codeword sequence c' i .
  • the codeword sequence d 1 is sent to the polar code encoder for encoding.
  • the length of the Polar mother code must be an integer power of 2, and the length of the output codeword may be arbitrary, so a rate matching operation is required, that is, a shortening or puncturing operation is performed.
  • the rate matching sequence used in the rate matching operation may be obtained by using a Gaussian approximation method, or another rate matching sequence that is insensitive to SNR, and the polar encoder outputs a code sequence after rate matching.
  • the encoded sequence is modulated by the modulator and sent to the receiver on the channel.
  • the Hash coder 1, the Hash coder 2, and the Hash coder i may be the same.
  • the Hash sequence generated by the Hash coder 1, the Hash coder 2, and the Hash coder i is 8 bits long.
  • the hash encoder 1, the hash encoder 2, and the hash encoder i may be different.
  • the hash sequences generated by the hash encoder 1 and the hash encoder 2 are all 8 bits long, and the hash encoder i generates the hash sequence.
  • the length of the Hash sequence is 32 bits, as long as the Hash encoder used in encoding is guaranteed to be the same as the Hash encoder used in decoding.
  • the bit number of the corresponding Hash encoder intercepted by the truncation function T1, the truncation function T2, and the truncation function Ti may be the same or different, as long as both the transmitting and receiving parties are known.
  • the hash coding feature is a change of the v-bit state corresponding to the segment sequence, which causes the v-bit state corresponding to the next segment sequence to be irregular, that is, an avalanche. Effect, so the hash rate can be further reduced by hash coding.
  • FIG. 9B is a schematic diagram of a polarization code decoding provided by an embodiment of the present application.
  • the receiving end after receiving the codeword d 1 sent by the transmitting end, the receiving end needs to obtain the codeword. It is sent to the demodulator for demodulation and de-rate matching.
  • the rate matching sequence used can be obtained by Gaussian method or by using Signal Noise Ratio (SNR). Sensitive other rate matching sequences.
  • SNR Signal Noise Ratio
  • the de-rate method at the receiving end corresponds to the rate matching method at the transmitting end.
  • the codeword is then fed Polar-Hash SCL joint decoder for decoding at this time, Polar-Hash combined policies decoder according to the segment shown in FIG. 9A, first translated code sequence c '1, assuming that there are L (L ⁇ 1 and L is a preset value) paths are retained, L codewords can be obtained sequence c '1, At this time, the L code sequence c' of each of yard 1
  • the word sequence c' 1 is checked by the Hash decoder 1 corresponding to the Hash Encoder 1, and if the L codeword sequences c' 1 are not verified by the Hash decoder 1, the decoding is considered to be unsuccessful. And terminate the decoding early. Otherwise, the Hash decoder 1 is reserved for the same path as the original Hash check segment in the sequence, and the decoding is continued based on these paths.
  • the Polar-Hash joint decoder performs the segmentation strategy shown in FIG. 9A and decodes the codeword sequence c' 2 based on the path that has passed the verification, each path at this time is verified. If the check passes, the paths in the Hash decoder 2 that are equal to the original Hash check segment are reserved, and the decoding is continued based on these paths.
  • the Hash decoder i passes the Q codeword sequence c' i to pass the verification, in order to improve the accuracy of the false alarm rate, it is still necessary to pass the Q codeword sequences c' i through the CRC total encoder.
  • Corresponding CRC total decoder performs verification. If the check passes, the first sequence of the Q codeword sequences c' i is outputted as a decoding output by the CRC total decoder. Otherwise, Q codes are used. word sequence c 'i as a decoding output sequence having the maximum path metric value in the path.
  • the first encoder uses a nonlinear convolutional code hash coder
  • the second coder uses a linear block code CRC encoder, as shown in FIG. 10
  • the information transmitting terminal sequence of m to be encoded by the first CRC coder total codeword sequence obtained by encoding e 1 then according to the segment strategy codeword recognized both transceivers
  • the sequence e 1 will be divided into I segment sequences, and the segment I segment sequence is ⁇ m 1 , m 2 , . . . , m I ⁇ .
  • the hash sequence h 1 (not shown) is generated by using the hash encoder 1 and the truncation function T1 according to the segment sequence m 1 and the output value S 1 of the hash encoder 1 known by both the transmitting and receiving parties, and then the hash sequence h 1 (not shown) is generated.
  • the segmentation sequence m 1 and the hash sequence h 1 are combined to generate a codeword sequence c' 1 .
  • the segment sequence m 1 is converted into a decimal value input Hash encoder 1 , and on the other hand, the output value S 1 of the Hash encoder 1 known to the transmitting and receiving parties is input into the Hash code. 1 , thereby generating the output value S 2 of the Hash Encoder 1, and then converting the output value S 2 into a bit stream, and intercepting part or all of the bit stream, so as the hash sequence h 1 corresponding to the information sequence,
  • the segmentation sequence m 1 and the hash sequence h 1 are combined to generate a codeword sequence c' 1 , thereby further reducing the false alarm rate.
  • the bit stream When part or all of the bit stream is intercepted, it may be intercepted according to a certain method. For example, if the length of the Hash sequence is set, the Hash sequence corresponding to the length may be intercepted in the bit stream, and the interception may be performed from the set position.
  • the fixed position may be the first position, or the first position, and may be intercepted from the first position, or may be intercepted from the end. As long as the interception mode of the hash sequence used in encoding is guaranteed, the interception method used in decoding is the same.
  • the length of the hash sequence obtained in the embodiment of the present application is no more than 32 bits.
  • the length of the hash sequence may be, for example, 8 bits, or 32 bits, or the like.
  • the Hash encoder 2 and the truncation function T2 are employed in accordance with the segmentation sequence m 2 and the output value S 2 of the Hash Encoder 1, thereby generating a hash sequence h 2 (not shown), followed by the segmentation sequence m 2 and the hash sequence. h 2 is combined to generate a codeword sequence c' 2 .
  • the segment sequence m 2 is converted into a decimal value input Hash encoder 2
  • the output value S 2 of the Hash encoder 1 is input to the Hash encoder 2, thereby generating hash 2 encoder output value S 3, S 3 and the output value is converted to a bit stream, the bit stream and intercept some or all of such information as the sequence corresponding to the sequence of hash H 2, the segment sequence m 2 Combined with the hash sequence h 2 , a codeword sequence c' 2 is generated, thereby further reducing the false alarm rate.
  • the Hash encoder 3 and the truncation function T3 are employed according to the segmentation sequence m 3 and the output value S 3 of the Hash Encoder 2, thereby generating a hash sequence h 3 (not shown), after which the segment sequence m 3 and the hash sequence are generated. h 3 is combined to generate a codeword sequence c' 3 .
  • the segment sequence m 3 is converted into a decimal value input Hash encoder 3, and on the other hand, the output value S 3 of the Hash encoder 2 is input to the Hash encoder 3, thereby generating The output value S 4 of the Hash encoder 3 (not shown), and then converting the output value S 4 into a bit stream, and intercepting part or all of the bit stream, so as the hash sequence h 3 corresponding to the information sequence,
  • the segmentation sequence m 3 and the hash sequence h 3 are combined to generate a codeword sequence c' 3 , thereby further reducing the false alarm rate.
  • the hash encoder i and the truncation function Ti are used according to the segment sequence mi and the output value S i of the hash encoder i-1, thereby generating a hash sequence h i (not shown), and then the segment sequence mi Combining with the hash sequence h i generates a codeword sequence c' i , thereby further reducing the false alarm rate.
  • the codeword sequence d 1 is sent to the polar code encoder for encoding.
  • the length of the Polar mother code must be an integer power of 2, and the length of the output codeword may be arbitrary, so a rate matching operation is required, that is, a shortening or puncturing operation is performed.
  • the rate matching sequence used in the rate matching operation may be obtained by using a Gaussian approximation method, or another rate matching sequence that is insensitive to SNR, and the polar encoder outputs a code sequence after rate matching.
  • the encoded sequence is modulated by the modulator and sent to the receiver on the channel.
  • the Hash coder 1, the Hash coder 2, and the Hash coder i may be the same.
  • the Hash sequence generated by the Hash coder 1, the Hash coder 2, and the Hash coder i is 8 bits long.
  • the hash encoder 1, the hash encoder 2, and the hash encoder i may be different.
  • the hash sequences generated by the hash encoder 1 and the hash encoder 2 are all 8 bits long, and the hash encoder i generates the hash sequence.
  • the length of the Hash sequence is 32 bits, as long as the Hash encoder used in encoding is guaranteed to be the same as the Hash encoder used in decoding.
  • the bit number of the corresponding Hash encoder intercepted by the truncation function T1, the truncation function T2, and the truncation function Ti may be the same or different, as long as both the transmitting and receiving parties are known.
  • the hash coding feature is a change of the v-bit state corresponding to the segment sequence, which causes the v-bit state corresponding to the next segment sequence to be irregular, that is, an avalanche. Effect, so the hash rate can be further reduced by hash coding.
  • the decoding process corresponding to the encoding process shown in FIG. 10 is similar to the decoding process shown in FIG. 9B, and will not be described again herein.
  • the second encoder is the encoding process and the decoding process of the non-linear encoder, and the encoding process and the decoding process shown in the fifth embodiment, the sixth embodiment, and the seventh embodiment are not described herein.
  • FIG. 11 is a schematic flowchart showing a method for decoding a polarization code provided by an embodiment of the present application. As shown in FIG. 11, the method may include:
  • S1101 Perform demodulation on the sequence encoded by the received polarization code
  • S1102 Perform a continuous deletion list SCL decoding on the demodulated sequence according to the segmentation strategy confirmed by the transmitting and receiving parties to obtain a codeword sequence C j of the jth segment; 1 ⁇ j ⁇ I and I>1; The number of segments corresponding to the segment policy;
  • the method for decoding a polarization code provided by the embodiment of the present application may be applied to a receiving end, where the receiving end may be a base station or a UE.
  • the method further includes: if the codeword sequence C j is verified, performing SCL decoding on the demodulated sequence to obtain a codeword sequence C j+1 of the j+1th segment;
  • the codeword sequence C j+1 is verified according to the first decoder corresponding to the j+1th segment until the j+1th codeword sequence check fails or the first segment codeword sequence The verification passed.
  • the method further includes:
  • the reserved Q is according to the second decoder pair corresponding to the second encoder.
  • the codeword sequence outputted by the path is verified, and the first path sequence that passes the check is used as the decoding output. Otherwise, the sequence in the path with the largest path metric value in the reserved Q path is used as the decoding output.
  • Q ⁇ L and L is a preset number of paths.
  • the embodiment of the present application further provides a polarization code encoding apparatus.
  • the apparatus may include: a segmentation module 1201, configured to be coded according to a segmentation policy that has been confirmed by both the transmitting and receiving parties.
  • the information sequence is segmented to generate I segmentation sequence m i ; 1 ⁇ i ⁇ I and I >1;
  • Combining module 1202 for a series of segments for any m i, m i, according to the sequence segment and a sequence segment of said first encoder corresponding to m i, to generate a first check sequence, the segment The sequence m i and the first check sequence are combined into a first codeword sequence;
  • the encoding module 1203 is configured to combine the first codeword sequences to obtain a second codeword sequence, and perform polarization code encoding on the second codeword sequence.
  • the segmentation module 1201 is further configured to: generate a second according to the information sequence to be encoded and the second encoder, before segmenting the information sequence to be encoded according to the segmentation policy confirmed by the transmitting and receiving parties Check sequence
  • the segmentation module 1201 is specifically configured to: after combining the information sequence to be encoded and the second check sequence, use the segmentation strategy to generate one segment sequence m i .
  • the first encoder is a linear encoder or a nonlinear encoder
  • the second encoder is a linear encoder or a nonlinear encoder
  • the linear encoder is a CRC encoder; and the nonlinear encoder is a hash encoder.
  • the first encoder is a hash encoder
  • the composition module is configured to: segment the input sequence the output value m i and m i the series of segments corresponding to segment Hash encoder corresponding to the sequence m i Hash encoder generates a first correction
  • the sequence of the Hash encoder corresponding to the segment sequence m i is a preset value.
  • the first encoder is a hash encoder
  • the combining module is specifically configured to: input an output value of the Hash encoder corresponding to the segment sequence m i and the segment sequence m i-1 to a Hash encoder corresponding to the segment sequence m i to generate a a check sequence; wherein, when the segment sequence m i-1 is the first segment sequence, the output value of the Hash encoder corresponding to the segment sequence m i-1 is a preset value.
  • the segmentation policy is any one of the following:
  • Equal division strategy non-division strategy, inter-segment overlap strategy, inter-segment non-overlapping strategy, sequential division strategy, out-of-order division strategy, all division strategy and partial division strategy.
  • the embodiment of the present application further provides a polarization code decoding device.
  • the device may include:
  • the demodulation module 1301 is configured to demodulate the sequence encoded by the received polarization code
  • the decoding module 1302 is configured to perform a continuous deletion list SCL decoding on the demodulated sequence according to the segmentation policy confirmed by the transmitting and receiving parties to obtain a codeword sequence C j of the jth segment; 1 ⁇ j ⁇ I and I>1; I is the number of segments corresponding to the segmentation strategy;
  • the first decoder corresponding to the segment corresponds to the first encoder of the jth segment of the transmitting end.
  • the first verification module 1303 is further configured to:
  • the demodulated sequence is SCL-decoded to obtain a codeword sequence C j+1 of the j+1th segment;
  • the codeword sequence C j+1 is verified according to the first decoder corresponding to the j+1th segment until the j+1th codeword sequence check fails or the first segment codeword sequence The verification passed.
  • the first verification module 1303 is specifically configured to:
  • the method further includes: a second check module 1304;
  • a second check module 1304 configured to: after the SCL decoding of the demodulated sequence to obtain the last Q subsequence, if there are still reserved Q paths, according to the second encoder
  • the second decoder verifies the codeword sequence output by the reserved Q path, and uses the first path sequence that passes the check as the decoding output. Otherwise, the reserved Q path has the largest path metric value.
  • the sequence in the path is used as a decoding output, where Q ⁇ L and L is a predetermined number of paths.
  • the embodiment of the present application further provides a polarization code encoding device.
  • the device may include: a processor 1400, a memory 1401, a transceiver 1402, and a bus interface 1403.
  • the processor 1400 is responsible for managing the bus architecture and general processing, and the memory 1401 can store data used by the processor 1400 in performing operations.
  • the bus architecture may include any number of interconnected buses and bridges, specifically linked by one or more processors 1400 and various circuits of one or more memories 1401.
  • the bus architecture can also link various other circuits such as peripherals, voltage regulators, and power management circuits, which are well known in the art and, therefore, will not be further described herein.
  • the bus interface provides an interface.
  • the processor 1400 is responsible for managing the bus architecture and general processing, and the memory 1401 can store data used by the processor 1400 in performing operations.
  • the flow disclosed in the embodiment of the present application may be applied to the processor 1400 or implemented by the processor 1400.
  • each step of the signal processing flow may be completed by an integrated logic circuit of hardware in the processor 1400 or an instruction in the form of software.
  • the processor 1400 can be a general-purpose processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or a transistor logic device, and a discrete hardware component, which can be implemented or executed in the embodiment of the present application.
  • a general purpose processor can be a microprocessor or any conventional processor or the like.
  • the steps of the method disclosed in the embodiments of the present application may be directly implemented as a hardware processor, or may be performed by a combination of hardware and software modules in the processor.
  • the software module can be located in a conventional storage medium such as random access memory, flash memory, read only memory, programmable read only memory or electrically erasable programmable memory, registers, and the like.
  • the storage medium is located in the memory 1401, and the processor 1400 reads the information in the memory 1401 and completes the steps of the signal processing flow in conjunction with its hardware.
  • the processor 1400 is configured to read a program in the memory 1401 and execute:
  • processor 1400 is further configured to:
  • the processor 1400 is specifically configured to:
  • the segmentation strategy is used to generate one segment sequence m i .
  • the first encoder is a linear encoder or a nonlinear encoder
  • the second encoder is a linear encoder or a nonlinear encoder
  • the linear encoder is a CRC encoder; and the nonlinear encoder is a hash encoder.
  • the first encoder is a hash encoder
  • the processor 1400 is specifically configured to:
  • the series of segments and segment I m m I sequence corresponding Hash value output of the encoder is input to the segment corresponding to the sequence of m I Hash encoder generating a first parity sequence; wherein the segment sequence of m
  • the output value of the Hash encoder corresponding to i is a preset value.
  • the first encoder is a hash encoder
  • the processor 1400 is specifically configured to:
  • the Hash Encoder corresponding to the segment sequence m i and the segment sequence m i-1 Inputting the output value of the Hash Encoder corresponding to the segment sequence m i and the segment sequence m i-1 to the Hash encoder corresponding to the segment sequence m i to generate a first check sequence;
  • the output value of the Hash encoder corresponding to the segment sequence m i-1 is a preset value.
  • the segmentation policy is any one of the following:
  • Equal division strategy non-division strategy, inter-segment overlap strategy, inter-segment non-overlapping strategy, sequential division strategy, out-of-order division strategy, all division strategy and partial division strategy.
  • the embodiment of the present application further provides a polarization code decoding apparatus.
  • the apparatus may include: a processor 1500, a memory 1501, a transceiver 1502, and a bus interface 1503.
  • the processor 1500 is responsible for managing the bus architecture and general processing, and the memory 1501 can store data used by the processor 1500 in performing operations.
  • the bus architecture may include any number of interconnected buses and bridges, specifically linked by one or more processors 1500 and various circuits of one or more memories 1501.
  • the bus architecture can also link various other circuits such as peripherals, voltage regulators, and power management circuits, which are well known in the art and, therefore, will not be further described herein.
  • the bus interface provides an interface.
  • the processor 1500 is responsible for managing the bus architecture and general processing, and the memory 1501 can store data used by the processor 1500 in performing operations.
  • the flow disclosed in the embodiment of the present application may be applied to the processor 1500 or implemented by the processor 1500.
  • each step of the signal processing flow may be completed by an integrated logic circuit of hardware in the processor 1500 or an instruction in the form of software.
  • the processor 1500 can be a general-purpose processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or a transistor logic device, and a discrete hardware component, which can be implemented or executed in the embodiment of the present application.
  • a general purpose processor can be a microprocessor or any conventional processor or the like.
  • the steps of the method disclosed in the embodiments of the present application may be directly implemented as a hardware processor, or may be performed by a combination of hardware and software modules in the processor.
  • the software module can be located in a conventional storage medium such as random access memory, flash memory, read only memory, programmable read only memory or electrically erasable programmable memory, registers, and the like.
  • the storage medium is located in the memory 1501, and the processor 1500 reads the information in the memory 1501 and completes the steps of the signal processing flow in conjunction with its hardware.
  • the processor 1500 is configured to read a program in the memory 1501 and execute:
  • processor 1500 is further configured to:
  • the demodulated sequence is SCL-decoded to obtain a codeword sequence Cj+1 of the j+1th segment; and corresponding to the j+1th segment.
  • the first decoder checks the codeword sequence Cj+1 until the j+1th codeword sequence check fails or the first segment codeword sequence check passes.
  • processor 1500 is specifically configured to:
  • processor 1500 is further configured to:
  • the reserved Q is according to the second decoder pair corresponding to the second encoder.
  • the codeword sequence outputted by the path is verified, and the first path sequence that passes the check is used as the decoding output. Otherwise, the sequence in the path with the largest path metric value in the reserved Q path is used as the decoding output.
  • Q ⁇ L and L is a preset number of paths.
  • the embodiment of the present application discloses a readable storage medium, comprising: program code, when the program code is run on a computing device, the program code is used to cause the computing device to execute a polarization code encoding device to execute The steps, or the steps performed by the polarization code decoding device.
  • the information sequence to be encoded is divided into one segment sequence m i , a corresponding check sequence is generated for any segment sequence m i , so that the segmentation can be performed according to the segmentation.
  • segment decoding strategy and check on the decoded segment sequence m i obtained according to the check sequence segment corresponding to the sequence m i, in the case where the check does not pass, the decoding is terminated, since the During decoding, any segment sequence m i is checked, and if the verification fails, the decoding is terminated instead of being verified after decoding the entire information sequence. If the data is not passed, the decoding is terminated.
  • the CRC total encoder and the CRC encoder or Hash encoder corresponding to all the segment sequences can be taken into consideration.
  • base station includes but is not limited to a node, a station controller, an access point (AP), or any other type of interface device capable of working in a wireless environment.
  • AP access point
  • the user equipment UE involved in the present application may include a handheld device having a wireless communication function, an in-vehicle device, a wearable device, a computing device, or other processing device connected to the wireless modem, and various forms of user equipment (User Equipment, referred to as UE), a mobile station (MS), a terminal, a terminal equipment, and the like.
  • UE User Equipment
  • MS mobile station
  • terminal a terminal equipment
  • UE User Equipment
  • the communication systems to which the embodiments of the present application are applicable include, but are not limited to, Global System of Mobile communication (GSM), Code Division Multiple Access (CDMA) IS-95, and Code Division Multiple Access (Code Division). Multiple Access, CDMA) 2000, Time Division-Synchronous Code Division Multiple Access (TD-SCDMA), Wideband Code Division Multiple Access (WCDMA), Time Division Duplex-Long Term Evolution ( Time Division Duplexing-Long Term Evolution (TDD LTE), Frequency Division Duplexing-Long Term Evolution (FDD LTE), Long Term Evolution-Advanced (LTE-advanced), personal hand-held Personal Handy-phone System (PHS), Wireless Fidelity (WiFi) specified by the 802.11 series of protocols, Worldwide Interoperability for Microwave Access (WiMAX), and various future wireless communications system.
  • GSM Global System of Mobile communication
  • CDMA Code Division Multiple Access
  • CDMA Code Division Multiple Access 2000
  • TD-SCDMA Time Division-Synchronous Code Division
  • the terminal may be a wireless terminal, and the wireless terminal may be a device that provides voice and/or data connectivity to the user, a handheld device with a wireless connection function, or other processing device connected to the wireless modem.
  • the wireless terminal can communicate with one or more core networks via a radio access network (eg, RAN, Radio Access Network), which can be a mobile terminal, such as a mobile phone (or "cellular" phone) and with a mobile terminal
  • RAN Radio Access Network
  • the computers for example, can be portable, pocket-sized, handheld, computer-integrated or in-vehicle mobile devices that exchange language and/or data with the wireless access network.
  • a wireless terminal may also be called a Subscriber Unit, a Subscriber Station, a Mobile Station, a Mobile, a Remote Station, an Access Point, and a Remote Terminal.
  • Remote Terminal Access Terminal, User Terminal, User Agent, User Device, or User Equipment.
  • embodiments of the present application can be provided as a method, or a computer program product.
  • the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment in combination of software and hardware.
  • the application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) including computer usable program code.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

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Abstract

本申请实施例涉及通信技术领域，尤其涉及一种极化码编译码方法及装置，包括：根据收发双方已确认的分段策略对待编码的信息序列进行分段，生成I个分段序列mi；针对任一分段序列mi，根据分段序列mi及分段序列mi对应的第一编码器，生成第一校验序列，将分段序列mi和第一校验序列组合成第一码字序列；将I个第一码字序列进行组合得到第二码字序列，并对第二码字序列进行极化码编码。由于在译码时针对任一分段序列mi均进行校验，并在校验不通过的情况下，则终止译码，而不是在译码得到整个信息序列之后再进行校验，因此，不仅能够降低虚警率和误块率，还能够降低译码的时延。

Description

一种极化码编译码方法及装置
本申请要求在2017年3月24日提交中国专利局、申请号为201710184823.8、申请名称为“一种极化码编译码方法及装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及通信技术领域，尤其涉及一种极化码编译码方法及装置。
背景技术
目前，随着4G(the 4 th Generation mobile communication technology，第四代移动通信技术)进入规模商用阶段，面向未来的第五代移动通信技术5G(5 th Generation，第五代)已成为全球研发的热点。确定统一的5G概念，制定全球统一的5G标准，已经成为业界的共同呼声。作为5G的eMBB(Enhanced Moblie BroadBand，增强移动带宽)场景控制信道编码方案的极化码(Polar Codes)，是一种可以达到二进制对称信道容量的新型编码方式，且具有优异的译码性能。
现有技术中的极化码编译码方式包括CRC(Cyclic Redundancy Check，循环冗余校验)辅助的极化码编译码、PC(Parity Check，奇偶校验)辅助的极化码编译码以及Hash序列辅助的极化码编译码。图1为现有技术中CRC辅助的极化码编译码的示意图，CRC辅助的极化码编译码过程包括：将待编码的信息序列首先经过CRC编码器编码，生成对应的CRC序列，再将信息序列和CRC序列一起送入Polar编码器，编码后经过调制器调制，再通过信道发送给接收端；译码时针对解调器解调后的比特流采用Polar-CRC联合译码器进行译码，主要是采用CRC辅助的连续删除列表(Successive Cancellation List，SCL)译码算法，在译码中选择最终译码的译码结果时，Polar-CRC联合译码器先将所有候选码字还原成含有CRC的候选信息序列，对所有候选信息序列做CRC译码处理，将通过CRC译码并且可靠度最高的候选信息序列作为最终的译码结果。
图2为现有技术中PC辅助的极化码编译码的示意图，PC辅助的极化码编译码过程包括：将待编码的信息序列首先经过CRC编码器编码，生成对应的CRC序列，再将信息序列和CRC序列一起送入PC-Polar编码器，编码后通过调制器调制，再通过信道发送给接收端；译码时针对调制器解调后的比特流采用Polar译码器进行译码，主要是采用PC辅助的SCL译码算法，在译码中选择最终译码的译码结果时，Polar译码器先将所述候选码字 还原成含有PC的候选信息序列，对所有候选信息序列做PC译码处理，将通过PC译码并且可靠度最高的候选信息序列作为最终的译码结果。
图3为现有技术中Hash辅助的极化码编译码的示意图，Hash辅助的极化码编译码过程包括：将待编码的信息序列首先经过CRC编码器编码，生成对应的CRC序列，将信息序列和CRC序列一起送入Hash编码器，生成对应的hash序列，再将信息序列、CRC序列以及hash序列一起送入Polar编码器，编码后通过调制器调制，再通过信道发送给接收端；译码时针对调制器解调后的比特流采用Polar译码器进行译码，主要是采用hash辅助的SCL译码算法，在译码中选择最终译码的译码结果时，Polar-Hash译码器先将所述候选码字还原成含有信息序列、CRC序列、hash序列的候选信息序列，对所有候选信息序列做hash译码处理，将通过hash译码并且可靠度最高的候选信息序列作为最终的译码结果。
控制信道的性能评估标准metric除了误块率(block error rate，BLER)以外，另一个重要的性能指标为虚警率(false alarm rates)。虚警率的计算方法有多种定义，常用的两种计算方法为：虚警率＝错误且通过CRC校验的帧数/总的传输帧数，或者虚警率＝错误且通过CRC校验的帧数/总的出错帧数。低的虚警率有利于降低UE(User Equipment，用户终端设备)上行碰撞概率，降低UE功耗，提高系统性能。
为了提高Polar译码的性能，一般采用SCL列表译码(list decoding)算法。对于CRC辅助的极化码译码(aided polar codes)，由于译码时利用附加的CRC比特进行list decoding译码的路径选择，会导致虚警率的提高。如果虚警率为N个CRC比特决定的虚警率，当采用列表大小(list size)为L的CRC aided SCL译码算法时，在最差的情况下，L路径都需要用CRC进行校验选择，这就导致虚警率变为，P fa,block＝1-(1-P fa,path) L且随着L的增大而增大，其中，P fa,path为虚警率。
对于PC-polar来说最后附加的N个比特只用于检测错误(error detection)并不用于辅助译码，故虚警率不会变差，但PC polar需要较多的校验比特开销，导致BLER性能变差。
发明内容
本申请实施例提供一种极化码编译码方法及装置，用以降低虚警率和误块率。
为达到上述目的，第一方面，本申请实施例公开了极化码编码方法，包括：
根据收发双方已确认的分段策略对待编码的信息序列进行分段，生成I个分段序列m i；1≤i≤I且I＞1；
针对任一分段序列m i，根据所述分段序列m i及所述分段序列m i对应的第一编码器， 生成第一校验序列，将所述分段序列m i和所述第一校验序列组合成第一码字序列；
将I个第一码字序列进行组合得到第二码字序列，并对所述第二码字序列进行极化码编码。
可选的，在根据收发双方已确认的分段策略对待编码的信息序列进行分段之前，还包括：
根据所述待编码的信息序列和第二编码器，生成第二校验序列；
所述根据收发双方已确认的分段策略对待编码的信息序列进行分段，包括：
将所述待编码的信息序列和所述第二校验序列进行组合后，采用所述分段策略，生成I个分段序列m i。
可选的，所述第一编码器为线性编码器或非线性编码器；所述第二编码器为线性编码器或非线性编码器。
可选的，所述线性编码器为CRC编码器；所述非线性编码器为Hash编码器。
可选的，所述第一编码器为Hash编码器；
所述根据所述分段序列m i及所述分段序列m i对应的第一编码器，生成第一校验序列，将所述分段序列m i和所述第一校验序列组合成第一码字序列，包括：
将所述分段序列m i和分段序列m i所对应的Hash编码器的输出值输入至分段序列m i所对应的Hash编码器，生成第一校验序列；其中，分段序列m i所对应的Hash编码器的输出值为预设值。
可选的，所述第一编码器为Hash编码器；
所述根据所述分段序列m i及所述分段序列m i对应的第一编码器，生成第一校验序列，将所述分段序列m i和所述第一校验序列组合成第一码字序列，包括：
将所述分段序列m i和分段序列m i-1所对应的Hash编码器的输出值输入至分段序列m i所对应的Hash编码器，生成第一校验序列；其中，当分段序列m i-1为排序第一的分段序列时，分段序列m i-1所对应的Hash编码器的输出值为预设值。
可选的，所述分段策略为以下任一种：
等分策略、非等分策略、段间重叠策略、段间无重叠策略、依序划分策略、乱序划分策略、全部划分策略及部分划分策略。
第二方面，本申请实施例还公开一种基于极化码编码的译码方法，包括：
对接收到的极化码编码后的序列进行解调；
根据收发双方已确认的分段策略，对解调后的序列进行连续删除列表SCL译码，得到第j段的码字序列C j；1≤j≤I且I＞1；I为分段策略对应的分段数量；
根据与所述第j段对应的第一译码器对所述码字序列C j进行校验，若校验不通过，则终止译码；所述第j段对应的第一译码器与发送端的所述第j段的第一编码器相对应。
可选的，该方法还包括：
若所述码字序列C j校验通过，则对解调后的序列进行SCL译码，得到第j+1段的码字序列C j+1；
根据与所述第j+1段对应的第一译码器对所述码字序列C j+1进行校验，直至第j+1段码字序列校验不通过或第I段码字序列校验通过。
可选的，所述根据与所述第j+1段对应的第一译码器对所述码字序列C j+1进行校验，包括：
在得到第j段的码字序列C j后，确定所保留的R条候选路径；
基于所述R条候选路径，对解调后的序列进行SCL译码得到码字序列C j+1；
对所述码字序列C j+1采用与所述第j+1段对应的第一译码算法对所述码字序列C j+1进行校验。
可选的，该方法还包括：
在对解调后的序列进行SCL译码得到最后一个码子序列后，若仍存在被保留的Q条路径，则根据与所述第二编码器相对应的第二译码器对被保留的Q路径所输出的码字序列进行校验，并将第一条通过校验的路径序列作为译码输出，否则，将被保留的Q路径中具有最大路径度量值的路径中序列作为译码输出，其中，Q≤L且L为预先设定的路径数量。
第三方面，本申请实施例公开一种极化码编码装置，包括：
分段模块，用于根据收发双方已确认的分段策略对待编码的信息序列进行分段，生成I个分段序列m i；1≤i≤I且I＞1；
组合模块，用于针对任一分段序列m i，根据所述分段序列m i及所述分段序列m i对应的第一编码器，生成第一校验序列，将所述分段序列m i和所述第一校验序列组合成第一码字序列；
编码模块，用于将I个第一码字序列进行组合得到第二码字序列，并对所述第二码字序列进行极化码编码。
可选的，所述分段模块，还用于：在根据收发双方已确认的分段策略对待编码的信息序列进行分段之前，根据所述待编码的信息序列和第二编码器，生成第二校验序列；
所述分段模块，具体用于：将所述待编码的信息序列和所述第二校验序列进行组合后，采用所述分段策略，生成I个分段序列m i。
可选的，所述第一编码器为线性编码器或非线性编码器；所述第二编码器为线性编码器或非线性编码器。
可选的，所述线性编码器为CRC编码器；所述非线性编码器为Hash编码器。
可选的，所述第一编码器为Hash编码器；
所述组合模块，具体用于：将所述分段序列m i和分段序列m i所对应的Hash编码器的输出值输入至分段序列m i所对应的Hash编码器，生成第一校验序列；其中，分段序列m i所对应的Hash编码器的输出值为预设值。
可选的，所述第一编码器为Hash编码器；
所述组合模块，具体用于：将所述分段序列m i和分段序列m i-1所对应的Hash编码器的输出值输入至分段序列m i所对应的Hash编码器，生成第一校验序列；其中，当分段序列m i-1为排序第一的分段序列时，分段序列m i-1所对应的Hash编码器的输出值为预设值。
可选的，所述分段策略为以下任一种：
等分策略、非等分策略、段间重叠策略、段间无重叠策略、依序划分策略、乱序划分策略、全部划分策略及部分划分策略。
第四方面，本申请实施例公开一种基于极化码编码的译码装置，包括：
解调模块，用于对接收到的极化码编码后的序列进行解调；
译码模块，用于根据收发双方已确认的分段策略，对解调后的序列进行连续删除列表SCL译码，得到第j段的码字序列C j；1≤j≤I且I＞1；I为分段策略对应的分段数量；
第一校验模块，用于根据与所述第j段对应的第一译码器对所述码字序列C j进行校验，若校验不通过，则终止译码；所述第j段对应的第一译码器与发送端的所述第j段的第一编码器相对应。
可选的，所述第一校验模块，还用于：
若所述码字序列C j校验通过，则对解调后的序列进行SCL译码，得到第j+1段的码字序列C j+1；
根据与所述第j+1段对应的第一译码器对所述码字序列C j+1进行校验，直至第j+1 段码字序列校验不通过或第I段码字序列校验通过。
可选的，所述第一校验模块，具体用于：
在得到第j段的码字序列C j后，确定所保留的R条候选路径；
基于所述R条候选路径，对解调后的序列进行SCL译码得到码字序列C j+1；
对所述码字序列C j+1采用与所述第j+1段对应的第一译码算法对所述码字序列C j+1进行校验。
可选的，还包括：第二校验模块；
所述第二校验模块，用于在对解调后的序列进行SCL译码得到最后一个码子序列后，仍存在被保留的Q条路径时，则根据与所述第二编码器相对应的第二译码器对被保留的Q路径所输出的码字序列进行校验，并将第一条通过校验的路径序列作为译码输出，否则，将被保留的Q路径中具有最大路径度量值的路径中序列作为译码输出，其中，Q≤L且L为预先设定的路径数量。
第五方面，本申请实施例还公开一种极化码编码装置，包括处理器、存储器和收发机；
处理器，用于读取存储器中的程序并执行下列过程：
根据收发双方已确认的分段策略对待编码的信息序列进行分段，生成I个分段序列m i；1≤i≤I且I＞1；针对任一分段序列m i，根据所述分段序列m i及所述分段序列m i对应的第一编码器，生成第一校验序列，将所述分段序列m i和所述第一校验序列组合成第一码字序列；将I个第一码字序列进行组合得到第二码字序列，并对所述第二码字序列进行极化码编码。
可选的，所述处理器，还用于：
在根据收发双方已确认的分段策略对待编码的信息序列进行分段之前，根据所述待编码的信息序列和第二编码器，生成第二校验序列；
所述处理器，具体用于：
将所述待编码的信息序列和所述第二校验序列进行组合后，采用所述分段策略，生成I个分段序列m i。
可选的，所述第一编码器为线性编码器或非线性编码器；所述第二编码器为线性编码器或非线性编码器。
可选的，所述线性编码器为CRC编码器；所述非线性编码器为Hash编码器。
可选的，所述第一编码器为Hash编码器；
所述处理器，具体用于：
将所述分段序列m i和分段序列m i所对应的Hash编码器的输出值输入至分段序列m i所对应的Hash编码器，生成第一校验序列；其中，分段序列m i所对应的Hash编码器的输出值为预设值。
可选的，所述第一编码器为Hash编码器；
所述处理器，具体用于：
将所述分段序列m i和分段序列m i-1所对应的Hash编码器的输出值输入至分段序列m i所对应的Hash编码器，生成第一校验序列；其中，当分段序列m i-1为排序第一的分段序列时，分段序列m i-1所对应的Hash编码器的输出值为预设值。
可选的，所述分段策略为以下任一种：
等分策略、非等分策略、段间重叠策略、段间无重叠策略、依序划分策略、乱序划分策略、全部划分策略及部分划分策略。
第六方面，本申请实施例还公开一种基于极化码编码的译码装置，包括处理器、存储器和收发机；
处理器，用于读取存储器中的程序并执行下列过程：
对接收到的极化码编码后的序列进行解调；根据收发双方已确认的分段策略，对解调后的序列进行连续删除列表SCL译码，得到第j段的码字序列C j；1≤j≤I且I＞1；I为分段策略对应的分段数量；根据与所述第j段对应的第一译码器对所述码字序列C j进行校验，若校验不通过，则终止译码；所述第j段对应的第一译码器与发送端的所述第j段的第一编码器相对应。
可选的，所述处理器，还用于：
若所述码字序列C j校验通过，则对解调后的序列进行SCL译码，得到第j+1段的码字序列C j+1；根据与所述第j+1段对应的第一译码器对所述码字序列C j+1进行校验，直至第j+1段码字序列校验不通过或第I段码字序列校验通过。
可选的，所述处理器，具体用于：
在得到第j段的码字序列C j后，确定所保留的R条候选路径；基于所述R条候选路径，对解调后的序列进行SCL译码得到码字序列C j+1；对所述码字序列C j+1采用与所述第j+1段对应的第一译码算法对所述码字序列C j+1进行校验。
可选的，所述处理器，还用于：
在对解调后的序列进行SCL译码得到最后一个码子序列后，若仍存在被保留的Q条路径，则根据与所述第二编码器相对应的第二译码器对被保留的Q路径所输出的码字序列进行校验，并将第一条通过校验的路径序列作为译码输出，否则，将被保留的Q路径中具有最大路径度量值的路径中序列作为译码输出，其中，Q≤L且L为预先设定的路径数量。
第七方面，本申请实施例公开一种可读存储介质，其特征在于，包括程序代码，当所述程序代码在计算设备上运行时，所述程序代码用于使所述计算设备执行第一方面所述方法的步骤，或执行第二方面所述方法的步骤。
上述实施例提供的一种极化码编译码方法及装置，包括：根据收发双方已确认的分段策略对待编码的信息序列进行分段，生成I个分段序列m i；1≤i≤I且I＞1；针对任一分段序列m i，根据所述分段序列m i及所述分段序列m i对应的第一编码器，生成第一校验序列，将所述分段序列m i和所述第一校验序列组合成第一码字序列；将I个第一码字序列进行组合得到第二码字序列，并对所述第二码字序列进行极化码编码。可以看出，本申请实施例是将待编码的信息序列分成I个分段序列m i，而针对任一分段序列m i又生成对应的校验序列，从而使得在译码时能够根据分段策略进行分段译码，并根据分段序列m i所对应的校验序列对译码得到的分段序列m i进行校验，在校验不通过的情况下，则终止译码，由于在译码时针对任一分段序列m i均进行校验，并在校验不通过的情况下，则终止译码，而不是在译码得到整个信息序列之后进行校验，此时，校验不通过，再终止译码，因此，不仅能够降低虚警率和误块率，还能够降低译码的时延。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简要介绍。
图1为现有技术中CRC辅助的极化码编译码的示意图；
图2为现有技术中PC辅助的极化码编译码的示意图；
图3为现有技术中Hash辅助的极化码编译码的示意图；
图4为本申请实施例一提供的一种极化码编码流程示意图；
图5A为本申请实施例二提供的一种极化码编码的示意图；
图5B为本申请实施例二提供的一种极化码译码的示意图；
图6A为本申请实施例三提供的一种极化码编码的示意图；
图6B为本申请实施例三提供的一种极化码译码的示意图；
图7为本申请实施例四提供的一种极化码编码的示意图；
图8A为本申请实施例五提供的一种极化码编码的示意图；
图8B为本申请实施例五提供的一种极化码译码的示意图；
图9A为本申请实施例六提供的一种极化码编码的示意图；
图9B为本申请实施例六提供的一种极化码译码的示意图；
图10为本申请实施例七提供的一种极化码编码的示意图；
图11为本申请实施例提供的一种极化码译码的流程示意图；
图12为本申请实施例提供的第一种极化码编码装置的结构示意图；
图13为本申请实施例提供的第一种极化码译码装置的结构示意图；
图14为本申请实施例提供的第二种极化码编码装置的结构示意图；
图15为本申请实施例提供的第二种极化码译码装置的结构示意图。
具体实施方式
为了使本申请的目的、技术方案及有益效果更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
实施例一
图4示例性示出了本申请实施例提供的一种极化码编码方法流程示意图，如图4所示，该方法可包括：
S401、根据收发双方已确认的分段策略对待编码的信息序列进行分段，生成I个分段序列m i；1≤i≤I且I＞1。
分段策略可以为等分策略、非等分策略、段间重叠策略、段间无重叠策略、依序划分策略、乱序划分策略、全部划分策略及部分划分策略。
具体的，根据收发双方已确认的分段策略对待编码的信息序列进行分段，生成I个分段序列m i时，这I个分段序列m i可以是将信息序列进行等分得到的，也可以是将信息序列进行不等分得到的，还可以是将信息序列依照次序进行划分得到的，也可以是将信息序列不依照次序进行划分得到的，即将信息序列乱序划分得到的，可以将信息序列的全部比特参与分段，也可以将信息序列的部分比特参与分段，此外，分段序列m i与分段序列m i-1之间可以重叠，也可以不重叠，只要保证上述分段策略是收发双方已知即可，即只要保证编码时采用的分段策略，与译码时采用的分段策略相同即可。
在进行仿真的过程中，信息序列可以由仿真设备随机产生，在进行实际的数据传输的过程中，信息序列中携带有待传输的数据。信息序列的长度由极化码的码长，以及码率共同决定。例如，在进行仿真的过程中，当极化码的码长为256bit(比特位)，码率为1/2时，信息序列的长度为128bit，则仿真设备随机产生长度为128bit的信息序列，并将该信息序列作为待编码的信息序列。
S402、针对任一分段序列m i，根据分段序列m i及分段序列m i对应的第一编码器，生成第一校验序列，将分段序列m i和第一校验序列组合成第一码字序列。
具体的，可根据分段序列m i的长度及分段序列m i对应的第一编码器，生成第一校验序列；也可根据分段序列m i的内容及分段序列m i对应的第一编码器，生成第一校验序列；也可根据分段序列m i的长度和内容及分段序列m i对应的第一编码器，生成第一校验序列。其中，在根据分段序列m i的内容及分段序列m i对应的第一编码器，生成第一校验序列时，可根据分段序列m i的全部内容及分段序列m i对应的第一编码器，生成第一校验序列；也可根据分段序列m i的部分内容及分段序列m i对应的第一编码器，生成第一校验序列。
在将分段序列m i和第一校验序列组合成第一码字序列时，可以是任意组合，例如可以是分段序列m i在前，第一校验序列在后，也可以是第一校验序列在前，分段序列m i在后，只要保证编码时采用的组合方式收发双方已知即可。
S403、将I个第一码字序列进行组合得到第二码字序列，并对第二码字序列进行极化码编码。
具体的，可以按照顺序将I个第一码字序列进行组合得到第二码字序列，也可以不依照次序将I个第一码字序列进行组合得到第二码字序列，还可以采用其它的方式将I个第一码字序列进行组合得到第二码字序列，只要保证编码时采用的组合方式，与译码时采用的组合方式相同即可。
可选的，可以将I个第一码字序列进行并串变换以得到第二码字序列。
在将I个第一码字序列进行组合得到第二码字序列后，可通过极化码编码器对第二码字序列进行编码。具体的，发送端可保存有极化码编码的编码矩阵，在对第二码字序列进行极化码编码时，可将第二码字序列和保存的编码矩阵进行二元域上的乘加运算，则可以得到极化码编码后的序列，极化码编码的过程属于现有技术，在本申请实施例中对该过程不进行赘述。
发送端中预先保存有速率匹配算法(rate matching)，在对第二码字序列进行极化码编 码后，可根据预先保存的速率匹配算法，对编码后的序列进行速率匹配。在进行速率匹配时，所采用的rate matching序列可选的可以利用高斯方法获得，或者采用对信噪比(Signal Noise Ratio，SNR)不敏感的其他rate matching序列。
在对编码后的序列完成速率匹配后，可以对编码后的序列再通过调制器进行调制，发送给接收端。
上述步骤S402中的第一编码器可以是线性编码器，也可以是非线性编码器。当第一编码器时线性编码器时，第一编码器可以为线性分组码编码器，例如，第一编码器采用CRC(Cyclic Redundancy Check，循环冗余校验)编码器；第一编码器也可以为线性卷积编码器，例如，第一编码器为采用卷积码编码器。
当第一编码器是非线性编码器时，第一编码器可以为非线性分组码编码器，例如，第一编码器可以采用每个分段序列m i所对应的Hash编码器的输出值为预设值的Hash编码器，第一编码器也可以为非线性卷积码编码器，例如，第一编码器可以采用每个分段序列m i所对应的Hash编码器的输出值为分段序列m i-1所对应的Hash编码器的输出值。
本申请实施例提供的极化码编码方法可以应用于发送端，所述发送端可以是基站，也可以是UE。
根据以上内容可以看出，由于将待编码的信息序列分成I个分段序列m i，而针对任一分段序列m i又生成对应的校验序列，从而提供了一种极化码编码方法，使用该种编码方法进行编码，能够使得在译码时能够根据分段策略进行分段译码，从而能够降低虚警率和误块率，还能够降低译码时延，提升系统性能。
实施例二
在实施例二中，第一编码器采用线性分组码CRC编码器，如图5A所示，为本申请实施例二提供的一种极化码编码的示意图，由图5A可以看出，发送端先根据收发双方已确认的分段策略将待编码的信息序列m划分为I个分段序列，记I段分段序列为{m 1,m 2,...,m I}。然后，根据分段序列m 1采用CRC编码器1，生成校验序列c 1(未示出)，将分段序列m 1和校验序列c 1进行组合，生成码字序列c′ 1；根据分段序列m 2采用CRC编码器2，生成校验序列c 2(未示出)，将分段序列m 2和校验序列c 2进行组合，生成码字序列c′ 2；根据分段序列m 3采用CRC编码器3，生成校验序列c 3(未示出)，将分段序列m 3和校验序列c 3进行组合后，生成码字序列c′ 3；根据分段序列m i采用CRC编码器i，生成校验序列c i(未示出)，将分段序列m i和校验序列c i进行组合后，生成码字序列c′ i。之后， 将码字序列c′ 1、码字序列c′ 2、码字序列c′ 3以及码字序列c′ i按照收发双方已确认的组合方式进行组合后得到码字序列d 1，最后将码字序列d 1送入polar码编码器，进行编码。Polar母码的长度一定是2的整数次幂，而输出码字的长度可能是任意的，故需要rate matching操作，即执行减缩(shortening)或者打孔(puncturing)操作。rate matching操作采用的rate matching序列可选的可以利用高斯近似方法获得，或者采用对SNR不敏感的其他rate matching序列，polar编码器输出的是rate matching后的编码序列。编码后的序列经过调制器调制，就可以在信道中发送给接收端了。
需要注意的是，CRC编码器1、CRC编码器2、CRC编码器i可以采用相同的多项式如CRC-8(CRC序列的长度为8比特位)，CRC-12(CRC序列的长度为12比特位)，CRC-16(CRC序列的长度为16比特位)，CRC-24(CRC序列的长度为24比特位)等，也可以采用不同的多项式，例如，CRC编码器1采用CRC-8，而CRC编码器2采用CRC-12，CRC编码器i采用CRC-24，只要保证编码时采用的多项式，与译码时采用的多项式相同即可。
为了描述简便起见，下面基于图5A所示的编码过程，来介绍译码过程。
如图5B所示，为本申请实施例提供的一种极化码译码的示意图，由图5B可以看出，接收端在接收到发送端发送的码字d 1后，需要将该码字送入解调器解调，并进行解速率匹配，在进行解速率匹配时，所采用的rate matching序列可选的可以利用高斯方法获得，或者采用对信噪比(Signal Noise Ratio，SNR)不敏感的其他rate matching序列。接收端的解速率方法与发送端的速率匹配方法是相对应的。
然后再将该码字送入Polar-CRC联合译码器进行SCL译码，此时，Polar-CRC联合译码器根据图5A所示的分段策略，首先译出码字序列c′ 1，假设此时有L(L≥1且L为预设值)条路径被保留，则可得到L个码字序列c′ 1，此时，对L个码字序列c′ 1中的每一个码字序列c′ 1均通过与CRC编码器1相对应的CRC译码器1进行校验，如果L个码字序列c′ 1均未通过CRC译码器1的校验，则认为译码失败，并提前终止译码。否则，则保留CRC译码器1输出校验和为0的路径，并基于这些路径继续译码。
同理，在Polar-CRC联合译码器根据图5A所示的分段策略，并基于已通过校验的路径译出码字序列c′ 2时，对此时的每条路径进行校验，若校验通过，则保留CRC译码器2输出校验和为0的路径，并基于这些路径继续译码。
在Polar-CRC联合译码器根据图5A所示的分段策略，并基于已通过校验的路径译出码字序列c′ 3时，对此时的每条路径进行校验，若校验通过，则保留CRC译码器3输出校验和为0的路径，并基于这些路径继续译码。
在Polar-CRC联合译码器根据图5A所示的分段策略，并基于已通过校验的路径译出码字序列c′ i时，假设此时有Q(Q≤L)条路径被保留，则可得到Q个码字序列c′ i，此时，对Q个码字序列c′ i中的每一个码字序列c′ i均通过与CRC编码器i相对应的CRC译码器i进行校验，如果Q个码字序列c′ i均未通过CRC译码器i的校验，则输出Q个码字序列c′ i中具有最大路径度量值的路径中的序列作为译码输出。否则，将Q个码字序列c′ i中第一条通过CRC译码器1校验的序列作为译码输出。
根据以上内容可以看出，由于将待编码的信息序列分成I个分段序列m i，而针对任一分段序列m i又生成对应的校验序列，从而使得在译码时能够根据分段策略进行分段译码，并根据分段序列m i所对应的校验序列对译码得到的分段序列m i进行校验，在校验不通过的情况下，则终止译码，由于在译码时针对任一分段序列m i均进行校验，并在校验不通过的情况下，则终止译码，而不是在译码得到整个信息序列之后进行校验，因此，不仅能够降低虚警率和误块率，还能够降低译码的时延，从而能够降低UE功耗，提高系统性能。此外，为了提高虚警率的准确度，可以将所有分段序列对应的CRC编码器均考虑在内。
实施例三
在实施例三中，第一编码器采用非线性分组码Hash编码器，如图6A所示，为本申请实施例三提供的一种极化码编码的示意图，由图6A可以看出，发送端先根据收发双方已确认的分段策略将待编码的信息序列m划分为I个分段序列，记I段分段序列为{m 1,m 2,...,m I}。然后，根据分段序列m 1以及预先设定的收发双方已知的Hash编码器1的输出值S 1采用Hash编码器1以及截断函数T1，生成hash序列h 1(未示出)，之后将分段序列m 1和hash序列h 1进行组合生成码字序列c′ 1。
具体的，在生成hash序列h 1时，一方面将分段序列m 1转化为十进制数值输入Hash编码器1，另一方面将收发双方已知的Hash编码器1的输出值S 1输入Hash编码器1，从而生成Hash编码器1的输出值，然后将该输出值转化为比特流，并截取该比特流的部分或全部，从而作为该信息序列对应的hash序列h 1，将分段序列m 1和hash序列h 1进行组合，从而生成码字序列c′ 1。
在截取该比特流的部分或全部时，可以按照一定的方法来截取，例如设置了Hash序列的长度，则在该比特流中截取该长度对应的Hash序列，可以从设定位置截取，该设定位置可以是第一位，或者非第一位，可以是从第一位开始往后截取，也可以是从末尾往前开始截取等等。只要保证编码时采用的Hash序列的截取方式，与译码时采用的截取方式 相同即可。
可选的，在本申请实施例中截取得到的Hash序列的长度不大于32比特位。该Hash序列的长度例如可以为8比特位、或32比特位等等。
同理，根据分段序列m 2以及预先设定的收发双方已知的Hash编码器2的输出值S 2采用Hash编码器2以及截断函数T2，从而生成hash序列h 2(未示出)，之后将分段序列m 2和hash序列h 2进行组合生成码字序列c′ 2。
根据分段序列m 3以及预先设定的收发双方已知的Hash编码器3的输出值S 3采用Hash编码器3以及截断函数T3，从而生成hash序列h 3(未示出)，之后将分段序列m 3和hash序列h 3进行组合生成码字序列c′ 3。
根据分段序列m i以及预先设定的收发双方已知的Hash编码器3的输出值S i采用Hash编码器i以及截断函数Ti，从而生成hash序列h i(未示出)，之后将分段序列m i和hash序列h i进行组合生成码字序列c′ i。
然后，将码字序列c′ 1、码字序列c′ 2、码字序列c′ 3以及码字序列c′ i按照收发双方已确认的组合方式进行组合后得到码字序列d 1，最后将码字序列d 1送入polar码编码器，进行编码。Polar母码的长度一定是2的整数次幂，而输出码字的长度可能是任意的，故需要rate matching操作，即执行减缩(shortening)或者打孔(puncturing)操作。rate matching操作采用的rate matching序列可选的可以利用高斯近似方法获得，或者采用对SNR不敏感的其他rate matching序列，polar编码器输出的是rate matching后的编码序列。编码后的序列经过调制器调制，就可以在信道中发送给接收端了。
需要注意的是，Hash编码器1、Hash编码器2以及Hash编码器i可以相同，例如，Hash编码器1、Hash编码器2以及Hash编码器i所生成的Hash序列的长度均为8比特位；Hash编码器1、Hash编码器2以及Hash编码器i也可以不同，例如，Hash编码器1、Hash编码器2所生成的Hash序列的长度均为8比特位，而Hash编码器i所生成的Hash序列的长度均为32比特位，只要保证编码时采用的Hash编码器，与译码时采用的Hash编码器相同即可。截断函数T1、截断函数T2以及截断函数Ti所截取的相应的Hash编码器的比特位数可以相同，也可以不同，只要保证收发双方已知即可。
为了进一步降低虚警率，在本申请实施例中该Hash编码特点为分段序列对应的v-bit状态的变化，会引起下一个分段序列对应的v-bit状态无规则的不同，即雪崩效应，从而通过Hash编码可以进一步降低虚警率。
为了描述简便起见，下面基于图6A所示的编码过程，来介绍译码过程。
如图6B所示，为本申请实施例提供的一种极化码译码的示意图，由图6B可以看出，接收端在接收到发送端发送的码字d 1后，需要将该码字送入解调器解调，并进行解速率匹配，在进行解速率匹配时，所采用的rate matching序列可选的可以利用高斯方法获得，或者采用对信噪比(Signal Noise Ratio，SNR)不敏感的其他rate matching序列。接收端的解速率方法与发送端的速率匹配方法是相对应的。
然后再将该码字送入Polar-Hash联合译码器进行SCL译码，此时，Polar-Hash联合译码器根据图6A所示的分段策略，首先译出码字序列c′ 1，假设此时有L(L≥1且L为预设值)条路径被保留，则可得到L个码字序列c′ 1，此时，对L个码字序列c′ 1中的每一个码字序列c′ 1均通过与Hash编码器1相对应的Hash译码器1进行校验，如果L个码字序列c′ 1均未通过Hash译码器1的校验，则认为译码失败，并提前终止译码。否则，则保留Hash译码器1译出序列中与原Hash校验段相等的路径，并基于这些路径继续译码。
同理，在Polar-Hash联合译码器根据图6A所示的分段策略，并基于已通过校验的路径译出码字序列c′ 2时，对此时的每条路径进行校验，若校验通过，则保留Hash译码器2译出序列中与原Hash校验段相等的路径，并基于这些路径继续译码。
在Polar-Hash联合译码器根据图6A所示的分段策略，并基于已通过校验的路径译出码字序列c′ 3时，对此时的每条路径进行校验，若校验通过，则保留Hash译码器2译出序列中与原Hash校验段相等的路径，并基于这些路径继续译码。
在Polar-Hash联合译码器根据图6A所示的分段策略，并基于已通过校验的路径译出码字序列c′ i时，假设此时有Q(Q≤L)条路径被保留，则可得到Q个码字序列c′ i，此时，对Q个码字序列c′ i中的每一个码字序列c′ i均通过与Hash编码器i相对应的Hash译码器i进行校验，如果Q个码字序列c′ i均未通过Hash译码器i的校验，则输出Q个码字序列c′ i中具有最大路径度量值的路径中的序列作为译码输出。否则，将Q个码字序列c′ i中第一条通过CRC译码器1校验的序列作为译码输出。
根据以上内容可以看出，由于将待编码的信息序列分成I个分段序列m i，而针对任一分段序列m i又生成对应的校验序列，从而使得在译码时能够根据分段策略进行分段译码，并根据分段序列m i所对应的校验序列对译码得到的分段序列m i进行校验，在校验不通过的情况下，则终止译码，由于在译码时针对任一分段序列m i均进行校验，并在校验不通过的情况下，则终止译码，而不是在译码得到整个信息序列之后再进行校验，因此，不仅能 够降低虚警率和误块率，还能够降低译码的时延，从而能够降低UE功耗，提高系统性能。此外，为了提高虚警率的准确度，可以将所有分段序列对应的Hash编码器均考虑在内。
实施例四
在实施例四中，第一编码器采用非线性卷积码Hash编码器，如图7所示，为本申请实施例四提供的一种极化码编码的示意图，由图7可以看出，发送端先根据收发双方已确认的分段策略将待编码的信息序列m划分为I个分段序列，记I段分段序列为{m 1,m 2,...,m I}。然后，根据分段序列m 1以及预先设定的收发双方已知的Hash编码器1的输出值S 1采用Hash编码器1以及截断函数T1，生成hash序列h 1(未示出)，之后将分段序列m 1和hash序列h 1进行组合生成码字序列c′ 1。
具体的，在生成hash序列h 1时，一方面将分段序列m 1转化为十进制数值输入Hash编码器1，另一方面将收发双方已知的Hash编码器1的输出值S 1输入Hash编码器1，从而生成Hash编码器1的输出值S 2，然后将该输出值S 2转化为比特流，并截取该比特流的部分或全部，从而作为该信息序列对应的hash序列h 1，将分段序列m 1和hash序列h 1进行组合，生成码字序列c′ 1，从而进一步降低了虚警率。
在截取该比特流的部分或全部时，可以按照一定的方法来截取，例如设置了Hash序列的长度，则在该比特流中截取该长度对应的Hash序列，可以从设定位置截取，该设定位置可以是第一位，或者非第一位，可以是从第一位开始往后截取，也可以是从末尾往前开始截取等等。只要保证编码时采用的Hash序列的截取方式，与译码时采用的截取方式相同即可。
可选的，在本申请实施例中截取得到的Hash序列的长度不大于32比特位。该Hash序列的长度例如可以为8比特位、或32比特位等等。
而在根据分段序列m 2以及Hash编码器1的输出值S 2采用Hash编码器2以及截断函数T2，从而生成hash序列h 2(未示出)，之后将分段序列m 2和hash序列h 2进行组合生成码字序列c′ 2。
具体的，在生成hash序列h 2时，一方面将分段序列m 2转化为十进制数值输入Hash编码器2，另一方面将Hash编码器1的输出值S 2输入Hash编码器2，从而生成Hash编码器2的输出值S 3，然后将该输出值S 3转化为比特流，并截取该比特流的部分或全部，从而作为该信息序列对应的hash序列h 2，将分段序列m 2和hash序列h 2进行组合，生成码字序列c′ 2，从而进一步降低了虚警率。
而在根据分段序列m 3以及Hash编码器2的输出值S 3采用Hash编码器3以及截断函数T3，从而生成hash序列h 3(未示出)，之后将分段序列m 3和hash序列h 3进行组合生成码字序列c′ 3。
具体的，在生成hash序列h 3时，一方面将分段序列m 3转化为十进制数值输入Hash编码器3，另一方面将Hash编码器2的输出值S 3输入Hash编码器3，从而生成Hash编码器3的输出值S 4(未示出)，然后将该输出值S 4转化为比特流，并截取该比特流的部分或全部，从而作为该信息序列对应的hash序列h 3，将分段序列m 3和hash序列h 3进行组合，生成码字序列c′ 3，从而进一步降低了虚警率。
同理，根据分段序列m i以及Hash编码器i-1的输出值S i采用Hash编码器i以及截断函数Ti，从而生成hash序列h i(未示出)，之后将分段序列m i和hash序列h i进行组合生成码字序列c′ i，从而进一步降低了虚警率。
然后，将码字序列c′ 1、码字序列c′ 2、码字序列c′ 3以及码字序列c′ i按照收发双方已确认的组合方式进行组合后得到码字序列d 1，最后将码字序列d 1送入polar码编码器，进行编码。Polar母码的长度一定是2的整数次幂，而输出码字的长度可能是任意的，故需要rate matching操作，即执行减缩(shortening)或者打孔(puncturing)操作。rate matching操作采用的rate matching序列可选的可以利用高斯近似方法获得，或者采用对SNR不敏感的其他rate matching序列，polar编码器输出的是rate matching后的编码序列。编码后的序列经过调制器调制，就可以在信道中发送给接收端了。
需要注意的是，Hash编码器1、Hash编码器2以及Hash编码器i可以相同，例如，Hash编码器1、Hash编码器2以及Hash编码器i所生成的Hash序列的长度均为8比特位；Hash编码器1、Hash编码器2以及Hash编码器i也可以不同，例如，Hash编码器1、Hash编码器2所生成的Hash序列的长度均为8比特位，而Hash编码器i所生成的Hash序列的长度均为32比特位，只要保证编码时采用的Hash编码器，与译码时采用的Hash编码器相同即可。截断函数T1、截断函数T2以及截断函数Ti所截取的相应的Hash编码器的比特位数可以相同，也可以不同，只要保证收发双方已知即可。
为了进一步降低虚警率，在本申请实施例中该Hash编码特点为分段序列对应的v-bit状态的变化，会引起下一个分段序列对应的v-bit状态无规则的不同，即雪崩效应，从而通过Hash编码可以进一步降低虚警率。
基于图7所示的编码过程相应的译码过程与图6B所示的译码过程类似，在此，不再 赘述。
根据以上内容可以看出，由于将待编码的信息序列分成I个分段序列m i，而针对任一分段序列m i又生成对应的校验序列，从而使得在译码时能够根据分段策略进行分段译码，并根据分段序列m i所对应的校验序列对译码得到的分段序列m i进行校验，在校验不通过的情况下，则终止译码，由于在译码时针对任一分段序列m i均进行校验，并在校验不通过的情况下，则终止译码，而不是在译码得到整个信息序列之后再进行校验，因此，不仅能够降低虚警率和误块率，还能够降低译码的时延，从而能够降低UE功耗，提高系统性能。此外，为了提高虚警率的准确度，可以将所有分段序列对应的Hash编码器均考虑在内。
可选的，为了提升虚警率的准确度，还可以包括第二编码器。
第二编码器可以是线性编码器，也可以是非线性编码器。当第二编码器时线性编码器时，第二编码器可以为线性分组码编码器，例如，第二编码器采用CRC编码器；第二编码器也可以为线性卷积编码器，例如，第二编码器为采用卷积码编码器。而当第二编码器是非线性编码器时，第二编码器可以为非线性分组码编码器，第二编码器也可以为非线性卷积码编码器。
实施例五
在实施例五中，第一编码器和第二编码器均采用线性分组码CRC编码器，如图8A所示，为本申请实施例五提供的一种极化码编码的示意图，由图8A可以看出，发送端先将待编码的信息序列m通过CRC总编码器编码后得到码字序列e 1，然后根据收发双方已确认的分段策略码字序列e 1将划分为I个分段序列，记I段分段序列为{m 1,m 2,...,m I}。
具体的，根据收发双方已确认的分段策略码字序列e 1将划分为I个分段序列时，可仅将码字序列e 1中的信息序列根据收发双方已确认的分段策略进行分段，也可将码字序列e 1根据收发双方已确认的分段策略进行分段，即将码字序列e 1中的信息序列和校验序列一起根据收发双方已确认的分段策略进行分段，只要保证，只要保证编码时采用的分段策略，与译码时采用的分段策略相同即可。
而在根据收发双方已确认的分段策略对码字序列e 1进行分段，生成I个分段序列m i时，这I个分段序列m i可以是将码字序列e 1进行等分得到的，也可以是将码字序列e 1进行不等分得到的，还可以是将码字序列e 1依照次序进行划分得到的，也可以是将码字序列e 1不依照次序进行划分得到的，即将码字序列e 1乱序划分得到的，可以将码字序列e 1的全部比特参与分段，也可以将码字序列e 1的部分比特参与分段，此外，分段序列m i与分段序列 m i-1之间可以重叠，也可以不重叠，只要保证上述分段策略是收发双方已知即可，即只要保证编码时采用的分段策略，与译码时采用的分段策略相同即可。
然后，根据分段序列m 1采用CRC编码器1，生成校验序列c 1(未示出)，将分段序列m 1和校验序列c 1进行组合，生成码字序列c′ 1；根据分段序列m 2采用CRC编码器2，生成校验序列c 2(未示出)，将分段序列m 2和校验序列c 2进行组合，生成码字序列c′ 2；根据分段序列m 3采用CRC编码器3，生成校验序列c 3(未示出)，将分段序列m 3和校验序列c 3进行组合后，生成码字序列c′ 3；根据分段序列m i采用CRC编码器i，生成校验序列c i(未示出)，将分段序列m i和校验序列c i进行组合后，生成码字序列c′ i。之后，将码字序列c′ 2、码字序列c′ 2、码字序列c′ 3以及码字序列c′ i按照收发双方已确认的组合方式进行组合后得到码字序列d 1，最后将码字序列d 1送入polar码编码器，进行编码。Polar母码的长度一定是2的整数次幂，而输出码字的长度可能是任意的，故需要rate matching操作，即执行减缩(shortening)或者打孔(puncturing)操作。rate matching操作采用的rate matching序列可选的可以利用高斯近似方法获得，或者采用对SNR不敏感的其他rate matching序列，polar编码器输出的是rate matching后的编码序列。编码后的序列经过调制器调制，就可以在信道中发送给接收端了。
需要注意的是，为了提高虚警率的准确度可以将CRC总编码器和每个分段序列所对应的CRC编码器都考虑在内，也可以将只考虑CRC总编码器，或者，只考虑每个分段序列所对应的CRC编码器，还可以只考虑分段序列所对应的部分CRC编码器。
为了描述简便起见，下面基于图8A所示的编码过程，来介绍译码过程。
如图8B所示，为本申请实施例提供的一种极化码译码的示意图，由图8B可以看出，接收端在接收到发送端发送的码字d 1后，需要将该码字送入解调器解调，并进行解速率匹配，然后再将该码字送入Polar-CRC联合译码器进行SCL译码，此时，Polar-CRC联合译码器根据图8A所示的分段策略，首先译出码字序列c′ 1，假设此时有L(L≥1且L为预设值)条路径被保留，则可得到L个码字序列c′ 1，此时，对L个码字序列c′ 1中的每一个码字序列c′ 1均通过与CRC编码器1相对应的CRC译码器1进行校验，如果L个码字序列c′ 1均未通过CRC译码器1的校验，则认为译码失败，并提前终止译码。否则，则保留CRC译码器1输出校验和为0的路径，并基于这些路径继续译码。
同理，在Polar-CRC联合译码器根据图8A所示的分段策略，并基于已通过校验的路径译出码字序列c′ 2时，对此时的每条路径进行校验，若校验通过，则保留CRC译码器2 输出校验和为0的路径，并基于这些路径继续译码。
在Polar-CRC联合译码器根据图8A所示的分段策略，并基于已通过校验的路径译出码字序列c′ 3时，对此时的每条路径进行校验，若校验通过，则保留CRC译码器3输出校验和为0的路径，并基于这些路径继续译码。
在Polar-CRC联合译码器根据图8A所示的分段策略，并基于已通过校验的路径译出码字序列c′ i时，假设此时有Q(Q≤L)条路径被保留，则可得到Q个码字序列c′ i，此时，对Q个码字序列c′ i中的每一个码字序列c′ i均通过与CRC编码器i相对应的CRC译码器i进行校验，如果Q个码字序列c′ i均未通过CRC译码器i的校验，则输出Q个码字序列c′ i中具有最大路径度量值的路径中的序列作为译码输出。
在CRC译码器i对Q个码字序列c′ i进行校验通过的情况下，为了提高虚警率的准确度，依然需要将Q个码字序列c′ i通过与CRC总编码器相对应的CRC总译码器进行校验，若校验通过，则将Q个码字序列c′ i中第一条通过CRC总译码器的序列作为译码输出，否则，则将Q个码字序列c′ i中具有最大路径度量值的路径中的序列作为译码输出。
实施例六
在实施例六中，第一编码器采用非线性分组码Hash编码器，而第二编码器均采用线性分组码CRC编码器，如图9A所示，为本申请实施例六提供的一种极化码编码的示意图，由图9A可以看出，发送端先将待编码的信息序列m通过CRC总编码器编码后得到码字序列e 1，然后根据收发双方已确认的分段策略码字序列e 1将划分为I个分段序列，记I段分段序列为{m 1,m 2,...,m I}。
具体的，根据收发双方已确认的分段策略码字序列e 1将划分为I个分段序列时，可仅将码字序列e 1中的信息序列根据收发双方已确认的分段策略进行分段，也可将码字序列e 1根据收发双方已确认的分段策略进行分段，即将码字序列e 1中的信息序列和校验序列一起根据收发双方已确认的分段策略进行分段，只要保证，只要保证编码时采用的分段策略，与译码时采用的分段策略相同即可。
而在根据收发双方已确认的分段策略对码字序列e 1进行分段，生成I个分段序列m i时，这I个分段序列m i可以是将码字序列e 1进行等分得到的，也可以是将码字序列e 1进行不等分得到的，还可以是将码字序列e 1依照次序进行划分得到的，也可以是将码字序列e 1不依照次序进行划分得到的，即将码字序列e 1乱序划分得到的，可以将码字序列e 1的全部 比特参与分段，也可以将码字序列e 1的部分比特参与分段，此外，分段序列m i与分段序列m i-1之间可以重叠，也可以不重叠，只要保证上述分段策略是收发双方已知即可，即只要保证编码时采用的分段策略，与译码时采用的分段策略相同即可。
然后，根据分段序列m 1以及预先设定的收发双方已知的Hash编码器1的输出值S 1采用Hash编码器1以及截断函数T1，生成hash序列h 1(未示出)，之后将分段序列m 1和hash序列h 1进行组合生成码字序列c′ 1。
具体的，在生成hash序列h 1时，一方面将分段序列m 1转化为十进制数值输入Hash编码器1，另一方面将收发双方已知的Hash编码器1的输出值S 1输入Hash编码器1，从而生成Hash编码器1的输出值，然后将该输出值转化为比特流，并截取该比特流的部分或全部，从而作为该信息序列对应的hash序列h 1，将分段序列m 1和hash序列h 1进行组合，从而生成码字序列c′ 1。
在截取该比特流的部分或全部时，可以按照一定的方法来截取，例如设置了Hash序列的长度，则在该比特流中截取该长度对应的Hash序列，可以从设定位置截取，该设定位置可以是第一位，或者非第一位，可以是从第一位开始往后截取，也可以是从末尾往前开始截取等等。只要保证编码时采用的Hash序列的截取方式，与译码时采用的截取方式相同即可。
可选的，在本申请实施例中截取得到的Hash序列的长度不大于32比特位。该Hash序列的长度例如可以为8比特位、或32比特位等等。
同理，根据分段序列m 2以及预先设定的收发双方已知的Hash编码器2的输出值S 2采用Hash编码器2以及截断函数T2，从而生成hash序列h 2(未示出)，之后将分段序列m 2和hash序列h 2进行组合生成码字序列c′ 2。
根据分段序列m 3以及预先设定的收发双方已知的Hash编码器3的输出值S 3采用Hash编码器3以及截断函数T3，从而生成hash序列h 3(未示出)，之后将分段序列m 3和hash序列h 3进行组合生成码字序列c′ 3。
根据分段序列m i以及预先设定的收发双方已知的Hash编码器3的输出值S i采用Hash编码器i以及截断函数Ti，从而生成hash序列h i(未示出)，之后将分段序列m i和hash序列h i进行组合生成码字序列c′ i。
然后，将码字序列c′ 1、码字序列c′ 2、码字序列c′ 3以及码字序列c′ i按照收发双方已确 认的组合方式进行组合后得到码字序列d 1，最后将码字序列d 1送入polar码编码器，进行编码。Polar母码的长度一定是2的整数次幂，而输出码字的长度可能是任意的，故需要rate matching操作，即执行减缩(shortening)或者打孔(puncturing)操作。rate matching操作采用的rate matching序列可选的可以利用高斯近似方法获得，或者采用对SNR不敏感的其他rate matching序列，polar编码器输出的是rate matching后的编码序列。编码后的序列经过调制器调制，就可以在信道中发送给接收端了。
需要注意的是，Hash编码器1、Hash编码器2以及Hash编码器i可以相同，例如，Hash编码器1、Hash编码器2以及Hash编码器i所生成的Hash序列的长度均为8比特位；Hash编码器1、Hash编码器2以及Hash编码器i也可以不同，例如，Hash编码器1、Hash编码器2所生成的Hash序列的长度均为8比特位，而Hash编码器i所生成的Hash序列的长度均为32比特位，只要保证编码时采用的Hash编码器，与译码时采用的Hash编码器相同即可。截断函数T1、截断函数T2以及截断函数Ti所截取的相应的Hash编码器的比特位数可以相同，也可以不同，只要保证收发双方已知即可。
为了进一步降低虚警率，在本申请实施例中该Hash编码特点为分段序列对应的v-bit状态的变化，会引起下一个分段序列对应的v-bit状态无规则的不同，即雪崩效应，从而通过Hash编码可以进一步降低虚警率。
为了描述简便起见，下面基于图9A所示的编码过程，来介绍译码过程。
如图9B所示，为本申请实施例提供的一种极化码译码的示意图，由图9B可以看出，接收端在接收到发送端发送的码字d 1后，需要将该码字送入解调器解调，并进行解速率匹配，在进行解速率匹配时，所采用的rate matching序列可选的可以利用高斯方法获得，或者采用对信噪比(Signal Noise Ratio，SNR)不敏感的其他rate matching序列。接收端的解速率方法与发送端的速率匹配方法是相对应的。
然后再将该码字送入Polar-Hash联合译码器进行SCL译码，此时，Polar-Hash联合译码器根据图9A所示的分段策略，首先译出码字序列c′ 1，假设此时有L(L≥1且L为预设值)条路径被保留，则可得到L个码字序列c′ 1，此时，对L个码字序列c′ 1中的每一个码字序列c′ 1均通过与Hash编码器1相对应的Hash译码器1进行校验，如果L个码字序列c′ 1均未通过Hash译码器1的校验，则认为译码失败，并提前终止译码。否则，则保留Hash译码器1译出序列中与原Hash校验段相等的路径，并基于这些路径继续译码。
同理，在Polar-Hash联合译码器根据图9A所示的分段策略，并基于已通过校验的路径译出码字序列c′ 2时，对此时的每条路径进行校验，若校验通过，则保留Hash译码器2 译出序列中与原Hash校验段相等的路径，并基于这些路径继续译码。
在Polar-Hash联合译码器根据图9A所示的分段策略，并基于已通过校验的路径译出码字序列c′ 3时，对此时的每条路径进行校验，若校验通过，则保留Hash译码器2译出序列中与原Hash校验段相等的路径，并基于这些路径继续译码。
在Polar-Hash联合译码器根据图9A所示的分段策略，并基于已通过校验的路径译出码字序列c′ i时，假设此时有Q(Q≤L)条路径被保留，则可得到Q个码字序列c′ i，此时，对Q个码字序列c′ i中的每一个码字序列c′ i均通过与Hash编码器i相对应的Hash译码器i进行校验，如果Q个码字序列c′ i均未通过Hash译码器i的校验，则输出Q个码字序列c′ i中具有最大路径度量值的路径中的序列作为译码输出。
在Hash译码器i对Q个码字序列c′ i进行校验通过的情况下，为了提高虚警率的准确度，依然需要将Q个码字序列c′ i通过与CRC总编码器相对应的CRC总译码器进行校验，若校验通过，则将Q个码字序列c′ i中第一条通过CRC总译码器的序列作为译码输出，否则，则将Q个码字序列c′ i中具有最大路径度量值的路径中的序列作为译码输出。
根据以上内容可以看出，由于将待编码的信息序列分成I个分段序列m i，而针对任一分段序列m i又生成对应的校验序列，从而使得在译码时能够根据分段策略进行分段译码，并根据分段序列m i所对应的校验序列对译码得到的分段序列m i进行校验，在校验不通过的情况下，则终止译码，由于在译码时针对任一分段序列m i均进行校验，并在校验不通过的情况下，则终止译码，而不是在译码得到整个信息序列之后再进行校验，因此，不仅能够降低虚警率和误块率，还能够降低译码的时延，从而能够降低UE功耗，提高系统性能。此外，为了提高虚警率的准确度，可以将CRC总编码器以及所有分段序列对应的Hash编码器均考虑在内。
实施例七
在实施例七中，第一编码器采用非线性卷积码Hash编码器，而第二编码器均采用线性分组码CRC编码器，如图10所示，为本申请实施例七提供的一种极化码编码的示意图，由图10可以看出，发送端先将待编码的信息序列m通过CRC总编码器编码后得到码字序列e 1，然后根据收发双方已确认的分段策略码字序列e 1将划分为I个分段序列，记I段分段序列为{m 1,m 2,...,m I}。
然后，根据分段序列m 1以及预先设定的收发双方已知的Hash编码器1的输出值S 1采用Hash编码器1以及截断函数T1，生成hash序列h 1(未示出)，之后将分段序列m 1和hash 序列h 1进行组合生成码字序列c′ 1。
具体的，在生成hash序列h 1时，一方面将分段序列m 1转化为十进制数值输入Hash编码器1，另一方面将收发双方已知的Hash编码器1的输出值S 1输入Hash编码器1，从而生成Hash编码器1的输出值S 2，然后将该输出值S 2转化为比特流，并截取该比特流的部分或全部，从而作为该信息序列对应的hash序列h 1，将分段序列m 1和hash序列h 1进行组合，生成码字序列c′ 1，从而进一步降低了虚警率。
在截取该比特流的部分或全部时，可以按照一定的方法来截取，例如设置了Hash序列的长度，则在该比特流中截取该长度对应的Hash序列，可以从设定位置截取，该设定位置可以是第一位，或者非第一位，可以是从第一位开始往后截取，也可以是从末尾往前开始截取等等。只要保证编码时采用的Hash序列的截取方式，与译码时采用的截取方式相同即可。
可选的，在本申请实施例中截取得到的Hash序列的长度不大于32比特位。该Hash序列的长度例如可以为8比特位、或32比特位等等。
而在根据分段序列m 2以及Hash编码器1的输出值S 2采用Hash编码器2以及截断函数T2，从而生成hash序列h 2(未示出)，之后将分段序列m 2和hash序列h 2进行组合生成码字序列c′ 2。
具体的，在生成hash序列h 2时，一方面将分段序列m 2转化为十进制数值输入Hash编码器2，另一方面将Hash编码器1的输出值S 2输入Hash编码器2，从而生成Hash编码器2的输出值S 3，然后将该输出值S 3转化为比特流，并截取该比特流的部分或全部，从而作为该信息序列对应的hash序列h 2，将分段序列m 2和hash序列h 2进行组合，生成码字序列c′ 2，从而进一步降低了虚警率。
而在根据分段序列m 3以及Hash编码器2的输出值S 3采用Hash编码器3以及截断函数T3，从而生成hash序列h 3(未示出)，之后将分段序列m 3和hash序列h 3进行组合生成码字序列c′ 3。
具体的，在生成hash序列h 3时，一方面将分段序列m 3转化为十进制数值输入Hash编码器3，另一方面将Hash编码器2的输出值S 3输入Hash编码器3，从而生成Hash编码器3的输出值S 4(未示出)，然后将该输出值S 4转化为比特流，并截取该比特流的部分或全部，从而作为该信息序列对应的hash序列h 3，将分段序列m 3和hash序列h 3进行组合， 生成码字序列c′ 3，从而进一步降低了虚警率。
同理，根据分段序列m i以及Hash编码器i-1的输出值S i采用Hash编码器i以及截断函数Ti，从而生成hash序列h i(未示出)，之后将分段序列m i和hash序列h i进行组合生成码字序列c′ i，从而进一步降低了虚警率。
然后，将码字序列c′ 1、码字序列c′ 2、码字序列c′ 3以及码字序列c′ i按照收发双方已确认的组合方式进行组合后得到码字序列d 1，最后将码字序列d 1送入polar码编码器，进行编码。Polar母码的长度一定是2的整数次幂，而输出码字的长度可能是任意的，故需要rate matching操作，即执行减缩(shortening)或者打孔(puncturing)操作。rate matching操作采用的rate matching序列可选的可以利用高斯近似方法获得，或者采用对SNR不敏感的其他rate matching序列，polar编码器输出的是rate matching后的编码序列。编码后的序列经过调制器调制，就可以在信道中发送给接收端了。
需要注意的是，Hash编码器1、Hash编码器2以及Hash编码器i可以相同，例如，Hash编码器1、Hash编码器2以及Hash编码器i所生成的Hash序列的长度均为8比特位；Hash编码器1、Hash编码器2以及Hash编码器i也可以不同，例如，Hash编码器1、Hash编码器2所生成的Hash序列的长度均为8比特位，而Hash编码器i所生成的Hash序列的长度均为32比特位，只要保证编码时采用的Hash编码器，与译码时采用的Hash编码器相同即可。截断函数T1、截断函数T2以及截断函数Ti所截取的相应的Hash编码器的比特位数可以相同，也可以不同，只要保证收发双方已知即可。
为了进一步降低虚警率，在本申请实施例中该Hash编码特点为分段序列对应的v-bit状态的变化，会引起下一个分段序列对应的v-bit状态无规则的不同，即雪崩效应，从而通过Hash编码可以进一步降低虚警率。
基于图10所示的编码过程相应的译码过程与图9B所示的译码过程类似，在此，不再赘述。
根据以上内容可以看出，由于将待编码的信息序列分成I个分段序列m i，而针对任一分段序列m i又生成对应的校验序列，从而使得在译码时能够根据分段策略进行分段译码，并根据分段序列m i所对应的校验序列对译码得到的分段序列m i进行校验，在校验不通过的情况下，则终止译码，由于在译码时针对任一分段序列m i均进行校验，并在校验不通过的情况下，则终止译码，而不是在译码得到整个信息序列之后再进行校验，因此，不仅能够降低虚警率和误块率，还能够降低译码的时延，从而能够降低UE功耗，提高系统性能。 此外，为了提高虚警率的准确度，可以将CRC总编码器以及所有分段序列对应的Hash编码器均考虑在内。
第二编码器为非线性编码器的编码流程和译码流程，与上述实施例五、实施例六、实施例七所示的编码流程和译码流程，在此不再赘述。
实施例八
图11示例性示出了本申请实施例提供的一种极化码译码方法流程示意图，如图11所示，该方法可包括：
S1101、对接收到的极化码编码后的序列进行解调；
S1102、根据收发双方已确认的分段策略，对解调后的序列进行连续删除列表SCL译码，得到第j段的码字序列C j；1≤j≤I且I＞1；I为分段策略对应的分段数量；
S1103、根据与所述第j段对应的第一译码器对所述码字序列C j进行校验，若校验不通过，则终止译码；所述第j段对应的第一译码器与发送端的所述第j段的第一编码器相对应。
本申请实施例提供的极化码译码方法可以应用于接收端，所述接收端可以是基站，也可以是UE。
可选的，该方法还包括：若所述码字序列C j校验通过，则对解调后的序列进行SCL译码，得到第j+1段的码字序列C j+1；
根据与所述第j+1段对应的第一译码器对所述码字序列C j+1进行校验，直至第j+1段码字序列校验不通过或第I段码字序列校验通过。
可选的，在得到第j段的码字序列C j后，确定所保留的R条候选路径；
基于所述R条候选路径，对解调后的序列进行SCL译码得到码字序列C j+1；
对所述码字序列C j+1采用与所述第j+1段对应的第一译码算法对所述码字序列C j+1进行校验。
可选的，该方法还包括：
在对解调后的序列进行SCL译码得到最后一个码子序列后，若仍存在被保留的Q条路径，则根据与所述第二编码器相对应的第二译码器对被保留的Q路径所输出的码字序列进行校验，并将第一条通过校验的路径序列作为译码输出，否则，将被保留的Q路径中具有最大路径度量值的路径中序列作为译码输出，其中，Q≤L且L为预先设定的路径数量。
根据以上内容可以看出，由于将待编码的信息序列分成I个分段序列m i，而针对任一分段序列m i又生成对应的校验序列，从而使得在译码时能够根据分段策略进行分段译码，并根据分段序列m i所对应的校验序列对译码得到的分段序列m i进行校验，在校验不通过的情况下，则终止译码，由于在译码时针对任一分段序列m i均进行校验，并在校验不通过的情况下，则终止译码，而不是在译码得到整个信息序列之后再进行校验，因此，不仅能够降低虚警率和误块率，还能够降低译码的时延，从而能够降低UE功耗，提高系统性能。此外，为了提高虚警率的准确度，可以将CRC总编码器和所有分段序列对应的CRC编码器均考虑在内。
基于相同的技术构思，本申请实施例还提供一种极化码编码装置，如图12所示，该装置可包括：分段模块1201，用于根据收发双方已确认的分段策略对待编码的信息序列进行分段，生成I个分段序列m i；1≤i≤I且I＞1；
组合模块1202，用于针对任一分段序列m i，根据所述分段序列m i及所述分段序列m i对应的第一编码器，生成第一校验序列，将所述分段序列m i和所述第一校验序列组合成第一码字序列；
编码模块1203，用于将I个第一码字序列进行组合得到第二码字序列，并对所述第二码字序列进行极化码编码。
可选的，分段模块1201，还用于：在根据收发双方已确认的分段策略对待编码的信息序列进行分段之前，根据所述待编码的信息序列和第二编码器，生成第二校验序列；
分段模块1201，具体用于：将所述待编码的信息序列和所述第二校验序列进行组合后，采用所述分段策略，生成I个分段序列m i。
可选的，所述第一编码器为线性编码器或非线性编码器；所述第二编码器为线性编码器或非线性编码器。
可选的，所述线性编码器为CRC编码器；所述非线性编码器为Hash编码器。
可选的，所述第一编码器为Hash编码器；
所述组合模块，具体用于：将所述分段序列m i和分段序列m i所对应的Hash编码器的输出值输入至分段序列m i所对应的Hash编码器，生成第一校验序列；其中，分段序列m i所对应的Hash编码器的输出值为预设值。
可选的，所述第一编码器为Hash编码器；
所述组合模块，具体用于：将所述分段序列m i和分段序列m i-1所对应的Hash编码器 的输出值输入至分段序列m i所对应的Hash编码器，生成第一校验序列；其中，当分段序列m i-1为排序第一的分段序列时，分段序列m i-1所对应的Hash编码器的输出值为预设值。
可选的，所述分段策略为以下任一种：
等分策略、非等分策略、段间重叠策略、段间无重叠策略、依序划分策略、乱序划分策略、全部划分策略及部分划分策略。
本申请实施例还提供一种极化码译码装置，如图13所示，该装置可包括：
解调模块1301，用于对接收到的极化码编码后的序列进行解调；
译码模块1302，用于根据收发双方已确认的分段策略，对解调后的序列进行连续删除列表SCL译码，得到第j段的码字序列C j；1≤j≤I且I＞1；I为分段策略对应的分段数量；
第一校验模块1303，用于根据与所述第j段对应的第一译码器对所述码字序列C j进行校验，若校验不通过，则终止译码；所述第j段对应的第一译码器与发送端的所述第j段的第一编码器相对应。
可选的，第一校验模块1303，还用于：
若所述码字序列C j校验通过，则对解调后的序列进行SCL译码，得到第j+1段的码字序列C j+1；
根据与所述第j+1段对应的第一译码器对所述码字序列C j+1进行校验，直至第j+1段码字序列校验不通过或第I段码字序列校验通过。
可选的，第一校验模块1303，具体用于：
在得到第j段的码字序列C j后，确定所保留的R条候选路径；
基于所述R条候选路径，对解调后的序列进行SCL译码得到码字序列C j+1；
对所述码字序列C j+1采用与所述第j+1段对应的第一译码算法对所述码字序列C j+1进行校验。
可选的，还包括：第二校验模块1304；
第二校验模块1304，用于在对解调后的序列进行SCL译码得到最后一个码子序列后，仍存在被保留的Q条路径时，则根据与所述第二编码器相对应的第二译码器对被保留的Q路径所输出的码字序列进行校验，并将第一条通过校验的路径序列作为译码输出，否则，将被保留的Q路径中具有最大路径度量值的路径中序列作为译码输出，其中，Q≤L且L 为预先设定的路径数量。
本申请实施例还提供一种极化码编码装置，如图14所示，该装置可包括：处理器1400、存储器1401、收发机1402以及总线接口1403。
处理器1400负责管理总线架构和通常的处理，存储器1401可以存储处理器1400在执行操作时所使用的数据。总线架构可以包括任意数量的互联的总线和桥，具体由一个或多个处理器1400和一个或多个存储器1401的各种电路链接在一起。总线架构还可以将诸如外围设备、稳压器和功率管理电路等之类的各种其他电路链接在一起，这些都是本领域所公知的，因此，本文不再对其进行进一步描述。总线接口提供接口。处理器1400负责管理总线架构和通常的处理，存储器1401可以存储处理器1400在执行操作时所使用的数据。
本申请实施例揭示的流程，可以应用于处理器1400中，或者由处理器1400实现。在实现过程中，信号处理流程的各步骤可以通过处理器1400中的硬件的集成逻辑电路或者软件形式的指令完成。处理器1400可以是通用处理器、数字信号处理器、专用集成电路、现场可编程门阵列或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件，可以实现或者执行本申请实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者任何常规的处理器等。结合本申请实施例所公开的方法的步骤可以直接体现为硬件处理器执行完成，或者用处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器1401，处理器1400读取存储器1401中的信息，结合其硬件完成信号处理流程的步骤。
具体地，处理器1400，用于读取存储器1401中的程序并执行：
根据收发双方已确认的分段策略对待编码的信息序列进行分段，生成I个分段序列m i；1≤i≤I且I＞1；针对任一分段序列m i，根据所述分段序列m i及所述分段序列m i对应的第一编码器，生成第一校验序列，将所述分段序列m i和所述第一校验序列组合成第一码字序列；将I个第一码字序列进行组合得到第二码字序列，并对所述第二码字序列进行极化码编码。
可选的，所述处理器1400，还用于：
在根据收发双方已确认的分段策略对待编码的信息序列进行分段之前，根据所述待编码的信息序列和第二编码器，生成第二校验序列；
所述处理器1400，具体用于：
将所述待编码的信息序列和所述第二校验序列进行组合后，采用所述分段策略，生成 I个分段序列m i。
可选的，所述第一编码器为线性编码器或非线性编码器；所述第二编码器为线性编码器或非线性编码器。
可选的，所述线性编码器为CRC编码器；所述非线性编码器为Hash编码器。
可选的，所述第一编码器为Hash编码器；
所述处理器1400，具体用于：
将所述分段序列m i和分段序列m i所对应的Hash编码器的输出值输入至分段序列m i所对应的Hash编码器，生成第一校验序列；其中，分段序列m i所对应的Hash编码器的输出值为预设值。
可选的，所述第一编码器为Hash编码器；
所述处理器1400，具体用于：
将所述分段序列m i和分段序列m i-1所对应的Hash编码器的输出值输入至分段序列m i所对应的Hash编码器，生成第一校验序列；其中，当分段序列m i-1为排序第一的分段序列时，分段序列m i-1所对应的Hash编码器的输出值为预设值。
可选的，所述分段策略为以下任一种：
等分策略、非等分策略、段间重叠策略、段间无重叠策略、依序划分策略、乱序划分策略、全部划分策略及部分划分策略。
本申请实施例还提供一种极化码译码装置，如图15所示，该装置可包括：处理器1500、存储器1501、收发机1502以及总线接口1503。
处理器1500负责管理总线架构和通常的处理，存储器1501可以存储处理器1500在执行操作时所使用的数据。总线架构可以包括任意数量的互联的总线和桥，具体由一个或多个处理器1500和一个或多个存储器1501的各种电路链接在一起。总线架构还可以将诸如外围设备、稳压器和功率管理电路等之类的各种其他电路链接在一起，这些都是本领域所公知的，因此，本文不再对其进行进一步描述。总线接口提供接口。处理器1500负责管理总线架构和通常的处理，存储器1501可以存储处理器1500在执行操作时所使用的数据。
本申请实施例揭示的流程，可以应用于处理器1500中，或者由处理器1500实现。在实现过程中，信号处理流程的各步骤可以通过处理器1500中的硬件的集成逻辑电路或者软件形式的指令完成。处理器1500可以是通用处理器、数字信号处理器、专用集成电路、现场可编程门阵列或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件， 可以实现或者执行本申请实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者任何常规的处理器等。结合本申请实施例所公开的方法的步骤可以直接体现为硬件处理器执行完成，或者用处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器1501，处理器1500读取存储器1501中的信息，结合其硬件完成信号处理流程的步骤。
具体地，处理器1500，用于读取存储器1501中的程序并执行：
对接收到的极化码编码后的序列进行解调；根据收发双方已确认的分段策略，对解调后的序列进行连续删除列表SCL译码，得到第j段的码字序列C j；1≤j≤I且I＞1；I为分段策略对应的分段数量；根据与所述第j段对应的第一译码器对所述码字序列C j进行校验，若校验不通过，则终止译码；所述第j段对应的第一译码器与发送端的所述第j段的第一编码器相对应。
可选的，所述处理器1500，还用于：
若所述码字序列C j校验通过，则对解调后的序列进行SCL译码，得到第j+1段的码字序列C j+1；根据与所述第j+1段对应的第一译码器对所述码字序列C j+1进行校验，直至第j+1段码字序列校验不通过或第I段码字序列校验通过。
可选的，所述处理器1500，具体用于：
在得到第j段的码字序列C j后，确定所保留的R条候选路径；基于所述R条候选路径，对解调后的序列进行SCL译码得到码字序列C j+1；对所述码字序列C j+1采用与所述第j+1段对应的第一译码算法对所述码字序列C j+1进行校验。
可选的，所述处理器1500，还用于：
在对解调后的序列进行SCL译码得到最后一个码子序列后，若仍存在被保留的Q条路径，则根据与所述第二编码器相对应的第二译码器对被保留的Q路径所输出的码字序列进行校验，并将第一条通过校验的路径序列作为译码输出，否则，将被保留的Q路径中具有最大路径度量值的路径中序列作为译码输出，其中，Q≤L且L为预先设定的路径数量。
本申请实施例公开一种可读存储介质，其特征在于，包括程序代码，当所述程序代码在计算设备上运行时，所述程序代码用于使所述计算设备执行极化码编码装置执行的步骤，或执行极化码译码装置执行的步骤。
综上，可以看出，由于将待编码的信息序列分成I个分段序列m i，而针对任一分段序列m i又生成对应的校验序列，从而使得在译码时能够根据分段策略进行分段译码，并根据分段序列m i所对应的校验序列对译码得到的分段序列m i进行校验，在校验不通过的情况下，则终止译码，由于在译码时针对任一分段序列m i均进行校验，并在校验不通过的情况下，则终止译码，而不是在译码得到整个信息序列之后进行校验，此时，校验不通过，再终止译码，因此，不仅能够降低虚警率和误块率，还能够降低译码的时延，从而能够降低UE功耗，提高系统性能。此外，为了提高虚警率的准确度，可以将CRC总编码器和所有分段序列对应的CRC编码器或Hash编码器均考虑在内。
本申请实施例中，术语“基站”包括但不限于节点、站控制器、接入点(Access Point，简称AP)、或任何其它类型的能够在无线环境中工作的接口设备。
本申请所涉及到的用户设备UE可以包括具有无线通信功能的手持设备、车载设备、可穿戴设备、计算设备或连接到无线调制解调器的其它处理设备,以及各种形式的用户设备(User Equipment,简称UE)，移动台(Mobile station,简称MS)，终端(terminal)，终端设备(Terminal Equipment)等等。为方便描述，本申请中，简称为用户设备或UE。
本申请实施例适用的通信制式包括但不限于：全球移动通信系统(Global System of Mobile communication，GSM)、码分多址(Code Division Multiple Access，CDMA)IS-95、码分多址(Code Division Multiple Access，CDMA)2000、时分同步码分多址(Time Division-Synchronous Code Division Multiple Access，TD-SCDMA)、宽带码分多址(Wideband Code Division Multiple Access，WCDMA)、时分双工-长期演进(Time Division Duplexing-Long Term Evolution，TDD LTE)、频分双工-长期演进(Frequency Division Duplexing-Long Term Evolution，FDD LTE)、长期演进-增强(Long Term Evolution-Advanced，LTE-advanced)、个人手持电话系统(Personal Handy-phone System，PHS)、802.11系列协议规定的无线保真(Wireless Fidelity，WiFi)、全球微波互联接入(Worldwide Interoperability for Microwave Access，WiMAX)，以及未来演进的各种无线通信系统。
本申请实施例中，终端可以是无线终端，无线终端可以是指向用户提供语音和/或数据连通性的设备，具有无线连接功能的手持式设备、或连接到无线调制解调器的其他处理设备。无线终端可以经无线接入网(例如，RAN，Radio Access Network)与一个或多个核心网进行通信，无线终端可以是移动终端，如移动电话(或称为“蜂窝”电话)和具有移动终端的计算机，例如，可以是便携式、袖珍式、手持式、计算机内置的或者车载的移动装置，它们与无线接入网交换语言和/或数据。例如，个人通信业务(PCS，Personal Communication  Service)电话、无绳电话、会话发起协议(SIP)话机、无线本地环路(WLL，Wireless Local Loop)站、个人数字助理(PDA，Personal Digital Assistant)等设备。无线终端也可以称为订户单元(Subscriber Unit)、订户站(Subscriber Station)，移动站(Mobile Station)、移动台(Mobile)、远程站(Remote Station)、接入点(Access Point)、远程终端(Remote Terminal)、接入终端(Access Terminal)、用户终端(User Terminal)、用户代理(User Agent)、用户设备(User Device)、或用户装备(User Equipment)。
本领域内的技术人员应明白，本申请的实施例可提供为方法、或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本申请是参照根据本申请实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
尽管已描述了本申请的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本申请范围的所有变更和修改。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内， 则本申请也意图包含这些改动和变型在内。

Claims (34)

  1. 一种极化码编码方法，其特征在于，包括：
    根据收发双方已确认的分段策略对待编码的信息序列进行分段，生成I个分段序列m i；1≤i≤I且I＞1；
    针对任一分段序列m i，根据所述分段序列m i及所述分段序列m i对应的第一编码器，生成第一校验序列，将所述分段序列m i和所述第一校验序列组合成第一码字序列；
    将I个第一码字序列进行组合得到第二码字序列，并对所述第二码字序列进行极化码编码。
  2. 如权利要求1所述的方法，其特征在于，在根据收发双方已确认的分段策略对待编码的信息序列进行分段之前，还包括：
    根据所述待编码的信息序列和第二编码器，生成第二校验序列；
    所述根据收发双方已确认的分段策略对待编码的信息序列进行分段，包括：
    将所述待编码的信息序列和所述第二校验序列进行组合后，采用所述分段策略，生成I个分段序列m i。
  3. 如权利要求1所述的方法，其特征在于，所述第一编码器为线性编码器或非线性编码器；所述第二编码器为线性编码器或非线性编码器。
  4. 如权利要求3所述的方法，其特征在于，所述线性编码器为CRC编码器；所述非线性编码器为Hash编码器。
  5. 如权利要求4所述的方法，其特征在于，所述第一编码器为Hash编码器；
    所述根据所述分段序列m i及所述分段序列m i对应的第一编码器，生成第一校验序列，将所述分段序列m i和所述第一校验序列组合成第一码字序列，包括：
    将所述分段序列m i和分段序列m i所对应的Hash编码器的输出值输入至分段序列m i所对应的Hash编码器，生成第一校验序列；其中，分段序列m i所对应的Hash编码器的输出值为预设值。
  6. 如权利要求4所述的方法，其特征在于，所述第一编码器为Hash编码器；
    所述根据所述分段序列m i及所述分段序列m i对应的第一编码器，生成第一校验序列，将所述分段序列m i和所述第一校验序列组合成第一码字序列，包括：
    将所述分段序列m i和分段序列m i-1所对应的Hash编码器的输出值输入至分段序列m i 所对应的Hash编码器，生成第一校验序列；其中，当分段序列m i-1为排序第一的分段序列时，分段序列m i-1所对应的Hash编码器的输出值为预设值。
  7. 如权利要求1所述的方法，其特征在于，所述分段策略为以下任一种：
    等分策略、非等分策略、段间重叠策略、段间无重叠策略、依序划分策略、乱序划分策略、全部划分策略及部分划分策略。
  8. 一种基于极化码编码的译码方法，其特征在于，包括：
    对接收到的极化码编码后的序列进行解调；
    根据收发双方已确认的分段策略，对解调后的序列进行连续删除列表SCL译码，得到第j段的码字序列C j；1≤j≤I且I＞1；I为分段策略对应的分段数量；
    根据与所述第j段对应的第一译码器对所述码字序列C j进行校验，若校验不通过，则终止译码；所述第j段对应的第一译码器与发送端的所述第j段的第一编码器相对应。
  9. 如权利要求8所述的方法，其特征在于，该方法还包括：
    若所述码字序列C j校验通过，则对解调后的序列进行SCL译码，得到第j+1段的码字序列C j+1；
    根据与所述第j+1段对应的第一译码器对所述码字序列C j+1进行校验，直至第j+1段码字序列校验不通过或第I段码字序列校验通过。
  10. 如权利要求9所述的方法，其特征在于，所述根据与所述第j+1段对应的第一译码器对所述码字序列C j+1进行校验，包括：
    在得到第j段的码字序列C j后，确定所保留的R条候选路径；
    基于所述R条候选路径，对解调后的序列进行SCL译码得到码字序列C j+1；
    对所述码字序列C j+1采用与所述第j+1段对应的第一译码算法对所述码字序列C j+1进行校验。
  11. 如权利要求10所述的方法，其特征在于，该方法还包括：
    在对解调后的序列进行SCL译码得到最后一个码子序列后，若仍存在被保留的Q条路径，则根据与所述第二编码器相对应的第二译码器对被保留的Q路径所输出的码字序列进行校验，并将第一条通过校验的路径序列作为译码输出，否则，将被保留的Q路径中具有最大路径度量值的路径中序列作为译码输出，其中，Q≤L且L为预先设定的路径数量。
  12. 一种极化码编码装置，其特征在于，包括：
    分段模块，用于根据收发双方已确认的分段策略对待编码的信息序列进行分段，生成I个分段序列m i；1≤i≤I且I＞1；
    组合模块，用于针对任一分段序列m i，根据所述分段序列m i及所述分段序列m i对应的第一编码器，生成第一校验序列，将所述分段序列m i和所述第一校验序列组合成第一码字序列；
    编码模块，用于将I个第一码字序列进行组合得到第二码字序列，并对所述第二码字序列进行极化码编码。
  13. 如权利要求12所述的装置，其特征在于，所述分段模块，还用于：在根据收发双方已确认的分段策略对待编码的信息序列进行分段之前，根据所述待编码的信息序列和第二编码器，生成第二校验序列；
    所述分段模块，具体用于：将所述待编码的信息序列和所述第二校验序列进行组合后，采用所述分段策略，生成I个分段序列m i。
  14. 如权利要求12所述的装置，其特征在于，所述第一编码器为线性编码器或非线性编码器；所述第二编码器为线性编码器或非线性编码器。
  15. 如权利要求14所述的装置，其特征在于，所述线性编码器为CRC编码器；所述非线性编码器为Hash编码器。
  16. 如权利要求15所述的装置，其特征在于，所述第一编码器为Hash编码器；
    所述组合模块，具体用于：将所述分段序列m i和分段序列m i所对应的Hash编码器的输出值输入至分段序列m i所对应的Hash编码器，生成第一校验序列；其中，分段序列m i所对应的Hash编码器的输出值为预设值。
  17. 如权利要求15所述的装置，其特征在于，所述第一编码器为Hash编码器；
    所述组合模块，具体用于：将所述分段序列m i和分段序列m i-1所对应的Hash编码器的输出值输入至分段序列m i所对应的Hash编码器，生成第一校验序列；其中，当分段序列m i-1为排序第一的分段序列时，分段序列m i-1所对应的Hash编码器的输出值为预设值。
  18. 如权利要求12所述的装置，其特征在于，所述分段策略为以下任一种：
    等分策略、非等分策略、段间重叠策略、段间无重叠策略、依序划分策略、乱序划分策略、全部划分策略及部分划分策略。
  19. 一种基于极化码编码的译码装置，其特征在于，包括：
    解调模块，用于对接收到的极化码编码后的序列进行解调；
    译码模块，用于根据收发双方已确认的分段策略，对解调后的序列进行连续删除列表 SCL译码，得到第j段的码字序列C j；1≤j≤I且I＞1；I为分段策略对应的分段数量；
    第一校验模块，用于根据与所述第j段对应的第一译码器对所述码字序列C j进行校验，若校验不通过，则终止译码；所述第j段对应的第一译码器与发送端的所述第j段的第一编码器相对应。
  20. 如权利要求19所述的装置，其特征在于，所述第一校验模块，还用于：
    若所述码字序列C j校验通过，则对解调后的序列进行SCL译码，得到第j+1段的码字序列C j+1；
    根据与所述第j+1段对应的第一译码器对所述码字序列C j+1进行校验，直至第j+1段码字序列校验不通过或第I段码字序列校验通过。
  21. 如权利要求20所述的装置，其特征在于，所述第一校验模块，具体用于：
    在得到第j段的码字序列C j后，确定所保留的R条候选路径；
    基于所述R条候选路径，对解调后的序列进行SCL译码得到码字序列C j+1；
    对所述码字序列C j+1采用与所述第j+1段对应的第一译码算法对所述码字序列C j+1进行校验。
  22. 如权利要求21所述的装置，其特征在于，还包括：第二校验模块；
    所述第二校验模块，用于在对解调后的序列进行SCL译码得到最后一个码子序列后，仍存在被保留的Q条路径时，则根据与所述第二编码器相对应的第二译码器对被保留的Q路径所输出的码字序列进行校验，并将第一条通过校验的路径序列作为译码输出，否则，将被保留的Q路径中具有最大路径度量值的路径中序列作为译码输出，其中，Q≤L且L为预先设定的路径数量。
  23. 一种极化码编码装置，其特征在于，包括处理器、存储器和收发机；
    处理器，用于读取存储器中的程序并执行下列过程：
    根据收发双方已确认的分段策略对待编码的信息序列进行分段，生成I个分段序列m i；1≤i≤I且I＞1；针对任一分段序列m i，根据所述分段序列m i及所述分段序列m i对应的第一编码器，生成第一校验序列，将所述分段序列m i和所述第一校验序列组合成第一码字序列；将I个第一码字序列进行组合得到第二码字序列，并对所述第二码字序列进行极化码编码。
  24. 如权利要求23所述的装置，其特征在于，所述处理器，还用于：
    在根据收发双方已确认的分段策略对待编码的信息序列进行分段之前，根据所述待编码的信息序列和第二编码器，生成第二校验序列；
    所述处理器，具体用于：
    将所述待编码的信息序列和所述第二校验序列进行组合后，采用所述分段策略，生成I个分段序列m i。
  25. 如权利要求23所述的装置，其特征在于，所述第一编码器为线性编码器或非线性编码器；所述第二编码器为线性编码器或非线性编码器。
  26. 如权利要求25所述的装置，其特征在于，所述线性编码器为CRC编码器；所述非线性编码器为Hash编码器。
  27. 如权利要求26所述的装置，其特征在于，所述第一编码器为Hash编码器；
    所述处理器，具体用于：
    将所述分段序列m i和分段序列m i所对应的Hash编码器的输出值输入至分段序列m i所对应的Hash编码器，生成第一校验序列；其中，分段序列m i所对应的Hash编码器的输出值为预设值。
  28. 如权利要求26所述的装置，其特征在于，所述第一编码器为Hash编码器；
    所述处理器，具体用于：
    将所述分段序列m i和分段序列m i-1所对应的Hash编码器的输出值输入至分段序列m i所对应的Hash编码器，生成第一校验序列；其中，当分段序列m i-1为排序第一的分段序列时，分段序列m i-1所对应的Hash编码器的输出值为预设值。
  29. 如权利要求23所述的装置，其特征在于，所述分段策略为以下任一种：
    等分策略、非等分策略、段间重叠策略、段间无重叠策略、依序划分策略、乱序划分策略、全部划分策略及部分划分策略。
  30. 一种基于极化码编码的译码装置，其特征在于，包括处理器、存储器和收发机；
    处理器，用于读取存储器中的程序并执行下列过程：
    对接收到的极化码编码后的序列进行解调；根据收发双方已确认的分段策略，对解调后的序列进行连续删除列表SCL译码，得到第j段的码字序列C j；1≤j≤I且I＞1；I为分段策略对应的分段数量；根据与所述第j段对应的第一译码器对所述码字序列C j进行校验，若校验不通过，则终止译码；所述第j段对应的第一译码器与发送端的所述第j段的第一编码器相对应。
  31. 如权利要求30所述的装置，其特征在于，所述处理器，还用于：
    若所述码字序列C j校验通过，则对解调后的序列进行SCL译码，得到第j+1段的码字序列C j+1；根据与所述第j+1段对应的第一译码器对所述码字序列C j+1进行校验，直至第j+1段码字序列校验不通过或第I段码字序列校验通过。
  32. 如权利要求31所述的装置，其特征在于，所述处理器，具体用于：
    在得到第j段的码字序列C j后，确定所保留的R条候选路径；基于所述R条候选路径，对解调后的序列进行SCL译码得到码字序列C j+1；对所述码字序列C j+1采用与所述第j+1段对应的第一译码算法对所述码字序列C j+1进行校验。
  33. 如权利要求32所述的装置，其特征在于，所述处理器，还用于：
    在对解调后的序列进行SCL译码得到最后一个码子序列后，若仍存在被保留的Q条路径，则根据与所述第二编码器相对应的第二译码器对被保留的Q路径所输出的码字序列进行校验，并将第一条通过校验的路径序列作为译码输出，否则，将被保留的Q路径中具有最大路径度量值的路径中序列作为译码输出，其中，Q≤L且L为预先设定的路径数量。
  34. 一种可读存储介质，其特征在于，包括程序代码，当所述程序代码在计算设备上运行时，所述程序代码用于使所述计算设备执行权利要求1～7任一所述方法的步骤，或执行权利要求8～11任一所述方法的步骤。
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