WO2018165816A1

WO2018165816A1 - Chip fanning out circuit and method

Info

Publication number: WO2018165816A1
Application number: PCT/CN2017/076432
Authority: WO
Inventors: 胡川; 刘俊军
Original assignee: 深圳修远电子科技有限公司
Priority date: 2017-03-13
Filing date: 2017-03-13
Publication date: 2018-09-20

Abstract

The present invention relates to a chip fanning out circuit and method. The chip fanning out method comprises: arranging a chip on a support board, and arranging an auxiliary net and a packaging material on the support board; at least a part of the chip being embedded in the packaging material, at least a part of the auxiliary net being embedded in the packaging material, curing the packaging material to form a packaging layer, and the packaging layer packaging and fixing the chip and the auxiliary net; and disengaging the support board from the chip or the packaging layer or the auxiliary net. Overall bending or deformation caused by packaging the chip by the packaging layer is prevented, thus ensuring that line connection relationship of a circuit is not destroyed by the packaging process.

Description

Chip fanout circuit and method

Technical field

The invention belongs to the field of electronics, and in particular relates to a chip fanout circuit and method.

Scene technology

In the conventional packaging process, the package material is covered by the chip, during which the package material undergoes a heating-cooling-curing process, and the final package circuit is bent or deformed due to thermal imbalance (for example, it may be formed as shown in FIG. 3). The bending), bending or deformation affects the positional relationship and connection relationship of the connection, and the connection error occurs. If the connection line width is very thin, the connection may be broken.

Summary of the invention

Based on this, the present invention overcomes the defects of the prior art, and provides a chip fan-out circuit and method, which avoids the overall bending or deformation of the chip by the package of the package layer, and ensures that the connection relationship of the circuit is not damaged by the packaging process.

Its technical solutions are as follows:

A chip fanout method includes: disposing a chip on a carrier board, and disposing an auxiliary net and a packaging material on the carrier board; the chip is at least partially embedded in the encapsulation material, and the auxiliary net is at least partially embedded in the Within the encapsulation material, the encapsulation material is cured into an encapsulation layer that secures the chip and the auxiliary mesh package; the carrier plate is detached from the chip or the encapsulation layer or the auxiliary mesh.

In one of the embodiments, the auxiliary net is provided with a window, the chip at least partially extending into the window.

In one of the embodiments, the chip and the auxiliary mesh both abut the carrier.

In one embodiment, the one side of the encapsulation layer facing the carrier is a first surface, and the side opposite to the first surface is a second surface; the chip is disposed adjacent to the first surface and An auxiliary net; or, the chip is disposed adjacent to the first surface, and the auxiliary net is disposed adjacent to the second surface.

In one embodiment, the chip is adjacent to the first surface, the auxiliary net is adjacent to the first surface, and the auxiliary network has a thermal expansion coefficient greater than a thermal expansion coefficient of the encapsulation layer.

In one embodiment, the chip is adjacent to the first surface, and the auxiliary net is adjacent to the second surface, and the auxiliary network has a thermal expansion coefficient smaller than a thermal expansion coefficient of the encapsulation layer.

In one embodiment, the coefficient of thermal expansion of the encapsulation layer, the coefficient of thermal expansion of the chip, and the coefficient of thermal expansion of the auxiliary net are such that the chip, the auxiliary net, and the The overall thermal stress balance of the encapsulating material.

In one of the embodiments, the maximum thickness of the auxiliary net is greater than the maximum thickness of the chip.

In one embodiment, the auxiliary mesh has a thickness at least less than 100 microns of the thickness of the encapsulation layer.

In one embodiment, the auxiliary network accounts for 10% to 90% of the total area of the encapsulation layer minus the area occupied by the chip.

In one embodiment, the auxiliary mesh is metal, ceramic, or plastic.

In one embodiment, the encapsulating material is a compression molded material.

In one embodiment, the Young's modulus of the auxiliary mesh is greater than the Young's modulus of the encapsulation layer.

A chip fan-out circuit includes: a chip, an encapsulation layer formed by encapsulating a material, and an auxiliary net; wherein the chip is at least partially embedded in the encapsulation layer, and the auxiliary net is at least partially embedded in the In the encapsulation layer, the encapsulation layer fixes the chip and the auxiliary net package, and the auxiliary net is used to reduce bending or deformation caused by curing of the encapsulation material into the encapsulation layer.

In one embodiment, the encapsulation layer has opposing first and second surfaces; the chip and the auxiliary mesh are adjacent to the first surface; or the chip is adjacent to the first surface, The auxiliary net is adjacent to the second surface.

In one embodiment, the chip and the auxiliary net are both flush with the first surface, and And the plane formed by the chip, the auxiliary net, and the first surface is flat.

In one embodiment, the auxiliary mesh is metal, ceramic, or plastic.

In one embodiment, the encapsulating material is a compression molded material.

A chip fan-out method includes: disposing a chip on a carrier board, and disposing an auxiliary fiber and a packaging material on the carrier board; the chip is at least partially embedded in the packaging material, and the auxiliary fiber is at least partially embedded in the package Within the encapsulation material, the encapsulation material is cured into an encapsulation layer that secures the chip and the auxiliary fiber package; the carrier plate is detached from the chip or the encapsulation layer or the auxiliary fiber.

In one of the embodiments, the auxiliary fibers constitute an auxiliary net, the auxiliary net being provided with a window, the chip at least partially extending into the window.

In one embodiment, the one side of the encapsulation layer facing the carrier is a first surface, and the side opposite to the first surface is a second surface; the chip is disposed adjacent to the first surface and An auxiliary fiber; or, the chip is disposed adjacent to the first surface, and the auxiliary fiber is disposed adjacent to the second surface.

In one embodiment, the chip is adjacent to the first surface, the auxiliary fiber is adjacent to the first surface, and the auxiliary fiber has a coefficient of thermal expansion greater than a coefficient of thermal expansion of the encapsulation layer.

In one embodiment, the chip is adjacent to the first surface, the auxiliary fiber is adjacent to the second surface, and the auxiliary fiber has a coefficient of thermal expansion that is less than a coefficient of thermal expansion of the encapsulation layer.

In one embodiment, the coefficient of thermal expansion of the encapsulation layer, the coefficient of thermal expansion of the chip, and the coefficient of thermal expansion of the auxiliary fiber are such that the chip, the auxiliary net, and the The overall thermal stress balance of the encapsulating material.

In one embodiment, the auxiliary fibers are metal, ceramic, or plastic.

In one embodiment, the encapsulating material is a compression molded material.

In one embodiment, the Young's modulus of the auxiliary fibers is greater than the Young's modulus of the encapsulating layer.

A chip fan-out circuit includes: a chip, an encapsulation layer cured from an encapsulation material, and an auxiliary fiber; wherein the chip is at least partially embedded in the encapsulation layer, and the auxiliary fiber is at least partially embedded in the In the encapsulation layer, the encapsulation layer fixes the chip and the auxiliary fiber package, and the auxiliary fiber is used to reduce bending or deformation caused by curing of the encapsulation material into the encapsulation layer.

In one embodiment, the encapsulation layer has opposing first and second surfaces; the chip and the auxiliary fiber are adjacent to the first surface; or the chip is adjacent to the first surface, The auxiliary fibers are adjacent to the second surface.

In one of the embodiments, the chip and the auxiliary net are both flush with the first surface, and the plane formed by the chip, the auxiliary net, and the first surface is flat.

In one embodiment, the coefficient of thermal expansion of the encapsulation layer, the coefficient of thermal expansion of the chip, and the coefficient of thermal expansion of the auxiliary fiber are such that the chip, the auxiliary fiber, and the The overall thermal stress of the encapsulating material tends to be balanced.

In one embodiment, the auxiliary fibers are metal, ceramic, or plastic.

In one embodiment, the encapsulating material is a compression molded material.

The beneficial effects of the invention are:

A method for fan-out of a chip, comprising: disposing a chip on a carrier board, and setting an auxiliary net and a packaging material on the carrier board; the chip is at least partially embedded in the encapsulation material, and the auxiliary net is at least partially embedded in the encapsulation material, The encapsulating material is cured into an encapsulation layer that secures the chip and the auxiliary mesh package; the carrier is detached from the chip or encapsulation layer or the auxiliary mesh.

The chip is arranged under the support of the carrier board, and the placement position of the chip is precise. One chip or more than two chips can be set. When two or more chips are set, the relative positions between the two chips can also be accurately set. The chip is at least partially embedded in the package material (including the chip is completely embedded in the package material, the chip portion is embedded in the package material, and the other portion is exposed to the package material, the chip is completely embedded in the package material and one surface of the chip is from the package layer The surface is bare. When the encapsulation material is cured, the position of the chip relative to the encapsulation layer is fixed. If more than two chips are provided, the relative position between the two chips is fixed by the encapsulation layer. The auxiliary net is at least partially embedded in the encapsulating material (including the auxiliary net is completely embedded in the encapsulating material, the auxiliary net portion is embedded in the encapsulating material, and the other portion is exposed to the encapsulating material, and the auxiliary net is exactly embedded in the encapsulating material and one of the chips The surface is exposed from the surface of the encapsulation layer. When the encapsulation material has a tendency to deform during curing, the interaction force between the auxiliary net and the encapsulation layer occurs, and the auxiliary net relieves the stress caused by the thermal imbalance of the encapsulation layer. The layer can pull or push the encapsulating material to avoid deformation of the thermal imbalance of the encapsulating material. In this way, the encapsulation layer realizes the chip encapsulation, and the auxiliary net avoids the overall bending of the encapsulation material and the chip composition during the process of curing the encapsulation material into the encapsulation layer.

Preferably, when the encapsulating material is granular or liquid or flowable before curing, the encapsulating material can enter the auxiliary net, and the interaction between the auxiliary net and the encapsulating material is increased when the encapsulating material has a tendency to deform during curing of the encapsulating material. The force enables the auxiliary net to better alleviate and balance the curing stress of the encapsulating material and avoid bending or deformation of the encapsulating layer.

2. The auxiliary net is provided with a window, and the chip at least partially protrudes into the window, and may be one chip correspondingly protruded into one window, or two or more chips may be deeply penetrated into one window, and the auxiliary net surrounds or partially surrounds the chip. Since the coefficient of thermal expansion of the chip is different from the coefficient of thermal expansion of the package material, usually the coefficient of thermal expansion of the chip is smaller than the coefficient of thermal expansion of the package material, so that the thermal imbalance of the chip portion is more obvious, and the chip is inserted into the window of the auxiliary network, and the auxiliary The mesh surrounds or partially surrounds the chip Around, it can better alleviate the stress caused by thermal imbalance, and better keep the chip in a predetermined position, so as to ensure that the connection relationship between the chips is not deformed or bent. In addition, the chip is inserted into the window of the auxiliary net to reduce the overall thickness.

3. The chip and the auxiliary network both abut the carrier board. The chip has externally connected contacts, and the chip has a contact side facing the carrier. After the carrier is removed, the chip and the auxiliary network are just embedded in the package layer, and the contacts of the chip are not covered by the package layer but are exposed. The contacts of the chip can be electrically connected to the connection; at this time, the chip protrudes into the window of the auxiliary net, and the auxiliary net is as close as possible to the side of the chip with the contacts, so as to keep the position of the chip as much as possible and There is no deformation in the vicinity, and the position of the contacts of the chip is kept unchanged. In the process of electrically connecting the contacts and the wires of the chip, precise alignment can be realized, and the precise electrical connection of the chip contacts and the wires can be ensured.

The traditional method can not overcome the problem of package deformation. It is usually necessary to widen the line width of the connection, increase the gap between the lines to compensate for the misalignment caused by the deformation, and cannot obtain a high-density connection, which limits the transmission speed of the chip. . However, the method of the present invention can overcome the deformation of the package, and can make the line width of the connection less than 10 micrometers, increase the density of the connection, and set more connections in the same space to obtain more data transmission channels.

4. The one side of the encapsulation layer facing the carrier board is a first surface, and the side opposite to the first surface is a second surface, and the chip and the auxiliary net are disposed adjacent to the first surface; on the one hand, since the first surface is close to the carrier board, it is more advantageous Limiting the deformation of the encapsulation layer near the chip; on the other hand, since the thermal expansion coefficient of the chip is different from the thermal expansion coefficient of the encapsulation material, usually the thermal expansion coefficient of the chip is smaller than the thermal expansion coefficient of the encapsulation material, so that the thermal imbalance of the chip portion is more obvious. The chip and the auxiliary net are simultaneously disposed at a position close to the first surface, and the auxiliary net limits the deformation of the first surface, thereby ensuring the position of the chip.

Alternatively, a chip is disposed adjacent to the first surface, and an auxiliary net is disposed adjacent to the second surface. Since the coefficient of thermal expansion of the chip is different from the coefficient of thermal expansion of the package material, usually the coefficient of thermal expansion of the chip is smaller than the coefficient of thermal expansion of the package material, so the first surface near the chip is more thermally uneven, but the package layer is usually sheet-like, The deformation of the first surface is limited by providing an auxiliary mesh near the second surface to limit deformation of the second surface.

5. The chip is close to the first surface, the auxiliary net is close to the first surface, and the thermal expansion coefficient of the auxiliary net is greater than The coefficient of thermal expansion of the encapsulation layer. The auxiliary net and the chip are disposed close to the first surface at the same time, the thermal expansion coefficient of the chip is smaller than the thermal expansion coefficient of the packaging material, the thermal expansion coefficient of the auxiliary net is larger than the thermal expansion coefficient of the encapsulation layer, the thermal stress of the chip and the thermal stress of the auxiliary fiber when the temperature changes. The mutual offset, the shape variable of the auxiliary net and the deformation of the encapsulation layer are offset to avoid deformation of the encapsulation layer. In particular, the first surface is the side of the encapsulation layer facing the carrier, and the auxiliary net and the chip are disposed adjacent to the first surface at the same time. The position can avoid deformation of the first surface. The thermal expansion coefficient of the auxiliary net is larger than the thermal expansion coefficient of the encapsulating layer. In the process of cooling and curing the encapsulating material, the shrinkage of the auxiliary net is greater than the shrinkage of the encapsulating material, and the auxiliary net pulls the encapsulating layer from the first surface so that the encapsulating layer does not bend.

6. The chip is close to the first surface, the thermal expansion coefficient of the chip is smaller than the thermal expansion coefficient of the packaging material; the auxiliary mesh is close to the second surface, the thermal expansion coefficient of the auxiliary mesh is smaller than the thermal expansion coefficient of the encapsulation layer, and the stress of the chip and the stress of the auxiliary mesh are on the encapsulation layer. It is symmetrical or approximately symmetrical to avoid deformation of the encapsulation layer. The thermal expansion coefficient of the auxiliary net is smaller than the thermal expansion coefficient of the encapsulating layer. During the process of cooling and curing the encapsulating particles, the shrinkage of the auxiliary net is smaller than the shrinkage of the encapsulating layer, and the auxiliary net resists shrinkage of the encapsulating layer on the second surface, so that the encapsulating layer is not bending.

Preferably, the maximum thickness of the auxiliary net is greater than the maximum thickness of the chip. The auxiliary net can prevent the deformation of the encapsulation layer and provide support for the chip to avoid chip damage.

The thickness of the auxiliary net is such that it is in the cross section as shown in FIG. 5, and the thickness of the auxiliary net is in the up and down direction as shown in FIG. 5. Similarly, the thickness of the chip refers to the horizontal direction as shown in FIG. In the cross section, the thickness of the chip in the up and down direction as shown in FIG.

Preferably, the thickness of the auxiliary net is at least 100 micrometers less than the thickness of the encapsulating layer, which facilitates the flow of the encapsulating material, ensures that the encapsulating material fills the space around the chip, and enables the encapsulating layer to better fix the chip. Moreover, the surface of the encapsulating material after curing the encapsulating layer can be flattened.

Preferably, the auxiliary network accounts for 10% to 90% of the total area of the encapsulation layer minus the area occupied by the chip. Conducive to the flow of the packaging material, to ensure that the packaging material fills the space around the chip, so that the encapsulation layer can better fix the chip.

7. The thermal expansion coefficient of the encapsulation layer, the thermal expansion coefficient of the chip, and the thermal expansion coefficient of the auxiliary net make the overall thermal stress of the chip, the auxiliary net and the encapsulating material balanced during the process of curing the encapsulating material. Selecting the thermal expansion coefficient and the set position of the chip, the auxiliary net and the encapsulating material can offset the integral shape variables of the encapsulation layer, the chip and the auxiliary fiber, and balance the thermal stress to avoid deformation.

8. The auxiliary net is metal, ceramic, or plastic.

9. The encapsulating material is a molding material, and the molding compound can form an encapsulation layer by curing, and the encapsulation layer fixes the chip package. Molded molding materials include, but are not limited to, molded resins.

10. The Young's modulus of the auxiliary net is larger than the Young's modulus of the encapsulation layer. The auxiliary net itself has strong bending resistance and can resist the deformation of the encapsulation layer. For example, the auxiliary material can be made by selecting a metal material.

11. A chip fanout method comprising: disposing a chip on a carrier board and disposing an auxiliary fiber and a packaging material on the carrier board; the chip is at least partially embedded in the encapsulation material, and the auxiliary fiber is at least partially embedded in the encapsulation material, The encapsulating material is cured into an encapsulation layer that secures the chip and the auxiliary fiber package; the carrier is detached from the chip or encapsulation layer or auxiliary fibers.

The chip is arranged under the support of the carrier board, and the placement position of the chip is precise. One chip or more than two chips can be set. When two or more chips are set, the relative positions between the two chips can also be accurately set. The chip is at least partially embedded in the package material (including the chip is completely embedded in the package material, the chip portion is embedded in the package material, and the other portion is exposed to the package material, the chip is completely embedded in the package material and one surface of the chip is from the package layer The surface is bare. When the encapsulation material is cured, the position of the chip relative to the encapsulation layer is fixed. If more than two chips are provided, the relative position between the two chips is fixed by the encapsulation layer. The auxiliary fiber is at least partially embedded in the encapsulating material (including the auxiliary fiber is completely embedded in the encapsulating material, the auxiliary fiber portion is embedded in the encapsulating material, and the other portion is exposed to the encapsulating material, and the auxiliary fiber is completely embedded in the encapsulating material and one of the chips The surface is exposed from the surface of the encapsulation layer. When the encapsulation material is cured, a force interaction force is generated between the auxiliary fiber and the encapsulation layer, the auxiliary fiber relieves the stress caused by the thermal imbalance of the encapsulation layer, and the auxiliary layer can pull or push the package. Material to avoid deformation of the thermal imbalance of the packaging material. In this way, the encapsulation layer realizes chip encapsulation, and the auxiliary fiber avoids the overall bending of the encapsulation material and the chip composition during the process of curing the encapsulation material into the encapsulation layer.

The auxiliary fibers may be distributed at any position of the encapsulating layer. Preferably, two or more auxiliary materials may be provided. The auxiliary fiber is interlaced or intertwined in the encapsulating layer. When the encapsulating layer has a tendency to deform, the auxiliary fiber and the encapsulating layer interact with each other to stress balance the encapsulating material, and the auxiliary fiber assists the supporting encapsulating layer. The shape avoids the deformation caused by the curing stress of the encapsulating material.

12. The auxiliary fibers constitute an auxiliary net, and the auxiliary net functions are similar to those described in the above 2.

13. The chip and the auxiliary network both abut the carrier board. The effect is similar to that described in the above 3.

14. The one side of the encapsulating layer facing the carrier board is a first surface, and the side opposite to the first surface is a second surface, and the chip and the auxiliary fiber are disposed adjacent to the first surface; on the one hand, the first surface is closer to the carrier board, which is more advantageous Limiting the deformation of the encapsulation layer near the chip; on the other hand, since the thermal expansion coefficient of the chip is different from the thermal expansion coefficient of the encapsulation material, usually the thermal expansion coefficient of the chip is smaller than the thermal expansion coefficient of the encapsulation material, so that the thermal imbalance of the chip portion is more obvious. The chip and the auxiliary fiber are simultaneously disposed at a position close to the first surface, and the auxiliary fiber limits the deformation of the first surface, thereby ensuring the position of the chip.

Alternatively, a chip is disposed adjacent to the first surface, and an auxiliary fiber is disposed adjacent to the second surface. Since the coefficient of thermal expansion of the chip is different from the coefficient of thermal expansion of the package material, usually the coefficient of thermal expansion of the chip is smaller than the coefficient of thermal expansion of the package material, so the first surface near the chip is more thermally uneven, but the package layer is usually sheet-like, The deformation of the first surface is limited by providing an auxiliary fiber near the second surface to limit deformation of the second surface.

15. The chip is adjacent to the first surface, the auxiliary fiber is adjacent to the first surface, and the thermal expansion coefficient of the auxiliary fiber is greater than the thermal expansion coefficient of the encapsulation layer. The auxiliary fiber and the chip are disposed close to the first surface at the same time, the thermal expansion coefficient of the chip is smaller than the thermal expansion coefficient of the packaging material, the thermal expansion coefficient of the auxiliary fiber is larger than the thermal expansion coefficient of the encapsulation layer, the thermal stress of the chip and the thermal stress of the auxiliary fiber when the temperature changes. The mutual offset, the deformation of the auxiliary fiber and the deformation of the encapsulation layer cancel out, thereby avoiding deformation of the encapsulation layer. In particular, the first surface is the side of the encapsulation layer facing the carrier plate, and the carrier plate provides flat support, auxiliary fiber and chip. Simultaneously located near the first surface, the deformation of the first surface can be further avoided.

16. The chip is close to the first surface, the thermal expansion coefficient of the chip is smaller than the thermal expansion coefficient of the packaging material; the auxiliary mesh is close to the second surface, the thermal expansion coefficient of the auxiliary fiber is smaller than the thermal expansion coefficient of the encapsulation layer, and the stress of the chip and the stress of the auxiliary fiber are on the encapsulation layer. They are symmetric or approximately symmetrical, cancel each other out, and the deformation of the auxiliary fiber and the deformation of the encapsulation layer cancel out to avoid deformation of the encapsulation layer.

17. The thermal expansion coefficient of the encapsulating layer, the thermal expansion coefficient of the chip, and the thermal expansion coefficient of the auxiliary fiber make the overall thermal stress of the chip, the auxiliary fiber and the encapsulating material balanced during the process of curing the encapsulating material. Selecting the thermal expansion coefficient of the chip, the auxiliary fiber and the encapsulating material and the set position can offset the integral shape variables of the encapsulation layer, the chip and the auxiliary fiber, and balance the thermal stress to avoid deformation.

18. The auxiliary fiber is metal, ceramic, or plastic.

19. The packaging material is a compression molding material.

20. The Young's modulus of the auxiliary fiber is greater than the Young's modulus of the encapsulating layer. The auxiliary fiber itself has strong bending resistance and can resist deformation of the encapsulation layer. In particular, two or more auxiliary fibers can be disposed, and the auxiliary fibers are vertically or horizontally interlaced or intertwined in the encapsulation layer, and the auxiliary fibers form a pulling relationship with each other. The structure is stable and is more conducive to preventing deformation caused by the curing stress of the encapsulating material. For example, a metal material can be selected to make an auxiliary fiber.

DRAWINGS

Figure 1 is a schematic view 1 of a conventional manufacturing process;

Figure 2 is a cross-sectional view taken along line A-A of Figure 1;

Figure 3 is a schematic view 2 of a conventional manufacturing process;

4 is a top plan view of a chip fanout method according to an embodiment of the present invention;

Figure 5 is a cross-sectional view taken along line B-B of Figure 4;

6 is a first schematic diagram of a chip fanout method according to an embodiment of the present invention;

FIG. 7 is a second schematic diagram of a chip fanout method according to an embodiment of the present invention; FIG.

8 is a schematic diagram 1 of a chip fanout circuit according to an embodiment of the present invention;

FIG. 9 is a second schematic diagram of a chip fanout circuit according to an embodiment of the present invention; FIG.

10 is a schematic diagram 3 of a chip fanout circuit according to an embodiment of the present invention;

11 is a schematic diagram 4 of a chip fanout circuit according to an embodiment of the present invention;

12 is a first schematic diagram of a chip fanout circuit according to a second embodiment of the present invention;

Figure 13 is a cross-sectional view taken along line C-C of Figure 12;

14 is a second schematic diagram of a chip fanout circuit according to an embodiment of the present invention;

15 is a third schematic diagram of a chip fanout circuit according to an embodiment of the present invention;

16 is a schematic diagram 4 of a chip-out circuit of a second embodiment of the present invention;

17 is a schematic diagram 5 of a chip fanout circuit according to an embodiment of the present invention;

Figure 18 is a cross-sectional view taken along line D-D of Figure 17;

19 is a first schematic diagram of a three-chip fan-out circuit according to an embodiment of the present invention;

Figure 20 is a cross-sectional view taken along line E-E of Figure 19;

21 is a schematic diagram 2 of a three-chip fan-out circuit according to an embodiment of the present invention;

22 is a schematic diagram 3 of a three-chip fan-out circuit according to an embodiment of the present invention;

FIG. 23 is a schematic diagram 4 of a three-chip fan-out circuit according to an embodiment of the present invention.

Description of the reference signs:

100, encapsulating material, 101, encapsulating particles, 110, encapsulating layer, 200, chip, 300, auxiliary net, 310, auxiliary fiber, 320, auxiliary particles, 410, carrier plate, 420, medium layer.

detailed description

The present invention will be further described in detail below, but embodiments of the invention are not limited thereto.

Embodiment 1

The package layer 110 is disposed on the chip 200 to encapsulate the chip 200. If the method of the embodiment is not employed, the package layer 110 is set to a regular rectangular parallelepiped during the temperature-cooling curing process, as shown in FIG. However, since the thermal expansion coefficient of the chip 200 is generally inconsistent with the thermal expansion coefficient of the encapsulation layer 110, the shrinkage ratio between the chip 200 and the encapsulation layer 110 is inconsistent, and the thermal stress is not balanced. The stress direction of the encapsulation layer 110 is as shown by F2 in FIG. 3, F2. The cured encapsulation layer 110 is bent as shown in FIG.

As shown in FIG. 4 and FIG. 5, in this embodiment, a medium layer 420 is disposed on the carrier 410, a chip 200 is disposed on the medium layer 420, and an auxiliary net 300 is disposed on the medium layer 420, and the auxiliary net 300 is provided with a window. The chip 200 is at least partially protruded into the window, and the chip 200 and the auxiliary net 300 are abutted on the carrier 410 through the medium layer 420. The chip 200 is disposed under the support of the carrier 410. The chip 200 is placed accurately, and a chip 200 can be disposed. Two or more chips 200 are provided, and two or more are provided in this embodiment. The relative position between the two chips 200 and the chip 200 can also be accurately set. As shown in FIG. 6, the encapsulation material 100 is disposed on the carrier 410. The chip 200 is completely embedded in the encapsulation material 100 and one surface of the chip 200 is exposed from the surface of the encapsulation layer 110 (but is not limited to this embodiment, and may be The chip 200 is at least partially embedded in the encapsulation material 100. The auxiliary net 300 is completely embedded in the encapsulation material 100 and one surface of the chip 200 is exposed from the surface of the encapsulation layer 110 (but not limited to this embodiment, and may also be an auxiliary network). 300 is at least partially embedded in the encapsulating material 100). As shown in FIG. 7, the encapsulation material 100 is cured into an encapsulation layer 110, and the encapsulation layer 110 encapsulates the chip 200 and the auxiliary net 300, and the relative position between the two chips 200 is fixed by the encapsulation layer 110; The board 410 is detached from the chip 200 or the encapsulation layer 110 or the auxiliary net 300. Wherein, when the encapsulating material 100 is cured, the position of the chip 200 relative to the encapsulating layer 110 is fixed, and when the encapsulating material 100 has a tendency to deform during curing of the encapsulating material 100, a force is generated between the auxiliary net 300 and the encapsulating layer 110. The interaction force, the auxiliary net 300 mitigates the stress caused by the thermal imbalance of the encapsulation layer 110, and the auxiliary layer can pull or push the encapsulation material 100 to avoid deformation of the thermal imbalance of the encapsulation material 100. As such, the encapsulation layer 110 implements the chip 200 package, and the auxiliary net 300 avoids the overall bending of the encapsulation material 100 and the chip 200 during the process of curing the encapsulation material 100 into the encapsulation layer 110. Preferably, when the encapsulating material 100 is granular or liquid or flowable before curing, the encapsulating material 100 can enter the auxiliary net 300. During the process of curing the encapsulating material 100, when the encapsulating material 100 has a tendency to deform, the auxiliary net 300 is added. The interaction force between the encapsulating materials 100 enables the auxiliary net 300 to better alleviate and equalize the curing stress of the encapsulating material 100, and avoid bending or deformation of the encapsulating layer 110.

The auxiliary net 300 prevents the entire structure of the encapsulating material 100 and the chip 200 from being bent during the curing of the encapsulating material 100 into the encapsulating layer 110. As shown in FIGS. 6 to 9, the one side of the encapsulating layer 110 facing the carrier plate 410 is the first surface. The side opposite to the first surface is a second surface; the chip 200 and the auxiliary net 300 are disposed adjacent to the first surface; the thermal expansion coefficient of the auxiliary net 300 is greater than the thermal expansion coefficient of the encapsulation layer 110. As shown in FIG. 9, when the encapsulating material 100 is cooled and cured, since the thermal expansion coefficient of the chip 200 is smaller than that of the encapsulating material 100, the second surface shrinkage of the encapsulating layer 110 is greater than the shrinkage of the first surface, and the thermal stress causes the encapsulating layer 110 to have a layer as shown in FIG. The direction of the direction shown by F2 is curved, and the coefficient of thermal expansion of the auxiliary net 300 is greater than the coefficient of thermal expansion of the encapsulating material 100, and the shrinkage of the auxiliary net 300 is greater than that of the encapsulating layer 110 when the temperature is solidified. Shrinking, the auxiliary net 300 is equivalent to pulling the first surface of the encapsulation layer 110 in the direction of F1 in FIG. 9, thereby preventing the encapsulation layer 110 from being bent in the direction of F2, and the auxiliary net 300 is abutted against the carrier 410, and the carrier 410 is The auxiliary net 300 provides support so that the auxiliary net 300 itself is not deformed. In addition, by selecting the thermal expansion coefficient and cross-sectional area of the encapsulating layer 110, the thermal expansion coefficient and the cross-sectional area of the auxiliary net 300, the encapsulating layer 110 can be cured without being deformed and solidified. It is consistent with the preset shape.

The auxiliary net 300 is made of metal, ceramic, or plastic, and the encapsulating material 100 is a molded material.

After the encapsulation layer 110 is cured, a connection is made on the first surface of the encapsulation layer 110, and the connection is electrically connected to the chip 200. The chip 200 and the chip 200 may be directly electrically connected to each other through a connection; and then in the encapsulation layer 110. The first surface is provided with an additional encapsulation layer 110, and the additional encapsulation layer 110 and the encapsulation layer 110 fix the chip 200, the wiring clip in the middle, and provide protection. The chip 200 is formed by the method of the embodiment. Since the chip 200 is disposed on the carrier 410, the chip 200 is positioned accurately. After the package is fabricated, the connection is made to electrically connect the connection and the chip 200. At this time, the chip 200 is electrically connected. The package layer 110 has been fixedly positioned, and when the connection is made, the pattern of the connection line is designed according to the measured specific position of the chip 200, and the connection is made, even if the line width and spacing of the connection are designed to be small, The connection is precisely connected to the chip 200. As described above, a line having a line width of less than 10 μm and a pitch of less than 10 μm can be fabricated (the conventional connection is larger than 50 μm and difficult to be fine), thereby increasing the density of the connection and increasing the density. The connection channel of the chip 200 increases the data transmission data of the chip 200. On the other hand, the auxiliary network 300 is provided to limit the deformation of the encapsulation layer 110, and the encapsulation layer 110 can be made thin. The whole of the encapsulation layer 110, the chip 200, and the auxiliary net 300 can be flexible and bendable, but can be broken. Made into a wearable device.

Not limited to this embodiment, as shown in FIG. 10, the chip 200 may be disposed adjacent to the first surface, and the auxiliary net 300 may be disposed adjacent to the second surface. Since the thermal expansion coefficient of the chip 200 is different from the thermal expansion coefficient of the encapsulation material 100, generally the thermal expansion coefficient of the chip 200 is smaller than the thermal expansion coefficient of the encapsulation material 100, so the first surface near the chip 200 is more thermally uneven, but the encapsulation layer 110 is usually It is sheet-like, and the deformation of the first surface can be restricted by providing the auxiliary net 300 near the second surface to restrict the deformation of the second surface. For example, the thermal expansion coefficient of the auxiliary net 300 may be selected to be smaller than the thermal expansion coefficient of the encapsulation layer 110, and the auxiliary net 300 is close to the second surface. The stress of the chip 200 and the stress of the auxiliary net 300 are symmetric or approximately symmetrical on the encapsulation layer 110, avoiding encapsulation. Layer 110 is deformed. Thermal expansion system of auxiliary net 300 The number is smaller than the thermal expansion coefficient of the encapsulation layer 110. During the process of cooling and curing the encapsulating particles 101, the shrinkage amount of the auxiliary net 300 is smaller than the shrinkage amount of the encapsulation layer 110, and the auxiliary net 300 resists shrinkage of the encapsulation layer 110 on the second surface, so that the package is made. Layer 110 is not bent. However, it is not limited thereto, and as shown in FIG. 11, the auxiliary net 300 may be disposed at a position close to the middle between the first surface and the second surface.

In this embodiment, the thermal expansion coefficient of the encapsulation layer 110 is alleviated by selecting the thermal expansion coefficient of the auxiliary net 300, and the thermal expansion coefficient of the encapsulation layer 110, the thermal expansion coefficient of the chip 200, the installed position, the thermal expansion coefficient of the auxiliary net 300, and The location of the mounting is such that during assembly of the encapsulating material 100, the overall thermal stresses of the chip 200, the auxiliary mesh 300, and the encapsulating material 100 are equalized. However, the present invention is not limited to this embodiment, and the Young's modulus of the auxiliary net 300 may be selected to be larger than the Young's modulus of the encapsulation layer 110. The auxiliary net 300 itself has strong bending resistance, and is sufficient to counter the thermal stress of the encapsulation layer 110 to ensure the encapsulation layer. The deformation does not occur at 110. Preferably, the auxiliary mesh 300 can be made of metal, ceramic, or plastic.

The carrier plate 410 can be selected from a glass material or a metal material. The glass and metal have a good flatness as the carrier 410, and the thermal deformation is small, which is advantageous in maintaining a reliable connection between the base circuit layer and the chip 200. The metal material is preferably made of stainless steel to provide a high degree of flatness on the stainless steel surface. The medium layer 420 may be a photosensitive adhesive medium, and the carrier plate 410 is made of a light-transmissive glass material. The light-transmissive glass is used to form the carrier plate 410. The light-transmitting property of the glass material can be adjusted from one side of the carrier plate 410. The light is applied to the photosensitive paste medium to disengage the carrier 410 from the chip 200 and the encapsulation layer 110. Alternatively, the dielectric layer 420 may be a heat sensitive adhesive medium, and the carrier 410 may be made of a metal material, from the side of the carrier 410. The temperature of the thermal paste medium is adjusted to disengage the carrier 410 from the chip 200 and the encapsulation layer 110. The metal has good thermal conductivity, is advantageous for using a heat-sensitive bonding material, and has high metal strength and is not easily worn. For example, the carrier plate 410 can be made of stainless steel to prevent rust. When the medium layer 420 is a photosensitive adhesive medium or a thermal paste medium, when the chip 200 is placed on the medium layer 420, the medium layer 420 adheres and fixes the chip 200 to the carrier 410, which can reduce the relative displacement of the chip 200 when the package material 100 is cured. dislocation. However, the present invention is not limited to the embodiment, and the medium layer 420 may be selected to fix or not fix the chip 200, the medium layer 420 is provided with the card position of the chip 200, the chip 200 is stuck on the card position of the medium layer 420, and the chip 200 is limited by the card position. mobile. It is also possible to select that the medium layer 420 itself is a pasting material, and the medium layer 420 pastes the chip 200 On the carrier plate 410, the displacement during the curing of the encapsulating material 100 is limited.

Embodiment 2

The difference between the second embodiment and the first embodiment is:

As shown in Figures 12 and 13, the auxiliary fibers 310 are arranged to form an auxiliary net 300. The auxiliary net 300 is provided with a window, and the chip 200 at least partially protrudes into the window. When the chip 200 and the auxiliary net 300 are disposed on the carrier 410, the chip 200 and the auxiliary net 300 are both abutted against the carrier 410, and then the encapsulation material 100 is disposed to cure the encapsulation material 100 into the encapsulation layer 110. 200 and auxiliary fiber 310 are fixed. As shown in FIG. 13, the auxiliary net 300 composed of the auxiliary fibers 310 is disposed near the first surface of the encapsulating layer 110, the thermal expansion coefficient of the auxiliary fibers 310 is larger than the thermal expansion coefficient of the encapsulating layer 110, and the shrinkage of the auxiliary fibers 310 is greater when the temperature is solidified. Upon shrinkage of the encapsulation layer 110, the auxiliary fibers 310 pull the first surface of the encapsulation layer 110 to prevent the encapsulation layer 110 from curling toward the second surface. Alternatively, as shown in FIG. 14, the auxiliary net 300 composed of the auxiliary fibers 310 is disposed at a position close to the second surface, and the thermal expansion coefficient of the auxiliary fibers 310 is smaller than the thermal expansion coefficient of the encapsulating layer 110. Since the thermal expansion coefficient of the chip 200 is different from the thermal expansion coefficient of the encapsulation material 100, generally the thermal expansion coefficient of the chip 200 is smaller than the thermal expansion coefficient of the encapsulation material 100, so the first surface near the chip 200 is more thermally uneven, but the encapsulation layer 110 is usually It is sheet-like, and the deformation of the first surface can be restricted by providing the auxiliary fiber 310 near the second surface to restrict the deformation of the second surface. For example, the coefficient of thermal expansion of the auxiliary fiber 310 may be selected to be smaller than the coefficient of thermal expansion of the encapsulation layer 110, the auxiliary fiber 310 is adjacent to the second surface, and the stress of the chip 200 and the stress of the auxiliary fiber 310 are symmetric or approximately symmetrical on the encapsulation layer 110, avoiding encapsulation. Layer 110 is deformed. The coefficient of thermal expansion of the auxiliary fiber 310 is smaller than the coefficient of thermal expansion of the encapsulating layer 110. In the process of cooling and curing the encapsulating particles 101, the shrinkage amount of the auxiliary fiber 310 is smaller than the shrinkage amount of the encapsulating layer 110, and the auxiliary fiber 310 resists the second surface of the encapsulating layer 110. The shrinkage causes the encapsulation layer 110 to not bend. Not limited to this, as shown in FIG. 15, the auxiliary net 300 composed of the auxiliary fibers 310 may be disposed at a position close to the middle between the first surface and the second surface. The encapsulation layer 110 is not deformed by selecting the thermal expansion coefficient and position of the auxiliary fiber 310, the thermal expansion coefficient and position of the chip 200, and the thermal expansion coefficient of the encapsulation layer 110.

Without limitation, the auxiliary fiber 310 may be disposed at any position of the encapsulation layer 110, for example, FIG. 18 is shown. The auxiliary fibers 310 are criss-crossed and entangled to form a stable frame structure, and the shape of the encapsulation layer 110 is stabilized to avoid deformation of the encapsulation layer 110. The Young's modulus of the auxiliary fibers 310 may be selected to be larger than the Young's modulus of the encapsulation layer 110. The fibers 310 are criss-crossed and entangled to form a stable frame structure, and the auxiliary fiber 310 itself has a strong bending resistance. Even if the thermal stress of the encapsulating layer 110 is unbalanced, the auxiliary fiber 310 can support the encapsulating layer 110 so as not to be deformed.

Preferably, the auxiliary fiber 310 is metal, ceramic, or plastic, and the encapsulating material 100 is a molded material.

Embodiment 3

The difference between the third embodiment and the first embodiment is:

As shown in Figures 19 and 20, the auxiliary particles 320 are arranged to form an auxiliary net 300. The auxiliary net 300 is provided with a window, and the chip 200 at least partially protrudes into the window. When the chip 200 and the auxiliary net 300 are disposed on the carrier 410, the chip 200 and the auxiliary net 300 are both abutted against the carrier 410, and then the package particles 101 are disposed to cure the package particles 101 into the package layer 110, and the package layer 110 will be the chip. 200 and the auxiliary particles 320 and the chip 200 are fixed. As shown in FIG. 20, the auxiliary net 300 composed of the auxiliary particles 320 is disposed near the first surface of the encapsulating layer 110, the thermal expansion coefficient of the auxiliary particles 320 is greater than the thermal expansion coefficient of the encapsulating layer 110, and the shrinkage of the auxiliary particles 320 is greater when the temperature is solidified. Shrinkage of the encapsulation layer 110 counteracts shrinkage of the encapsulation layer 110, thereby preventing the encapsulation layer 110 from curling toward the second surface. Alternatively, as shown in FIG. 21, the auxiliary net 300 composed of the auxiliary particles 320 is disposed at a position close to the second surface, and the thermal expansion coefficient of the auxiliary particles 320 is smaller than the thermal expansion coefficient of the encapsulating layer 110. Since the thermal expansion coefficient of the chip 200 is different from the thermal expansion coefficient of the encapsulation material 100, generally the thermal expansion coefficient of the chip 200 is smaller than the thermal expansion coefficient of the encapsulation material 100, so the first surface near the chip 200 is more thermally uneven, but the encapsulation layer 110 is usually It is sheet-like, and the deformation of the first surface can be restricted by providing the auxiliary particles 320 near the second surface to restrict the deformation of the second surface. For example, the thermal expansion coefficient of the auxiliary particles 320 may be selected to be smaller than the thermal expansion coefficient of the encapsulation layer 110, and the auxiliary particles 320 are close to the second surface. In the process of cooling and curing the encapsulating particles 101, the shrinkage amount of the auxiliary particles 320 is smaller than the shrinkage amount of the encapsulation layer 110. The auxiliary particles 320 resist shrinkage of the encapsulation layer 110 at the second surface such that the encapsulation layer 110 does not bend. Not limited to this, you can also As shown in FIG. 22, the auxiliary net 300 composed of the auxiliary particles 320 is disposed at a position intermediate the first surface and the second surface; or, as shown in FIG. 23, the auxiliary particles 320 may be distributed at any position of the encapsulating layer 110 by selecting The thermal expansion coefficient and position of the auxiliary particles 320, the thermal expansion coefficient and position of the chip 200, and the thermal expansion coefficient of the encapsulation layer 110 prevent the encapsulation layer 110 from being deformed.

Preferably, the auxiliary particles 320 are metal, ceramic, or plastic, and the encapsulating material 100 is a molded material.

The excellent effects of this embodiment include:

1. The chip 200 is disposed on the carrier 410, and the encapsulation material 100 is disposed on the carrier 410. The encapsulation material 100 includes the encapsulating particles 101 and the buffer particles. The thermal expansion coefficient of the buffer particles is greater than or less than the thermal expansion coefficient of the encapsulating particles 101; Partially embedded in the encapsulation material 100, the encapsulation particles 101 are cured into an encapsulation layer 110, and the encapsulation layer 110 encapsulates the chip 200 and the auxiliary net 300; the carrier plate 410 is detached from the chip 200 or the encapsulation layer 110.

The chip 200 is disposed under the support of the carrier board 410. The chip 200 is placed at a precise position, and one chip 200 or two or more chips 200 may be disposed. When two or more chips 200 are disposed, the relative relationship between the two chips 200 is The position can also be set precisely. The chip 200 is at least partially embedded in the encapsulation material 100 (including the chip 200 is completely embedded in the encapsulation material 100, the chip 200 is partially embedded in the encapsulation material 100, and the other portion is exposed to the encapsulation material 100. The chip 200 is completely embedded in the encapsulation material 100. And one surface of the chip 200 is exposed from the surface of the package layer 110. When the package particles 101 are cured, the position of the chip 200 relative to the package layer 110 is fixed. If more than two chips 200 are provided, then two chips The relative position between 200 is fixed by the encapsulation layer 110. The buffer particles are at least partially embedded in the encapsulation material 100 (including the buffer particles are completely embedded in the encapsulation material 100, the buffer particles are partially embedded in the encapsulation material 100, and the other portion is exposed to the encapsulation material 100, and the buffer particles are all embedded in the encapsulation material 100. And one surface of the chip 200 is exposed from the surface of the encapsulation layer 110. When the encapsulating particles 101 are cured, a force interaction force occurs between the buffer particles and the encapsulating particles 101, and the buffering particles alleviate the stress caused by the thermal imbalance of the encapsulating layer 110. To avoid deformation of the thermal imbalance of the encapsulating material 100. The coefficient of thermal expansion of the buffer particles is greater than or less than the coefficient of thermal expansion of the encapsulated particles 101, and the coefficient of thermal expansion of the appropriate buffer particles is selected according to the coefficient of thermal expansion of the encapsulated particles 101 and The position is set such that the stress of the buffering particles 101 during the curing process, the deformation amount of the buffer particles, and the deformation amount of the encapsulating particles 101 are canceled each other, and the entire composition of the encapsulating material 100 and the chip 200 is prevented from being bent.

2. At least two buffer particles are provided, the buffer particles forming a secondary mesh 300 with a window, the chip 200 extending at least partially into the window. The role of the auxiliary net 300 is similar to that described in 2.

3. The one side of the encapsulation layer 110 facing the carrier board 410 is a first surface, and the side opposite to the first surface is a second surface. The chip 200 is disposed adjacent to the first surface, and buffer particles are disposed adjacent to the first surface, and the thermal expansion coefficient of the buffer particles is greater than The thermal expansion coefficient of the encapsulation layer 110; generally, the thermal expansion coefficient of the chip 200 is smaller than the thermal expansion coefficient of the encapsulating particles 101, and the thermal stress of the chip 200 and the thermal stress of the auxiliary fibers cancel each other, thereby preventing the encapsulation layer 110 from being deformed.

Alternatively, the chip 200 is disposed adjacent to the first surface, and the auxiliary particles 320 are disposed adjacent to the second surface, and the coefficient of thermal expansion of the buffer particles is smaller than the coefficient of thermal expansion of the encapsulation layer 110. Generally, the thermal expansion coefficient of the chip 200 is smaller than the thermal expansion coefficient of the package particles 101, and the stress of the chip 200 and the stress of the buffer particles are symmetric or approximately symmetrical on the encapsulation layer 110, and can cancel each other, thereby avoiding deformation of the encapsulation layer 110.

4. The thermal expansion coefficient of the encapsulation layer 110, the thermal expansion coefficient of the chip 200, and the thermal expansion coefficient of the buffer particles make the overall thermal stress of the chip 200, the auxiliary net 300, and the encapsulating material 100 equalized during the curing of the encapsulating material 100. By selecting the thermal expansion coefficient of the chip 200, the buffer particles and the encapsulating particles 101 and the set position, the integral shape variables of the encapsulation layer 110, the chip 200, and the auxiliary fibers can be offset, and the thermal stresses are balanced with each other to avoid deformation.

The technical features of the above embodiments may be arbitrarily combined. For the sake of brevity of description, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, It is considered to be the range described in this specification.

The above embodiments are merely illustrative of several embodiments of the present invention, and the description thereof is more specific and detailed, but is not to be construed as limiting the scope of the invention. It should be noted that a number of variations and modifications may be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of the invention should be determined by the appended claims.

Claims

A chip fanout method, comprising:

Providing a chip on the carrier board and setting an auxiliary net and a packaging material on the carrier board;

The chip is at least partially embedded in the encapsulation material, the auxiliary net is at least partially embedded in the encapsulation material, and the encapsulation material is cured into an encapsulation layer, and the encapsulation layer fixes the chip and the auxiliary net package;

The carrier is detached from the chip or the encapsulation layer or/and the auxiliary mesh.
The chip fan-out method according to claim 1, wherein the auxiliary net is provided with a window, and the chip at least partially protrudes into the window.
The chip fan-out method according to claim 2, wherein the chip and the auxiliary net both abut against the carrier.
The chip fan-out method according to claim 1, wherein a side of the encapsulation layer facing the carrier is a first surface, and a side opposite to the first surface is a second surface;

The chip and the auxiliary net are disposed adjacent to the first surface; or the chip is disposed adjacent to the first surface, and the auxiliary net is disposed adjacent to the second surface.
The chip fan-out method according to claim 4, wherein the chip is close to the first surface, the auxiliary net is close to the first surface, and the thermal expansion coefficient of the auxiliary net is larger than that of the encapsulation layer Thermal expansion coefficient.
The chip fan-out method according to claim 4, wherein the chip is close to the first surface, the auxiliary net is close to the second surface, and the thermal expansion coefficient of the auxiliary net is smaller than that of the encapsulation layer Thermal expansion coefficient.
The chip fan-out method according to claim 1, wherein a maximum thickness of the auxiliary net is greater than a maximum thickness of the chip.
The chip fan-out method according to claim 1, wherein the auxiliary mesh has a thickness at least less than 100 μm of the thickness of the encapsulation layer.
The chip fan-out method according to claim 1, wherein the auxiliary network accounts for 10% to 90% of the total area of the encapsulation layer minus the area occupied by the chip.
The chip fanout method according to any one of claims 1 to 9, wherein The coefficient of thermal expansion of the encapsulation layer, the coefficient of thermal expansion of the chip, and the coefficient of thermal expansion of the auxiliary web such that the overall thermal stress balance of the chip, the auxiliary net, and the encapsulating material is balanced during curing of the encapsulating material .
The chip fan-out method according to any one of claims 1 to 9, wherein the auxiliary net is metal, ceramic, or plastic.
The chip fan-out method according to any one of claims 1 to 9, wherein the encapsulating material is a press molding material.
The chip fan-out method according to any one of claims 1 to 9, wherein the Young's modulus of the auxiliary net is larger than the Young's modulus of the encapsulating layer.
A chip fanout circuit, comprising:

a chip, an encapsulation layer formed by encapsulating the material, and an auxiliary net;

Wherein the chip is at least partially embedded in the encapsulation layer, the auxiliary net is at least partially embedded in the encapsulation layer, and the encapsulation layer fixes the chip and the auxiliary net package, the auxiliary The mesh is used to reduce the bending or deformation of the encapsulating material that is cured into the encapsulating layer.
The chip fanout circuit of claim 14 wherein said auxiliary net is provided with a window, said chip extending at least partially into said window.
The chip fanout circuit according to claim 14, wherein the encapsulation layer has opposing first and second surfaces;

The chip and the auxiliary net are adjacent to the first surface; or the chip is adjacent to the first surface, and the auxiliary net is adjacent to the second surface.
The chip fan-out circuit according to claim 16, wherein the chip is close to the first surface, the auxiliary net is close to the first surface, and the thermal expansion coefficient of the auxiliary net is larger than that of the encapsulation layer. Thermal expansion coefficient.
The chip fanout circuit according to claim 16, wherein said chip and said auxiliary net are both flush with said first surface, and said chip, said auxiliary net, and said first surface The plane of the formation is flat.
A chip fanout circuit according to claim 16 wherein said chip is close The first surface, the auxiliary net is adjacent to the second surface, and the auxiliary network has a thermal expansion coefficient smaller than a thermal expansion coefficient of the encapsulation layer.
The chip fan-out circuit according to any one of claims 14 to 19, wherein a coefficient of thermal expansion of the encapsulation layer, a coefficient of thermal expansion of the chip, and a coefficient of thermal expansion of the auxiliary net are such that the encapsulating material is cured. The overall thermal stress of the chip, the auxiliary mesh, and the encapsulating material is balanced during the process.
The chip fan-out circuit according to any one of claims 14 to 19, wherein the auxiliary net is metal, ceramic, or plastic.
The chip fan-out circuit according to any one of claims 14 to 19, wherein the encapsulating material is a press molding material.
The chip fan-out circuit according to any one of claims 14 to 19, wherein the Young's modulus of the auxiliary net is larger than the Young's modulus of the encapsulating layer.
A chip fanout method, comprising:

Providing a chip on the carrier board and arranging auxiliary fibers and packaging materials on the carrier board;

The chip is at least partially embedded in the encapsulating material, the auxiliary fiber is at least partially embedded in the encapsulating material, and the encapsulating material is cured into an encapsulating layer, and the encapsulating layer fixes the chip and the auxiliary fiber package;

The carrier is detached from the chip or the encapsulation layer or the auxiliary fibers.
The chip fan-out method according to claim 24, wherein the auxiliary fibers constitute an auxiliary net, the auxiliary net is provided with a window, and the chip at least partially protrudes into the window.
The chip fan-out method according to claim 25, wherein said chip and said auxiliary net both abut against said carrier.
[Correct according to Rule 91 07.04.2017]

The chip fan-out method according to claim 24, wherein one side of the encapsulation layer facing the carrier is a first surface, and a side opposite to the first surface is a second surface;

The chip and the auxiliary fiber are disposed adjacent to the first surface; or the chip is disposed adjacent to the first surface, and the auxiliary fiber is disposed adjacent to the second surface.
The chip fanout method according to claim 27, wherein said chip is close to The first surface, the auxiliary fiber is adjacent to the first surface, and the auxiliary fiber has a thermal expansion coefficient greater than a thermal expansion coefficient of the encapsulation layer.
The chip fan-out method according to claim 27, wherein the chip is close to the first surface, the auxiliary fiber is close to the second surface, and the auxiliary fiber has a thermal expansion coefficient smaller than that of the encapsulation layer. Thermal expansion coefficient.
The chip fan-out method according to any one of claims 24 to 29, wherein a thermal expansion coefficient of the encapsulation layer, a thermal expansion coefficient of the chip, and a thermal expansion coefficient of the auxiliary fiber cause curing of the encapsulating material The overall thermal stress of the chip, the auxiliary mesh, and the encapsulating material is balanced during the process.
The chip fan-out method according to any one of claims 24 to 29, wherein the auxiliary fiber is metal, ceramic, or plastic.
The chip fan-out method according to any one of claims 24 to 29, wherein the encapsulating material is a press molding material.
The chip fan-out method according to any one of claims 24 to 29, wherein a Young's modulus of the auxiliary fiber is larger than a Young's modulus of the encapsulating layer.
A chip fanout circuit, comprising:

a chip, an encapsulation layer cured from an encapsulating material, and an auxiliary fiber;

Wherein the chip is at least partially embedded in the encapsulation layer, the auxiliary fiber is at least partially embedded in the encapsulation layer, and the encapsulation layer fixes the chip and the auxiliary fiber package, the auxiliary The fibers are used to reduce the bending or deformation of the encapsulating material that is cured into the encapsulating layer.
A chip fanout circuit according to claim 34, wherein said auxiliary fibers constitute an auxiliary net, said auxiliary net being provided with a window, said chip extending at least partially into said window.
The chip fanout circuit of claim 34, wherein the encapsulation layer has opposing first and second surfaces;

The chip and the auxiliary fiber are adjacent to the first surface; or the chip is adjacent to the first surface, and the auxiliary fiber is adjacent to the second surface.
A chip fanout circuit according to claim 36, wherein said chip is close The first surface, the auxiliary net is adjacent to the first surface, and the auxiliary network has a thermal expansion coefficient greater than a thermal expansion coefficient of the encapsulation layer.
A chip fanout circuit according to claim 36, wherein said chip and said auxiliary net are both flush with said first surface, and said chip, said auxiliary net, and said first surface The plane of the formation is flat.
The chip fan-out circuit according to claim 36, wherein the chip is adjacent to the first surface, the auxiliary net is adjacent to the second surface, and the thermal expansion coefficient of the auxiliary net is smaller than that of the encapsulation layer Thermal expansion coefficient.
The chip fan-out circuit according to any one of claims 34 to 39, wherein a coefficient of thermal expansion of the encapsulation layer, a coefficient of thermal expansion of the chip, and a coefficient of thermal expansion of the auxiliary fiber cause curing of the encapsulating material During the process, the overall thermal stress of the chip, the auxiliary fiber and the encapsulating material tends to be equalized.
A chip fan-out circuit according to any one of claims 34 to 39, wherein the auxiliary fiber is metal, ceramic, or plastic.
The chip fan-out circuit according to any one of claims 34 to 39, wherein the encapsulating material is a press molding material.
The chip fan-out circuit according to any one of claims 34 to 39, wherein the auxiliary fiber has a Young's modulus greater than a Young's modulus of the encapsulation layer.