WO2018157854A1 - Polar码编译码方法及装置 - Google Patents

Polar码编译码方法及装置 Download PDF

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Publication number
WO2018157854A1
WO2018157854A1 PCT/CN2018/077853 CN2018077853W WO2018157854A1 WO 2018157854 A1 WO2018157854 A1 WO 2018157854A1 CN 2018077853 W CN2018077853 W CN 2018077853W WO 2018157854 A1 WO2018157854 A1 WO 2018157854A1
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lpc
crc
lcrc
bits
bit
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PCT/CN2018/077853
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English (en)
French (fr)
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黄凌晨
李榕
徐晨
张公正
戴胜辰
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华为技术有限公司
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Priority to BR112019018177-6A priority Critical patent/BR112019018177A2/pt
Priority to EP18761250.2A priority patent/EP3579423A4/en
Publication of WO2018157854A1 publication Critical patent/WO2018157854A1/zh
Priority to US16/556,920 priority patent/US11095312B2/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2792—Interleaver wherein interleaving is performed jointly with another technique such as puncturing, multiplexing or routing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques

Definitions

  • Embodiments of the present invention relate to the field of wireless communications, and in particular, to a Polar code encoding and decoding method and apparatus.
  • Polar code (Polar codes) proposed by Turkish professor Arikan is the first good code that theoretically proves to reach Shannon's capacity and has low coding and decoding complexity.
  • the Polar code is a linear block code whose coding matrix is G N and the encoding process is among them Is a binary line vector with a length of N (ie, the length of the mother code); G N is an N ⁇ N matrix, and Defined as the Kronecker product of log 2 N matrices F 2 . Above matrix
  • G N. (A) is a sub-matrix obtained from those rows corresponding to the index in the set A in G N.
  • G N (A C ) is obtained from the rows corresponding to the indexes in the set A C in G N . Submatrix.
  • the encoded output of the Polar code can be simplified to: Is a K ⁇ N matrix.
  • the construction process of the Polar code is a collection
  • the selection process determines the performance of the Polar code.
  • the construction process of the Polar code is generally: determining that there are N polarized channels in total according to the length N of the mother code, respectively corresponding to N rows of the coding matrix, calculating the reliability of the polarized channel, and the first K polarizations with higher reliability.
  • the index of the channel is the element of set A, and the index corresponding to the remaining (NK) polarized channels is used as the index set of fixed bits.
  • Set A determines the position of the information bits, the set The position of the fixed bit is determined.
  • the Polar code can use the serial cancellation (English: Successive Cancellation, SC) decoding algorithm to sequentially decode from the first bit.
  • the Serial Cancellation List (SCL) decoding algorithm is an improvement of the SC decoding algorithm, and multiple candidate decoding results are retained in the decoding process.
  • SCL regards the decoding process as a path search process, that is, the path is extended by using the first bit as the root node, and the path is evaluated by a metric value, which is dynamically updated according to a predetermined rule as the path is expanded. .
  • the extension decoding the next bit
  • the L candidate paths with the best path metric in the current layer are retained until the last layer is extended (the last bit is decoded).
  • the path with the best metric value among the L candidate paths is output as the decoding output.
  • the SCL decoding algorithm can obtain maximum likelihood decoding performance.
  • the CA-Polar code is a Polar code of a CRC (Cyclic Redundancy Check), which is referred to as a CA-Polar code.
  • the CRC-encoded bits are mapped into information bits by CRC encoding the information block.
  • the CA-SCL (CRC-Aided Successive Cancellation List) decoding algorithm is used for decoding, that is, the candidate path through which the CRC passes is selected as the decoding output among the L candidate paths outputted by the SCL decoding. If the correct path is deleted at the intermediate node of the CA-SCL decoding because the metric value is poor, the subsequent CRC check cannot improve the performance of the SCL decoding.
  • the embodiment of the present application provides a Polar code encoding method, an encoding device, a decoding method, and a decoding device, which can further improve the performance of the CA-Polar code.
  • a Polar coding method including:
  • the Lpc CRC bits in the interleaved coding block are located between the bits of the information block, and each of the Lpc CRC bits is located after all the bits it verifies, Where Lpc is an integer greater than 0 and less than Lcrc;
  • an encoding apparatus including:
  • An interleaving unit interleaves the CRC-encoded coding block, wherein Lpc CRC bits in the interleaved coding block are located between bits of the information block, and each of the Lpc CRC bits is located at the checksum thereof After the bit, where Lpc is an integer greater than 0 and less than Lcrc;
  • a Polar coding unit configured to map the coded block that is interleaved by the interleaving unit to information bits, set a freeze bit to a predetermined fixed value, and perform Polar coding on the information bit and the frozen bit to obtain a Polar coded codeword;
  • the position of the information bit is a position corresponding to the B polarized channels with the most reliable reliability;
  • the position of the frozen bit is the position corresponding to the remaining NB polarized channels, and N is the length of the Polar code mother code.
  • an encoding apparatus including:
  • an encoding apparatus including:
  • At least one input terminal for receiving information blocks
  • the coding block is interleaved, and the Lpc CRC bits in the interleaved coding block are located between the bits of the information block, and each of the Lpc CRC bits is located after all the bits it checks, where Lpc is greater than 0 An integer smaller than Lcrc; mapping the interleaved coding block to information bits, setting the freeze bit to an agreed fixed value, and performing Polar coding on the information bit and the frozen bit to obtain a Polar coded codeword; wherein the information bit The location of the B-polarized channel with the most reliable reliability; the location of the frozen bit is the position corresponding to the remaining NB polarized channels, and N is the length of the Polar code mother code;
  • a Polar decoding method including:
  • the information bits including K bits of the information block and Lcrc CRC bits, wherein Lpc CRC bits are located between bits of the information block, and Lpc CRC bits Each CRC bit is located after all bits it verifies, where Lpc is an integer greater than 0 and less than Lcrc;
  • the serial offset list SCL decoding algorithm is used to decode the decoded bits in order, and the L candidate paths with the best metric value are output, wherein the value of the frozen bits in each candidate path is set as an agreement in the decoding process.
  • a fixed value the value of each of the Lpc CRC bits is determined according to the value of the bit of the information block that is checked before the CRC bit, and the remaining (Lcrc-Lpc) CRC bits are performed according to the information bits.
  • T candidate paths with optimal metric values among L candidate paths where T is an integer greater than 0 and less than or equal to L;
  • a decoding apparatus including:
  • an acquiring unit configured to obtain information bits and freeze bits in the bits to be decoded, where the information bits include K bits of the information block and Lcrc CRC bits, where Lpc CRC bits are located between bits of the information block, and Lpc Each of the CRC bits is located after all of the bits it verifies, where Lpc is an integer greater than 0 and less than Lcrc;
  • the decoding unit uses the serial cancellation list SCL decoding algorithm to decode the decoded bits in order, and outputs L candidate paths with the best metric value, wherein the frozen bits in each candidate path in the decoding process
  • the value is set to a predetermined fixed value, and the value of each of the Lpc CRC bits is determined according to the value of the bit of the information block it checks before the CRC bit, and the remaining (Lcrc-Lpc) CRC bits Decoding according to information bits;
  • the interleaving unit deinterleaves the T candidate paths with the best metric values among the L candidate paths, where T is an integer greater than 0 and less than or equal to L;
  • a CRC check unit configured to perform CRC check on the T candidate paths, and use the information block in the candidate path that is CRC checked and the path metric is optimal as a decoding output.
  • a decoding apparatus including:
  • a processor configured to execute the program stored by the memory, when the program is executed, the processor is configured to acquire a position of an information bit and a frozen bit in a bit to be decoded, where the information bit includes K pieces of the information block Bits and Lcrc CRC bits, wherein Lpc CRC bits are located between bits of the information block, and each of the Lpc CRC bits is located after all bits it verifies, where Lpc is greater than 0 less than Lcrc The integer is used; the SCL decoding algorithm is used to decode the decoded bits in order, and the L candidate paths with the best metric value are output, wherein the value of the frozen bits in each candidate path in the decoding process Set to a fixed value of the convention, the value of each of the Lpc CRC bits is determined according to the value of the bit of the information block that is checked before the CRC bit, and the remaining (Lcrc-Lpc) CRC bits are The information bits are decoded; the T candidate paths with the best metric values
  • a decoding apparatus including:
  • At least one input terminal for receiving bit information to be decoded
  • a signal processor configured to acquire a position of an information bit and a frozen bit in the bit to be decoded, where the information bit includes K bits of the information block and Lcrc CRC bits, wherein Lpc CRC bits are located between bits of the information block, and Each of the Lpc CRC bits is located after all of the bits it verifies, where Lpc is an integer greater than 0 and less than Lcrc; the serialized cancellation list SCL decoding algorithm is used to decode the decoded bits in order, Outputting L candidate paths with optimal metric values, wherein the value of the frozen bits in each candidate path is set to a predetermined fixed value during the decoding process, and the value of each of the Lpc CRC bits is located according to the The value of the bit of the information block that is checked before the CRC bit is determined, and the remaining (Lcrc-Lpc) CRC bits are decoded according to the information bits; T candidate paths that are optimal for the metric values in the L candidate paths Deinterleaving, T is
  • At least one output terminal is used as a decoding output for the information block in the candidate path that passes the CRC check and the path metric is optimal.
  • the performing, by using the interleaving sequence ⁇ [ ⁇ 1, ⁇ 2, . . . , ⁇ n], encoding the CRC encoding
  • the block is interleaved to convert the CRC-encoded bit sequence [b1, b2, ..., bn] into b ⁇ 1, b ⁇ 2, ..., b ⁇ n; where n is an integer greater than 0 and less than or equal to B, and the value of ⁇ n indicates interleaving
  • n is an integer greater than 0 and less than or equal to B
  • the Lpc, Lcrc, T, and the false alarm probability upper limit FAR specified by the communication system satisfy the following relationship:
  • the Lcrc is 27, Lpc is 8; or Lcrc is 24, Lpc is 6; or Lcrc is 22, 23, 14 or 15, Lpc is 4; or.
  • the metric value is a path value PM.
  • the metric value of the T candidate paths is the most The information block of the superior path is output as a decoding or determined to be a decoding failure.
  • the CRC coding is: one-time CRC coding. It is only necessary to perform CRC coding once in accordance with the length of Lcrc to obtain a code block after CRC coding.
  • a ninth aspect of the present application is directed to a computer readable storage medium having instructions stored therein that, when executed on a computer, cause the computer to perform the various aspects or various possible implementations described above The encoding method or decoding method.
  • Yet another aspect of the present application provides a computer program product comprising instructions which, when executed on a computer, cause the computer to perform the encoding method or the decoding method described in the above aspects or various possible implementations.
  • Yet another aspect of the present application provides a computer program that, when executed on a computer, causes the computer to perform the encoding method or the decoding method described in the above aspects or various possible implementations.
  • the CRC-encoded coding block is interleaved, so that part of the CRC bits in the interleaved coding block are distributed between the bits of the information block, and each CRC bit in the partial CRC bit It is located after all the bits it has checked, that is to say that the partial CRC bits only check the bits of the information block located before it.
  • the partial CRC bit is decoded as a parity bit. If the previous information bit is decoded incorrectly, the value of the CRC bit calculated according to the previous information bit is more likely to be inconsistent with the received LLR. Large, making the metric of the path worse, so that the error path is more likely to be deleted when the metric values of the candidate path are sorted, which improves the performance of CA-SCL decoding.
  • FIG. 1 is a schematic diagram of a basic flow of a wireless communication transmitting end and a receiving end;
  • 2a is a schematic diagram of path expansion and metric calculation in the case where the LLR of the current bit is greater than 0 in the embodiment of the present application;
  • 2b is a schematic diagram of path expansion and metric calculation in the case where the LLR of the current bit is less than 0 in the embodiment of the present application;
  • FIG. 3 is a schematic diagram of a path extension and PM value update of SCL decoding
  • FIG. 4 is a schematic diagram of a process of CA-Polar coding
  • Figure 5 is a schematic illustration of a CA-Polar configuration
  • FIG. 6 is a schematic diagram of an encoding process provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of an encoding apparatus provided by an implementation of the present application.
  • FIG. 8 is a schematic flowchart diagram of an encoding method provided by an implementation of the present application.
  • FIG. 9 is a schematic diagram of relationship between each special CRC bit and its previous information bits in the embodiment of the present application.
  • FIG. 10 is a schematic diagram of a CA-Polar structure provided by an embodiment of the present application.
  • FIG. 11 is a flowchart of another coding method provided by an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of still another encoding apparatus provided by the implementation of the present application.
  • FIG. 13 is a schematic structural diagram of still another encoding apparatus provided by the implementation of the present application.
  • FIG. 14 is a schematic structural diagram of a decoding apparatus provided by an implementation of the present application.
  • 15 is a schematic flowchart of a decoding method provided by an implementation of the present application.
  • 16 is a schematic diagram of a path extension and path value update of SCL decoding provided by an embodiment of the present application.
  • FIG. 18 is a schematic structural diagram of still another decoding apparatus provided by the implementation of the present application.
  • FIG. 19 is a schematic structural diagram of still another decoding apparatus provided by the implementation of the present application.
  • the technical solution of the embodiment of the present application can be applied to a 5G communication system or a future communication system, and can also be applied to other various wireless communication systems, such as a Global System of Mobile communication (GSM) system, and code division multiple access (CDMA, Code Division Multiple Access system, Wideband Code Division Multiple Access (WCDMA) system, General Packet Radio Service (GPRS), Long Term Evolution (LTE) system, LTE Frequency Division Duplex (FDD) system, LTE Time Division Duplex (TDD), Universal Mobile Telecommunication System (UMTS), and the like.
  • GSM Global System of Mobile communication
  • CDMA Code Division Multiple Access
  • WCDMA Wideband Code Division Multiple Access
  • GPRS General Packet Radio Service
  • LTE Long Term Evolution
  • FDD Frequency Division Duplex
  • TDD Time Division Duplex
  • UMTS Universal Mobile Telecommunication System
  • FIG. 1 is a basic flow of wireless communication.
  • the source is sequentially transmitted after source coding, channel coding, and digital modulation.
  • digital demodulation, channel decoding, and source decoding are sequentially outputted to the sink.
  • the channel codec can use a Polar code, and in channel decoding, SC decoding and SCL decoding can be used.
  • the SCL decoding algorithm is an improvement on the SC decoding algorithm. Multiple candidate paths are reserved in the decoding process, and finally a path is selected as the decoding result according to the metric value of each candidate path.
  • the metric value of the lth path, PM1(i), that is, the path value (English: path metric, PM for short) is as shown in formula (1) when decoding to the ith bit (set LLR>0) The corresponding value is 0, and the value corresponding to LLR ⁇ 0 is 1):
  • LLR(i) is the log-likelihood ratio (LLR) of the current bit.
  • the value corresponding to the LLR may be 0 or 1, for example, when LLR ⁇ 0, the corresponding value is 1, and when LLR>0, the corresponding value is 0.
  • the PM is unchanged; if the value corresponding to the LLR of the current bit (0 or 1) is inconsistent with the decision result, the PM increases the penalty value
  • each path is expanded into two paths, a total of 2L paths are extended, and L is the number of candidate paths that need to be reserved.
  • the decision result of each node is 0 and 1, respectively, and the PM of each path is calculated according to the above formula, and then the extended path is sorted according to the PM, the L paths with the smallest PM are reserved, and the remaining L paths are deleted, also called a clipping. branch. If the current bit is a frozen bit, the corresponding node in each path does not expand, directly determines the corresponding known fixed value, and calculates the PM of each path according to formula (1).
  • the following describes the value corresponding to 1 when LLR ⁇ 0, and the value corresponding to 0 when LLR>0.
  • the LLR(i) of the current decoding bit is greater than 0 (the corresponding value is 0)
  • the current bit is an information bit in the path extension process
  • two paths need to be extended.
  • the result is inconsistent with the value corresponding to the LLR (indicated by "x" in Fig.
  • the known fixed value is 0 and the LLR corresponding value is also 1, the known fixed value does not match the value corresponding to the LLR.
  • PM(i) PM(i-1)+
  • ; if the known fixed value is 1, the known fixed value is consistent with the value corresponding to the LLR, PM(i) PM (i-1).
  • Fig. 2 by retaining the path with the smallest PM value at each expansion, two candidate paths L1 and L2 as indicated by the arrows are finally obtained.
  • the final PM value of the path L1 is 0.0
  • the PM value of the other path L2 is finally 0.2. Therefore, the 0.0 path L1 with a small PM is selected as the decoding output, and the value of the decoded information bits is 0011.
  • CA-Polar Polar Code Cascading CRC (Cyclic Redundancy Check), referred to as CA-Polar
  • CA-SCL CRC-Aided Successive Cancellation List
  • CA-Polar code construction process assuming that the information block size is Kinfo, the CRC length is Kcrc, and the mother code length of the Polar code is N, it is necessary to select Kinfo+Kcrc from the N polarized channels as the information bits with the highest reliability. The rest are used as frozen bits.
  • the CA-Polar encoding process is as shown in FIG. 4, which first performs CRC encoding on the information block, then maps the CRC encoded bit to the position of the information bit, and places a fixed value agreed by the transmitting end and the receiving end at the position of the frozen bit, and then Then perform Polar coding to obtain a CA-Polar coding block.
  • the information block and the CRC bits are unknown, and decoding is performed according to the normal SCL decoding process.
  • L candidate decoding results are obtained, and the decoding result includes an information block and a CRC bit.
  • the CRC is checked for each candidate result. If the check passes, the information block of the path is used as the decoding output. If the CRC check fails, the information block of the path with the smallest PM is obtained. As the decoding output, it is also possible to directly indicate the decoding failure.
  • the CRC bits are treated as information bits, and the CRC bits are used to assist in selecting the path at the end of SCL decoding. But at the intermediate node of SCL, the correct path may be deleted because of the larger PM.
  • a partial CRC bit is moved to the middle of the bit of the information block, and the value of the partial CRC bit is determined by the value of the bit of the information block before it, that is, using the
  • the CRC bit performs parity check on the previous information bits, which is used to assist the CA-Polar SCL decoding, and improves the probability of deleting the error path at the intermediate node, thereby improving the performance of the CA-Polar.
  • This part of the CRC bits may also be called parity (PC) bits or special CRC bits.
  • these special CRC bits satisfy the condition that, in the coding order (the order after interleaving), it is located in the middle of the bits of the information block, only Check the bits of the previous information block.
  • the check equations for the special CRC bits are determined by CRC coding, ie they are used to check which bits are determined during the CRC encoding process. Interleaving does not change the bits checked by a particular CRC bit, but simply changes the position of the checked bits such that the bits checked by a particular CRC bit are located before the particular CRC bit. Thus, when decoding, when the special CRC bit is translated, the value of the special CRC bit is directly determined according to the previously checked bit.
  • the position of the special CRC bit will change, and it is not always fixed at a certain position.
  • the number of special CRC bits can also be set to different numbers according to actual needs. For convenience of description, the following is collectively referred to as a special CRC bit.
  • the encoding process includes:
  • CRC coding CRC coding the information block to obtain a CRC coded coding block.
  • Polar coding The interleaved coding block is mapped to the position of the information bits (the polarization channel can be a highly high bit position). The remaining polarized channels correspond to the positions of the frozen bits and are set to the agreed fixed values, for example, both are 0 or both. Polar coding of information bits and frozen bits to obtain a Polar coded codeword.
  • the SCL decoding algorithm is used for decoding, the information bits are path-extended, and the decision is made according to the path value, but for the special CRC bits distributed in the middle of the information block and the verified information bits are before it, The path extension is not required and the value of the special CRC bit is determined by the information bits previously decoded.
  • the frozen bits are not path-extended and translated directly into the agreed fixed values.
  • L candidate paths are obtained, and part or all of the L candidate paths are deinterleaved to obtain information blocks and CRC bits, and CRC check is performed for each path, and CRC check is selected from the candidate paths.
  • the optimal path is used as the decoded output.
  • the CRC bit can be used to select the decoding result from the candidate path, or can be used for error detection to determine whether the decoding result is correct or not.
  • the special CRC bit can be decoded as a PC bit decoding auxiliary SCL during decoding, which increases the probability of deleting the wrong path. It is also possible to perform error detection during the decoding process.
  • the value of the special CRC bit is determined by the value of the information bit obtained by the previous decoding, once the previously decoded information bit is incorrect, the value of the special CRC bit calculated by the information bit is decoded when the special CRC bit is decoded.
  • the value of the received LLR corresponding to the inconsistency may increase.
  • the encoding apparatus 700 shown in FIG. 7 can perform an encoding method as shown in FIG. 7, which includes a CRC encoding unit 701, an interleaving unit 702, and a Polar encoding unit 703.
  • the encoding method of the embodiment of the present application may include the following process:
  • the CRC encoding unit 701 performs CRC encoding on the information block to be transmitted, and obtains K+Lcrc CRC encoded bits.
  • the matrix G is a matrix of K*n, and the row number of each row can be understood as the serial number of one bit of the corresponding information block.
  • the column number of each column can be understood as the bit number corresponding to the output after the CRC encoding, and each bit after the CRC encoding.
  • the value of the value is the sum of the bit values corresponding to all the rows in the column.
  • each column of the matrix P corresponds to a CRC bit, and a bit corresponding to the row number where 1 is located in each column serves as a bit of the information block checked by the CRC bit.
  • the information block can be CRC encoded once.
  • the sequence [a1, a2, ..., a12] represents a block of information
  • [b1, b2, ... b16] represents a coded block after CRC encoding
  • b13, b14, b15, b16 are CRC bits, which can be from the table
  • the bits of the information block corresponding to the value of b13 are a2, a3, a4, a5, a7, a9, a10
  • the corresponding CRC encoded bits are b2, b3, b4, b5, b7, B9, b10
  • the sequence [2, 3, 4, 5, 7, 9, 10, 13] represents the check equation.
  • CRC lengths have different CRC generator polynomials; the same CRC length can also have a variety of different polynomials.
  • CRC lengths and corresponding generator polynomials are listed below.
  • the corresponding CRC generator polynomial includes:
  • the corresponding CRC generator polynomial includes:
  • the corresponding CRC generator polynomial includes:
  • the corresponding CRC generator polynomial includes:
  • the corresponding CRC generator polynomial includes:
  • the corresponding CRC generator polynomial includes:
  • the corresponding CRC generator polynomial includes:
  • the corresponding CRC generator polynomial includes:
  • the interleaving unit 702 interleaves the CRC encoded coded block, the result of the interleaving is such that there are Lpc CRC bits located between the bits of the information block, and each of the Lpc CRC bits is located at all bits it checks Thereafter, Lpc is an integer greater than 0 and less than Lcrc.
  • bit sequence [b1, b2, ..., bn] is transformed into b ⁇ 1 , b ⁇ 2 , ..., b ⁇ n ; where n is an integer greater than 0 and less than or equal to B, and the value of ⁇ n represents the coded block after interleaving The bit position number in the coded block of the nth bit in the interleaving.
  • the interleaved partial CRC bits are distributed between the bits of the information block, and each of the partial CRC bits checks the bits of the previous information block, as indicated by the arrows in FIG.
  • the value of Lpc is related to the CRC length Lcrc, the number of paths T that are decoded by the CRC after SCL decoding, and the requirement for false alarm rate (FAR).
  • the false alarm probability refers to the probability that the decoding result is wrong, but the event passed by the CRC check occurs.
  • the value of Lpc can be selected by referring to the following formula (2):
  • Lpc is the partial CRC length
  • Lcrc is the total length of the CRC
  • T is a predetermined number of candidate paths that need to be selected by the CRC check at the time of decoding. If there are L candidate paths, T is an integer greater than 0 and less than or equal to L.
  • T and FAR take different values, and the value of (Lcrc-Lpc) will be different.
  • the CRC-encoded CRC bits are located at the last position usually located in the coding block. As shown in Table 1, b13, b14, b15, b16 are located after b1, b2, ..., b12. After all the information blocks and the CRC bits are decoded at the decoding end, the CRC check is performed. In order to enable partial CRC bits to be verified before the end of decoding, the bits of the information block and the position of the CRC bits can be changed by interleaving such that part of the CRC bits are located between the information bits and the bits of the verified information block Also before the CRC bit.
  • the CRC bit b13 is interleaved to the position of C8, and b2, b3, b4, b5, b7, b9, b10 before C8 are all bits of the b13 check, corresponding to C1, C2, C3, C4, C5, respectively.
  • B14 is interleaved to the position of C12, b3, b4, b5, b7, b9, b10, b11 are all bits of b14 check, corresponding to the interleaved C 2 , C 3 , C 4 , C 5 , C 6 , C 7 , C 9 , C 10 , C 11 , are also located before b14.
  • the positions of b15 and b16 do not change, but the bit positions checked have changed.
  • the bits b4, b5, b6, b7, b9, b11, b12 of b15 check correspond to C 3 , C 4 , C 10 after interleaving. , C 5 , C 6 , C 11 , C 13 .
  • the b16 check bits b1, b2, b3, b4, b6, b8, b9, b12 correspond to the interleaved C 14 , C 1 , C 2 , C 3 , C 10 , C 9 , C 6 , C 13 .
  • the check equation is updated to:
  • b13 is the position as far as possible before moving to all the bits of its check, but is not limited thereto, for example, b13 can also be moved to a later position, for example, after moving to b8.
  • b14 which can also be moved after b12.
  • B13 and b14 are called special CRC bits, they are distributed between the bits of the information block after interleaving, and the bits of the information block they check are before the special CRC bits.
  • the remaining CRC bits b15 and b16 may not be used as special CRC bits, as normal CRC bits, for CRC check.
  • the positions of the two CRC bits in the interleaving process are at the end, and can also be moved to any other position.
  • the Polar encoding unit 703 maps the interleaved coding block to information bits, sets the freeze bit to a predetermined fixed value, and performs Arikan Polar coding on the information bits and the frozen bits to obtain a Polar coded code word.
  • the encoded codeword can also be called a coding block, a coding sequence, and the like.
  • the position of the information bit corresponds to the first B polarized channels sorted according to the reliability level in the polarized channel of the Polar code, and the bits corresponding to the remaining (NB) polarized channels are used as frozen bits, and are set to a predetermined fixed value.
  • N is the mother code length of the Polar code.
  • the Polar code constructed by the embodiment of the present application the information block and the CRC bits are distributed together on the most reliable polarization channel, and the frozen bits are distributed on the polarization channel with lower reliability than the information bits;
  • the CRC bits are distributed between the bits of the information block.
  • the partial CRC bit is used as the parity bit at the time of decoding, the probability of deleting the error path in the CA-SCL decoding process can be improved, and the remaining CRC can still be used for the CRC check. Since the check equation of the special CRC bit is determined by the CRC check process, it is not necessary to separately set the check equation.
  • the interleaving sequence may be pre-set after calculation, or may be calculated in real time during the encoding process. There are several ways to determine the interleaving sequence, some examples are given below.
  • the interleaving sequence ⁇ is calculated according to the CRC generation matrix, the CRC length Lcrc, the information bit length K, and the special CRC bit number Lpc.
  • the process may include the following:
  • the first p1 of the first column of P' acts as 1, then all elements are 0; the second (p 1 +1) to the (p 1 + p 2 ) behavior of the second column is 1, after All elements are 0; and so on, the behavior of (p 1 + p 2 ... + p n-1 +1) in the n-1th column is 1, and all elements are then 0.
  • the initial interleaving sequence ⁇ 0 is obtained .
  • the following describes a generation process of an interleaving sequence by taking CRC-4 as an example.
  • the 2nd, 3rd, 4th, 5th, 7th, 9th, and 10th rows are switched to the 1st, 2nd, 3rd, 4th, 5th, 6th, and 7th rows according to the row number of the element 1 in the 13th column, according to the 14th column.
  • Element 1 of the inserted row may be adjacent to the last element 1 of the column in P', or may be spaced apart from the last element 1 of the column in P'.
  • the row represents the position of the CRC bit after interleaving. For example, the row is inserted in the 8th, 12th, 14th, and 16th rows of the matrix P', and the inserted row number sequence is [8, 12, 14, 16], as shown in Table 5. Show.
  • the position of the inserted line is not limited, and the bit of the information block satisfying the check may be forwarded as far as possible before the special CRC bit, and the insertion position may be arbitrary for the normal CRC bit.
  • the check equations for the four CRC bits can be expressed as: [1, 2, 3, 4, 5, 6, 7, 9], [2, 3, 4, 7, 8, 10, 11, 13], [ 3,4,5,6,10,11,13,14], [1,2,3,6,9,10,13,15,16].
  • FIG. 11 is a schematic flowchart diagram of still another encoding method provided by an embodiment of the present application, and the method may be performed by the encoding apparatus shown in FIG. 7, FIG. 12 or FIG.
  • the method includes:
  • CRC length Lcrc Acquire a CRC length Lcrc and a CRC polynomial, which may be performed by the acquisition unit 701 of FIG. 7, the processor 1202 of FIG. 12, or the signal processor 1302 of FIG.
  • the CRC length Lcrc can usually be pre-configured in the transceiver of the communication system.
  • Step 1102 Perform CRC encoding on the information block. This step can be performed by the CRC encoding unit 701 of FIG. 7, the processor 1202 of FIG. 12, or the signal processor 1302 of FIG.
  • the input of the CRC code is the sequence a0, a1, a2, ..., a A-1
  • the check bits generated after the CRC coding are p 0 , p 1 ,... , p Lcrc-1
  • CRC encoded output sequence is b1, b2, ..., b B-1 .
  • the sequence obtained by CRC coding satisfies the formula (3).
  • Lpc CRC bits can be located between the bits of the information block, and the verified information bits are located before the CRC bits.
  • Lpc can select less than the number of Lcrc, or can be selected according to the range determined by equation (2). The Lpc is selected according to a predetermined rule and can be configured in the transceiver end of the communication system.
  • Step 2105 may be performed by a rate matching unit (not shown) in the encoding device of FIG. 7, processor 1102 of FIG. 11, or signal processor 1202 of FIG.
  • the present application provides another encoding apparatus 1200 that can implement the encoding method of the present application.
  • the encoding device 1200 includes:
  • the processor 1202 is configured to execute the program stored in the memory, and when the program is executed, execute the encoding method shown in FIG. 8.
  • the memory 1201 may be a physically separate unit or may be integrated with the processor 1202.
  • the encoding apparatus of FIG. 12 may further include a transmitter (not shown) for transmitting a coded block obtained by the processor 1102 by performing Polar encoding on the information bits and the frozen bits.
  • the present application provides another encoding apparatus 1300 that can implement the encoding method of the present application.
  • the encoding device 1300 includes:
  • the block is interleaved, and the Lpc CRC bits in the interleaved coding block are located between the bits of the information block, and each of the Lpc CRC bits is located after all the bits it checks, wherein Lpc is greater than 0 and less than An integer of Lcrc; mapping the interleaved coding block to information bits, setting the freeze bit to a predetermined fixed value, and performing Polar coding on the information bit and the frozen bit to obtain a Polar coded codeword; wherein the information bit is The position is the location corresponding to the B polarization channels with the best reliability; the position of the frozen bit is the position corresponding to the remaining NB polarization channels, and N is the length of the Polar code mother code;
  • At least one output (outPut) 1303 is used to output the coded block obtained by the signal processor 1302.
  • the signal processor 1302 may be implemented by hardware, for example, a baseband processor, a processing circuit, an encoder, or an encoding circuit.
  • a baseband processor for example, a baseband processor, a processing circuit, an encoder, or an encoding circuit.
  • the encoding apparatus of FIG. 12 may further include a transmitter (not shown) for transmitting the encoded block output by the output (outPut) 1303.
  • the encoding device in this application may be any device having wireless communication capabilities, such as an access point, a site, a user equipment, a base station, and the like.
  • the decoding device 1400 shown in FIG. 14 can be used to perform the decoding method of the present application.
  • the decoding process includes the following process:
  • the obtaining unit 1401 acquires the position of the information bit and the frozen bit in the bit to be decoded, the information bit includes K bits of the information block and Lcrc CRC bits, wherein Lpc CRC bits are located between the bits of the information block, and Lpc CRC Each CRC bit in the bit is located after all of the bits it verifies.
  • the obtaining unit 1401 may obtain the position of the information bit and the frozen bit according to the reliability order of the polarized channel, and the reliability of the polarized channel corresponding to the information bit is higher than the reliability of the polarized channel corresponding to the frozen bit.
  • the obtaining unit 1401 sorts the reliability of the polarized channels, and selects K+Lcrc as the most reliable information bits, the remaining polarized channels as the frozen bits, K is the size of the information block, and Lcrc is the CRC bits. number.
  • the serial offset list SCL decoding algorithm is used to decode the decoded bits in order, and output L candidate paths with the best metric value.
  • the decoding unit 1402 sequentially decodes the to-be-decoded bits by using a serial cancellation list SCL decoding algorithm, and outputs L candidate paths with optimal metric values, where each candidate path is in the decoding process.
  • the value of the frozen bit is set to a predetermined fixed value, and the value of each of the Lpc CRC bits is determined according to the value of the bit of the information block that is checked before the CRC bit, and the remaining (Lcrc-Lpc)
  • the CRC bits are decoded according to the information bits.
  • the CRC bits are decoded as information bits, which are unknown bits, and path expansion is required in the decoding process. Since at the encoding end, the value of the partial CRC bit is determined only by the information bits preceding it by interleaving, if the partial CRC bit is used as the parity bit, the decoding is the same as the frozen bit, and is decoded as a known bit.
  • the path extension is not performed during the decoding process, except that the partial CRC bit decoding result is determined by the previously decoded information bits and the check equation.
  • the freeze bit does not require path expansion as long as the corresponding bit is directly set to the agreed fixed value during the decoding process.
  • T candidate paths with the best metric values among the L candidate paths, where T is an integer greater than 0 and less than or equal to L.
  • the CRC check unit 1404 may perform CRC check on the T candidate paths in turn starting from the candidate path with the best metric value.
  • the CRC check unit 1404 can perform CRC check on all T candidate paths respectively, and obtain a result of verification pass or check failure. It is also possible to obtain the candidate path through which the first CRC check passes and no longer check the remaining candidate paths.
  • the information block in the candidate path that passes the CRC check and the path metric is optimal is used as a decoding output.
  • the output unit 1405 selects a candidate path that will pass the CRC check and the path metric is optimal, and the information block corresponding to the information bit is used as the output of the current decoding. If the CRC check unit 1404 performs the CRC check from the candidate path with the best metric value, the first candidate path passed by the CRC check may be directly used as the decoding result, and the information block therein may be output.
  • Step 1501 can also include obtaining a check equation.
  • the determination of the check equation can be determined by a CRC polynomial and an interleaving sequence.
  • the generator matrix determined by the CRC polynomial determines the information bits of each CRC check, and the interleaving sequence can determine the position of the information bits of each CRC check after interleaving, thereby obtaining an interleaved check equation.
  • the calculation of the PM value is calculated by the formula (1), and by retaining the path with the smallest PM value at each expansion, the two candidate paths L1 and L2 as indicated by the arrows are obtained.
  • the final PM value of path L1 is 0.3, and the PM value of the other path L2 is finally 0.2.
  • the CRC check is performed first from the path L2 with the smallest PM (the metric value is optimal), and if the check passes, L2 is selected as the decoded output.
  • the i-th bit indicated in Fig. 16 is a partial CRC bit (special CRC bit) as referred to in the present application, and two arrows 1601 indicate that the value of the special CRC bit is determined by the i-th bit (information bit). It can be seen that when decoding the i-th bit, path expansion is not required, and the value of the i-th bit is determined by the value of the i-th bit in the path, so the value of the special CRC bit in the path L1 is 0, the value of the special CRC bit in L2 is 1.
  • FIG. 16 and FIG. 3 is that the i-th bit corresponds to a freeze bit in FIG. 3 and a special CRC bit in FIG. In Fig.
  • FIG. 16 assumes that the LLR(i) of the special CRC bits of the L1 and L2 paths is less than 0, assuming that the value corresponding to LLR(i) is less than 0 is 1, and the decoding result of the i bits in the L1 path is 0 and LLR ( The results of i) are inconsistent.
  • assuming 0.3.
  • the special CRC bit i is determined according to the result obtained by the previous decoding, or may be incorrect, which may cause the decoding result of the i bit to be inconsistent with the value corresponding to LLR(i).
  • PM(i) adds the penalty value
  • all CRC bits are used for CRC check for error correction or error detection.
  • the solution of the present application is to interleave part of the CRC bits to the bits between the information blocks, and the bits of the checked information block are all before the CRC bits, and are regarded as PC-specific decoding at the time of decoding.
  • the performance curve indicated by the solid line corresponds to the CRC length 27, in which 8-bit interleaving is performed as PC bit-assisted SCL, and the remaining CRC bits are used in SCL decoding.
  • the trailing path is selected; the dashed line is the CRC length 27, all used to pick the path after SCL decoding.
  • the decoding apparatus 1800 shown in FIG. 18 can also be used to perform a decoding method.
  • the decoding apparatus 1800 includes:
  • the processor 1802 is configured to execute the program stored in the memory, and when the program is executed, execute the decoding method shown in FIG.
  • the method includes: obtaining a position of an information bit and a frozen bit in a bit to be decoded, where the information bit includes K bits of the information block and Lcrc CRC bits, wherein Lpc CRC bits are located between bits of the information block, and Lpc Each CRC bit in the CRC bit is located after all bits it checks, where Lpc is an integer greater than 0 and less than Lcrc; the serialized offset list SCL decoding algorithm is used to decode the decoded bits in order, and output The L candidate paths with the best metric, wherein the value of the frozen bit in each candidate path is set to a fixed value in the decoding process, and the value of each CRC bit in the Lpc CRC bits is based on the CRC The value of the bit of the information block that is checked before the bit is determined, and the remaining (Lcrc-Lpc) CRC
  • the path with the best metric value may be selected as the decoding output, and the decoding failure may be confirmed.
  • the memory 1801 may be a physically separate unit or may be integrated with the processor 1802.
  • the decoding apparatus of FIG. 18 may further include a receiver (not shown) for receiving bit information to be decoded.
  • the present application provides another decoding apparatus 1900 that can implement the encoding method of the present application.
  • the decoding device 1900 includes:
  • At least one input (1901) for receiving bit information to be decoded At least one input (1901) for receiving bit information to be decoded
  • the signal processor 1902 is configured to obtain a position of the information bit and the frozen bit in the bit to be decoded, where the information bit includes K bits of the information block and Lcrc CRC bits, where the Lpc CRC bits are located between the bits of the information block, And each of the Lpc CRC bits is located after all the bits it checks, wherein Lpc is an integer greater than 0 and less than Lcrc; the serialized offset list SCL decoding algorithm is used to decode the decoded bits in order And outputting L candidate paths with the best metric value, wherein the value of the frozen bit in each candidate path is set to a predetermined fixed value in the decoding process, and the value of each CRC bit in the Lpc CRC bits is located according to The value of the bit of the information block that is checked before the CRC bit is determined, and the remaining (Lcrc-Lpc) CRC bits are decoded according to the information bits; T candidates that are optimal for the metric values in the L candidate paths The path is deinter
  • At least one output 1903 is configured to output the information block in the first candidate path through which the CRC check passes.
  • the signal processor 1902 described above may be implemented by hardware, such as a baseband processor, a processing circuit, a decoder, or a decoding circuit.
  • the decoding apparatus of FIG. 19 may further include a receiver (not shown) for receiving bit information to be decoded.
  • the decoding device of the embodiment of the present application may be any device having a wireless communication function, such as an access point, a site, a user equipment, a base station, and the like.
  • the information block referred to in the embodiment of the present application refers to information bits to be transmitted, and may also be called an information bit sequence, a to-be-coded bit sequence, and data.
  • the information block length may be called the information block size, and refers to the number of bits in the information bit sequence, the number of bits to be encoded in the bit sequence to be encoded, the number of bits in the data block, the number of data bits or information. The number of elements in the set of bits.
  • the coded blocks in the embodiments of the present application may also be referred to as coded bits, coded bit sequences, and the like.
  • serial cancellation list SCL decoding algorithm in the embodiment of the present application includes other SCL-like decoding algorithms that sequentially decode, provide multiple candidate paths, or an improved algorithm for the SCL decoding algorithm.
  • the encoding device or the decoding device in the embodiment of the present application may be separate devices in actual use; or may be integrated devices for transmitting information to be sent after being encoded, or receiving information. Perform decoding.
  • the unit and method processes of the examples described in the embodiments of the present application can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the solution. The skilled person can use different methods for each particular application to implement the described functionality.
  • the disclosed apparatus and method may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division, and the actual implementation may have another division manner.
  • multiple units or components may be combined or integrated into another system. Some of the steps in the method can be ignored or not executed.
  • the coupling or direct coupling or communication connection of the various units to one another may be achieved through some interfaces, which may be in electrical, mechanical or other form.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above embodiments it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof.
  • software it may be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions.
  • the computer program instructions When the computer program instructions are loaded and executed on a computer, the processes or functions described in accordance with embodiments of the present invention are generated in whole or in part.
  • the computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable device.
  • the computer instructions can be stored in or transmitted by a computer readable storage medium.
  • the computer instructions can be from a website site, computer, server or data center to another website site by wire (eg, coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (eg, infrared, wireless, microwave, etc.) Transfer from a computer, server, or data center.
  • wire eg, coaxial cable, fiber optic, digital subscriber line (DSL)
  • wireless eg, infrared, wireless, microwave, etc.
  • the computer readable storage medium can be any available media that can be accessed by a computer or a server, data center, or equivalent data storage device that includes one or more available media.
  • the usable medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape, a USB flash drive, a ROM, a RAM, etc.), an optical medium (eg, a CD, a DVD, etc.), or a semiconductor medium (eg, a solid state hard disk Solid State Disk (SSD) ))Wait.
  • a magnetic medium eg, a floppy disk, a hard disk, a magnetic tape, a USB flash drive, a ROM, a RAM, etc.
  • an optical medium eg, a CD, a DVD, etc.
  • a semiconductor medium eg, a solid state hard disk Solid State Disk (SSD)

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Abstract

本申请实施例提供一种Polar编码方法，包括：对信息块进行CRC编码，得到长度为B的CRC编码后的编码块，其中CRC长度为Lcrc，信息块长度为K，B＝K+Lcrc；对CRC编码后的编码块进行交织，交织后的编码块中的Lpc个CRC比特位于信息块的比特之间，且Lpc个CRC比特中的每个CRC比特位于其所校验的所有比特之后，其中Lpc为大于0小于Lcrc的整数；将交织后的编码块映射到信息比特，冻结比特设置为约定的固定值，对所述信息比特和所述冻结比特进行Polar编码，得到Polar编码码字；其中所述信息比特的位置为可靠度最优的B个极化信道对应的位置；所述冻结比特的位置为剩下的N-B个极化信道对应的位置，N为Polar码母码长度。该编码方法能够进一步提高CA-Polar码的性能。

Description

Polar码编译码方法及装置 技术领域
本发明实施例涉及无线通信领域，更具体地，涉及Polar码编译码方法及装置。
背景技术
通信系统通常采用信道编码提高数据传输的可靠性，以保证通信的质量。土耳其教授Arikan提出的极化码(英文：Polar codes)是第一个理论上证明可以达到香农容量且具有低编译码复杂度的好码。Polar码是一种线性块码，其编码矩阵为G N，编码过程为
Figure PCTCN2018077853-appb-000001
其中
Figure PCTCN2018077853-appb-000002
是一个二进制的行矢量，长度为N(即母码长度)；G N是一个N×N的矩阵，且
Figure PCTCN2018077853-appb-000003
定义为log 2N个矩阵F 2的克罗内克(Kronecker)乘积。上述矩阵
Figure PCTCN2018077853-appb-000004
传统Polar码的编码过程中，
Figure PCTCN2018077853-appb-000005
中的一部分比特用来携带信息，称为信息比特，这些比特的索引的集合记作
Figure PCTCN2018077853-appb-000006
另外的一部分比特设置为收发端预先约定的固定值，称之为固定比特或冻结比特(frozen bits)，其索引的集合用
Figure PCTCN2018077853-appb-000007
的补集
Figure PCTCN2018077853-appb-000008
表示。Polar码的编码过程相当于：
Figure PCTCN2018077853-appb-000009
这里，G N.(A)是G N.中由集合A中的索引对应的那些行得到的子矩阵，G N(A C)是G N中由集合A C中的索引对应的那些行得到的子矩阵。
Figure PCTCN2018077853-appb-000010
为
Figure PCTCN2018077853-appb-000011
中的信息比特集合，信息比特个数为K；
Figure PCTCN2018077853-appb-000012
为
Figure PCTCN2018077853-appb-000013
中的冻结比特集合，冻结比特个数为(N-K)，是已知比特。这些冻结比特的值通常被设置为0，但是只要收发端预先约定，固定比特可以被任意设置。固定比特设置为0时，Polar码的编码输出可简化为：
Figure PCTCN2018077853-appb-000014
是一个K×N的矩阵。
Polar码的构造过程即集合
Figure PCTCN2018077853-appb-000015
的选取过程，决定了Polar码的性能。Polar码的构造过程通常是，根据母码码长N确定共存在N个极化信道，分别对应编码矩阵的N个行，计算极化信道可靠度，将可靠度较高的前K个极化信道的索引作为集合A的元素，剩余(N-K)个极化信道对应的索引作为固定比特的索引集合
Figure PCTCN2018077853-appb-000016
的元素。集合A决定了信息比特的位置，集合
Figure PCTCN2018077853-appb-000017
决定了固定比特的位置。
在译码端，Polar码可以采用串行抵消(英文：Successive Cancellation,简称SC)译码 算法，从第1个比特开始顺序译码。串行抵消列表(英文Successive Cancellation List,简称SCL)译码算法是对SC译码算法的改进，在译码过程中保留多个候选译码结果。SCL把译码过程看成一个路径搜索过程，即以第1个比特作为根结点进行路径扩展，采用一个度量值对该路径进行评估，该度量值随着路径的扩展按照预定的规则动态更新。每一次扩展(译码下一个比特)时，保留当前层中具有最优路径度量的L条候选路径，直到扩展到最后一层(译码最后一个比特)。最终输出L条候选路径中度量值最优的路径作为译码输出。SCL译码算法可以获得最大似然译码性能。
为了提高Polar码的性能，现有技术对Polar码进行改进，提出了CA-Polar码。CA-Polar码是级联CRC(英文：Cyclic Redundancy Check，循环冗余校验)的Polar码，简称CA-Polar码。通过对信息块进行CRC编码，再将CRC编码后的比特映射到信息比特中。相应的，译码的时候采用CA-SCL(CRC-Aided Successive Cancellation List)译码算法进行译码，即在SCL译码输出的L条候选路径中选择CRC通过的候选路径作为译码输出。如果在CA-SCL译码的中间节点，正确路径因为度量值较差而被删除，则后续的CRC校验无法提升SCL译码的性能。
发明内容
本申请实施例提供Polar码编码方法及编码装置、译码方法及译码装置，能够进一步提高CA-Polar码的性能。
第一方面，提供一种Polar编码方法，包括：
对信息块进行CRC编码，得到长度为B的CRC编码后的编码块，其中CRC长度为Lcrc，信息块长度为K，B＝K+Lcrc；
对CRC编码后的编码块进行交织，交织后的编码块中的Lpc个CRC比特位于信息块的比特之间，且Lpc个CRC比特中的每个CRC比特位于其所校验的所有比特之后，其中Lpc为大于0小于Lcrc的整数；
将交织后的编码块映射到信息比特，冻结比特设置为约定的固定值，对所述信息比特和所述冻结比特进行Polar编码，得到Polar编码码字；其中所述信息比特的位置为可靠度最优的B个极化信道对应的位置；所述冻结比特的位置为剩下的N-B个极化信道对应的位置，N为Polar码母码长度。
第二方面，提供一种编码装置，包括：
CRC编码单元，用于对信息块进行CRC编码，得到长度为B的CRC编码后的编码块，其中CRC长度为Lcrc，信息块长度为K，B＝K+Lcrc；
交织单元，对CRC编码后的编码块进行交织，交织后的编码块中的Lpc个CRC比特位于信息块的比特之间，且Lpc个CRC比特中的每个CRC比特位于其所校验的所有比特之后，其中Lpc为大于0小于Lcrc的整数；
Polar编码单元，用于将所述交织单元交织后的编码块映射到信息比特，冻结比特设置为约定的固定值，对所述信息比特和所述冻结比特进行Polar编码，得到Polar编码码字； 其中，所述信息比特的位置为可靠度最优的B个极化信道对应的位置；所述冻结比特的位置为剩下的N-B个极化信道对应的位置，N为Polar码母码长度。
第三方面，提供一种编码装置，包括：
存储器，用于存储程序；
处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，所述处理器用于对信息块进行CRC编码，得到长度为B的CRC编码后的编码块，其中CRC长度为Lcrc，信息块长度为K，B＝K+Lcrc；对CRC编码后的编码块进行交织，交织后的编码块中的Lpc个CRC比特位于信息块的比特之间，且Lpc个CRC比特中的每个CRC比特位于其所校验的所有比特之后，其中Lpc为大于0小于Lcrc的整数；将交织后的编码块映射到信息比特，冻结比特设置为约定的固定值，对所述信息比特和所述冻结比特进行Polar编码，得到Polar编码码字；其中所述信息比特的位置为可靠度最优的B个极化信道对应的位置；所述冻结比特的位置为剩下的N-B个极化信道对应的位置，N为Polar码母码长度。
第四方面，提供一种编码装置，包括：
至少一个输入端，用于接收信息块；
信号处理器，用于对所述信息块进行CRC编码，得到长度为B的CRC编码后的编码块，其中CRC长度为Lcrc，信息块长度为K，B＝K+Lcrc；对CRC编码后的编码块进行交织，交织后的编码块中的Lpc个CRC比特位于信息块的比特之间，且Lpc个CRC比特中的每个CRC比特位于其所校验的所有比特之后，其中Lpc为大于0小于Lcrc的整数；将交织后的编码块映射到信息比特，冻结比特设置为约定的固定值，对所述信息比特和所述冻结比特进行Polar编码，得到Polar编码码字；其中所述信息比特的位置为可靠度最优的B个极化信道对应的位置；所述冻结比特的位置为剩下的N-B个极化信道对应的位置，N为Polar码母码长度；
至少一个输出端，用于输出信号处理器得到的Polar编码码字。
第五方面，提供一种Polar译码方法，包括：
获取待译码比特中信息比特和冻结比特的位置，信息比特包括信息块的K个比特和Lcrc个CRC比特，其中，Lpc个CRC比特位于信息块的比特之间，且Lpc个CRC比特中的每个CRC比特位于其所校验的所有比特之后，其中，Lpc为大于0小于Lcrc的整数；
采用串行抵消列表SCL译码算法按顺序对待译码比特进行译码，输出度量值最优的L条候选路径，其中，在译码过程中每条候选路径中的冻结比特的值设为约定的固定值，Lpc个CRC比特中的每个CRC比特的值根据位于该CRC比特之前的其所校验的信息块的比特的值确定，剩余的(Lcrc-Lpc)个CRC比特按照信息比特进行译码；
对L个候选路径中的度量值最优的T个候选路径进行解交织，T为大于0小于等于L的整数；
对所述T个候选路径进行CRC校验，将通过CRC校验且路径度量最优的候选路径中的信息块作为译码输出。
第六方面，提供一种译码装置，包括：
获取单元，用于获取待译码比特中信息比特和冻结比特的位置，信息比特包括信息块的K个比特和Lcrc个CRC比特，其中，Lpc个CRC比特位于信息块的比特之间，且Lpc个CRC比特中的每个CRC比特位于其所校验的所有比特之后，其中，Lpc为大于0小于Lcrc的整数；
译码单元，采用串行抵消列表SCL译码算法按顺序对待译码比特进行译码，输出度量值最优的L条候选路径，其中，在译码过程中每条候选路径中的冻结比特的值设为约定的固定值，Lpc个CRC比特中的每个CRC比特的值根据位于该CRC比特之前的其所校验的信息块的比特的值确定，剩余的(Lcrc-Lpc)个CRC比特按照信息比特进行译码；
交织单元，对L个候选路径中的度量值最优的T个候选路径进行解交织，T为大于0小于等于L的整数；
CRC校验单元，用于对所述T个候选路径进行CRC校验，将通过CRC校验且路径度量最优的候选路径中的信息块作为译码输出。
第七方面，提供一种译码装置，包括：
存储器，用于存储程序；
处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，所述处理器用于获取待译码比特中信息比特和冻结比特的位置，信息比特包括信息块的K个比特和Lcrc个CRC比特，其中，Lpc个CRC比特位于信息块的比特之间，且Lpc个CRC比特中的每个CRC比特位于其所校验的所有比特之后，其中，Lpc为大于0小于Lcrc的整数；采用串行抵消列表SCL译码算法按顺序对待译码比特进行译码，输出度量值最优的L条候选路径，其中，在译码过程中每条候选路径中的冻结比特的值设为约定的固定值，Lpc个CRC比特中的每个CRC比特的值根据位于该CRC比特之前的其所校验的信息块的比特的值确定，剩余的(Lcrc-Lpc)个CRC比特按照信息比特进行译码；对L个候选路径中的度量值最优的T个候选路径进行解交织，T为大于0小于等于L的整数；对所述T个候选路径进行CRC校验，将通过CRC校验且路径度量最优的候选路径中的信息块作为译码输出。
第八方面、提供一种译码装置，包括：
至少一个输入端，用于接收待译码比特信息；
信号处理器，用于获取待译码比特中信息比特和冻结比特的位置，信息比特包括信息块的K个比特和Lcrc个CRC比特，其中，Lpc个CRC比特位于信息块的比特之间，且Lpc个CRC比特中的每个CRC比特位于其所校验的所有比特之后，其中，Lpc为大于0小于Lcrc的整数；采用串行抵消列表SCL译码算法按顺序对待译码比特进行译码，输出度量值最优的L条候选路径，其中，在译码过程中每条候选路径中的冻结比特的值设为约定的固定值，Lpc个CRC比特中的每个CRC比特的值根据位于该CRC比特之前的其所校验的信息块的比特的值确定，剩余的(Lcrc-Lpc)个CRC比特按照信息比特进行译码；对L个候选路径中的度量值最优的T个候选路径进行解交织，T为大于0小于等于L的整数； 对所述T个候选路径进行CRC校验；
至少一个输出端，用于将通过CRC校验且路径度量最优的候选路径中的信息块作为译码输出。
结合以上所有方面，在第一种可能的实现方式中，所述对CRC编码后的编码块进行交织包括：采用交织序列π＝[π1,π2,...,πn]对CRC编码后的编码块进行交织，将CRC编码后的比特序列[b1,b2,...,bn]变换为bπ1,bπ2,...,bπn；其中n为大于0小于等于B的整数，πn的值表示交织后的编码块中的第n个比特在交织之前的编码块中的比特位置序号。
结合以上所有方面以及第一种可能的实现方式，在第二种可能的实现方式中，Lpc、Lcrc、T以及通信系统规定的虚警概率上限FAR满足以下关系：
L pc≤L crc-log 2T+log 2FAR。
结合以上所有方面以及所有可能的实现方式，在第三种可能的实现方式中，所述Lcrc为27，Lpc为8；或者Lcrc为24，Lpc为6；或者，Lcrc为22,23,14或15，Lpc为4；或者。
结合第五至第八方面的任意方面，在第四种可能的实现方式中，所述度量值为路径值PM。
结合第五至第八方面的任意方面或第四种可能的实现方式，在第五种可能的实现方式中，若T条候选路径的CRC校验均未通过，T条候选路径中度量值最优的路径的信息块作为译码输出或者确定为译码失败。
结合第一至第四方面，在第六种可能的实现方式中，所述CRC编码为：一次CRC编码。只需要按照Lcrc的长度进行一次CRC编码，得到CRC编码后的编码块。
结合以上所有方面以及所有可能的实现方式，在第六种可能的实现方式中，Lcrc和Lpc满足以下关系：Lcrc-Lpc＝10；或者Lcrc-Lpc＝18。
结合以上所有方面以及所有可能的实现方式，在第七种可能的实现方式中，Lpc＝1,Lcrc＝11；或者Lpc＝2,Lcrc＝12；或者Lpc＝4,Lcrc＝14；或者Lpc＝6,Lcrc＝16；或者Lpc＝8,Lcrc＝18。
结合以上所有方面以及所有可能的实现方式，在第八种可能的实现方式中，Lpc＝1,Lcrc＝19；或Lpc＝2,Lcrc＝20；或Lpc＝4,Lcrc＝22；或Lpc＝6,Lcrc＝24；或Lpc＝8,Lcrc＝26。
本申请的第九方面提了供一种计算机可读存储介质，所述计算机可读存储介质中存储有指令，当其在计算机上运行时，使得计算机执行上述各方面或各种可能的实现方式所述的编码方法或译码方法。
本申请的又一方面提供了一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行上述各方面或各种可能的实现方式所述的编码方法或译码方法。
本申请的又一方面提供了一种计算机程序，当其在计算机上运行时，使得计算机执行上述各方面或各种可能的实现方式所述的编码方法或译码方法。
本申请实施例在CRC编码后，对CRC编码后的编码块进行交织，使得交织后的编码块中的部分CRC比特分布于信息块的比特之间，且该部分CRC比特中的每个CRC比特位于其所校验的所有比特之后，也就是说该部分CRC比特仅校验位于其之前的信息块的比特。在译码过程中，该部分CRC比特当做奇偶校验比特译码，如果前面的信息比特译码有错，根据前面的信息比特计算得到的CRC比特的值与接收到的LLR不符的可能性更大，使得该路径的度量值变劣，从而在候选路径的度量值排序时更可能把该错误路径删除，提高了CA-SCL译码的性能。
附图说明
图1是无线通信发送端和接收端的基本流程示意图；
图2a是本申请实施例中当前比特的LLR大于0的情况下，路径扩展及度量值计算示意图；
图2b是本申请实施例中当前比特的LLR小于0情况下，路径扩展及度量值计算示意图；
图3是SCL译码的一种路径扩展和PM值更新的示意图；
图4是CA-Polar编码的过程示意图；
图5是CA-Polar构造的示意图；
图6是本申请实施例提供的编码过程示意图；
图7是本申请实施提供的一种编码装置的结构示意图；
图8是本申请实施提供的一种编码方法的流程示意图；
图9是本申请实施例的各个特殊CRC比特与其之前信息比特的校验关系示意图；
图10是本申请实施例提供的一种CA-Polar构造的示意图；
图11是本申请实施例提供的另一种编码方法的流程图；
图12是本申请实施提供的又一种编码装置的结构示意图；
图13是本申请实施提供的又一种编码装置的结构示意图；
图14是本申请实施提供的一种译码装置的结构示意图；
图15是本申请实施提供的一种译码方法的流程示意图；
图16是本申请实施例提供的SCL译码的一种路径扩展和路径值更新的示意图；
图17(a)是List＝8，K＝32时，本申请的方案与传统的CA-Polar在AWGN信道下的性能对比；
图17(b)是K＝48时本申请的方案与传统的CA-Polar在AWGN信道下的性能对比；
图18是本申请实施提供的又一种译码装置的结构示意图；
图19是本申请实施提供的又一种译码装置的结构示意图；
具体实施方式
本申请实施例的技术方案可以应用5G通信系统或未来的通信系统，也可以用于其他各种无线通信系统，例如：全球移动通讯(GSM，Global System of Mobile communication)系统、码分多址(CDMA，Code Division Multiple Access)系统、宽带码分多址(WCDMA，Wideband Code Division Multiple Access)系统、通用分组无线业务(GPRS，General Packet  Radio Service)、长期演进(LTE，Long Term Evolution)系统、LTE频分双工(FDD，Frequency Division Duplex)系统、LTE时分双工(TDD，Time Division Duplex)、通用移动通信系统(UMTS，Universal Mobile Telecommunication System)等。
图1是无线通信的基本流程，在发送端，信源依次经过信源编码、信道编码、数字调制后发出。在接收端，依次经过数字解调、信道译码、信源解码输出信宿。信道编解码可以采用Polar码，而在信道解码的时候，可以采用SC译码以及SCL译码。SCL译码算法是对SC译码算法的改进，在译码过程中保留多个候选路径，最后根据每个候选路径的度量值选择一个路径作为译码结果。
第l条路径的度量值PMl(i)，即路径值(英文：path metric，简称PM)在译码到第i个比特时的度量值的如公式(1)所示(设定LLR>0对应的值为0，LLR<0对应的值为1)：
Figure PCTCN2018077853-appb-000018
其中，LLR(i)是当前比特的对数似然比(英文：Log-likelihood Ratio，简称LLR)。LLR对应的值可以是0也可以是1，例如，当LLR<0时对应的值为1，当LLR>0时对应的值为0。当然，在实际应用时也可以采用其它的方式，例如将LLR<0对应的值设置为0，将LLR>0对应的值设置为1。LLR＝0时，可以认为其对应的值是0也可以认为其对应的值是1，在实际应用时可以根据需要进行设置。如果当前比特的LLR对应的值与判决结果一致，PM不变；如果当前比特的LLR对应的值(0或1)与判决结果不一致，PM增加惩罚值|LLR(i)|，即惩罚值为当前比特的LLR的绝对值。从PM的计算公式可以看出，PM越小，表示该路径对应的码字与接收信号越近，代表该路径的度量值越优，因此最后可以输出PM最小的路径作为译码结果。公式(1)中如果当前比特的LLR对应的值(0或1)与判决结果不一致，PM也可以改为减去惩罚值|LLR(i)|，即PMl(i)＝PMl(i-1)-|LLR(i)|，相应的，选择最优度量值的路径即表示选择PM最大的路径。本申请以公式(1)为例进行描述。
在SCL译码过程，如果当前比特是信息比特，每条路径会扩展成2条路径，总共扩展出2L条路径，L是最终需要保留的候选路径个数。每个节点的判决结果分别为0和1，并根据上式计算各路径的PM，然后对扩展后的路径根据PM进行排序，保留PM最小的L条路径，删除其余L条路径，也叫做剪枝。如果当前比特是冻结比特，各条路径中的相应节点不进行扩展，直接判决为相应的已知的固定值，并根据式(1)计算各路径的PM。
为方便描述，下面都以LLR<0时对应的值为1，LLR>0时对应的值为0作为例子进行描述。如图2(a)所示，若当前译码比特的LLR(i)大于0(对应的值为0)，在路径扩展过程中，若当前比特是信息比特，则需要扩展两条路径，若判决结果也为0，则判决结果与LLR对应的值一致(图2中以“√”表示)，此种情况下PM(i)＝PM(i-1)；若判决结果为1，则判决结果与LLR对应的值不一致(图2中以“x”表示)，此种情况下PM(i)＝PM(i-1)+|LLR(i)|。若当前比特是冻结比特，则对路径不进行扩展，按照已知的固定值计算PM，若已知的固定值是0，LLR对应的值也为0，则该已知的固定值与LLR对应的值一致，此种情况下PM(i)＝PM(i-1)；若已知的固定值是1，则该已知的固定值与LLR对应的值不一致，此种情况下PM(i)＝PM(i-1)+|LLR(i)|。如图2(b)所示，若当前译码比特的LLR(i)小于0(对应的值 为1)，在路径扩展过程中，若当前比特是信息比特，则需要扩展两条路径，若判决结果为0，则判决结果与LLR对应的值不一致，此种情况下PM(i)＝PM(i-1)+|LLR(i)|；若判决结果为1，则判决结果与LLR对应的值一致，此种情况下PM(i)＝PM(i-1)。若当前比特是冻结比特，不进行扩展，按照已知的固定值计算PM，若已知的固定值是0，LLR对应的值也为1，则该已知的固定值与LLR对应的值不一致，PM(i)＝PM(i-1)+|LLR(i)|；若已知的固定值是1，则该已知的固定值与与LLR对应的值一致，PM(i)＝PM(i-1)。
图3是SCL译码算法List＝2的示例,在译码过程中保留2个候选路径。通常前面的几个比特是冻结比特，设置为固定的值，如0。因此实际上从第一个信息比特开始译码。图2中通过在每次扩展的时候，保留PM值最小的路径，最后得到如箭头所示的两条候选路径L1和L2。路径L1最终的PM值为0.0，另一条路径L2的PM值最终为0.2，因此选择PM较小的0.0那条路径L1作为译码输出，译码得到的信息比特的值为0011。对Polar码级联CRC(Cyclic Redundancy Check，循环冗余校验)，简称CA-Polar，并通过CRC校验在SCL译码输出的候选路径中选择CRC通过的路径作为译码输出，CA-SCL(CRC-Aided Successive Cancellation List)译码算法，能显著提高Polar码的性能。
CA-Polar码构造过程：假设信息块大小为Kinfo，CRC长度为Kcrc，Polar编码的母码码长为N，则需要从N个极化信道中选择Kinfo+Kcrc个可靠度最高的作为信息比特，其余的作为冻结比特。CA-Polar编码过程如图4所示，先对信息块进行CRC编码，然后将CRC编码后的比特映射到信息比特的位置，在冻结比特的位置放置发送端和接收端约定的固定值，然后再进行Polar编码，得到CA-Polar的编码块。SCL译码过程中，信息块和CRC比特均未知，按照正常的SCL译码过程进行译码。在SCL译码结束后，得到L个候选译码结果，译码结果中包括信息块和CRC比特。从PM最小的路径开始，对每个候选结果进行CRC校验，如果校验通过，则将该路径的信息块作为译码输出；如果CRC校验均未通过，将PM最小的路径的信息块作为译码输出，或者也可以直接指示译码失败。
如图5所示，在CA-Polar的编译码过程中，CRC比特均作为信息比特处理，在SCL译码结束时CRC比特用于辅助选择路径。但是在SCL的中间节点，正确路径可能因为PM较大被删除。
本申请实施例在CA-Polar中，通过交织将使得部分CRC比特被移动到信息块的比特中间，该部分CRC比特的值由其前面的信息块的比特的值确定，也就是说，利用该CRC比特对前面的信息比特进行奇偶校验，用于辅助CA-Polar的SCL译码，在中间节点提高删除错误路径的概率，提高CA-Polar的性能。这部分CRC比特也可以叫做奇偶校验(PC)比特或者特殊CRC比特，无论如何称呼，这些特殊CRC比特满足这样的条件：按照编码顺序(交织后的顺序)，位于信息块的比特中间，仅校验其之前的信息块的比特。特殊CRC比特的校验方程通过CRC编码确定，即它们用于校验哪些比特是在CRC编码过程中确定的。交织并不会改变某个特殊CRC比特所校验的比特，只是改变了所校验的比特的位置，使得某个特殊CRC比特所校验的比特都位于该特殊CRC比特之前。这样在译码的时候，译到该特殊CRC比特的时候，该特殊CRC比特的值直接根据其之前所校验的比特确定。每次发送的信息块长度、CRC长度、CRC生成多项式等参数不同，特殊CRC比特所处的位置会改变，并不一定总是固定在某个位置。特殊CRC比特的个数也可以根据实际需要设 定不同的数量。为了便于描述，以下统一称作特殊CRC比特。
如图6所示，编码过程包括：
(1)CRC编码：对信息块进行CRC编码，得到CRC编码后的编码块。
(2)交织：对CRC编码后的编码块进行交织。由于使用串行的SCL译码算法，部分CRC比特当做PC校验的话，这些CRC比特仅与之前的译码比特相关。通过交织可以确保部分分布在信息块的比特中间的CRC比特校验的信息比特在该CRC比特之前。
(3)Polar编码：将交织后的编码块映射到信息比特的位置上(极化信道可高度较高的比特位置)。剩余的极化信道对应冻结比特的位置，设置为约定的固定值，例如都是0或者都是1。对信息比特和冻结比特进行Polar编码，得到Polar编码码字。
接收端译码时，采用SCL译码算法进行译码，对信息比特进行路径扩展，根据路径值进行判决，但是对于分布在信息块中间且校验的信息比特都在其之前的特殊CRC比特，不需要进行路径扩展，该特殊CRC比特的值由其前面译码得到的信息比特确定。对冻结比特作不进行路径扩展，直接译为约定的固定值。SCL译码结束后，得到L条候选路径，对L条候选路径的部分或者全部进行解交织，得到信息块和CRC比特，对每条路径进行CRC校验，从候选路径中选择CRC校验通过的最优路径作为译码输出。译码时，CRC比特既可以用于从候选路径中挑选译码结果，也可以用于检错即判断译码结果正确与否。特殊CRC比特可以在译码的过程中当作PC比特译码辅助SCL译码，提高删除错误路径的概率。也可以在译码过程中进行检错，一旦发现所有的扩展路径均无法通过CRC比特的校验，停止后续的译码，即终止译码，并确定为译码失败
由于特殊CRC比特的值由前面译码得到的信息比特的值确定，一旦前面译码的信息比特有误，那么在译码该特殊CRC比特时，该特殊CRC比特通过信息比特计算得到的值与接收的LLR对应的值不一致性的可能增大，相应的在计算该条路径的PM值时，根据前述公式(1)的计算，PM值会加上该特殊CRC比特LLR的绝对值，从而加大了该路径的PM值，该路径在后续译码过程中被删除的可能性加大。
如图7所示的编码装置700可以执行如图7所示的编码方法，该编码装置700包括CRC编码单元701，交织单元702和Polar编码单元703。如图7所示，本申请实施例的编码方法可以包括以下过程：
801、对信息块进行循环冗余校验CRC编码，得到长度为B的CRC编码后的编码块，其中CRC长度为Lcrc，信息块长度为K，B＝K+Lcrc。
CRC编码单元701对待发送的信息块进行CRC编码，得到K+Lcrc个CRC编码比特。CRC的生成多项式为[C 0,C 1,...,C n-K]，K为信息块长度，n＝K+Lcrc，CRC编码的一种原始生成矩阵是K*n的矩阵：
Figure PCTCN2018077853-appb-000019
通过高斯消元法，对上述生成矩阵简化为：G＝[I P]，I是K*K的单位矩阵，P是K*Lcrc的矩阵。矩阵G是K*n的矩阵，每一行的行号可以理解为对应信息块的一个比特的序号， 每一列的列号可以理解为对应CRC编码后输出的比特序号，CRC编码后的每个比特的值为该列中值为1的所有行对应的比特值相加。因此，矩阵P每一列对应CRC比特，每一列中1所在的行号对应的比特作为该CRC比特所校验的信息块的比特。以Lcrc＝4，K＝12为例，根据CRC-4的生成多项式[1 0 0 1 1]，计算生成矩阵G＝[I P]如表1所示。
这里对信息块进行一次CRC编码即可。
Figure PCTCN2018077853-appb-000020
表1 K＝12，CRC长度为4的CRC生成矩阵
序列[a1,a2,...,a12]表示信息块，[b1,b2,...b16]表示CRC编码后的编码块，其中b13,b14,b15,b16为CRC比特，从表中可以看出来，b13所在列的值为1对应的信息块的比特分别为a2,a3,a4,a5,a7,a9,a10，对应的CRC编码后的比特是b2,b3,b4,b5,b7,b9,b10,因此b13＝b2+b3+b4+b5+b7+b9+b10,校验方程为：b2+b3+b4+b5+b7+b9+b1+b13＝0，可以用序列[2,3,4,5,7,9,10,13]表示校验方程。同理，对于b14,b15,b16，根据表1可得校验方程分别表示为：[3,4,5,7,9,10,11,14],[4,5,6,7,9,11,12],和[1,2,3,4,6,8,9,12]。
不同的CRC长度，具有不同的CRC生成多项式；同一种CRC长度，也可以有多种不同的多项式。以下列举几种CRC长度和对应的生成多项式。
假设Lcrc长度为14，对应的CRC生成多项式包括：
[100111110011111]
[101000101010011]
[110111111011111]
[100000000101011]
[111010101110111]
[110100100101111]
[100111011010011]
[101010010011111]
[100011001000101]
[100011000111101]
[110011101010111]
[100000000000111]
[110111111111111]
[100100000000101]
[110111001010111]
[101111111110111]
[100001111010001]
[101000111011101]
[101010110011101]
[111110111011111]
[100001001011011]
[100011011100011]
[101110111111011]
假设Lcrc长度为15，对应的CRC生成多项式包括：
[1001111001000111]
[1011111111111111]
[1001111010100011]
[1011011010101111]
[1001011111110011]
[1001101001111001]
[1010100110101101]
[1000000000000011]
[1011010010001111]
[1000011000001101]
[1010111111001111]
[1110111101111111]
[1100111101001011]
[1100011000010111]
[1000000000101001]
[1011100110111101]
[1001001011101101]
[1001101011001011]
[1011011110101011]
[1101010100011011]
[1010111001110101]
[1100010110011001]
[1001000010111001]
[1110100000010101]
假设Lcrc长度为18，对应的CRC生成多项式包括：
[1000111001011110011]
[1000000000000100111]
[1000111000101111101]
[1011010000100111111]
[1000011011101010111]
[1010111110110101101]
[1011101110010010011]
[1001101010001111011]
[1010000111101110011]
[1000000000000110001]
[1001011111010100111]
[1011100111110111101]
[1001111011101111001]
[1100101100011010011]
[1110010101010100111]
[1001011111011010101]
假设Lcrc长度为19，对应的CRC生成多项式包括：
[11011111011010101111]
[10010000000100111111]
[10000001001101110101]
[11011010001001100111]
[10001011111000111001]
[11101010111001111111]
[10011110110101000101]
[10000000000000100111]
[10010111010110011001]
[11101111011000011111]
[10000000000000101001]
[10100011101011110011]
[10001001111011101011]
[10101101000010110101]
[10100001011010010011]
[11101111001110001111]
假设Lcrc长度为22，对应的CRC生成多项式包括：
[11000010001111110100111]
[11011011100100000000001]
[10100101001101010101001]
[11100100010101111010011]
[10011100101001101101011]
[11101111000011000101101]
[11111011111000101100011]
[10010111101111011111011]
[11011011100000100110001]
[11100010110000110100101]
[10000000000000000000011]
[10101011101101110100111]
[11011011110110001001111]
[10010010000111100101001]
[10000000000000010001111]
[11100101011011010100111]
[10101010010101001010101]
[10110111001110100100011]
[10100010011100111111101]
[10010001111011110001001]
[10001011101111101101111]
假设Lcrc长度为23，对应的CRC生成多项式包括：
[101010000001101111100001]
[100101101011000010110001]
[101101100111100101001001]
[110011100110001011100011]
[100011010110001101010111]
[100001010010111101100001]
[100001001001111001110111]
[101111001111011001000111]
[100000000000000000100001]
[100000000000001010101001]
[100000000000000000110111]
[100100110101101010100101]
[101001111011111011011101]
[100101101111001110100011]
[110101111000000111101011]
[101111000100100000110011]
[100011010011101011111001]
[100011000111011011101111]
假设Lcrc长度为26，对应的CRC生成多项式包括：
[110011110000011001111011111]
[111010011001101110010011111]
[100111111010110111101100111]
[101001000010100010111110101]
[110110010010101010110010111]
[111011011000010100011001111]
[111110100110010001001010111]
[101001010011110111100111101]
[101110100000001111101001111]
[101101100000111011100111111]
[111010010010111110010011111]
[100000000000000000001000111]
[110000011011111110011101011]
[100111100010110100100101011]
[100000000000000000000010011]
[100011101110110110000100101]
[110001000111101001101011011]
[100101000111110110011010111]
[100001100001101100001100001]
[101100010001010100010001101]
[101011110110001001001110111]
[100100100011010011101111101]
[101011111110111101100011111]
[110010110111101111011010011]
假设Lcrc长度为27，对应的CRC生成多项式包括：
[1011110000001000110001101011]
[1000100001010010110100001101]
[1000000000000000000000100111]
[1101001100001100011000100111]
[1110100010111101000101111111]
[1000000000000000000000100011]
[1101010011000010001101111111]
[1010001101011111111100110101]
[1100101101111010101000100111]
[1011000011010010101111000111]
[1101100001111111111000011011]
[1001100101101100101100011111]
[1010010000111110110010010111]
[1000010010110001100000011111]
[1000111010011111101010001111]
802、对CRC编码后的编码块进行交织，交织后的编码块中的Lpc个CRC比特位于信息块的比特之间，且Lpc个CRC比特中的每个CRC比特位于其所校验的所有比特之后。
交织单元702对CRC编码后的编码块进行交织，交织的结果使得其中有Lpc个CRC比特位于信息块的比特之间，且Lpc个CRC比特中的每个CRC比特位于其所校验的所有比特之后，Lpc为大于0小于Lcrc的整数。交织单元702可以所述对CRC编码后的编码块进行交织包括：采用交织序列π=[π 1,π 2,...,π n]对CRC编码后的编码块进行交织，将CRC编码后的比特序列[b1,b2,...,bn]变换为bπ 1,bπ 2,...,bπ n；其中n为大于0小于等于B的整数，π n的值表示交织后的编码块中的第n个比特在交织之前的编码块中的比特位置序号。如图9所示，交织后部分CRC比特分布于信息块的比特之间，且部分CRC比特中的每一个CRC比特校验其之前的信息块的比特，如图9中的箭头所示。
部分特殊CRC比特数量Lpc的设置，可以是大于0小于Lcrc中的任意整数。例如，Lcrc=27，则Lpc可以选1-26的任意数值，例如可以选8。例如Lcrc为22,23,14或15，Lpc为4。也可以规定为，如果Lcrc在某个范围之间，Lpc的值是固定的，例如Lcrc小于等于23的话，Lpc统一取为4。
如果考虑虚警概率(FAR)，则Lpc的值与CRC长度Lcrc、SCL译码后通过CRC辅助译码的路径数T、对虚警概率(false alarm rate,FAR)的要求有关。虚警概率指译码结果出错，但CRC校验通过的事件出现的概率。例如，Lpc的值可以参考以下公式（2）选取：
L pc≤L crc-log 2T+log 2FAR  （2）
公式（2）中，Lpc是部分CRC长度，Lcrc是CRC总长度，其中T是预先约定的在译码时需通过CRC校验而选择译码结果的候选路径数量。若候选路径有L个，则T为大于0小于等于L的整数。
通信系统中可能规定有虚警概率上限。举例而言，假设5G NR中的下行控制信道要求的虚警概率小于等于2 -16（不考虑盲检），Polar码的SCL译码后通过CRC进行辅助译码的路径数T为4，CRC长度Lcrc为24，则可用作奇偶校验的CRC比特的数量为Lpc≤(24-2-16)=6个；上行控制信道要求的虚警概率小于等于2 -8，Polar码的SCL译码后通过CRC进行辅助 译码的路径数T为8，CRC长度为Lcrc24，则可用作奇偶校验的CRC比特的数量为Lpc≤24-3-8＝13个。
在一个实施方式中，Lcrc和Lpc可以通过L pc＝L crc-log 2T+log 2FAR计算出固定的值，也就是Lcrc-Lpc＝log 2T-log 2FAR，例如，若FAR＝2 -16，T＝4，则Lcrc-Lpc＝18；若FAR＝2 -8，T＝4，则Lcrc-Lpc＝10；FAR＝2 -16，T＝8，则Lcrc-Lpc＝19；若FAR＝2 -8，T＝8，则Lcrc-Lpc＝11。当然，T和FAR取不同的值，(Lcrc-Lpc)的值也会不同。也可以根据(Lcrc-Lpc)的值设置不同的组合，并保存在编译码端。例如，当Lcrc-Lpc＝10时，Lpc和Lcrc可以为：Lpc＝1,Lcrc＝11；或者Lpc＝2,Lcrc＝12；或者Lpc＝4,Lcrc＝14；或者Lpc＝6,Lcrc＝16；或者Lpc＝8,Lcrc＝18。当Lcrc-Lpc＝18时，Lpc和Lcrc可以为Lpc＝1,Lcrc＝19；或Lpc＝2,Lcrc＝20；或Lpc＝4,Lcrc＝22；或Lpc＝6,Lcrc＝24；或Lpc＝8,Lcrc＝26。
CRC编码后的CRC比特位于通常位于编码块的最后位置，如表1所示，b13,b14,b15,b16位于b1,b2,...,b12的后面。在译码端等所有信息块和CRC比特译码结束之后，再进行CRC校验。为了使得部分CRC比特能在译码结束之前就能进行校验，可以通过交织改变信息块的比特和CRC比特的位置，使得部分CRC比特位于信息比特之间，并且所校验的信息块的比特也在该CRC比特之前。
交织可以采用交织序列π＝[π 1,π 2,...,π n]对CRC编码后的编码块[b1,b2,...bn]进行交织，其中π中每个元素的取值是CRC编码后的编码块的序号，表示交织后的编码块C＝[C 1,C 2,...,C n]＝[bπ 1,bπ 2,...,bπ n]。以表1所示的例子为例，交织序列可以为：π＝[2,3,4,5,7,9,10,13,8,6,11,14,12,1,15,16]，表示交织后的序列C＝[C 1,C 2,...,C 12]＝[b2,b3,b4,b5,b7,b9,b10, b13,b8,b6,b11, b14,b12,b1, b15, b16]，其中划线的比特是CRC比特，交织前后的比特对应关系如表二所示。可以看到，CRC比特b13被交织到了C8的位置，C8之前的b2,b3,b4,b5,b7,b9,b10是b13校验的所有比特，分别对应C1,C2,C3,C4,C5,C6,C7。b14被交织到了C12的位置，b3,b4,b5,b7,b9,b10,b11是b14校验的所有比特，分别对应交织后的C 2,C 3,C 4,C 5,C 6,C 7,C 9,C 10,C 11,也都位于b14之前。b15和b16的位置没有变动，但其所校验的比特位置发生了变动，b15校验的比特b4,b5,b6,b7,b9,b11,b12对应交织后的C 3,C 4,C 10,C 5,C 6,C 11,C 13。b16校验的比特b1,b2,b3,b4,b6,b8,b9,b12对应交织后的C 14,C 1,C 2,C 3,C 10,C 9,C 6,C 13。针对交织后的编码块的序号，校验方程分别更新为:
C 1+C 2+C 3+C 4+C 5+C 6+C 7+C 8＝0；
C 2+C 3+C 4+C 5+C 6+C 7+C 9+C 10+C 11+C 12＝0；
C 3+C 4+C 10+C 5+C 6+C 11+C 13+C 15＝0；
C 14+C 1+C 2+C 3+C 10+C 9+C 6+C 13+C 16＝0；
用序列表示的校验方程分别为：
[1,2,3,4,5,6,7,8]；[2,3,4,5,6,7,9,10,11,12]；[3,4,10,5,6,11,13,15]；[14,1,2,3,10,9,6,13,16]。
b2 b3 b4 b5 b7 b9 b10 b13 b8 b6 b11 b14 b12 b1 b15 b16
C 1 C 2 C 3 C 4 C 5 C 6 C 7 C 8 C 9 C 10 C 11 C 12 C 13 C 14 C 15 C 16
表2
表2的例子中，b13是移动到了其校验的所有比特之后中尽量靠前的位置，但并不限制 于此，例如b13也可以移动到靠后一些的位置，例如移动到b8之后。b14也是如此，也可以移动到b12之后。b13和b14称为特殊CRC比特，经过交织后他们分布于信息块的比特之间，并且其所校验的信息块的比特均在该特殊CRC比特之前。剩余的CRC比特b15和b16可不做特殊CRC比特，当做正常的CRC比特，用于CRC校验。由于CRC校验是在译码结束后用于挑选候选路径，那么交织过程中这两个CRC比特的位置位于最后，也可以移动到任何其他的位置。例如，可以采用交织序列π＝[2,3,15,4,5,16,7,9,10,8，13,6,11,14,12,1]，相比于表3所示的交织方式，b13移动到了b8之后，b15和b16也分布于信息块的比特之间。
b2 b3 b15 b4 b5 b16 b7 b9 b10 b8 b13 b6 b11 b14 b12 b1
C 1 C 2 C 3 C 4 C 5 C 6 C 7 C 8 C 9 C 10 C 11 C 12 C 13 C 14 C 15 C 16
表3
803、将交织后的编码块映射到信息比特，冻结比特设置为约定的固定值，对所述信息比特和所述冻结比特进行Polar编码，得到Polar编码码字。
Polar编码单元703将交织后的编码块映射到信息比特，冻结比特设置为约定的固定值，并对信息比特、冻结比特进行Arikan Polar编码，得到Polar编码的码字。编码得到的码字也可以叫做编码块、编码序列等。信息比特的位置对应Polar码的极化信道中按照可靠度高低排序后的前B个极化信道，剩余的(N-B)个极化信道对应的比特作为冻结比特，设置为约定的固定值，这里N是Polar码的母码长度。
如图10所示，本申请实施例构造的Polar码，信息块和CRC比特一起分布在最可靠的极化信道上，冻结比特分布在可靠度低于信息比特的极化信道上；经过交织后的编码块，映射到极化信道对应的信息比特位置后，CRC比特分布于信息块的比特之间。在译码的时候将部分CRC比特作为奇偶校验比特，可以提高在CA-SCL译码过程中删除错误路径的概率，另外剩余的CRC仍然可以用于CRC校验。由于特殊CRC比特的校验方程是通过CRC校验过程确定的，不需要单独设置校验方程。
步骤802中，交织序列可以是计算好后预先设置好，也可以在编码过程中实时计算。确定交织序列的方式有多种，下面举一些例子。
根据CRC的生成矩阵、CRC长度Lcrc、信息比特长度K和特俗CRC比特个数Lpc，计算交织序列π，过程可以包括如下：
(1)对CRC生成矩阵G＝[I P]进行初等行交换，得到G＝[I’P’]。
a)、通过行交换，使得P’的第1列的前p1行为1，之后所有元素为0；第2列的第(p 1+1)到第(p 1+p 2)行为1，之后所有元素为0；以此类推，第n-1列的(p 1+p 2...+p n-1+1)的行为1，之后所有元素为0。
b)、根据I’每一行的元素1的列序号，得到初始交织序列π 0。
(2)对P’插入Lpc行，得到P”。选择P’中的Lpc列对应特殊CRC比特，然后针对所有CRC比特对应的列按照以下方式逐列处理P’：
a)若第i列对应特殊CRC比特，在第i列最后一个元素1所在的行之后插入行，记录插入行号；插入的行的第i个元素为1，其余为0。
b)若第i列对应普通CRC比特，在任意行后插入一行，记录插入行号，插入的行的第i个元素为1，其余为0。
(3)读取P”。对P”中与特殊CRC比特的Lpc列，逐列读取元素1所在的行序号集合。对第i列，读取的集合为代表校验方程PCF i。
(4)根据步骤(2)中记录的插入行的行号，将序列π p＝[K+1,K+2,...,K+Lcrc]，依次插入初始交织序列π 0，获得最终的交织序列π＝[π 1,π 2,...,π n]，并得到最终的校验方程。
注意到，步骤(1)-(2)中对矩阵P的操作过程并不唯一，只需保证其中与特殊CRC比特对应的Lpc列的每一列，最后一个元素1位于步骤(2)中插入的行。
下面以CRC-4举例，介绍交织序列的一种生成过程。
(1)根据CRC-4的生成多项式[1 0 0 1 1]，对K＝12，计算生成矩阵G＝[I P]，如表1所示。对生成矩阵G进行行交换。根据第13列中元素1所在的行号将第2,3,4,5,7,9,10行交换到第1,2,3,4,5,6,7行，根据第14列中1所在的行号将11行交换到第10行；根据第15列中1所在的行号将第12行交换到第11行，最后得到G＝[I’P’]，如表4所示。根据G’左侧方阵I’，逐行读取元素1所在的列序号，得到初始交织序列π 0＝[2,3,4,5,7,9,10,8,6,11,12,1]，π 0表示对信息块的初始交织。
Figure PCTCN2018077853-appb-000021
表4
(2)对P’插入行，得到P”。插入行的元素1可与P′中该列最后一个元素1相邻，也可与P’中该列最后一个元素1间隔若干行。插入的行代表的是交织后CRC比特的位置，例如依次对矩阵P’在第8、12、14、16行插入行，插入的行号序列是[8,12,14,16]，如表5所示。
(3)将CRC比特[13,14,15,16]按照[8,12,14,16]的位置插入到初始交织序列，得到最终的交织序列π＝[2,3,4,5,7,9,10, 13,8,6,11, 14,12, 15,1, 16]。四个CRC比特的校验方程可依次表示为：[1,2,3,4,5,6,7,8]、[2,3,4,7,9,10,11,12]、[3,4,5,6,10，11,13,14]、[1,2,3,6,9,10,13,15,16]。
插入行的位置不做限定，可以在满足校验的信息块的比特在特殊CRC比特之前，尽量向前，对于普通CRC比特则插入位置是可以任意的。例如，还可以依次对矩阵P’在第9、 13、14、16行插入行，插入的行号序列是[9,13,14,16]，如表6所示。将CRC比特[13,14,15,16]按照[9,13,14,16]的位置插入到初始交织序列，得到最终的交织序列π＝[2,3,4,5,7,9,10,8, 13,6,11,12, 14, 15,1, 16]。四个CRC比特的校验方程可依次表示为：[1,2,3,4,5,6,7,9]、[2,3,4,7,8,10,11,13]、[3,4,5,6,10,11,13,14]、[1,2,3,6,9,10,13,15,16]。
Figure PCTCN2018077853-appb-000022
表5
Figure PCTCN2018077853-appb-000023
Figure PCTCN2018077853-appb-000024
表6
图11是本申请实施例提供的又一种编码方法的流程示意图，该方法可以由图7、图12或图13所示的编码装置执行。该方法包括：
1101：获取CRC长度Lcrc和CRC多项式，该步骤可以由图7的获取单元701、图12的处理器1202或图13的信号处理器1302执行。CRC长度Lcrc通常可以在通信系统的收发端中预先配置好。
1102：对信息块进行CRC编码。该步骤可以由图7的CRC编码单元701、图12的处理器1202或图13的信号处理器1302执行。
假设A＝K,B＝K+Lcrc，CRC编码的输入是序列a0,a1,a2,...,a A-1，CRC编码后生成的校验比特是p 0,p 1,...,p Lcrc-1，CRC编码后输出序列是b1,b2,...,b B-1。CRC编码得到的序列满足公式(3)。
Figure PCTCN2018077853-appb-000025
1103：获取交织序列π＝[π 1,π 2,...,π B]，交织序列可以是预先设置好的，也可以是根据CRC生成矩阵、信息块长度和CRC长度Lcrc计算得到。通过交织，可以使得Lpc个CRC比特位于信息块的比特之间，且其校验的信息比特位于该CRC比特之前。Lpc可以选取小于Lcrc的数量，也可以可以根据公式(2)确定的范围选择。Lpc根据预定的规则选好，可以配置在通信系统的收发端中。
1104：根据交织序列对CRC编码后输出序列是b1,b2,...,b B-1进行交织，得到交织后的序列C 0,C 1,..,C C-1，C＝B。C 0,C 1,C 2,...,C C-1序列的值对应bπ 1,bπ 2,...,bπ B。
1105：设置信息比特和冻结比特的值，得到d 0,d 1,d 2,d D-1，D＝N，N为Polar编码的母码长度。该步骤可以由图7的Polar编码单元703、图12的处理器1202或图13的信号处理器1302执行。设置信息比特和冻结比特的值根据公式(4)获得。
Figure PCTCN2018077853-appb-000026
1106：Arikan Polar编码，输出的编码序列为e 0,e 1,e 2,...,e E-1其中E＝N。Polar编码的计算过程可以由以下公式(5)表示。该步骤可以由图7的Polar编码单元703执行。
Figure PCTCN2018077853-appb-000027
可选的，该方法还可以包括步骤1105：对编码序列进行速率匹配，输出速率匹配后的编码序列F 0,F 1,F 2,...,F F-1，F＝M,M为目标码长。若目标码长M与母码长度N不相同，则对1105得到的编码序列进行速率匹配，例如通过重复、缩短或者打孔的方法进行速率匹配。当母码长度N小于目标码长M时，可以将编码序列重复(M-N)个比特，得到目标码长M的编码序列。若母码长度N大于目标码长M，可以通过打孔或者缩短(N-M)个比特，得 到目标码长M的编码序列，打孔或者缩短的的方案可以预先设置好。步骤2105可以由图7的编码装置中的速率匹配单元(图中未示出)、图11的处理器1102或图12的信号处理器1202执行。
如图12所示，本申请提供了另一种可以实施本申请的编码方法的编码装置1200。该编码装置1200包括：
存储器1201，用于存储程序；
处理器1202，用于执行所述存储器存储的所述程序，当所述程序被执行时，执行图8所示的编码方法。例如，该方法包括：对信息块进行CRC编码，得到长度为B的CRC编码后的编码块，其中CRC长度为Lcrc，信息块长度为K，B＝K+Lcrc；对CRC编码后的编码块进行交织，交织后的编码块中的Lpc个CRC比特位于信息块的比特之间，且Lpc个CRC比特中的每个CRC比特位于其所校验的所有比特之后，其中Lpc为大于0小于Lcrc的整数；将交织后的编码块映射到信息比特，冻结比特设置为约定的固定值，对所述信息比特和所述冻结比特进行Polar编码，得到Polar编码码字；其中所述信息比特的位置为可靠度最优的B个极化信道对应的位置；所述冻结比特的位置为剩下的N-B个极化信道对应的位置，N为Polar码母码长度。
有关特殊CRC比特的数量Lpc、交织序列及生成方式等内容可以参照前述的编码方法。存储器1201可以是物理上独立的单元，也可以与处理器1202集成在一起。涉及编码方法的其他内容，可以参见图8以及图8对应实施例相关部分，此处不再赘述。
图12的编码装置还可以进一步包括发送器(图中未示出)，用于发送处理器1102对所述信息比特和冻结比特进行Polar编码后得到的编码块。
如图13所示，本申请提供了另一种可以实施本申请的编码方法的编码装置1300。该编码装置1300包括：
至少一个输入端(inPut)1301，用于接收信息块；
信号处理器1302，用于对信息块进行CRC编码，得到长度为B的CRC编码后的编码块，其中CRC长度为Lcrc，信息块长度为K，B＝K+Lcrc；对CRC编码后的编码块进行交织，交织后的编码块中的Lpc个CRC比特位于信息块的比特之间，且Lpc个CRC比特中的每个CRC比特位于其所校验的所有比特之后，其中Lpc为大于0小于Lcrc的整数；将交织后的编码块映射到信息比特，冻结比特设置为约定的固定值，对所述信息比特和所述冻结比特进行Polar编码，得到Polar编码码字；其中所述信息比特的位置为可靠度最优的B个极化信道对应的位置；所述冻结比特的位置为剩下的N-B个极化信道对应的位置，N为Polar码母码长度；
至少一个输出端(outPut)1303，用于输出信号处理器1302得到的编码块。
有关特殊CRC比特的数量Lpc、交织序列及生成方式、等内容可以参照前述的编码方法。可选的，上述信号处理器1302可以是通过硬件实现的，例如，基带处理器，处理电路，编码器，或者编码电路。涉及编码方法的其他内容，可以参见图8以及图8对应实施例相 关部分，此处不再赘述。
图12的编码装置还可以进一步包括发送器(图中未示出)，用于发送输出端(outPut)1303输出的编码块。
本申请中的编码装置可以是任何具有无线通信功能的设备，例如接入点、站点、用户设备、基站等。
图14所示的译码装置1400可以用来执行本申请的译码方法。如图15所示，译码过程包括以下过程：
1501、获取待译码比特中信息比特和冻结比特的位置。
获取单元1401获取待译码比特中信息比特和冻结比特的位置，信息比特包括信息块的K个比特和Lcrc个CRC比特，其中，Lpc个CRC比特位于信息块的比特之间，且Lpc个CRC比特中的每个CRC比特位于其所校验的所有比特之后。获取单元1401可以根据极化信道的可靠度排序获取信息比特和冻结比特的位置，所述信息比特对应的极化信道的可靠度高于所述冻结比特对应的极化信道的可靠度。具体的，获取单元1401根据极化信道的可靠度排序，从中选择K+Lcrc个最可靠的作为信息比特，剩余的极化信道作为冻结比特，K是信息块的大小，Lcrc是CRC比特的个数。
1502、采用串行抵消列表SCL译码算法按顺序对待译码比特进行译码，输出度量值最优的L条候选路径。
译码单元1402采用串行抵消列表SCL译码算法按顺序对所述待译码比特进行译码，输出度量值最优的L条候选路径，其中，在译码过程中每条候选路径中的冻结比特的值设为约定的固定值，Lpc个CRC比特中的每个CRC比特的值根据位于该CRC比特之前的其所校验的信息块的比特的值确定，剩余的(Lcrc-Lpc)个CRC比特按照信息比特进行译码。
在SCL译码过程中，将CRC比特作为信息比特译码，是未知比特，在译码过程中需要进行路径扩展。由于在编码端，通过交织使得部分CRC比特的值是只由其前面的信息比特确定的，因此若该部分CRC比特作为奇偶校验比特，译码同冻结比特一样，作为已知比特进行译码，在译码过程中不进行路径扩展，只是该部分CRC比特译码结果用前面已经译码的信息比特和校验方程确定。冻结比特则不需要进行路径扩展，只要在译码过程中将对应的比特直接设置为约定的固定值。具体的译码过程参考图2和图3及其相应的描述。
1503、对L个候选路径中的度量值最优的T个候选路径进行解交织，T为大于0小于等于L的整数。
解交织单元1403对L个候选路径中的度量值最优的T个候选路径进行解交织，T为大于0小于等于L的整数。也就是说，解交织单元1403可以对全部的L个候选路径都进行解交织(T＝L)，也可以选择部分路径进行解交织(T<L)。在给定的Lrc，Lpc和虚警概率的上限下，T的数值可以参考公式(2)确定。
1504、对所述T个候选路径进行CRC校验。
CRC校验单元1404可以从度量值最优的候选路径开始，依次对T条候选路径进行CRC校验。CRC校验单元1404可以对所有T条候选路径都分别进行CRC校验，得出校验通过或者校验失败的结果。也可以得到第一个CRC校验通过的候选路径后，不再校验剩余的候 选路径。
1505、将通过CRC校验且路径度量最优的候选路径中的信息块作为译码输出。
输出单元1405选择将通过CRC校验且路径度量最优的候选路径，其中的信息比特对应的信息块作为本次译码的输出。若CRC校验单元1404是从度量值最优的候选路径开始进行CRC校验，则可以直接将CRC校验通过的第一个候选路径作为译码结果，输出其中的信息块。
步骤1501还可以包括获取校验方程。校验方程的确定可以通过CRC多项式和交织序列确定。CRC多项式确定的生成矩阵决定了各个CRC校验的信息比特，而交织序列可以确定每个CRC校验的信息比特在交织后的位置，从而得到交织后的校验方程。
图16是SCL译码算法List＝2的示例，在译码过程中保留2个候选路径。通常前面的几个比特是冻结比特，设置为固定的值，如0或者1。因此实际上从第一个信息比特开始译码。图16中，PM值的计算采用公式(1)计算，通过在每次扩展的时候保留PM值最小的路径，后得到如箭头所示的两条候选路径L1和L2。路径L1最终的PM值为0.3，另一条路径L2的PM值最终为0.2。从PM最小(度量值最优)的路径L2先进行CRC校验，若校验通过则选择L2作为译码输出。若L2路径校验不通过，继续校验L1路径，若校验通过，选择L1作为译码输出。若L1和L2均校验未通过，可以选择PM较小的(度量值最优)的L2路径作为译码结果输出。若L1和L2均校验未通过，也可以确认为本次译码失败。在译码过程中，List的取值可以不同，比如List＝8,16,32，或64等。
图16中标示的第i个比特是本申请所说的部分CRC比特(特殊CRC比特)，两个箭头1601表示该特殊CRC比特的值是由第i-3个比特(信息比特)确定。可以看到在译码第i个比特的时候，不需要进行路径扩展，第i个比特的值由该路径中第i-3个比特的值确定，因此路径L1中的特殊CRC比特的值是0，L2中的特殊CRC比特的值是1。图16和图3的区别在于，第i个比特在图3中对应的是冻结比特，而在图15中对应的是特殊CRC比特。图16中，PM值在译码到校特殊CRC比特的时候，PM值与图3相比发生了变化。具体的，图16中假设L1和L2路径的特殊CRC比特的LLR(i)小于0，假设LLR(i)小于0对应的值是1，L1路径中的i比特的译码结果0与LLR(i)的结果不一致，根据公式(1)PM值加|LLR(i)|，假设为0.3。L2路径中，i比特的译码结果1与LLR(i)对应的值一致，根据公式(1)，PM(i)＝PM(i-1)＝0.2。如果L1前面的译码有误，那么该特殊CRC比特i根据前面译码得到的结果确定，也可能是有误的，这样就会导致i比特的译码结果与LLR(i)对应的值不一致的概率增加，PM(i)就会加上惩罚值|LLR(i)|，导致该路径的PM值加大，在译码过程中该错误路径被删除的概率也加大，因为本例中PM值越小，表示所在的路径才是越优的，PM值越大，表示所在的路径越劣。
图17(a)是List＝8，K＝32时，本申请的方案与传统的CA-Polar在AWGN信道下的性能对比。图17(b)是K＝48时本申请的方案与传统的CA-Polar在AWGN信道下的性能对比。在传统的CA-Polar中，所有的CRC比特均用做CRC校验，进行纠错或者检错。本申请的方案则是将部分CRC比特交织到信息块之间的比特，并且所校验的信息块的比特均 在CRC比特之前，在译码的时候当做PC比译码特。在图17(a)和图17(b)中，实线所表示的性能曲线对应CRC长度27，其中的8比特交织并作为PC比特辅助SCL译码，剩余的CRC比特用于在SCL译码后挑选路径；虚线为CRC长度27，全部用于在SCL译码后挑选路径。可以看到，本申请方案相对CA-Polar，对K＝32的情况有超过0.4dB的性能增益，对K＝48的情况有超过0.1dB的增益。
如图18所示的译码装置1800也可以用于执行译码方法，该译码装置1800包括：
存储器1801，用于存储程序；
处理器1802，用于执行所述存储器存储的所述程序，当所述程序被执行时，执行图15所示的译码方法。该方法包括：获取待译码比特中信息比特和冻结比特的位置，信息比特包括信息块的K个比特和Lcrc个CRC比特，其中，Lpc个CRC比特位于信息块的比特之间，且Lpc个CRC比特中的每个CRC比特位于其所校验的所有比特之后，其中，其中Lpc为大于0小于Lcrc的整数；采用串行抵消列表SCL译码算法按顺序对待译码比特进行译码，输出度量值最优的L条候选路径，其中，在译码过程中每条候选路径中的冻结比特的值设为约定的固定值，Lpc个CRC比特中的每个CRC比特的值根据位于该CRC比特之前的其所校验的信息块的比特的值确定，剩余的(Lcrc-Lpc)个CRC比特按照信息比特进行译码；对L个候选路径中的度量值最优的T个候选路径进行解交织，T为大于0小于等于L的整数；对所述T个候选路径进行CRC校验，将通过CRC校验且路径度量最优的候选路径中的信息块作为译码输出。
若T条候选路径的CRC校验均未通过，可以选择度量值最优的路径作为译码输出，也可以确认为译码失败。
有关特殊CRC比特的数量Lpc、交织序列及生成方式、CRC校验数量等内容可以参照前述的编码方法和译码方法的实施例。存储器1801可以是物理上独立的单元，也可以与处理器1802集成在一起。
图18的译码装置还可以进一步包括接收器(图中未示出)，用于接收待译码的比特信息。
如图19所示，本申请提供了另一种可以实施本申请的编码方法的译码装置1900。该译码装置1900包括：
至少一个输入端(input)1901，用于接收待译码比特信息；
信号处理器1902，用于获取待译码比特中信息比特和冻结比特的位置，信息比特包括信息块的K个比特和Lcrc个CRC比特，其中，Lpc个CRC比特位于信息块的比特之间，且Lpc个CRC比特中的每个CRC比特位于其所校验的所有比特之后，其中，Lpc为大于0小于Lcrc的整数；采用串行抵消列表SCL译码算法按顺序对待译码比特进行译码，输出度量值最优的L条候选路径，其中，在译码过程中每条候选路径中的冻结比特的值设为约定的固定值，Lpc个CRC比特中的每个CRC比特的值根据位于该CRC比特之前的其所校验的信息块的比特的值确定，剩余的(Lcrc-Lpc)个CRC比特按照信息比特进行译码；对L个候选路径中的度量值最优的T个候选路径进行解交织，T为大于0小于等于L的整数； 对所述T个候选路径进行CRC校验；
至少一个输出端(output)1903，用于将CRC校验通过的第一个候选路径中的信息块作为译码输出。
有关特殊CRC比特的数量Lpc、交织序列及生成方式、CRC校验数量等内容可以参照前述的编码方法和译码方法的实施例。
可选的，上述信号处理器1902可以是通过硬件实现的，例如，基带处理器，处理电路，解码器，或者解码电路。
图19的译码装置还可以进一步包括接收器(图中未示出)，用于接收待译码的比特信息。
本申请实施例的译码装置可以是任何具有无线通信功能的设备，例如接入点、站点、用户设备、基站等。
本申请实施例所说的信息块，指的是待发送的信息比特(information bits)，也可以叫做信息比特序列(Information bit sequence)、待编码比特序列(to-be-coded bit sequence)、数据块(data block)、数据比特(data bits)、信息比特集合(information bit set)、信息比特向量(information bit vector)等。相应的，信息块长度可以叫做信息块大小，指的是信息比特序列中的比特个数、待编码比特序列中待编码比特的个数、数据块中的比特个数、数据比特个数或信息比特集合中的元素个数。本申请实施例所说的编码块(coded block)，也可以称作编码比特(coded bits)、编码比特序列(coded bit sequence)等。
本申请实施例所说的串行抵消列表SCL译码算法，包括其他按顺序译码、提供多条候选路径的类似SCL的译码算法或者对SCL译码算法的改进算法。
本申请实施例所说的编码装置或译码装置，在实际使用中可能是分别独立的设备；也可能是集成在一起的设备，用于待发送信息进行编码后发送，或者对接收到的信息进行译码。
本申请实施例描述的各示例的单元及方法过程，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能。
在本申请所提供的几个实施例中，应该理解到，所揭露的装置和方法，可以通过其它的方式实现。以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。例如多个单元或组件可以结合或者可以集成到另一个系统。方法中的一些步骤可以忽略，或不执行。此外，各个单元相互之间的耦合或直接耦合或通信连接可以是通过一些接口实现，这些接口可以是电性、机械或其它的形式。
作为分离部件说明的单元可以是或者也可以不是物理上分开的，既可以位于一个地方，也可以分布到多个网络单元上。另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。 当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本发明实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者通过所述计算机可读存储介质进行传输。所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心、等数据存储设备。所述可用介质可以是磁性介质，(例如，软盘、硬盘、磁带、U盘、ROM、RAM等)、光介质(例如，CD、DVD等)、或者半导体介质(例如固态硬盘Solid State Disk(SSD))等。
以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，
并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (34)

  1. 一种Polar编码方法，其特征在于，包括：
    对信息块进行循环冗余校验CRC编码，得到长度为B的CRC编码后的编码块，其中CRC长度为Lcrc，信息块长度为K，B＝K+Lcrc；
    对CRC编码后的编码块进行交织，交织后的编码块中的Lpc个CRC比特位于信息块的比特之间，且Lpc个CRC比特中的每个CRC比特位于其所校验的所有比特之后，其中Lpc为大于0小于Lcrc的整数；
    将交织后的编码块映射到信息比特，冻结比特设置为约定的固定值，对所述信息比特和所述冻结比特进行Polar编码，得到Polar编码码字；其中所述信息比特的位置为可靠度最优的B个极化信道对应的位置；所述冻结比特的位置为剩下的N-B个极化信道对应的位置，N为Polar码母码长度。
  2. 根据权利要求1所述的方法，其特征在于，所述对CRC编码后的编码块进行交织包括：采用交织序列π＝[π 1,π 2,...,π n]对CRC编码后的编码块进行交织，将CRC编码后的比特序列[b1,b2,...,bn]变换为bπ 1,bπ 2,...,bπ n；其中n为大于0小于等于B的整数，π n的值表示交织后的编码块中的第n个比特在交织之前的编码块中的比特位置序号。
  3. 根据权利要求1或2所述的方法，其特征在于，Lpc满足以下条件：L pc≤L crc-log 2T+log 2FAR，
    其中T是预先约定的在译码时需通过CRC校验而选择译码结果的候选路径数量，FAR是通信系统规定的虚警概率上限。
  4. 根据权利要求1-3任意一项所述的方法，其特征在于，Lcrc和Lpc满足以下关系：Lcrc-Lpc＝10；或者Lcrc-Lpc＝18。
  5. 根据权利要求1-4任意一项所述的方法，其特征在于，Lpc＝1,Lcrc＝11；或者Lpc＝2,Lcrc＝12；或者Lpc＝4,Lcrc＝14；或者Lpc＝6,Lcrc＝16；或者Lpc＝8,Lcrc＝18。
  6. 根据权利要求1-4任意一项所述的方法，其特征在于，Lpc＝1,Lcrc＝19；或Lpc＝2,Lcrc＝20；或Lpc＝4,Lcrc＝22；或Lpc＝6,Lcrc＝24；或Lpc＝8,Lcrc＝26。
  7. 一种编码装置，其特征在于，包括：
    CRC编码单元，用于对信息块进行循环冗余校验CRC编码，得到长度为B的CRC编码后的编码块，其中CRC长度为Lcrc，信息块长度为K，B＝K+Lcrc；
    交织单元，对CRC编码后的编码块进行交织，交织后的编码块中的Lpc个CRC比特位于信息块的比特之间，且Lpc个CRC比特中的每个CRC比特位于其所校验的所有比特之后，其中Lpc为大于0小于Lcrc的整数；
    Polar编码单元，用于将所述交织单元交织后的编码块映射到信息比特，冻结比特设置为约定的固定值，对所述信息比特和所述冻结比特进行Polar编码，得到Polar编码码字；其中，所述信息比特的位置为可靠度最优的B个极化信道对应的位置；所述冻结比特的位置为剩下的N-B个极化信道对应的位置，N为Polar码母码长度。
  8. 根据权利要求7所述的装置，其特征在于，所述交织单元采用交织序列π＝[π 1,π 2,...,π n]对CRC编码后的编码块进行交织，将CRC编码后的比特序列[b1,b2,...,bn]变换为bπ 1,bπ 2,...,bπ n；其中n为大于0小于等于B的整数，π n的值表示交织后的编码块中的第n个比 特在交织之前的编码块中的比特位置序号。
  9. 根据权利要求7或8所述的装置，Lpc满足以下条件：L pc≤L crc-log 2T+log 2FAR，
    其中T是预先约定的在译码时需通过CRC校验而选择译码结果的候选路径数量，FAR是通信系统对虚警概率的上限。
  10. 根据权利要求7-9任意一项所述的装置，其特征在于，Lcrc和Lpc满足以下关系：Lcrc-Lpc＝10；或者Lcrc-Lpc＝18。
  11. 根据权利要求7-10任意一项所述的装置，其特征在于，Lpc＝1,Lcrc＝11；或者Lpc＝2,Lcrc＝12；或者Lpc＝4,Lcrc＝14；或者Lpc＝6,Lcrc＝16；或者Lpc＝8,Lcrc＝18。
  12. 根据权利要求7-10任意一项所述的装置，其特征在于，Lpc＝1,Lcrc＝19；或Lpc＝2,Lcrc＝20；或Lpc＝4,Lcrc＝22；或Lpc＝6,Lcrc＝24；或Lpc＝8,Lcrc＝26。
  13. 一种编码装置，其特征在于，包括：
    存储器，用于存储程序；
    处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，所述处理器用于对信息块进行循环冗余校验CRC编码，得到长度为B的CRC编码后的编码块，其中CRC长度为Lcrc，信息块长度为K，B＝K+Lcrc；对CRC编码后的编码块进行交织，交织后的编码块中的Lpc个CRC比特位于信息块的比特之间，且Lpc个CRC比特中的每个CRC比特位于其所校验的所有比特之后，其中Lpc为大于0小于Lcrc的整数；将交织后的编码块映射到信息比特，冻结比特设置为约定的固定值，对所述信息比特和所述冻结比特进行Polar编码，得到Polar编码码字；其中所述信息比特的位置为可靠度最优的B个极化信道对应的位置；所述冻结比特的位置为剩下的N-B个极化信道对应的位置，N为Polar码母码长度。
  14. 根据权利要求13所述的装置，Lpc满足以下条件：L pc≤L crc-log 2T+log 2FAR，
    其中T是预先约定的在译码时需通过CRC校验而选择译码结果的候选路径数量，FAR是通信系统规定的虚警概率上限。
  15. 根据权利要求13-14任意一项所述的装置，其特征在于，Lcrc和Lpc满足以下关系：Lcrc-Lpc＝10；或者Lcrc-Lpc＝18。
  16. 根据权利要求13-15任意一项所述的装置，其特征在于，Lpc＝1,Lcrc＝11；或者Lpc＝2,Lcrc＝12；或者Lpc＝4,Lcrc＝14；或者Lpc＝6,Lcrc＝16；或者Lpc＝8,Lcrc＝18。
  17. 根据权利要求13-15任意一项所述的装置，其特征在于，Lpc＝1,Lcrc＝19；或Lpc＝2,Lcrc＝20；或Lpc＝4,Lcrc＝22；或Lpc＝6,Lcrc＝24；或Lpc＝8,Lcrc＝26。
  18. 一种编码装置，其特征在于，包括：
    至少一个输入端，用于接收信息块；
    信号处理器，用于对所述信息块进行循环冗余校验CRC编码，得到长度为B的CRC编码后的编码块，其中CRC长度为Lcrc，信息块长度为K，B＝K+Lcrc；对CRC编码后的编码块进行交织，交织后的编码块中的Lpc个CRC比特位于信息块的比特之间，且Lpc个CRC比特中的每个CRC比特位于其所校验的所有比特之后，其中Lpc为大于0小于Lcrc的整数；将交织后的编码块映射到信息比特，冻结比特设置为约定的固定值，对所述信息比特和所述冻结比特进行Polar编码，得到Polar编码码字；其中所述信息比特的位置为可 靠度最优的B个极化信道对应的位置；所述冻结比特的位置为剩下的N-B个极化信道对应的位置，N为Polar码母码长度；
    至少一个输出端，用于输出信号处理器得到的Polar编码码字。
  19. 根据权利要求18所述的装置，其特征在于，Lpc满足以下条件：
    L pc≤L crc-log 2T+log 2FAR，
    其中T是预先约定的在译码时需通过CRC校验而选择译码结果的候选路径数量，FAR是通信系统规定的虚警概率上限。
  20. 根据权利要求18-19任意一项所述的装置，其特征在于，Lcrc和Lpc满足以下关系：Lcrc-Lpc＝10；或者Lcrc-Lpc＝18。
  21. 根据权利要求18-20任意一项所述的装置，其特征在于，Lpc＝1,Lcrc＝11；或者Lpc＝2,Lcrc＝12；或者Lpc＝4,Lcrc＝14；或者Lpc＝6,Lcrc＝16；或者Lpc＝8,Lcrc＝18。
  22. 根据权利要求18-20任意一项所述的装置，其特征在于，Lpc＝1,Lcrc＝19；或Lpc＝2,Lcrc＝20；或Lpc＝4,Lcrc＝22；或Lpc＝6,Lcrc＝24；或Lpc＝8,Lcrc＝26。
  23. 一种Polar译码方法，其特征在于，包括：
    获取待译码比特中信息比特和冻结比特的位置，信息比特包括信息块的K个比特和Lcrc个循环冗余校验CRC比特，其中，Lpc个CRC比特位于信息块的比特之间，且Lpc个CRC比特中的每个CRC比特位于其所校验的所有比特之后，其中，其中Lpc为大于0小于Lcrc的整数；
    采用串行抵消列表SCL译码算法按顺序对待译码比特进行译码，输出度量值最优的L条候选路径，其中，在译码过程中每条候选路径中的冻结比特的值设为约定的固定值，Lpc个CRC比特中的每个CRC比特的值根据位于该CRC比特之前的其所校验的信息块的比特的值确定，剩余的(Lcrc-Lpc)个CRC比特按照信息比特进行译码；
    对L个候选路径中的度量值最优的T个候选路径进行解交织，T为大于0小于等于L的整数；
    对所述T个候选路径进行CRC校验，将通过CRC校验且路径度量最优的候选路径中的信息块作为译码输出。
  24. 根据权利要求23所述的方法，其特征在于，Lpc、Lcrc、T以及通信系统规定的虚警概率上限FAR满足以下关系：L pc≤L crc-log 2T+log 2FAR。
  25. 根据权利要求23-24任意一项所述的方法，其特征在于，Lcrc和Lpc满足以下关系：Lcrc-Lpc＝10；或者Lcrc-Lpc＝18。
  26. 一种译码装置，其特征在于，包括：
    获取单元，用于获取待译码比特中信息比特和冻结比特的位置，信息比特包括信息块的K个比特和Lcrc个循环冗余校验CRC比特，其中，Lpc个CRC比特位于信息块的比特之间，且Lpc个CRC比特中的每个CRC比特位于其所校验的所有比特之后，其中，Lpc为大于0小于Lcrc的整数；
    译码单元，采用串行抵消列表SCL译码算法按顺序对待译码比特进行译码，输出度量值最优的L条候选路径，其中，在译码过程中每条候选路径中的冻结比特的值设为约定的固定值，Lpc个CRC比特中的每个CRC比特的值根据位于该CRC比特之前的其所校验的 信息块的比特的值确定，剩余的(Lcrc-Lpc)个CRC比特按照信息比特进行译码；
    交织单元，对L个候选路径中的度量值最优的T个候选路径进行解交织，T为大于0小于等于L的整数；
    CRC校验单元，用于对所述T个候选路径进行CRC校验；
    输出单元，用于将通过CRC校验且路径度量最优的候选路径中的信息块作为译码输出。
  27. 根据权利要求26所述的装置，其特征在于，Lpc，Lcrc，T以及通信系统规定的虚警概率上限FAR满足以下关系：L pc≤L crc-log 2T+log 2FAR。
  28. 根据权利要求25-26任意一项所述的装置，其特征在于，Lcrc和Lpc满足以下关系：Lcrc-Lpc＝10；或者Lcrc-Lpc＝18。
  29. 一种译码装置，其特征在于，包括：
    存储器，用于存储程序；
    处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，获取待译码比特中信息比特和冻结比特的位置，信息比特包括信息块的K个比特和Lcrc个循环冗余校验CRC比特，其中，Lpc个CRC比特位于信息块的比特之间，且Lpc个CRC比特中的每个CRC比特位于其所校验的所有比特之后，其中，Lpc为大于0小于Lcrc的整数；采用串行抵消列表SCL译码算法按顺序对待译码比特进行译码，输出度量值最优的L条候选路径，其中，在译码过程中每条候选路径中的冻结比特的值设为约定的固定值，Lpc个CRC比特中的每个CRC比特的值根据位于该CRC比特之前的其所校验的信息块的比特的值确定，剩余的(Lcrc-Lpc)个CRC比特按照信息比特进行译码；对L个候选路径中的度量值最优的T个候选路径进行解交织，T为大于0小于等于L的整数；对所述T个候选路径进行CRC校验，将通过CRC校验且路径度量最优的候选路径中的信息块作为译码输出。
  30. 根据权利要求29所述的装置，其特征在于，Lpc，Lcrc，T以及通信系统规定的虚警概率上限FAR满足以下关系：L pc≤L crc-log 2T+log 2FAR。
  31. 根据权利要求29-30任意一项所述的装置，其特征在于，Lcrc和Lpc满足以下关系：Lcrc-Lpc＝10；或者Lcrc-Lpc＝18。
  32. 一种译码装置，其特征在于，包括：
    至少一个输入端，用于接收待译码比特信息；
    信号处理器，用于获取待译码比特中信息比特和冻结比特的位置，信息比特包括信息块的K个比特和Lcrc个循环冗余校验CRC比特，其中，Lpc个CRC比特位于信息块的比特之间，且Lpc个CRC比特中的每个CRC比特位于其所校验的所有比特之后，其中，Lpc为大于0小于Lcrc的整数；采用串行抵消列表SCL译码算法按顺序对待译码比特进行译码，输出度量值最优的L条候选路径，其中，在译码过程中每条候选路径中的冻结比特的值设为约定的固定值，Lpc个CRC比特中的每个CRC比特的值根据位于该CRC比特之前的其所校验的信息块的比特的值确定，剩余的(Lcrc-Lpc)个CRC比特按照信息比特进行译码；对L个候选路径中的度量值最优的T个候选路径进行解交织，T为大于0小于等于L的整数；对所述T个候选路径进行CRC校验；
    至少一个输出端，用于将通过CRC校验且路径度量最优的候选路径中的信息块作为译码输出。
  33. 根据权利要求32所述的装置，其特征在于，Lpc，Lcrc，T以及通信系统规定的虚警概率上限FAR满足以下关系：L pc≤L crc-log 2T+log 2FAR。
  34. 根据权利要求31-33任意一项所述的装置，其特征在于，Lcrc和Lpc满足以下关系：Lcrc-Lpc＝10；或者Lcrc-Lpc＝18。
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