WO2018148864A1 - Procédé et dispositif de synchronisation d'horloge - Google Patents

Procédé et dispositif de synchronisation d'horloge Download PDF

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Publication number
WO2018148864A1
WO2018148864A1 PCT/CN2017/073474 CN2017073474W WO2018148864A1 WO 2018148864 A1 WO2018148864 A1 WO 2018148864A1 CN 2017073474 W CN2017073474 W CN 2017073474W WO 2018148864 A1 WO2018148864 A1 WO 2018148864A1
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WO
WIPO (PCT)
Prior art keywords
signal
sequence code
clock
transmitting
receiving end
Prior art date
Application number
PCT/CN2017/073474
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English (en)
Chinese (zh)
Inventor
方李明
张晓风
隋猛
周雷
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2017/073474 priority Critical patent/WO2018148864A1/fr
Priority to CN201780059077.8A priority patent/CN109792376B/zh
Publication of WO2018148864A1 publication Critical patent/WO2018148864A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W56/00—Synchronisation arrangements

Definitions

  • the present application relates to the field of communications technologies, and in particular, to a clock synchronization method and device.
  • FIG. 4 is a schematic structural diagram of a medium centralized modulation system according to an embodiment of the present application.
  • the demodulation unit is specifically configured to:
  • the first sequence code is a sequence code in a preset codeword set, the preset sequence code set further includes at least one sequence code, and the first sequence code and the at least one sequence code Orthogonal to each other; each of the at least one sequence code is used to demodulate a data modulated signal;
  • the first sequence code can be ⁇ 1, 1, 1, 1 ⁇
  • the square wave signal is the periodic signal shown in FIG. 6(a)
  • the first sequence code in the square wave signal The distribution is shown in Figure 7(a).
  • the square wave signal is the data signal shown in Fig. 6(b)
  • the distribution of the first sequence code in the square wave signal is as shown in Fig. 7(b).
  • -1 indicates a low level
  • +1 indicates a high level
  • 2N indicates that the length of time between two hop edges may be twice the length of time at which the first sequence code is transmitted.
  • the transmitting end may send the transmitting signal including the signal carrying the clock to the receiving end through the channel between the transmitting end and the receiving end.
  • the receiving end can perform low-pass filtering processing on the received signal through the low-pass filter LPF, and filter out the DC component DC, and then phase through the phase-locked loop PLL or CDR circuit. Lock and convert to a certain clock frequency for output, thus obtaining a clock signal.
  • the receiving end may continuously accumulate the received signal or preset the sliding window accumulation processing, and perform low-pass filtering on the processed signal through the low-pass filter LPF. Processing, and filtering out the DC component DC, and then phase-locking through a phase-locked loop PLL or CDR circuit to obtain a clock signal.
  • FIG. 9 is a schematic diagram corresponding to the continuous accumulation processing, and the waveform of the signal obtained by the continuous accumulation processing can be as shown in FIG.
  • FIG. 10 is a schematic diagram corresponding to the preset sliding window accumulation processing, and the waveform of the signal obtained by the preset sliding window accumulation processing may be as shown in FIG. 12 .
  • the transmitting end transmits a signal for each of the at least one modulated data signal before transmitting the transmission signal to the receiving end through step 202,
  • the method further includes: step 2011-step 2012.
  • Step 2011 The transmitting end modulates the user data signal by driving the second serial code by the transmitting clock to obtain a signal of the modulated data.
  • the first sequence code is a sequence code in the preset codeword set, and the preset sequence code set further includes at least one sequence code, and the first sequence code and the at least one sequence code are orthogonal to each other.
  • Each of the at least one sequence code is used to modulate a user data signal, and the second sequence code is a sequence code in at least one of the sequence codes.
  • the transmitting end modulates the user data signal by driving the second serial code to generate a signal of the modulated data.
  • the transmitting end may separately divide the first sequence by using a preset sequence code set The other sequence codes other than the code respectively modulate the plurality of user data signals according to the above-described step 2011 to obtain signals of a plurality of modulated data, and one user data signal corresponds to one modulated data signal.
  • Step 2012 The transmitting end superimposes the signal carrying the clock and the signal of the at least one modulated data to obtain the transmitted signal.
  • the transmitting signal sent by the transmitting end further includes the signal of the at least one modulated data
  • the received signal received by the receiving end further includes at least one signal of the modulated data
  • the receiving end obtains the clock signal according to the above step 203
  • the method also includes: step 204.
  • Step 204 For each of the modulated data signals of the at least one modulated data signal, the receiving end demodulates the signal of the modulated data included in the received signal by the receiving clock driving the second serial code, and the signal of the modulated data after the demodulation Perform preset processing to obtain user data signals.
  • the device at the transmitting end obtains a signal carrying a clock by driving a first sequence code by sending a clock, where the first sequence code is a sequence code with the same symbol, and between two hop edges of the signal carrying the clock
  • the length of time is an integer multiple of the length of time in which the first sequence code is transmitted, and the length of time of each of the N symbols is equal.
  • the transmitting end modulates the user data by transmitting the clock to drive other serial codes orthogonal to the first sequence code, and superimposes the signal carrying the clock and the modulated data modulated signal, and then transmits the signal to the receiving end device through a channel.
  • the device at the receiving end After receiving the received signal, the device at the receiving end obtains a clock signal through preset processing, and demodulates the data modulated signal by driving the other corresponding sequence code through the receiving clock determined by the clock signal, thereby obtaining user data.
  • the problem that the service data is not interrupted in the transparent transmission system can be solved while providing a clock with higher precision.
  • each device such as a transmitting device and a receiving device, etc., in order to implement the above functions, includes hardware structures and/or software modules corresponding to the respective functions.
  • the present application can be implemented in a combination of hardware or hardware and computer software in conjunction with the network elements and algorithm steps of the various examples described in the embodiments disclosed herein. Whether a function is implemented in hardware or computer software to drive hardware depends on the specific application and design constraints of the solution. A person skilled in the art can use different methods to implement the described functions for each particular application, but such implementation should not be considered to be beyond the scope of the present application.
  • FIG. 14 is a schematic diagram showing a possible structure of a transmitting end device involved in the foregoing embodiment.
  • the transmitting end device 300 includes a modulating unit 301 and a transmitting unit 302.
  • the modulating unit 301 is configured to perform step 201 in FIG. 5 and FIG. 13 and step 2011 and step 2012 in FIG. 13;
  • the transmitting unit 302 is configured to perform step 202 in FIG. 5 and FIG. All the related content of the steps involved in the foregoing method embodiments may be referred to the functional description of the corresponding functional modules, and details are not described herein again.
  • the above modulation unit 301 can be a processor, and the sending unit 302 can be a transmitter, which can form a communication interface with the receiver.
  • the processor 312 can be a central processing unit, a general purpose processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, a transistor logic device, a hardware component, or any combination thereof. It is possible to implement or carry out the various illustrative logical blocks, modules and circuits described in connection with the present disclosure.
  • the processor may also be a combination of computing functions, for example, including one or more microprocessor combinations, combinations of digital signal processors and microprocessors, and the like.
  • the bus 314 can be a peripheral component interconnect standard (English: peripheral component interconnect, PCI for short) or an extended industry standard architecture (English: extended industry standard architecture, EISA) bus.
  • the bus can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, only one thick line is shown in Figure 15, but it does not mean that there is only one bus or one type of bus.
  • FIG. 16 is a schematic diagram showing a possible structure of the receiving end device involved in the foregoing embodiment.
  • the receiving end device 400 includes: a receiving unit 401 and a demodulating unit 402. .
  • the receiving unit 401 is configured to perform the process of receiving the signal sent by the transmitting end in FIG. 5 and FIG. 13;
  • the demodulating unit 402 is configured to perform step 203 in FIG. 5, FIG. 13, and step 204 in FIG. All the related content of the steps involved in the foregoing method embodiments may be referred to the functional description of the corresponding functional modules, and details are not described herein again.
  • FIG. 17 is a schematic diagram showing a possible logical structure of the receiving end device 410 involved in the foregoing embodiment provided by the embodiment of the present application.
  • the receiving end device 410 includes a processor 412, a communication interface 413, a memory 411, and a bus 414.
  • the processor 412, the communication interface 413, and the memory 411 are connected to one another via a bus 414.
  • the processor 412 is configured to perform control management on the action of the receiving device 410.
  • the processor 412 is configured to perform step 201 in FIG. 5 or FIG. 13 and step 2011 in FIG. 13 and Step 2012, and/or other processes for the techniques described herein.
  • Communication interface 413 is used to communicate with the transmitting device.
  • the memory 411 is configured to store program codes and data of the receiving end device 410.
  • the processor 412 can be a central processing unit, a general purpose processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, a transistor logic device, a hardware component, or any combination thereof. It is possible to implement or carry out the various illustrative logical blocks, modules and circuits described in connection with the present disclosure.
  • the processor may also be a combination of computing functions, for example, including one or more microprocessor combinations, combinations of digital signal processors and microprocessors, and the like.
  • the bus 414 may be a peripheral component interconnect standard (English: interconnected component: PCI) bus or an extended industry standard architecture (English: extended industry standard architecture, EISA) bus.
  • the bus can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, only one thick line is shown in Figure 17, but it does not mean that there is only one bus or one type of bus.
  • a computer readable storage medium having stored therein computer executed instructions, when the at least one processor of the device executes the computer to execute an instruction, the device executes the above figure 5.
  • a computer program product comprising computer executed instructions stored in a computer readable storage medium; at least one processor of the device may be The reading storage medium reads the computer execution instructions, and the at least one processor executes the computer execution instructions to cause the device to perform the steps of the transmitting end or the receiving end in the clock synchronization method shown in FIG. 5 or FIG.
  • a passive optical network system comprising a transmitting end device and a receiving end device.
  • the transmitting device is the transmitting device shown in FIG. 14 or FIG. 15, and/or the receiving device is the receiving device shown in FIG. 16 or FIG.
  • the transmitting end device is configured to perform the step of transmitting end in the clock synchronization method shown in FIG. 5 or FIG. 13; and the receiving end device is configured to perform the step of receiving end in the clock synchronization method shown in FIG. 5 or FIG. 13 .
  • the device at the transmitting end drives the first sequence code by using a sending clock to obtain a signal carrying a clock.
  • the first sequence code is a sequence code with the same symbol, and between two hop edges of the signal carrying the clock.
  • the length of time is an integer multiple of the length of time in which the first sequence code is transmitted, and the length of time of each of the N symbols is equal.
  • the transmitting end modulates the user data by transmitting the clock to drive other serial codes orthogonal to the first sequence code, and superimposes the signal carrying the clock and the modulated data modulated signal, and then transmits the signal to the receiving end device through a channel.
  • the device at the receiving end After receiving the received signal, the device at the receiving end obtains a clock signal through a preset process, and drives the other corresponding sequence code through the receiving clock determined by the clock signal to demodulate the modulated data signal, thereby obtaining user data.
  • the problem that the service data is not interrupted in the transparent transmission system can be solved while providing a clock with higher precision.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Mobile Radio Communication Systems (AREA)

Abstract

L'invention concerne un procédé et un dispositif de synchronisation d'horloge, qui se rapportent au domaine technique des communications et résolvent le problème des informations de données d'utilisateur qui sont interrompues lorsqu'un système CDMA existant met en œuvre une synchronisation d'horloge. Le procédé est appliqué à un système d'accès multiple par répartition en code, et comprend les étapes suivantes : commande, par une extrémité d'émission, d'un premier code de séquence au moyen de l'envoi d'une horloge de façon à obtenir un signal portant l'horloge, le signal portant l'horloge étant un signal d'onde carrée, le premier code de séquence comprenant N symboles, la durée entre deux fronts de transition quelconques du signal d'onde carrée étant un multiple entier de la durée pour envoyer le premier code de séquence, la durée de chaque symbole parmi les N symboles étant égale, N étant un nombre entier supérieur ou égal à 1, et lorsque N ≥ 2, les N symboles étant les mêmes ; et envoi, par l'extrémité d'émission, d'un signal d'émission à une extrémité de réception, le signal d'émission comprenant le signal portant l'horloge, et le signal portant l'horloge étant utilisé pour mettre en œuvre une synchronisation d'horloge entre l'extrémité de réception et l'extrémité d'émission.
PCT/CN2017/073474 2017-02-14 2017-02-14 Procédé et dispositif de synchronisation d'horloge WO2018148864A1 (fr)

Priority Applications (2)

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PCT/CN2017/073474 WO2018148864A1 (fr) 2017-02-14 2017-02-14 Procédé et dispositif de synchronisation d'horloge
CN201780059077.8A CN109792376B (zh) 2017-02-14 2017-02-14 一种时钟同步方法及设备

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PCT/CN2017/073474 WO2018148864A1 (fr) 2017-02-14 2017-02-14 Procédé et dispositif de synchronisation d'horloge

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CN114448594B (zh) * 2021-12-29 2023-08-08 苏州浪潮智能科技有限公司 一种通信频率同步方法及系统

Citations (4)

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US20020167991A1 (en) * 2001-05-08 2002-11-14 Mitsuhiro Suzuki Transmitter, receiver, transmitting method, and receiving method
CN1905037A (zh) * 1998-02-13 2007-01-31 索尼公司 记录设备、记录介质、播放设备、记录方法和播放方法
CN1943153A (zh) * 2005-02-09 2007-04-04 松下电器产业株式会社 脉冲调制无线通信装置
CN101710890A (zh) * 2009-12-15 2010-05-19 华东理工大学 脉冲和ofdm双重数据调制方法

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Publication number Priority date Publication date Assignee Title
TW306102B (fr) * 1993-06-14 1997-05-21 Ericsson Telefon Ab L M
DE69737670T2 (de) * 1996-03-05 2007-10-04 Ntt Docomo Inc. Signalübertragungsverfahren, sender und empfänger für ein mobiles kommunikationssystem
JP3856261B2 (ja) * 1998-03-18 2006-12-13 ソニー株式会社 同期検出装置
US7701978B2 (en) * 2003-04-09 2010-04-20 Braodcom Corporation Method and apparatus for maintaining synchronization in a communication system

Patent Citations (4)

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Publication number Priority date Publication date Assignee Title
CN1905037A (zh) * 1998-02-13 2007-01-31 索尼公司 记录设备、记录介质、播放设备、记录方法和播放方法
US20020167991A1 (en) * 2001-05-08 2002-11-14 Mitsuhiro Suzuki Transmitter, receiver, transmitting method, and receiving method
CN1943153A (zh) * 2005-02-09 2007-04-04 松下电器产业株式会社 脉冲调制无线通信装置
CN101710890A (zh) * 2009-12-15 2010-05-19 华东理工大学 脉冲和ofdm双重数据调制方法

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