WO2018143987A1 - Circuit frontal intégré à nitrure du groupe iii - Google Patents

Circuit frontal intégré à nitrure du groupe iii Download PDF

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Publication number
WO2018143987A1
WO2018143987A1 PCT/US2017/016162 US2017016162W WO2018143987A1 WO 2018143987 A1 WO2018143987 A1 WO 2018143987A1 US 2017016162 W US2017016162 W US 2017016162W WO 2018143987 A1 WO2018143987 A1 WO 2018143987A1
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iii
semiconductor substrate
layer
sti
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PCT/US2017/016162
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English (en)
Inventor
Han Wui Then
Sansaptak DASGUPTA
Marko Radosavljevic
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Intel Corporation
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Priority to PCT/US2017/016162 priority Critical patent/WO2018143987A1/fr
Priority to US16/475,220 priority patent/US11101380B2/en
Publication of WO2018143987A1 publication Critical patent/WO2018143987A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode

Definitions

  • FIG. 5 is a computing device built in accordance with an implementation of the present disclosure.
  • Wireless communication devices include an antenna to transmit and receive signals and an RF front-end circuit to process the signals.
  • RF front-end circuits include different functional blocks and each functional block may be on a different semiconductor substrate and may be implemented in different types of technology. Different functional blocks may be implemented in gallium arsenide (GaAs) heteroj unction bipolar transistor (HBT), GaAs high-electron-mobility transistor (HEMT), silicon (Si) bulk complementary-metal-oxide-semiconductor (CMOS), aluminum nitride (AIN) film bulk acoustic resonators (FBAR), or bulk acoustic ware (BAW).
  • GaAs gallium arsenide
  • HBT GaAs heteroj unction bipolar transistor
  • HEMT high-electron-mobility transistor
  • CMOS bulk complementary-metal-oxide-semiconductor
  • AIN aluminum nitride
  • FBAR film bulk acoustic resonators
  • the VR may be implemented in Si, the PA in GaAs, the LNA GaAs, and a switch in silicon on insulator (SOI).
  • SOI silicon on insulator
  • the present disclosure addresses the above-mentioned and other deficiencies by using a III-N integrated RF front-end circuit.
  • the III-N integrated RF front-end circuit includes two or more functional blocks of VR, PA, LNA, n-type metal-oxide-semiconductor logic (NMOS) logic, or a switch on the same semiconductor substrate. Each functional block on the same
  • semiconductor substrate includes a III-N structure on the semiconductor substrate.
  • the 5-10% power loss is avoided by providing the functional blocks on the same semiconductor substrate.
  • the III-N used in the integrated RF front-end circuit may be gallium nitride (GaN).
  • Each functional block may include one or more GaN transistors.
  • GaN transistors outperform GaAs and Si technology in VR, PA, LNA, and switch in terms of RF power output, RF power-added efficiency, transistor on-resistance (e.g., a built-in parameter of a component that represents the component's internal resistance when the component is in a fully conducting state), larger breakdown voltage, lower noise figure, smaller capacitance, and lower losses.
  • Filters may be integrated in the form of a multi-chip package with the monolithic III-N chip.
  • Monolithic integration of functional blocks with III-N technology offers reduction in form factor and reduces parasitic losses by removing the package interfaces between the discrete functional blocks (e.g., modules). Reducing the losses allows higher frequency bands (e.g., 5 th generation (5G) bands (3.5-6 gigahertz (GHz) and millimeter wave (e.g., 27-32 GHz)) to be deployed for high bandwidth wireless communications.
  • 5G 5 th generation
  • GHz gigahertz
  • millimeter wave e.g., 27-32 GHz
  • FIGS. 1A-C illustrate a wireless communication device 100 (e.g., an apparatus) including a III-N integrated RF front-end circuit 110, according to an implementation of the present disclosure.
  • a wireless communication device includes an application processor 102, a modem 104, and a transceiver 106, a III-N integrated RF front-end circuit 110, filters 122, an antenna 124, and a CMOS companion chip 126.
  • the application processor 102 may be coupled to the modem 104 and the modem may be coupled to the transceiver 106.
  • the transceiver 106 may be coupled to the III-N integrated RF front-end circuit 110.
  • the III-N integrated RF front-end circuit 110 is to be coupled to the antenna 124. In one implementation, the III-N integrated RF front-end circuit 110 is to be coupled to the CMOS companion chip 126. One or more filters 122 and the filters 122 may be coupled to antenna 124. The III-N integrated RF front-end circuit 110 is also coupled to the CMOS companion chip 126.
  • the CMOS companion chip 126 may be a silicon (Si) CMOS companion chip and may include memory and registers.
  • the III-N integrated RF front-end circuit 110 includes a semiconductor substrate 130, functional blocks, and an interface to be coupled to an antenna 124 (e.g., an interface to be coupled to filters 122 which is to be coupled to antenna 124).
  • Each of the functional blocks include a III-N structure on the semiconductor substrate 130 (see FIG. 2).
  • the functional blocks include two or more of VR 112, PA 114, LNA 116, switch 118 (e.g., a single pole switch, double pole switch), and NMOS logic 120.
  • the III-N structure includes a group III element (e.g., aluminum (Al), gallium (Ga), indium (In), etc.).
  • III-N e.g., GaN
  • two or more of the III-N structures on the semiconductor substrate 130 are different types of III-N (e.g., GaN structure and A1N structure).
  • VR 112, PA 114, LNA 116, and NMOS logic 120 are on semiconductor substrate 132 and switch 118 is on semiconductor substrate 134. At least each of VR 112, PA 114, LNA 116, and NMOS logic 120 include a III-N structure on the semiconductor substrate 132. In one implementation, switch 118 includes a III-N structure on the semiconductor substrate 134. At least one of the functional blocks on semiconductor substrate 132 is coupled to the switch 118 on semiconductor substrate 134. At least one of semiconductor substrate 132 or semiconductor substrate 134 is coupled to an interface to be coupled to the antenna 124.
  • a first set of functional blocks include PA 114 including a first III-N structure on the semiconductor substrate 132, LNA 116 including a second III-N structure on the semiconductor substrate 132, VR 112 including a third III-N structure on the semiconductor substrate 132, NMOS logic 120 including a fourth III-N structure on the semiconductor substrate 132.
  • Switch 118 may include a fifth III-N structure on the semiconductor substrate 134.
  • a first set of functional blocks include PA 114 including a first III-N structure on the semiconductor substrate 136 and LNA 116 including a second III-N structure on the semiconductor substrate 136.
  • the first set of functional blocks is coupled to a second set of functional blocks including VR 112 including a third III-N structure on the semiconductor substrate 138 and NMOS logic 120 including a fourth III-N structure on the semiconductor substrate 138.
  • the first set of functional blocks is coupled to a switch 118 including a fifth III-N structure on the semiconductor substrate 134.
  • one of VR 112, PA 114, LNA 116, switch 118, or NMOS logic 120 includes a corresponding III-N structure on a semiconductor substrate.
  • any two of VR 112, PA 114, LNA 116, switch 118, or NMOS logic 120 include a corresponding III-N structure on a common semiconductor substrate.
  • FIGS. 2A-R illustrate a fabrication process 200 for a semiconductor structure 201 (e.g., transistor) of an III-N integrated RF front-end circuit 110, according to an implementation of the present disclosure.
  • Fabrication process 200 includes semiconductor structure 201 at various stages of the fabrication process 200, according to one exemplary implementation. It may be noted that fabrication process 200 is shown for purposes of illustration, rather than limitation. Fabrication process 200 may be performed in any order, include any number of processes, and include more, the same, or fewer processes. It may also be noted that for purposes of illustration, rather than limitation, materials are illustrated in the various layers of fabrication process 200. Other materials, other or in addition to the materials illustrated in FIGS. 2A-R, may also be used in other implementations. FIGS.
  • semiconductor substrate 210 may be silicon on insulator (SOI). In one implementation, semiconductor substrate 210 is silicon. Crystallographic orientation of a substantially monocrystalline semiconductor substrate 210 may be any of (100), (111), or (110) on the Miller Indices. Other crystallographic orientations are also possible. The crystallographic orientations of semiconductor substrate 210 may be offcut. In one implementation, semiconductor substrate 210 is (100) silicon with crystalline semiconductor substrate surface region having cubic crystallinity. In another implementation, for a (100) silicon semiconductor substrate 210, the semiconductor surface may be miscut, or offcut, for example 2-10° toward [110]. In another implementation, semiconductor substrate 210 is (111) silicon with crystalline semiconductor substrate surface region having hexagonal crystallinity.
  • a buffer layer (not shown) may be disposed between the
  • An appropriate buffer layer may be disposed corresponding to the material type of semiconductor substrate 210.
  • FIG. 2B illustrates a cross section in the first plane of structure 201B.
  • Structure 201B illustrates cutting the semiconductor substrate 210.
  • the semiconductor substrate 210 may be fin cut.
  • the semiconductor substrate may be diffusion cut.
  • a first indentation 214a and a second indentation 214b may be cut in semiconductor substrate 210 to form a semiconductor substrate fin 216.
  • the semiconductor substrate fin 216 may have a width of 10 micrometers ( ⁇ ) and a height of 200 nanometers (nm).
  • FIG. 2E illustrates a cross section in the first plane of structure 201E.
  • Structure 201E illustrates forming a III-N structure 220 (e.g., III-N island, III-N discrete structure) on the semiconductor substrate 210, oxide 218a, and oxide 218b.
  • the III-N structure 220 may be grown on the semiconductor substrate 210 in a reactor.
  • the one or more III-N structures 220 are grown directly on the semiconductor substrate 210 in a reactor.
  • the III-N structure 220 may be separated by one or more shallow trench isolations (STI) 420 from other III- N structures 220 (see FIG. 4).
  • the III-N structure 220 may be selectively grown to 0.05 microns to about 10 microns.
  • STI shallow trench isolations
  • Structure 201E also illustrates forming a polarization layer 250 above the III-N structure 220 (e.g., above an upper surface and sidewalls of the III-N structure 220).
  • the polarization layer 250 may be 5 to 15 nm in height.
  • the polarization layer 250 may be a thin sheet of electron gas (e.g., two-dimension electron gas (2DEG) layer).
  • the polarization layer 250 may provide doping of the III-N structure 220.
  • an A1N layer 252 (1 nm height) may be formed on the III-N structure 220 and the polarization layer 250 (e.g., InAIN polarization layer) may be formed on the A1N layer 252.
  • the width of the III-N structure 220 between the oxide 218a and oxide 218b may be about 25 ⁇ .
  • the height of the III-N structure 220 from the upper surface of oxide 218a to the upper surface of the III-N structure 220 may be 2 ⁇ .
  • FIG. 2F illustrates a cross section in the first plane of structure 201F.
  • Structure 201F illustrates forming a mask 224 on the polarization layer 250 above a portion of the semiconductor substrate 210 between the oxide 218a and oxide 218b and removing portions of the III-N structure 220, A1N layer 252, and polarization layer 250 that are not under the mask 224 (e.g., fin or diffusion cut).
  • FIG. 2G illustrates a cross section in the first plane of structure 201G.
  • Structure 201G illustrates removing further portions of the III-N structure 220, A1N layer 252, and polarization layer 250 that are not under the mask 224 to be substantially the same height as the oxide 218a (e.g., 200 nm).
  • the mask 224 is removed and a planarization oxide 228 is formed on the first oxide 218a, III-N structure 220, and the second oxide 218b (e.g., STI oxide fill and polish).
  • FIG. 2J illustrates a cross section in the second plane of structure 201J.
  • Structure 201J illustrates removing a first portion and a second portion of the III-N structure 220, polarization layer 250, and A1N layer 252, and forming (e.g., growing) a drain terminal 230 and a source terminal 240 on the III-N structure 220.
  • An inter-layer dielectric (ILD) 280 e.g., an oxide
  • ILD inter-layer dielectric
  • FIG. 2L illustrates a cross section in the second plane of structure 201L.
  • Structure 201L illustrates forming ILD 280 on the ILD 280 and the spacer 258 (e.g., spacer 258 on the spacer 256, spacer 258 on the sidewall of polysilicon column 270) (e.g., planarizing).
  • FIG. 2M illustrates a cross section in the second plane of structure 201M.
  • Structure 201M illustrates removing the second polysilicon column 270b, forming a mask 272a above the drain terminal 230 (e.g., on the first polysilicon column 270a, the spacer 258 on the sidewalls of the first polysilicon column 270a, and the ILD 280), and forming a mask 272b above the source terminal 240 (e.g., on the third polysilicon column 270c, the spacer 258 on the sidewalls of the third polysilicon column 270c, and the ILD 280).
  • the mask 272 may be a nitride or oxide mask
  • FIG. 2N illustrates a cross section in the second plane of structure 201N.
  • Structure 201N illustrates removing a portion of the ILD 280 and spacer 258 that is not blocked by mask 272a or mask 272b (e.g., the portion of the ILD 280 and spacer 258 between masks 272a and 272b, recess etching).
  • Structure 201N further illustrates removing a portion of spacer 258 and spacer 256 below where the second polysilicon column 270b was located (e.g., polarization layer 250 etch). A portion 251 of the polarization layer 250 below where the second polysilicon column 270b was located may be removed.
  • the portion 251 corresponding to a first transistor has a 1 nm thickness and a portion 251 corresponding to a second transistor has a 2 nm thickness, etc.).
  • the portion 251 is completely removed and the A1N layer 252 serves as an etch stop.
  • Different transistors of different thresholds e.g., different thicknesses of portion 251 of polarization layer 250 may be integrated in a III-N integrated RF front-end circuit 110.
  • FIG. 2Q illustrates a cross section in the second plane of structure 201Q.
  • Structure 201Q illustrates removing the first polysilicon column 270a, spacer 258 surrounding the first polysilicon column 270a, ILD 280 below the first polysilicon column 270a and surrounding spacer 258, and a portion of the drain terminal 230 below the first polysilicon column 270a and surrounding spacer 258.
  • Structure 201Q further illustrates forming a trench contact 232 on the drain terminal 230 where the first polysilicon column 270a and surrounding spacer 258 and ILD 280 were removed.
  • Structure 201Q further illustrates removing the third polysilicon column 270c, spacer 258 surrounding the third polysilicon column 270c, ILD 280 below the third polysilicon column 270c and surrounding spacer 258, and a portion of the source terminal 240 below the third polysilicon column 270c and surrounding spacer 258.
  • Structure 201Q further illustrates forming a trench contact 242 on the source terminal 240 where the third polysilicon column 270c and surrounding spacer 258 and ILD 280 were removed.
  • Trench contact 232 and trench contact 242 may be tungsten.
  • the inner sidewall of each of trench contact 232 and 242 may be 50 to 500 nm from the sidewall of the upper portion 264 of gate terminal 260.
  • Structure 201Q further illustrates forming ILD 282 on ILD 280, sidewalls of trench contact 232, sidewalls of trench contact 242, and on the sidewalls and upper surface of the upper portion 264 of the gate terminal 260.
  • FIG. 2R illustrates a cross-section in the second plane of structure 201R.
  • FIG. 2R may be a zoomed out view compared to the views shown in FIGS. 2H-Q.
  • Structure 201R is a transistor of the III-N integrated RF front-end circuit 110.
  • the components of the transistor may enable the integration of the functional blocks of the III-N integrated RF front-end circuit 110 on a single silicon chip (see FIGS. 1A-C and FIG. 4).
  • the structure 201R includes a first shallow trench isolation (STI) 212a and a second STI 212b on the semiconductor substrate 210.
  • STI 212a and STI 212b may be an oxide.
  • the structure 201R may include a first layer of III-N 222 on the semiconductor substrate 210 between the first STI 212a and the second STI 212b.
  • the III-N structure 220 is on the first layer of III-N 222.
  • the structure 201R includes a first spacer 256 on the
  • the structure 201R may include a second spacer 258 on the first spacer 256 and on the second portion of the high-k dielectric layer 254.
  • the structure 201R may include a first inter-layer dielectric (ILD) 280 on the first STI 212a, the second STI 212b, the III-N structure 220, the drain terminal 230, the source terminal 240, the first trench contact 232, first spacer 256, the second spacer 258, a lower surface of the upper portion 264 of the gate terminal 260, and the second trench contact 242.
  • the structure 201R may include a second ILD 282 on the first ILD 280, the first trench contact 232, sidewalls of the upper portion 264 of the gate terminal 260, and the second trench contact 242.
  • the semiconductor substrate is a silicon (Si) (111) structure. In another implementation, the semiconductor substrate is a Si (110) structure. In another implementation, the semiconductor substrate is a Si (100) structure. In some implementations, the first STI and the second STI are a first oxide.
  • the III-N structure 220 and first layer of III-N 222 are GaN. In another implementation, the III-N structure 220 and first layer of III-N 222 are A1N. In another implementation, the III-N structure 220 and first layer of III-N 222 are AlInN. In another implementation, the III-N structure 220 and first layer of III-N 222 are AlGaN.
  • the polarization layer 250 is AlInN. In another implementation, the polarization layer 250 is AlGaN. In another implementation, the polarization layer 250 includes AlInN and AlGaN (e.g., is a combination of AlInN and AlGaN).
  • the first spacer 256 is a silicon oxide and the second spacer 258 is a silicon nitride.
  • the first ILD 280 is an oxide.
  • the second ILD 282 may be an oxide different from the oxide of the first ILD 280.
  • the source terminal 240 may include indium gallium nitride (InGaN) and n-type doping.
  • the drain terminal 230 may include InGaN and n-type doping.
  • FIG. 3 illustrates a process flow for fabricating a transistor of a III-N integrated RF front- end circuit 110, according to another implementation. It may be noted that features of FIGS. 2A- R may be described below to help illustrate method 300. Method 300 may be performed as operations. It may be noted that method 300 may be performed in any order and may include the same, more, or fewer operations. It may be noted that method 300 may be performed by one or more pieces of semiconductor fabrication equipment or fabrication tools.
  • the method 300 may further include forming a first shallow trench isolation (STI) 212a and a second STI 212b on the semiconductor substrate 210, forming a first layer of III-N 222 on the semiconductor substrate 110 between the first STI 212a and the second STI 212b, where the III-N structure 220 is formed on the first layer of III-N 222.
  • Operation 310 may be further described with respect to structures 201A-E of FIGS. 2A-E.
  • a polarization layer 250 is formed above the III-N structure 220.
  • Operation 320 may be further described with respect to structures 201E-201N of FIGS. 2E-N.
  • operation 320 further includes forming an A1N layer 252 on the III-N structure 220 between the source terminal 240 and the drain terminal 230 (see FIGS. 2E-Q), where the polarization layer 250 is formed on the A1N layer 252.
  • a drain terminal 230 and a source terminal 240 are formed on the III-N structure 220.
  • the polarization layer 250 is between the drain terminal 230 and the source terminal 240.
  • Operation 330 may be further described with respect to structure 201J of FIG. 2J.
  • the method 300 may further include forming a first trench contact 232 on the drain terminal 230 and a second trench contact 242 on the source terminal 240 (see FIGS. 2K-Q).
  • Operation 340 may be further described with respect to structures 201O-201P of FIGS. 20-P.
  • the gate terminal 260 may include a lower portion 262 and an upper portion 264 (e.g., gate terminal may be a t- shape), A first portion of a high-k dielectric layer 254 may be formed on the lower surface of the lower portion 262 of the gate terminal 260 and a second portion of the high-k dielectric layer 254 may be formed on sidewalls of the lower portion 262 of the gate terminal 260 (see FIG. 20).
  • the polarization layer 250 is between the A1N layer 252 and the first portion of the high-k dielectric layer 254.
  • the method 300 may further include disposing a first spacer on the polarization layer and the second portion of the high-k dielectric layer (see FIGS. 2I-0) and disposing a second spacer on the first spacer and on the second portion of the high-k dielectric layer (see FIGS. 2I-0).
  • the method 300 may further include disposing a first inter-layer dielectric (ILD) 280 on the first STI 212a, the second STI 212b, the III-N structure 220, the drain terminal 230, the source terminal 240, the first trench contact 232, first spacer 256, the second spacer 258, a lower surface of the upper portion 264 of the gate terminal 260, and the second trench contact 242 (see FIGS. 2J-P).
  • the method 300 may further include disposing a second ILD 282 on the first ILD 280, the first trench contact 232, sidewalls of the upper portion 264 of the gate terminal 260, and the second trench contact 242 (see FIG. 2Q).
  • ILD inter-layer dielectric
  • FIG. 4 illustrates a III-N integrated RF front-end circuit 110 including functional blocks, according to an implementation of the present disclosure.
  • the III-N integrated RF front-end circuit 110 may include a semiconductor substrate 410 (e.g., semiconductor substrate 130 of FIG. 1A, semiconductor substrate 136 of FIG. 1C, semiconductor substrate 210 of FIGS. 2A-R, etc.) and two or more functional blocks (e.g., VR 112, PA 114, LNA 116, switch 118, NMOS logic 120).
  • Each of the functional blocks may include a III-N structure 220 on the semiconductor substrate 410.
  • the III-N integrated RF front-end circuit 110 may also include an interface to be coupled to an antenna.
  • the transistor width of NMOS logic 120 is about 0.05-0.5 microns.
  • the transistor width of LNA 116 is about 20 to 40 microns.
  • the transistor width of the PA 114 is about 500 microns to 1 millimeter (mm).
  • the transistor width of the switch 118 is about 1 to 2 mm.
  • the transistor width of the VR 112 is about 5 to 10 mm.
  • the PA 114 has source terminals 240 coupled to a ground node, gate terminals 260 coupled to an input node, and drain terminals coupled to an output node.
  • the NMOS logic 120 and LNA 116 may configured similar to the PA 114.
  • the switch 118 has gate terminals 260 coupled to a ground node, source terminals 240 coupled to an input node or an output node, and drain terminals 230 coupled to the input node or the output node (e.g., opposite to which the source terminals 240 are coupled).
  • FIG. 5 is a computing device built in accordance with an implementation of the present disclosure.
  • the computing device 500 may include a number of components. In one
  • the components are attached to one or more motherboards. In an alternate implementation, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die, such as an SoC used for mobile devices.
  • SoC system-on-a-chip
  • the components in the computing device 500 include, but are not limited to, an integrated circuit die 502 and at least one communications logic unit 508.
  • the communications logic unit 508 is fabricated within the integrated circuit die 502 while in other implementations the communications logic unit 508 is fabricated in a separate integrated circuit chip that may be bonded to a substrate or motherboard that is shared with or electronically coupled to the integrated circuit die 502.
  • integrated circuit die 502 may be LED display with multiple monolithic multi-color LED pixels 505A (or multiple LEDs 505B) and a TFT backplane, with or without processor 504 and/or on-die memory 506.
  • integrated circuit die 502 may include some or all the elements described herein, as well as include additional elements.
  • the communications logic unit 508 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Infrared (IR), Near Field Communication (NFC), Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the computing device 500 may include a plurality of communications logic units 508.
  • a first communications logic unit 508 may be dedicated to shorter range wireless communications such as Wi-Fi, NFC, and Bluetooth and a second communications logic unit 508 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • the processor 504 (also referred to "processing device” herein) of the computing device 500 includes one or more devices, such as transistors, RF filters, or LEDs, that are formed in accordance with implementations of the present disclosure.
  • the term "processor” or “processing device” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • Processor 504 represents one or more general-purpose processing devices such as a microprocessor, a central processing unit, or the like. More particularly, the processor 504 may be complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW)
  • Processor 504 may also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like.
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • DSP digital signal processor
  • the communications logic unit 508 may also include one or more devices, such as transistors, RF filters, or LEDs, that are formed in accordance with implementations of the present disclosure.
  • Example 2 the apparatus of Example 1, wherein the plurality of functional blocks comprises: a power amplifier (PA) comprising a first III-N structure on the semiconductor substrate; and a low-noise amplifier (LNA) comprising a second III-N structure on the semiconductor substrate.
  • PA power amplifier
  • LNA low-noise amplifier
  • Example 4 the apparatus of any one of Examples 1-3, wherein the plurality of functional blocks further comprises a switch comprising a fifth III-N structure on the
  • Example 6 the apparatus of any one of Examples 1-5, wherein the plurality of functional blocks is coupled to a switch, the switch comprising a fifth III-N structure on a third semiconductor substrate.
  • Example 8 the apparatus of any one of Examples 1-7, wherein a wireless
  • Example 10 the apparatus of any one of Examples 1-9, wherein each GaN structure is grown directly on the semiconductor substrate, wherein the GaN structures are separated by one or more shallow trench isolations (STI).
  • STI shallow trench isolations
  • Example 11 the apparatus of any one of Examples 1-10, wherein the semiconductor substrate comprises silicon.
  • Example 13 the integrated circuit die of any one of Example 12 further comprising: a first trench contact on the drain terminal; a second trench contact on the source terminal; an aluminum nitride (A1N) layer on the III-N structure between the source terminal and the drain terminal, wherein the polarization layer is on the A1N layer; and a high-k dielectric layer, wherein: the gate terminal is a t-shape and comprises a lower portion and an upper portion; a first portion of the high-k dielectric layer is on the lower surface of the lower portion of the gate terminal; a second portion of the high-k dielectric layer is on sidewalls of the lower portion of the gate terminal; and the polarization layer is between the A1N layer and the first portion of the high- k dielectric layer.
  • A1N aluminum nitride
  • Example 15 the integrated circuit die of any one of Examples 12-14, further comprising: a first spacer on the polarization layer and the second portion of the high-k dielectric layer; a second spacer on the first spacer and on the second portion of the high-k dielectric layer; a first inter-layer dielectric (ILD) on the first STI, the second STI, the III-N structure, the drain terminal, the source terminal, the first trench contact, first spacer, the second spacer, a lower surface of the upper portion of the gate terminal, and the second trench contact; and a second ILD on the first ILD, the first trench contact, sidewalls of the upper portion of the gate terminal, and the second trench contact.
  • ILD inter-layer dielectric
  • Example 16 the integrated circuit die of any one of Examples 12-15, wherein: the semiconductor substrate is a silicon (Si) (111) structure; the first STI and the second STI are a first oxide; the III-N structure and first layer of III-N are gallium nitride (GaN); the polarization layer is indium aluminum nitride (InAlN); the first spacer is a silicon oxide; the second spacer is a silicon nitride; and the first ILD is a second oxide.
  • the semiconductor substrate is a silicon (Si) (111) structure
  • the first STI and the second STI are a first oxide
  • the III-N structure and first layer of III-N are gallium nitride (GaN)
  • the polarization layer is indium aluminum nitride (InAlN)
  • the first spacer is a silicon oxide
  • the second spacer is a silicon nitride
  • the first ILD is a second oxide.
  • Example 17 the integrated circuit die of any one of Examples 12-16, wherein: the source terminal comprises indium gallium nitride (InGaN) and n-type doping; and the drain terminal comprises InGaN and n-type doping.
  • the source terminal comprises indium gallium nitride (InGaN) and n-type doping; and the drain terminal comprises InGaN and n-type doping.
  • Example 18 the integrated circuit die of any one of Examples 12-17, wherein the III-N structure is grown directly on the semiconductor substrate in a reactor.
  • Example 21 the integrated circuit die of any one of Examples 19-20 further comprises
  • Example 22 the integrated circuit die of any one of Examples 19-21, further comprising: disposing a first spacer on the polarization layer and the second portion of the high-k dielectric layer; disposing a second spacer on the first spacer and on the second portion of the high-k dielectric layer; disposing a first inter-layer dielectric (ILD) on the first STI, the second STI, the III-N structure, the drain terminal, the source terminal, the first trench contact, first spacer, the second spacer, a lower surface of the upper portion of the gate terminal, and the second trench contact; and disposing a second ILD on the first ILD, the first trench contact, sidewalls of the upper portion of the gate terminal, and the second trench contact.
  • ILD inter-layer dielectric
  • Example 23 the integrated circuit die of any one of Examples 19-22, wherein: the semiconductor substrate is a silicon (Si) (111) structure; the first STI and the second STI are a first oxide; the III-N structure and first layer of III-N are gallium nitride (GaN); the polarization layer is indium aluminum nitride (InAlN); the first spacer is a silicon oxide; the second spacer is a silicon nitride; the first ILD is a second oxide; the source terminal comprises indium gallium nitride (InGaN) and n-type doping; and the drain terminal comprises InGaN and n-type doping.
  • the semiconductor substrate is a silicon (Si) (111) structure
  • the first STI and the second STI are a first oxide
  • the III-N structure and first layer of III-N are gallium nitride (GaN)
  • the polarization layer is indium aluminum nitride (InAlN)
  • Example 24 the integrated circuit die of any one of Examples 19-23, wherein the III-N structure is grown directly on the semiconductor substrate in a reactor.
  • Example 25 is one or more functional blocks of a group Ill-nitride (III-N) integrated radio frequency (RF) front-end circuit, each functional block comprising a group Ill-nitride (III-N) structure on a semiconductor substrate.
  • III-N group Ill-nitride
  • RF radio frequency
  • Example 26 the one or more functional blocks of Example 25, wherein each functional block further comprises a source terminal and a drain terminal on the III-N structure; a polarization layer above the III-N structure between the source terminal and the drain terminal; and a gate terminal above the polarization layer.
  • Example 27 the one or more functional blocks of any one of Examples 25-26, wherein each functional block further comprises: a first trench contact on the drain terminal; a second trench contact on the source terminal; an aluminum nitride (A1N) layer on the III-N structure between the source terminal and the drain terminal, wherein the polarization layer is on the A1N layer; and a high-k dielectric layer, wherein: the gate terminal is a t-shape and comprises a lower portion and an upper portion; a first portion of the high-k dielectric layer is on the lower surface of the lower portion of the gate terminal; a second portion of the high-k dielectric layer is on sidewalls of the lower portion of the gate terminal; and the polarization layer is between the A1N layer and the first portion of the high-k dielectric layer.
  • A1N aluminum nitride
  • Example 28 the one or more functional blocks of any one of Examples 25-27, wherein each functional block further comprises: a first shallow trench isolation (STI) and a second STI on the semiconductor substrate; and a first layer of III-N on the semiconductor substrate between the first STI and the second STI, wherein the III-N structure is on the first layer of III-N.
  • STI shallow trench isolation
  • III-N structure is on the first layer of III-N.
  • Example 29 the one or more functional blocks of any one of Examples 25-28, wherein each functional block further comprises: a first spacer on the polarization layer and the second portion of the high-k dielectric layer; a second spacer on the first spacer and on the second portion of the high-k dielectric layer; a first inter-layer dielectric (ILD) on the first STI, the second STI, the III-N structure, the drain terminal, the source terminal, the first trench contact, first spacer, the second spacer, a lower surface of the upper portion of the gate terminal, and the second trench contact; and a second ILD on the first ILD, the first trench contact, sidewalls of the upper portion of the gate terminal, and the second trench contact.
  • ILD inter-layer dielectric
  • Example 30 the one or more functional blocks of any one of Examples 25-29, wherein: the semiconductor substrate is a silicon (Si) (111) structure; the first STI and the second STI are a first oxide; the III-N structure and first layer of III-N are gallium nitride (GaN); the polarization layer is indium aluminum nitride (InAlN); the first spacer is a silicon oxide; the second spacer is a silicon nitride; and the first ILD is a second oxide.
  • the semiconductor substrate is a silicon (Si) (111) structure
  • the first STI and the second STI are a first oxide
  • the III-N structure and first layer of III-N are gallium nitride (GaN)
  • the polarization layer is indium aluminum nitride (InAlN)
  • the first spacer is a silicon oxide
  • the second spacer is a silicon nitride
  • the first ILD is a second oxide.
  • Example 31 the one or more functional blocks of any one of Examples 25-30, wherein: the source terminal comprises indium gallium nitride (InGaN) and n-type doping; and the drain terminal comprises InGaN and n-type doping.
  • the source terminal comprises indium gallium nitride (InGaN) and n-type doping
  • the drain terminal comprises InGaN and n-type doping.
  • Example 32 the one or more functional blocks of any one of Examples 25-31, wherein the III-N structure is grown directly on the semiconductor substrate in a reactor.
  • Example 34 the one or more functional blocks of any one of Examples 25-33 comprise a second functional block comprising a low-noise amplifier (LNA), the LNA comprising a second III-N structure on the semiconductor substrate.
  • LNA low-noise amplifier
  • Example 35 the one or more functional blocks of any one of Examples 25-34 comprise a third functional block comprising a voltage regulator (VR), the VR comprising a third III-N structure on the semiconductor substrate.
  • Example 36 the one or more functional blocks of any one of Examples 25-35 comprise a fourth functional block comprising an n-type metal-oxide- semiconductor logic (NMOS), the NMOS comprising a fourth III-N structure on the semiconductor substrate.
  • NMOS n-type metal-oxide- semiconductor logic
  • Example 37 the one or more functional blocks of any one of Examples 25-36 comprise a fifth functional block comprising a switch, the switch comprising a fifth III-N structure on the semiconductor substrate.
  • Example 38 the one or more functional blocks of any one of Examples 25-37, wherein at least one of the one or more functional blocks is to be coupled to one or more filters.
  • Example 39 the one or more functional blocks of any one of Examples 25-38, wherein at least one of the one or more functional blocks is to be coupled to an antenna.
  • Example 40 the one or more functional blocks of any one of Examples 25-39, wherein at least one of the one or more functional blocks is coupled a complementary metal-oxide- semiconductor (CMOS) companion chip.
  • CMOS complementary metal-oxide- semiconductor
  • the terms “over,” “above” “under,” “between,” and “on” as used herein refer to a relative position of one material layer or component with respect to other layers or components.
  • one layer disposed above or over or under another layer may be directly in contact with the other layer or may have one or more intervening layers.
  • one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers.
  • a first layer “on” a second layer is in direct contact with that second layer.
  • one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.
  • Implementations of the disclosure may be formed or carried out on a substrate, such as a semiconductor substrate.
  • the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure.
  • the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to Germanium, Indium Antimonide, Lead Telluride, Indium Arsenide, Indium Phosphide, Gallium Arsenide, Indium Gallium Arsenide, Gallium Antimonide, or other combinations of group III-V or group IV materials. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the present disclosure.
  • a plurality of transistors such as metal-oxide-semiconductor field-effect transistors (MOSFET or simply MOS transistors), may be fabricated on the substrate.
  • MOSFET metal-oxide-semiconductor field-effect transistors
  • the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both.
  • Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors.
  • FinFET transistors such as double-gate transistors and tri-gate transistors
  • wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors.
  • Each MOS transistor includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer.
  • the gate dielectric layer may include one layer or a stack of layers.
  • the one or more layers may include silicon oxide, silicon dioxide (Si0 2 ) and/or a high-k dielectric material.
  • the high-k dielectric material may include elements such as Hafnium, Silicon, Oxygen, Titanium, Tantalum, Lanthanum, Aluminum, Zirconium, Barium, Strontium, Yttrium, Lead, Scandium, Niobium, and Zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, Hafnium Oxide, Hafnium Silicon Oxide,
  • an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.
  • the gate electrode layer is formed on the gate dielectric layer and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor.
  • the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.
  • metals that may be used for the gate electrode include, but are not limited to, Ruthenium, Palladium, Platinum, Cobalt, Nickel, and conductive metal oxides, e.g., Ruthenium Oxide.
  • a P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV.
  • metals that may be used for the gate electrode include, but are not limited to, Hafnium, Zirconium, Titanium, Tantalum, Aluminum, alloys of these metals, and carbides of these metals such as Hafnium Carbide, Zirconium Carbide, Titanium Carbide, Tantalum Carbide, and Aluminum Carbide.
  • An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV.
  • the gate electrode when viewed as a cross-section of the transistor along the source-channel-drain direction, may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate.
  • at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate.
  • the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures.
  • the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
  • a pair of sidewall spacers may be formed on opposing sides of the gate stack that bracket the gate stack.
  • the sidewall spacers may be formed from a material such as Silicon Nitride, Silicon Oxide, Silicon Carbide, Silicon Nitride doped with Carbon, and Silicon Oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process operations. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.
  • source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor.
  • the source and drain regions may be formed using either an implantation/diffusion process or an etching/deposition process.
  • dopants such as Boron, Aluminum, Antimony, Phosphorous, or Arsenic may be ion-implanted into the substrate to form the source and drain regions.
  • An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process.
  • the substrate may first be etched to form recesses at the locations of the source and drain regions.
  • An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source and drain regions.
  • the source and drain regions may be fabricated using a Silicon alloy such as Silicon Germanium or Silicon Carbide.
  • the epitaxially deposited silicon alloy may be doped in situ with dopants such as Boron, Arsenic, or Phosphorous.
  • the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy.
  • one or more layers of metal and/or metal alloys may be used to form the source and drain regions.
  • one or more interlayer dielectrics are deposited over the MOS transistors.
  • the ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials. Examples of dielectric materials that may be used include, but are not limited to, Silicon Dioxide (Si0 2 ), Carbon doped oxide (CDO), Silicon Nitride, organic polymers such as Perfluorocyclobutane or Polytetrafluoroethylene, Fluorosilicate glass (FSG), and organosilicates such as Silsesquioxane, Siloxane, or Organosilicate glass.
  • the ILD layers may include pores or air gaps to further reduce their dielectric constant.

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Abstract

L'invention concerne un appareil, une puce de circuit intégré et un procédé de fabrication d'un circuit frontal RF intégré à nitrure du groupe III (III-N). L'appareil comprend un circuit frontal radiofréquence (RF) intégré III-N qui comprend un substrat semi-conducteur, une pluralité de blocs fonctionnels, chacun de la pluralité de blocs fonctionnels comprenant une structure III-N sur le substrat semi-conducteur. Le circuit frontal RF intégré III-N doit être couplé à une antenne.
PCT/US2017/016162 2017-02-02 2017-02-02 Circuit frontal intégré à nitrure du groupe iii WO2018143987A1 (fr)

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WO2015157701A1 (fr) * 2014-04-11 2015-10-15 Cree, Inc. Amplificateur au gan pour applications wi-fi

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