WO2018141270A1 - 编码方法、通信方法及装置 - Google Patents

编码方法、通信方法及装置 Download PDF

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Publication number
WO2018141270A1
WO2018141270A1 PCT/CN2018/075128 CN2018075128W WO2018141270A1 WO 2018141270 A1 WO2018141270 A1 WO 2018141270A1 CN 2018075128 W CN2018075128 W CN 2018075128W WO 2018141270 A1 WO2018141270 A1 WO 2018141270A1
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max
matrix
information sequence
int
value
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PCT/CN2018/075128
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English (en)
French (fr)
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刘晓健
魏岳军
郑晨
马亮
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华为技术有限公司
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Priority to EP18748161.9A priority Critical patent/EP3570470A4/en
Publication of WO2018141270A1 publication Critical patent/WO2018141270A1/zh
Priority to US16/527,626 priority patent/US11211952B2/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/615—Use of computational or mathematical techniques
    • H03M13/616—Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/1157—Low-density generator matrices [LDGM]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
    • H03M13/1185—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/618—Shortening and extension of codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/6306—Error control coding in combination with Automatic Repeat reQuest [ARQ] and diversity transmission, e.g. coding schemes for the multiple transmission of the same information or the transmission of incremental redundancy
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H03M13/6362—Error control coding in combination with rate matching by puncturing
    • H03M13/6368—Error control coding in combination with rate matching by puncturing using rate compatible puncturing or complementary puncturing
    • H03M13/6393—Rate compatible low-density parity check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation
    • H03M13/6516—Support of multiple code parameters, e.g. generalized Reed-Solomon decoder for a variety of generator polynomials or Galois fields
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes

Definitions

  • the embodiments of the present invention relate to the field of communications, and in particular, to an encoding method, a communication method, and an apparatus.
  • a low density parity check (LDPC) code is a type of linear block coding with a sparse check matrix. Since LDPC not only has good performance close to Shannon's limit, but also has the characteristics of flexible structure and low decoding complexity, it can be widely used in various communication systems.
  • the quasi-cyclic low parity parity check (QC-LDPC) code is an important branch of the LDPC code.
  • the check matrix is composed of many block matrices of the same size. These block matrices are all zeros. Matrix and cyclic shift matrix. It has been adopted by multiple communication systems because of its ease of implementation.
  • the embodiment of the present application provides an encoding method, a communication method, and a device, which can maintain a low bit error rate leveling layer.
  • an encoding method comprising:
  • the first matrix is a matrix of size m b z ⁇ n b z, where z is an expansion factor
  • the first matrix includes m b ⁇ n b sub-matrices of size z ⁇ z, m b ⁇ n b sub-matrices of size z ⁇ z including at least one cyclic displacement matrix of a unit matrix of size z ⁇ z, each of said cyclic displacement matrices
  • the cyclic displacement value is an element in the matrix E(H) corresponding to the respective cyclic displacement matrix, wherein the matrix E(H) is
  • a ij E max is the element in the cyclic displacement value matrix E max (H) corresponding to the maximum expansion factor z max
  • r 1 (a ij E max , z) represents a function of the parameters a ij E max and z
  • f(r 1 (a ij E max ,z),r 2 (z)) represents a function of the parameters r 1 (a ij E max ,z) and r 2 (z), f(r 1 (a ij E max , z) , r 2 (z)) have a value less than z;
  • the second sequence of information is output.
  • the above coding method provided by the embodiment of the present application can maintain a low bit error rate leveling layer and can reduce the occupation of the storage space.
  • z max can be a predefined value.
  • the value of the spreading factor is determined according to the first information sequence or other functional units input the value of the spreading factor to the encoder, the value of the spreading factor is corrected, and after the correction, The value of z is the final use.
  • the value of z is the final use.
  • the value of r 1 (a ij E max , z) is determined from the sum of the offset value corresponding to z and a ij E max .
  • r 1 (a ij E max , z) may include any of the following:
  • r 1 (a ij ,z) a ij E max +Int(a ij E max /c) ⁇ s z ;
  • r 1 (a ij ,z) a ijE max +Int(c/a ij E max ) ⁇ s z ;
  • r 1 (a ij ,z) a ijE max +Int(s z /a ijE max );
  • r 1 (a ij ,z) a ijE max +Int(a ijE max /z);
  • r 1 (a ij ,z) a ijE max +(z max -a ijE max ) ⁇ s z ;
  • r 1 (a ijE max ,z) a ijE max +Int((s z ⁇ a ijE max )/c).
  • N z is a positive integer associated with z
  • f(r 1 (a ijE max , z), r 2 (z)) r 1 (a ijE max ,z) modr 2 (z).
  • a communication method which applies the above coding method to obtain a second information sequence; the second information sequence is processed and transmitted.
  • the above communication method using the coding method of the first aspect can improve the performance of data transmission.
  • an apparatus comprising: a memory and a processor; wherein the memory is configured to store the first sequence of information; and the processor is configured to implement the processing in the encoding method of the first aspect above.
  • an apparatus comprising: at least one processor and a memory coupled to the at least one processor, wherein
  • the at least one processor is configured to execute instructions in a memory to implement the encoding method of the first aspect.
  • the apparatus of the third aspect or the fourth aspect described above may be an encoder.
  • a communication device comprising the apparatus of the third aspect or the fourth aspect described above.
  • the above communication device may be a terminal device or a network device.
  • Yet another aspect of the present application provides a computer readable storage medium having instructions stored therein that, when executed on a computer, cause the computer to perform the methods described in the above aspects.
  • FIG. 1 is a schematic flowchart of an encoding method according to an embodiment of the present application.
  • FIG. 2 is a performance simulation diagram of an encoding method using an embodiment of the present application
  • 3a-3e are performance simulation diagrams of an encoding method using an embodiment of the present application.
  • FIG. 5 is a schematic flowchart of a communication method according to an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a coding and processing process according to an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a device according to an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a communication device according to an embodiment of the present application.
  • the embodiments of the present application can be applied to a wireless communication system including a wireless communication device such as a network device and a terminal device.
  • a wireless communication device such as a network device and a terminal device.
  • an LTE system or other wireless communication system using various radio access technologies, for example, using code division multiple access, frequency division multiple access, time division multiple access, orthogonal frequency division multiple access, single carrier frequency division multiple access, etc.
  • the subsequent evolution system such as the fifth generation (5G) system.
  • the wireless communication device in the embodiments of the present application may be any device in the wireless communication system, such as a network device or a terminal device.
  • the terminal device may be a device that provides voice or data connectivity to the user, a handheld device with a wireless connection function, or other processing device connected to the wireless modem.
  • the wireless terminal can communicate with one or more core networks via a radio access network (RAN), which can be a mobile terminal, such as a mobile phone (or "cellular" phone) and a mobile terminal.
  • RAN radio access network
  • the computer for example, can be a portable, pocket, handheld, computer built-in or in-vehicle mobile device that exchanges language and or data with the wireless access network.
  • PCS personal communication service
  • SIP session initiation protocol
  • WLL wireless local loop
  • PDA personal Digital assistant
  • a wireless terminal may also be referred to as a system, a subscriber unit (SU), a subscriber station (SS), a mobile station (MS), a remote station (RS), and an access station.
  • Point access point, AP for short), remote terminal (RT), access terminal (AT), user terminal (UT), user agent (UA) User equipment, or user equipment (UE).
  • the network device may be a base station, or an access point, or may refer to a device in the access network that communicates with the wireless terminal over one or more sectors over the air interface.
  • the base station can be used to convert the received air frame and the IP packet into a router between the wireless terminal and the rest of the access network, wherein the rest of the access network can include an Internet Protocol (IP) network.
  • IP Internet Protocol
  • the base station can also coordinate attribute management of the air interface.
  • the base station may be a Base Transceiver Station (BTS) in GSM or CDMA, or may be a base station (NodeB) in WCDMA, or may be an evolved base station (eNodeB) in LTE.
  • BTS Base Transceiver Station
  • NodeB base station
  • eNodeB evolved base station
  • An embodiment of the present application provides an encoding method, which may be implemented by, for example, an encoder on a communication device. As shown in FIG. 1, the encoding method may include:
  • the first matrix is a matrix of size m b z ⁇ n b z, where z is an expansion factor, and the first matrix includes m b ⁇ n b sub-matrices of size z ⁇ z, m b ⁇ n b sub-matrices of size z ⁇ z include at least one cyclic displacement matrix of a unit matrix of size z ⁇ z, each of the above cyclic displacement matrices
  • the cyclic displacement value is an element in the matrix E(H) corresponding to the respective cyclic displacement matrix, wherein the matrix E(H) is
  • a ij E max is the element in the cyclic displacement value matrix E max (H) corresponding to the maximum expansion factor z max
  • r 1 (a ij E max , z) represents a function of the parameters a ij E max and z
  • r 2 ( z) represents a function of the parameter z
  • f(r 1 (a ij E max ,z),r 2 (z)) represents a function of the parameters r 1 (a ij E max ,z) and r 2 (z)
  • f(r 1 (a ij E max , z), r 2 (z)) has a value less than z;
  • z max can be a predefined value, and then E max (H) can also be fixed.
  • an all-zero sub-matrix of size z ⁇ z can also be included in the first matrix, and the value of the element at the corresponding position in E(H) is -1 for the all-zero sub-matrix.
  • E(H) can be understood as a result of adjustment based on E max (H).
  • E max (H) may be saved on the communication device, and for different spreading factors, the corresponding E(H) may be obtained by using E max (H), thereby finally obtaining the first matrix.
  • the encoder may determine the value of z according to the length of the first information sequence; or, in a possible implementation manner, the value of z may be determined by other functional units and then input to Encoders; in different scenarios or criteria, the manner in which the encoder or other functional unit determines the value of z may be different.
  • the manner in which the encoder or other functional unit determines the value of z is not limited in this embodiment.
  • the encoder determines the value of the spreading factor according to the first information sequence or the other functional unit inputs the value of the spreading factor to the encoder, and then corrects the value, and the modified value is corrected.
  • the value is the final used z, and the specific modification is described in the subsequent embodiments.
  • the communication device performs encoding of the first information sequence by using the first matrix to obtain a second information sequence.
  • the first information sequence may be filled by zero padding or filled with other known bit sequences, so that the length of the filled information sequence and the input supported by the first matrix are The information sequences are of equal length, and then the first matrix and the filled information sequence are used to obtain a parity bit, and the information bits and the parity bits are combined and output to obtain a coded sequence, that is, a second information sequence.
  • the cyclic displacement matrix of the unit matrix may refer to a matrix obtained based on the unit matrix and the cyclic displacement value, and the cyclic displacement value represents the number of times the unit matrix is cyclically shifted to the right.
  • the cyclic displacement matrix is passed. Each row of the identity matrix is rotated to the right by the same number of cycles.
  • the cyclic displacement value is 0, it is expressed as the unit matrix itself.
  • the second information sequence obtained in S101 is output by the encoder.
  • the first matrix satisfies the functions related to the spreading factor and the elements in E max (H), can maintain a low bit error rate leveling layer, and can reduce the occupation of the storage space.
  • performance can be improved while ensuring a small expansion factor of the expansion factor.
  • the spreading factor granularity refers to an interval between two adjacent spreading factors.
  • E max (H) can be used to obtain the corresponding E(H), which may have different methods, that is, r 1 (a ijE max, z), r 2 (z), and Each function in f(r 1( a ij E max ,z),r 2 (z)) can have many different expressions, for example:
  • c is a preset constant
  • s Z is a value corresponding to z, and the value may be a non-negative integer within a certain interval.
  • the s corresponding to z may be obtained by looking up the table.
  • Int() is a rounding function that can be rounded up or rounded down.
  • Mod is a modulo operation.
  • a)-g) can be understood as adding an offset value to a ijE max , except that in the manner shown by f), after adding an offset value based on ai jE max The results were limited in scope. Further, the offset value is determined in different manners. For example, an offset value corresponding to z may be determined according to z.
  • N z is a positive integer less than z, for example, N z corresponding to z can be obtained, and N z can be in the range of 2 t or k ⁇ 2 t , k And t are both non-negative integers.
  • r 1 (a ij E max ,z), r 2 (z) and f( r 1( aijE max ,z),r 2 (z)) may be combined according to different expression forms.
  • the value of finally f(r 1 (a ij E max ,z),r 2 (z)) is less than z.
  • the constraint may be further made such that the result of the offset value is not greater than z, for example, r 2 (z) and f(r 1 ( a ijE max ,z),r 2 (z)), and r 2 (z) can generally select one of h)j)k) and further adopt, for example, f(r 1 (a ijE max , z), r 2 (z)) m) way to complete Constraint
  • the respective first matrices corresponding to the values of the different z can be obtained by the formula (1).
  • s z can be as shown in Table 1. It can be understood that Table 1 is only an example of the value of s z , and based on the example shown in Table 1, the s z / obtained according to the z table is obtained. value of 256, by a further multiplication can obtain s z values.
  • Fig. 2 shows the manner of formula (1) and table 1, the first information sequence length is from 96 to 8192, and the code rates are 8/9, 5/6, 3/4, 2/3, 1 respectively.
  • QPSK quadrature phase shift keying
  • BP belief propagation
  • Figure 3a-3e shows the error block rate simulation results of the first information sequence lengths of 8000, 6000, 4000, 2000 and 1000 using the formula (2).
  • the code rate used in the simulation includes 1/5, 1/4. , 1/3, 2/5, 1/2, 2/3, 3/4, 5/6, 8/9, modulation mode is QPSK, and the algorithm is BP algorithm.
  • the performance is better over the above code length and code rate.
  • a modified spreading factor may be used, wherein the scaling factor may be modified in various ways, for example, by using an extended factor offset value pair.
  • the initial expansion factor z orig is corrected, or the value of z that is allowed to be used is saved. When z orig does not belong to the allowed z, the value of z that is allowed to be used is greater than the minimum value of z orig as the corrected value. Expansion factor.
  • the z orig may be, for example, the encoder determines the value of the spreading factor according to the first information sequence, or may be the value of the expansion factor input by the other functional unit to the encoder. This is not limited.
  • the value of ⁇ z may be related to different factors, for example, related to at least one of the following factors: a formula that ij satisfies, system requirements, z orig, etc., and the specific value of ⁇ z can be obtained by looking up the table.
  • ⁇ z and t can be determined by using Table 2. It can be understood that Table 2 is only an example, and the corresponding relationship between ⁇ z and t and z orig may be different from that of Table 2, and this embodiment does not do this. limited.
  • FIG. 4 shows that using the formula (3) and Table 2, the first information sequence length is from 96 to 8000, and the code rates are 8/9, 5/6, 3/4, 2/3, 1/2, respectively.
  • Es / No is the signal to noise ratio
  • the unit is dB
  • Rate or CR is the code rate
  • information length K is the length of the information sequence.
  • the value of ⁇ z can be determined by Table 3. It can be understood that Table 3 is only an example, and the correspondence between z orig and ⁇ z may be different. In the manner of Table 3, the embodiment of the present application does not limit this. For example, you can save ⁇ z nonzero z orig, zero or save ⁇ z z orig.
  • the labeling of z is realized, so that certain specific zs are not used, and a lower BLER can be realized.
  • the coding method in the foregoing embodiments of the present application is applicable to a QC-LDPC code check matrix code check matrix.
  • the first matrix in the embodiments of the foregoing encoding methods can also be applied to the decoding method, that is, in the decoding process, the same matrix as in the encoding process is also used for decoding.
  • the manner in which the first matrix is obtained may also be the same as the above embodiment.
  • the third information sequence is decoded using the first matrix to obtain a fourth information sequence.
  • the third information sequence may correspond to the second information sequence, and the fourth information sequence corresponds to the first information sequence.
  • the decoding method can be applied to a corresponding communication method, and the communication method is implemented by a corresponding communication device.
  • the embodiment of the present application further provides a communication method, which is applied to the various coding methods described in the foregoing embodiments. As shown in FIG. 5, the method may include:
  • the first information sequence may be processed by other functional units and input to the encoder.
  • the embodiment of the present application does not make the source and content of the first information sequence. limited.
  • the second information sequence may be sent after bit rearrangement, rate matching, interleaving, symbol mapping, and modulation, etc.
  • FIG. 6 illustrates a method of encoding the first information sequence and performing a series of The process of processing. It can be understood that, for different systems or application scenarios, the process of processing the second information sequence may be different. For example, bit rearrangement may be used as an optional process, and the present application does not have a pair of various processes. Give an example.
  • the performance of data transmission can be improved by applying various coding methods described in the foregoing embodiments in the communication method.
  • the embodiment of the present application provides a device 700, as shown in FIG. 7, comprising: a memory 701, configured to store a first information sequence; and a processor 702, configured to encode the first information sequence by using the first matrix, to obtain a first Two information sequences.
  • a device 700 as shown in FIG. 7, comprising: a memory 701, configured to store a first information sequence; and a processor 702, configured to encode the first information sequence by using the first matrix, to obtain a first Two information sequences.
  • the manner in which the processor 702 encodes the first information sequence may refer to related descriptions of the foregoing various embodiments, and details are not described herein again.
  • the length of the first information sequence is obtained; or, in a possible implementation manner, the value of z orig may also be determined by other functional units and then input to the device 700.
  • An embodiment of the present application further provides an apparatus, including at least one processor and a memory coupled to the at least one processor, wherein the at least one processor is configured to execute an instruction in a memory, and utilize the first information sequence A matrix is encoded to obtain a second sequence of information.
  • the processor encodes the first information sequence reference may be made to the related description of the foregoing embodiments, and details are not described herein again.
  • the apparatus in each of the foregoing embodiments may be an encoder, and the second information sequence is used as an output of the encoder.
  • the embodiment of the present application further provides a communication device 800, as shown in FIG. 8, which may include:
  • An encoder 801 configured to encode the first information sequence by using the first matrix to obtain a second information sequence
  • At least one processor 802 configured to process the second information sequence
  • the transceiver 803 is configured to send the processed second information sequence.
  • the manner in which the encoder 801 encodes the first information sequence can be referred to the related description of the foregoing embodiments.
  • the encoder 801 For the structure and implementation of the encoder, reference may be made to the foregoing embodiments, and details are not described herein again.
  • At least one processor 802 can implement a series of processes including bit reordering, rate matching, interleaving, symbol mapping, and modulation. It is to be understood that the processing performed by the processor 802 and the composition of the processor 802 may be different for different systems or application scenarios, and the embodiments of the present application are not illustrated.
  • the communication device 800 can be a terminal device or a network device.
  • the above embodiments it may be implemented in whole or in part by software, hardware, firmware or any combination thereof.
  • software it may be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions.
  • the computer program instructions When the computer program instructions are loaded and executed on a computer, the processes or functions described in accordance with embodiments of the present invention are generated in whole or in part.
  • the computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable device.
  • the computer instructions can be stored in a computer readable storage medium or transferred from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions can be from a website site, computer, server or data center Transfer to another website site, computer, server, or data center by wire (eg, coaxial cable, fiber optic, digital subscriber line (DSL), or wireless (eg, infrared, wireless, microwave, etc.).
  • the computer readable storage medium can be any available media that can be accessed by a computer or a data storage device such as a server, data center, or the like that includes one or more available media.
  • the usable medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (such as a solid state disk (SSD)).
  • the technology in the embodiments of the present application can be implemented by means of software plus a necessary general hardware platform.
  • the technical solution in the embodiments of the present application may be embodied in the form of a software product in essence or in the form of a software product, and the computer software product may be stored in a storage medium such as a ROM/RAM. , a diskette, an optical disk, etc., including instructions for causing a computer device (which may be a personal computer, server, or network device, etc.) to perform the methods described in various embodiments of the present application or portions of the embodiments.
  • a computer device which may be a personal computer, server, or network device, etc.

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Abstract

本申请实施例公开了一种编码方法、通信方法和装置，对第一信息序列利用第一矩阵进行编码得到第二信息序列，其中，第一矩阵满足与扩展因子以及E max(H)中的元素相关的函数，保证能够保持较低的误码率平层，并可以减少对存储空间的占用。

Description

编码方法、通信方法及装置
本申请要求于2017年02月4日提交中国专利局、申请号为201710064592.7、申请名称为“编码方法、通信方法及装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明实施例涉及通信领域，尤其涉及编码方法、通信方法及装置。
背景技术
低密度奇偶校验(low density parity check，简称LDPC)码是一类具有稀疏校验矩阵的线性分组编码。由于LDPC不仅具有逼近香农极限的良好性能，而且具有结构灵活译码复杂度较低的特点，因此可以被广泛应用于各种通信系统中。
准循环低密度奇偶校验(quasi-cycliclow density parity check，简称QC-LDPC)码是LDPC码的一个重要分支，其校验矩阵由很多尺寸相同的分块矩阵构成，这些分块矩阵为全零矩阵和循环移位矩阵。由于其便于实现，已被多个通信系统采用。
在确定了QC-LDPC码校验矩阵中非零循环移位矩阵的位置以后，各个循环移位矩阵的偏移值对于相应码字的错误平层影响很大。对于支持码长灵活可调的QC-LDPC码，通常通过设置一系列分块矩阵的扩展因子z来定义分块矩阵的尺寸，每个分块矩阵的尺寸是z×z，从而获得不同大小的校验矩阵以适应不同的码长。
然而，现有的LDPC码校验矩阵的计算方法需要进一步优化。
发明内容
本申请实施例提供了一种编码方法、通信方法以及装置，可以保持较低的误码率平层。
第一方面，提供了一种编码方法，包括：
对第一信息序列利用第一矩阵进行编码得到第二信息序列，其中第一矩阵为尺寸为m bz×n bz的矩阵，其中，z为扩展因子，所述第一矩阵包括m b×n b个尺寸为z×z的子矩阵，m b×n b个尺寸为z×z的子矩阵中至少包括一个尺寸为z×z的单位矩阵的循环位移矩阵，各个所述循环位移矩阵的循环位移值是矩阵E(H)中与所述各个循环位移矩阵对应位置处的元素，其中，矩阵E(H)为
Figure PCTCN2018075128-appb-000001
E(H)中的元素a ij满足：
Figure PCTCN2018075128-appb-000002
a ij E max为最大扩展因子z max对应的循环位移值矩阵E max(H)中的元素，r 1(a ij E max,z)表示参数为a ij E max和z的函数，r 2(z)表示参数为z的函数，
f(r 1(a ij E max,z),r 2(z))表示参数为r 1(a ij E max,z)和r 2(z)的函数，f(r 1(a ij E max,z) ,r 2(z))的值小于z；
输出所述第二信息序列。
本申请实施例提供的上述编码方法，能够保持较低的误码率平层，并可以减少对存储空间的占用。
在一个可能的设计中，z max可以为一个预先定义的数值。
在一个可能的设计中，可以在根据第一信息序列确定出扩展因子的取值后或者其他功能单元将扩展因子的取值输入给编码器后，对上述扩展因子的取值进行修正，修正后的值为最终使用的z。本申请实施例的方法中，通过对扩展因子的修正，可以实现对z的标注，可以避免一些性能较差的z，性能得到了进一步的优化。
在一个可能的设计中，r 1(a ij E max,z)的取值是根据z对应的偏置值与a ij E max之和确定的。
在一个可能的设计中，r 1(a ij E max,z)可以包括以下任意一种：
r 1(a ij,z)＝a ij E max+Int(a ij E max/c)·s z；
r 1(a ij,z)＝a ijE max+Int(c/a ij E max)·s z；
r 1(a ij,z)＝a ijE max+Int(s z/a ijE max)；
r 1(a ij,z)＝a ijE max+Int(a ijE max/z)；
r 1(a ij,z)＝a ijE max+(z max-a ijE max)·s z；
r 1(a ijE max,z)＝a ijE max+Int((s z·a ijE max)/c)。
基于上述r 1(a ijE max,z)，可以通过r 2(z)和f(r 1(a ijE max,z),r 2(z))进一步进行约束，其中，r 2(z)包括以下任意一种：
r 2(z)＝z；
Figure PCTCN2018075128-appb-000003
r 2(z)＝N z；
其中N z是与z有关的正整数，f(r 1(a ijE max,z),r 2(z))＝r 1(a ijE max,z)modr 2(z)。
在一种可能的设计中，r 1(a ij,z)＝(a ijE max+s z)MOD z max，r 2(z)＝z/z max，
f(r 1(a ijE max,z),r 2(z))＝Int(r 1(a ijE max,z)·r 2(z))。
通过上述方法，能够保持较低的误码率平层，并可以减少对存储空间的占用。此外，可以在保证扩展因子较小颗粒度的同时，提升性能。
第二方面，提供了一种通信方法，该通信方法应用了上述编码方法，得到第二信息序列；对所述第二信息序列进行处理并发送。
上述应用了第一方面的编码方法的通信方法，可以提升数据传输的性能。
第三方面，提供了一种装置，包括：存储器和处理器；其中，存储器，用于存储第一信息序列；处理器用于实现上述第一方面的编码方法中的处理过程。
第四方面，提供了一种装置，包括：包括至少一个处理器以及与所述至少一个处理器耦合的存储器，其中，
所述至少一个处理器用于执行存储器中的指令，实现第一方面的编码方法。
在一个可能的设计中，上述第三方面或第四方面的装置可以为编码器。
第五方面，还提供了一种包括了上述第三方面或第四方面的装置的通信设备。
在一个可能的设计中，上述通信设备可以为终端设备或者网络设备。
本申请的又一方面提供了一种计算机可读存储介质，所述计算机可读存储介质中存储有指令，当其在计算机上运行时，使得计算机执行上述各方面所述的方法。
附图说明
图1为本申请一实施例的编码方法流程示意图；
图2为采用本申请实施例的编码方法的性能仿真图；
图3a-3e为采用本申请实施例的编码方法的性能仿真图；
图4为采用本申请实施例的编码方法的性能仿真图；
图5为本申请一实施例的通信方法流程示意图；
图6为本申请实施例的编码以及处理过程示意图；
图7为本申请一实施例的装置结构示意图；
图8为本申请一实施例的通信设备结构示意图。
具体实施方式
本申请实施例可以应用于包括网络设备和终端设备(terminal device or terminal  equipment)等无线通信设备的无线通信系统中。例如，LTE系统，或其他采用各种无线接入技术的无线通信系统，例如采用码分多址，频分多址，时分多址，正交频分多址，单载波频分多址等接入技术的系统，后续的演进系统，如第五代(5G)系统等。本申请各实施例中所说的无线通信设备可以是无线通信系统中的任意设备，例如网络设备或终端设备等。
其中，所述终端设备可以是指向用户提供语音或数据连通性的设备，具有无线连接功能的手持式设备、或连接到无线调制解调器的其他处理设备。无线终端可以经无线接入网(radio access network，简称RAN)与一个或多个核心网进行通信，无线终端可以是移动终端，如移动电话(或称为“蜂窝”电话)和具有移动终端的计算机，例如，可以是便携式、袖珍式、手持式、计算机内置的或车载的移动装置，它们与无线接入网交换语言和或数据。例如，个人通信业务(personal communication service，简称PCS)电话、无绳电话、会话发起协议(session initiation protocol，简称SIP)话机、无线本地环路(wireless local loop，简称WLL)站、个人数字助理(personal digital assistant，简称PDA)等设备。无线终端也可以称为系统、订户单元(subscriber unit，简称SU)、订户站(subscriber station，简称SS)，移动站(mobile station，简称MS)、远程站(remote station，简称RS)、接入点(access point，简称AP)、远端设备(remote terminal，简称RT)、接入终端(access terminal，简称AT)、用户终端(user terminal，简称UT)、用户代理(user agent，简称UA)、用户设备、或用户装备(user equipment，简称UE)。
所述网络设备可以是基站，或者接入点，或者可以是指接入网中在空中接口上通过一个或多个扇区与无线终端通信的设备。基站可用于将收到的空中帧与IP分组进行相互转换，作为无线终端与接入网的其余部分之间的路由器，其中接入网的其余部分可包括网际协议(Internet protocol，简称IP)网络。基站还可协调对空中接口的属性管理。例如，基站可以是GSM或CDMA中的基站(Base Transceiver Station，简称BTS)，也可以是WCDMA中的基站(NodeB)，还可以是LTE中的演进型基站(evolutional Node B，简称eNodeB)，本申请并不限定。
本申请一实施例提供了一种编码方法，该编码方法可以通过例如通信设备上的编码器实现，如图1所示，该编码方法可以包括：
S101，对第一信息序列利用第一矩阵进行编码得到第二信息序列，其中第一矩阵为尺寸为m bz×n bz的矩阵，其中，z为扩展因子，所述第一矩阵包括m b×n b个尺寸为z×z的子矩阵，m b×n b个尺寸为z×z的子矩阵中至少包括一个尺寸为z×z的单位矩阵的循环位移矩阵，上述各个循环位移矩阵的循环位移值是矩阵E(H)中与所述各个循环位移矩阵对应位置处的元素，其中，矩阵E(H)为
Figure PCTCN2018075128-appb-000004
E(H)中的元素a ij满足：
Figure PCTCN2018075128-appb-000005
a ij∈{-1,0,1,2,....z-1}；
a ij E max为最大扩展因子z max对应的循环位移值矩阵E max(H)中的元素，r 1(a ij E max,z)表示参数为a ij E max和z的函数，r 2(z)表示参数为z的函数，而f(r 1(a ij E max,z),r  2(z))表示参数为r 1(a ij E max,z)和r 2(z)的函数,f(r 1(a ij E max,z),r 2(z))的值小于z；
其中，一种可能的实现方式中，z max可以为一个预先定义的数值，那么E max(H)也可以是固定的。
可以理解的是，在第一矩阵中还可以包括为尺寸为z×z的全零子矩阵，对于全零子矩阵，其在E(H)中的对应位置处的元素的值为-1。
一种可能的实现方式中，上述的E(H)可以理解为是在E max(H)基础上进行调整后的结果。具体的，可以在通信设备上保存E max(H)，而针对不同的扩展因子，可以利用E max(H)获取到相应的E(H)，从而最终得到第一矩阵。
举例来说，假设z max＝8，一个尺寸为(8z max，4z max)的LDPC码矩阵可以用
Figure PCTCN2018075128-appb-000006
和
Figure PCTCN2018075128-appb-000007
(H)表示如下：
Figure PCTCN2018075128-appb-000008
其中，O表示全零矩阵的子矩阵，
Figure PCTCN2018075128-appb-000009
表示偏移值为的a ij E max循环位移矩阵，a ijE max的具体取值是根据
Figure PCTCN2018075128-appb-000010
(H)确定的，其中，
Figure PCTCN2018075128-appb-000011
那么对应于z＝4，假设是用
Figure PCTCN2018075128-appb-000012
确定E(H)，那么得到的对应的E(H)和H可以分别如下：
Figure PCTCN2018075128-appb-000013
Figure PCTCN2018075128-appb-000014
一种可能的实现方式中，可以是由编码器根据第一信息序列的长度确定z的取值；或者，一种可能的实现方式中，也可以通过其他功能单元确定z的取值后输入给编码器；在不同的场景或者准则下，编码器或者其他功能单元确定z的取值的方式可能不同，本申请实施例对编码器或者其他功能单元确定z的取值的方式不做限定。
可选的，为了进一步提升性能，上述编码器根据第一信息序列确定出扩展因子的取值或者其他功能单元将扩展因子的取值输入给编码器后，对上述取值进行修正，修正后的值为最终使用的z，具体的修正方式在后续实施例中描述。
进一步的，通信设备会利用第一矩阵完成对第一信息序列的编码，得到第二信息序列。
一种可能的实现方式中，可以将第一信息序列通过补0(zero padding)的方式填充，或使用其他已知比特序列填充，使得填充后的信息序列的长度与第一矩阵所支持的输入信息序列长度相等，然后使用第一矩阵与填充后的信息序列进行运算获得校验位，将信息位和校验位合并后输出，获得编码后的序列，即第二信息序列。
一种可能的实现方式中，上述单位矩阵的循环位移矩阵可以是指基于单位矩阵和循环位移值得到的矩阵，循环位移值表示将单位矩阵向右循环位移的次数，例如，循环位移矩阵是通过将单位矩阵的每一行都进行相同次数的循环右移得到的。当循环位移值为0时，表示为单位矩阵本身。
一种示例中，假设尺寸为4单位矩阵为
Figure PCTCN2018075128-appb-000015
循环位移值为1，那么对应的循环位移矩阵为
Figure PCTCN2018075128-appb-000016
S102，输出第二信息序列。
一种可能的实现方式中，S101中得到的第二信息序列，由编码器输出。
本申请实施例中，使得第一矩阵满足与扩展因子以及E max(H)中的元素相关的函数，能够保持较低的误码率平层，并可以减少对存储空间的占用。此外，可以在保证扩展因子较小颗粒度的同时，提升性能。其中，所述扩展因子颗粒度指的是相邻两个扩展因子之间的间隔。
具体的，针对不同的扩展因子，可以利用E max(H)获取到相应的E(H)，可能有不同的方法，也就是说r 1(a ijE max,z)、r 2(z)和f(r 1(a ij E max,z),r 2(z))中的每个函数都可以有多种不同的表现形式，例如：
对于r 1(a ij E max,z)，可以有如下表现形式
a)r 1(a ij,z)＝a ij E max+Int(a ij E max/c)·s z，
b)r 1(a ij,z)＝a ij E max+Int(c/a ij E max)·s z，
c)r 1(a ij,z)＝a ij E max+Int(s z/a ij E max)，
d)r 1(a ij,z)＝a ij E max+Int(a ij E max/z)，
e)r 1(a ij,z)＝a ij E max+(z max-a ij E max)·s z
f)r 1(a ij,z)＝(a ij E max+s z)mod z max
g)r 1(a ij E max,z)＝a ij E max+Int((s z·a ij E max)/c)
以上公式中，c为预设常数，s Z为与z对应的数值，其取值可以为一定区间内的非负整数，一种可能的实现方式中，可以通过查表获得与z对应的s z。Int()为取整函数，可以向上取整也可以向下取整。mod为取模运算。以上，a)-g)均可以理解为在a ijE max的基础上加上偏置值，所不同的是f)所示的方式中，在ai jE max的基础上加上偏置值后的结果上进行了范围限定。进一步的，偏置值通过不同的方式确定，例如可以根据z确定一个与z对应的偏置值本申请实施例不一一例举。
对于r 2(z)，可以有如下表现形式：
h)r 2(z)＝z，
i)r 2(z)＝z/z max
j)
Figure PCTCN2018075128-appb-000017
其中，floor表示向下取整。
k)r 2(z)＝N z，其中N z是小于z的正整数，例如可以查表得到和z对应的N z，而N z取值范围可以是2 t或者k·2 t，k和t都是非负整数。
对于f( r1(a ijE max,z),r 2(z))，可以有如下表现形式：
m)f(r 1(a ijE max,z),r 2(z))＝r 1(a ijE max,z)modr 2(z)，
n)f(r 1(a ijE max,z),r 2(z))＝Int(r 1(a ijE max,z)·r 2(z))
以上r 1(a ij E max,z)，r 2(z)和f( r1( aijE max,z),r 2(z))，可以根据各自不同的表现形式，采用不同的组合方式，最终f(r 1(a ij E max,z),r 2(z))的值是小于z的。
(1)对于r1(a ij E max,z)的范围没有被限定的情况，可以进一步进行约束，使得偏移值的结果不大于z，例如，采用r 2(z)和f(r 1(a ijE max,z),r 2(z))，而r 2(z)通常可以选择h)j)k)中的一种，并进一步采用例如f(r 1(a ijE max,z),r 2(z))中m)方式完成对
Figure PCTCN2018075128-appb-000018
的约束；
举例来说，假设
Figure PCTCN2018075128-appb-000019
取采用方式c)，且向下取整，r2(z)采用方式h)，f(r 1(a ijE max,z),r 2(z))采用方式m)，那么a ij满足：
Figure PCTCN2018075128-appb-000020
通过公式(1)可以得到对应于不同z的取值的各个第一矩阵。
而s z的取值可以如表1所示，可以理解的是，表1只是s z的取值的一种示例，而表1所示例的基础上，根据z查表得到的是s z/256的取值，通过进一步的乘法运算便可以得到s z的取值。
表1
Figure PCTCN2018075128-appb-000021
Figure PCTCN2018075128-appb-000022
进一步的，图2给出了用公式(1)和表1的方式，第一信息序列长度从96到8192，码率分别为8/9、5/6、3/4、2/3、1/2、2/5、1/3、1/4和1/5的误块率(BLER)仿真结果，其中，调制方式为正交相移键控(QPSK)，仿真算法为置信度传播(belief propagation，简称BP)算法，迭代次数为50次。
由图2可见，在各个码率和全长度范围内，误块率曲线都比较平滑。
(2)对于r 1(a ij E max,z)的范围被限定的情况，例如f)中，其通过取模运算，取值被限定在了0-z max之间，那么可以采用r 2(z)＝z/z max和
f(r 1(a ijE max,z),r 2(z))＝Int(r 1(a ijE max,z)·r 2(z))进行进一步的修正，也就是说a ij满足：
Figure PCTCN2018075128-appb-000023
图3a-3e为采用公式(2)的方式，第一信息序列长度分别为8000,6000,4000,2000和1000的误块率仿真结果，其中仿真所采用码率包括1/5,1/4,1/3,2/5,1/2,2/3,3/4,5/6,8/9，调制方式为QPSK，算法为BP算法。由图3a-e可以看出，在以上码长和码率内，性能都较好。
可选地，如前所述，为了进一步提升性能，可以使用修正过的扩展因子取值，其中，对扩展因子取值进行修正的方式可能有多种，例如可以通过一个扩展因子偏置值对初始得到的扩展因子z orig进行修正，或者保存允许使用的z的取值，当z orig不属于允许使用的z时，将允许使用的z的取值中大于z orig的最小值作为修正过的扩展因子。
一种可能的实现方式中，z orig例如可以是编码器根据第一信息序列确定出扩展因 子的取值，或者可以是其他功能单元输入给编码器的扩展因子的取值，本申请实施例对此不做限定。本申请实施例中，通过一个扩展因子偏置值对扩展因子取值进行修正，例如，z＝z orig+Δz，其中，Δz为扩展因子偏置值。
Δz的取值可能与不同的因素相关，例如与以下至少一种因素相关：a ij满足的公式，系统需求，z orig等，而Δz的具体取值，可以通过查表的方式获得。
一种示例中，假设
Figure PCTCN2018075128-appb-000024
采用方式b)，其中s z＝0；r 2(z)采用方式k)，f(r 1(a ijE max,z),r 2(z))采用方式m)，那么a ij满足：
Figure PCTCN2018075128-appb-000025
可以通过表2确定Δz以及t的取值，可以理解的是，表2只是一种示例，Δz以及t与z orig的对应关系可以有不同于表2的方式，本申请实施例对此不做限定。
表2
Figure PCTCN2018075128-appb-000026
Figure PCTCN2018075128-appb-000027
Figure PCTCN2018075128-appb-000028
Figure PCTCN2018075128-appb-000029
进一步的，图4给出了采用公式(3)以及表2，第一信息序列长度从96到8000，码率分别为8/9、5/6、3/4、2/3、1/2、2/5、1/3、1/4和1/5的误块率仿真结果，其中，仿真采用的调制方式为QPSK，仿真算法为BP算法，迭代次数为50次。由图4可以看出，经过扩展因子的修正，性能得到了进一步的优化。
上述图2-图4中，Es/No是信噪比，单位是dB，Rate或者CR是码率，information lengthK是信息序列长度。
又一种可能的实现方式中，假设a ij满足公式(1)，可以通过表3确定Δz的取值，可以理解的是，表3只是一种示例，z orig与Δz的对应关系可以有不同于表3的方式，本申请实施例对此不做限定。例如，可以保存Δz为非零的z orig，或者保存Δz为零的z orig。
表3
Figure PCTCN2018075128-appb-000030
Figure PCTCN2018075128-appb-000031
本申请实施例中，通过对z的修正，实现了对z的标注，使得某些特定的z不使用，可以实现更低的BLER。
一种可能的实现方式中，本申请上述各实施例的编码方法适用于QC-LDPC码校验矩阵码校验矩阵。
可以理解的是，上述各编码方法的实施例中的第一矩阵也同样可以适用于译码方法，也就是说，在译码过程中，也会使用与编码过程中相同的矩阵进行译码。一种可能的实现方式中，第一矩阵的获得方式也可以与上述实施例相同。一种示例中，利用第一矩阵对第三信息序列进行译码，得到第四信息序列。一种可能的实现方式中，第三信息序列可以与第二信息序列对应，第四信息序列与第一信息序列对应。
一种可能的实现方式中，该译码方法可以应用于相应的通信方法中，而该通信方法由相应的通信设备实现。
本申请实施例还提供了一种通信方法，该通信方法应用了上述实施例所描述的各种编码方法，如图5所示，可以包括：
S501，对第一信息序列利用第一矩阵进行编码得到第二信息序列。
其中，关于对第一信息序列进行编码的方法可以参考上述各个实施例中的相关描述，此处不再赘述。
可选的，在S501之前也可以包括一些处理，也就是说第一信息序列可以是由经过其他功能单元处理后输入到编码器的，本申请实施例对第一信息序列的来源和内容不做限定。
S502，对第二信息序列进行处理并发送。
一种可能的实现方式中，第二信息序列可以经过比特重排，速率匹配，交织、符号 映射和调制等处理后被发送，图6示意了一种对第一信息序列进行编码并进行一系列处理的过程。可以理解的是，对于不同的系统或者应用场景，对第二信息序列处理的过程可能有所不同，例如，比特重排可以作为可选的处理，本申请实施例不一一对各种处理过程进行举例说明。
本申请实施例中，通过在通信方法中，应用了上述实施例所描述的各种编码方法，可以提升数据传输的性能。
本申请实施例提供了一种装置700，如图7所示，包括：存储器701，用于存储第一信息序列；处理器702，用于对第一信息序列利用第一矩阵进行编码，得到第二信息序列。具体的，处理器702对第一信息序列进行编码的方式可以参考上述各个实施例的相关描述，此处不再赘述。
一种可能的实现方式中，处理器702还用于所述处理器用于根据z＝z orig+Δz确定z，而z orig为初始得到的扩展因子取值，z orig可以是由处理器702根据第一信息序列的长度得到的；或者，一种可能的实现方式中，也可以通过其他功能单元确定z orig的取值后输入给装置700。
本申请实施例还提供了一种装置，包括至少一个处理器以及与所述至少一个处理器耦合的存储器，其中，所述至少一个处理器用于执行存储器中的指令，对第一信息序列利用第一矩阵进行编码，得到第二信息序列。其中，该处理器对第一信息序列进行编码的方式可以参考上述各个实施例的相关描述，此处不再赘述。
一种可能的实现方式中，上述各个实施例中的装置可以为编码器，第二信息序列作为编码器的输出。
本申请实施例还提供了一种通信设备800，如图8所示，可以包括：
编码器801，用于对第一信息序列利用第一矩阵进行编码得到第二信息序列；
至少一个处理器802，用于对所述第二信息序列进行处理；
收发器803，用于发送处理后的第二信息序列。
具体的，编码器801对第一信息序列进行编码的方式可以参考上述各个实施例的相关描述，而编码器的结构和实现方式可以参考前述实施例，此处不再赘述。
一种可能的实现方式中，至少一个处理器802可以实现包括比特重排，速率匹配，交织、符号映射和调制等一系列的处理。可以理解的是，对于不同的系统或者应用场景，处理器802实现的处理过程以及处理器802的组成结构可能有所不同，本申请实施例不一一进行举例说明。
一种可能的实现方式中，通信设备800可以为终端设备或者网络设备。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实 现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本发明实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质，(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质(例如固态硬盘Solid State Disk(SSD))等。
本领域的技术人员可以清楚地了解到本申请实施例中的技术可借助软件加必需的通用硬件平台的方式来实现。基于这样的理解，本申请实施例中的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品可以存储在存储介质中，如ROM/RAM、磁碟、光盘等，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例或者实施例的某些部分所述的方法。
本说明书中各个实施例之间相同相似的部分可以互相参考。
以上所述的本申请实施方式并不构成对本申请保护范围的限定。

Claims (21)

  1. 一种编码方法，其特征在于，包括：
    对第一信息序列利用第一矩阵进行编码得到第二信息序列，其中第一矩阵为尺寸为m bz×n bz的矩阵，其中，z为扩展因子，所述第一矩阵包括m b×n b个尺寸为z×z的子矩阵，m b×n b个尺寸为z×z的子矩阵中至少包括一个尺寸为z×z的单位矩阵的循环位移矩阵，各个所述循环位移矩阵的循环位移值是矩阵E(H)中与所述各个循环位移矩阵对应位置处的元素，其中，矩阵E(H)为
    Figure PCTCN2018075128-appb-100001
    E(H)中的元素a ij满足：
    Figure PCTCN2018075128-appb-100002
    a ij E max为最大扩展因子z max对应的循环位移值矩阵E max(H)中的元素，r 1(a ij E max,z)表示参数为a ij E max和z的函数，r 2(z)表示参数为z的函数，f(r 1(a ij E max,z),r 2(z))表示参数为r 1(a ij E max,z)和r 2(z)的函数，f(r 1(a ij E max,z),r 2(z))的值小于z；
    输出所述第二信息序列。
  2. 根据权利要求1所述的方法，其特征在于，r 1(a ij E max,z)的取值是根据z对应的偏置值与a ij E max之和确定的。
  3. 根据权利要求2所述的方法，其特征在于，r 1(a ij E max,z)包括以下任意一种：
    r 1(a ij,z)＝a ij E max+Int(a ij E max/c)·s z；
    r 1(a ij,z)＝a ij E max+Int(c/a ij E max)·s z；
    r 1(a ij,z)＝a ij E max+Int(s z/a ij E max)；
    r 1(a ij,z)＝a ij E max+Int(a ij E max/z)；
    r 1(a ij,z)＝a ij E max+(z max-a ij E max)·s z；
    r 1(a ij E max,z)＝a ij E max+Int((s z·a ij E max)/c)
    其中，c为预设常数，s Z为与z对应的非负整数，Int()为取整函数。
  4. 根据权利要求3所述的方法，其特征在于，r 2(z)包括以下任意一种：
    r 2(z)＝z；
    Figure PCTCN2018075128-appb-100003
    r 2(z)＝N z；
    其中N z是小于z的正整数，floor为向下取整函数。
  5. 根据权利要求4所述的方法，其特征在于，：
    f(r 1(a ij E max,z),r 2(z))＝r 1(a ij E max,z)mod r 2(z)。
  6. 根据权利要求2所述的方法，其特征在于，r 1(a ij,z)＝(a ij E max+s z)mod z max。
  7. 根据权利要求6所述的方法，其特征在于，r 2(z)＝z/z max。
  8. 根据权利要求7所述的方法，其特征在于，
    f(r 1(a ij E max,z),r 2(z))＝Int(r 1(a ij E max,z)·r 2(z))。
  9. 根据权利要求1-8任一项所述的方法，其特征在于，z＝z orig+Δz，
    其中，Δz为扩展因子偏置值，z orig为初始得到的扩展因子取值。
  10. 一种通信方法，其特征在于，包括：
    应用权利要求1-9任一项所述的编码方法对第一信息序列进行编码，得到第二信息序列；
    对所述第二信息序列进行处理并发送。
  11. 一种装置，其特征在于，包括：
    存储器，用于存储第一信息序列；
    处理器，用于对第一信息序列利用第一矩阵进行编码，得到第二信息序列，其中第一矩阵为尺寸为m bz×n bz的矩阵，其中，z为扩展因子，所述第一矩阵包括m b×n b个尺寸为z×z的子矩阵，m b×n b个尺寸为z×z的子矩阵中至少包括一个尺寸为z×z的单位矩阵的循环位移矩阵，各个所述循环位移矩阵的循环位移值是矩阵E(H)中与所述各个循环位移矩阵对应位置处的元素，其中，矩阵E(H)为
    Figure PCTCN2018075128-appb-100004
    E(H)中的元素a ij满足
    Figure PCTCN2018075128-appb-100005
    a ij E max为最大扩展因子z max对应的循环位移值矩阵E max(H)中的元素，r 1(a ij E max,z)表示参数为a ij E max和z的函数，r 2(z)表示参数为z的函数，f(r 1(a ij E max,z),r 2(z))表示参数为r 1(a ij E max,z)和r 2(z)的函数，f(r 1(a ij E max,z),r 2(z))的值小于z。
  12. 根据权利要求11所述的装置，其特征在于，r 1(a ij E max,z)的取值是根据z对应的偏置值与a ij E max之和确定的。
  13. 根据权利要求12所述的装置，其特征在于，r 1(a ij E max,z)包括以下任意一种：
    r 1(a ij,z)＝a ij E max+Int(a ij E max/c)·s z；
    r 1(a ij,z)＝a ij E max+Int(c/a ij E max)·s z；
    r 1(a ij,z)＝a ij E max+Int(s z/a ij E max)；
    r 1(a ij,z)＝a ij E max+Int(a ij E max/z)；
    r 1(a ij,z)＝a ij E max+(z max-a ij E max)·s z；
    r 1(a ij E max,z)＝a ij E max+Int((s z·a ij E max)/c)
    其中，c为预设常数，s Z为与z对应的非负整数，Int()为取整函数。
  14. 根据权利要求13所述的装置，其特征在于，r 2(z)包括以下任意一种：
    r 2(z)＝z；
    Figure PCTCN2018075128-appb-100006
    r 2(z)＝N z；
    其中N z是小于z的正整数，floor为向下取整函数。
  15. 根据权利要求14所述的装置，其特征在于，：
    f(r 1(a ij E max,z),r 2(z))＝r 1(a ij E max,z)mod r 2(z)。
  16. 根据权利要求12所述的装置，其特征在于，r 1(a ij,z)＝(a ij E max+s z)mod z max。
  17. 根据权利要求16所述的装置，其特征在于，r 2(z)＝z/z max。
  18. 根据权利要求17所述的装置，其特征在于，
    f(r 1(a ij E max,z),r 2(z))＝Int(r 1(a ij E max,z)·r 2(z))。
  19. 根据权利要求11-18任一项所述的装置，其特征在于，所述处理器用于根据z＝z orig+Δz确定z，其中，Δz为扩展因子偏置值，z orig为初始得到的扩展因子取值。
  20. 一种装置，其特征在于，包括至少一个处理器以及与所述至少一个处理器耦合的存储器，其中，
    所述至少一个处理器用于执行存储器中的指令，实现权利要求1-9任一项所述的方法。
  21. 一种通信设备，其特征在于，包括：
    编码器，用于根据权利要求1-9任一项所述的方法对第一信息序列进行编码，得到第二信息序列，并输出所述第二信息序列；
    处理器，用于对所述第二信息序列进行处理；
    收发器，用于发送处理后的第二信息序列。
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