WO2018137224A1 - 晶片封装结构及封装方法 - Google Patents

晶片封装结构及封装方法 Download PDF

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Publication number
WO2018137224A1
WO2018137224A1 PCT/CN2017/072710 CN2017072710W WO2018137224A1 WO 2018137224 A1 WO2018137224 A1 WO 2018137224A1 CN 2017072710 W CN2017072710 W CN 2017072710W WO 2018137224 A1 WO2018137224 A1 WO 2018137224A1
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WIPO (PCT)
Prior art keywords
wafer
adhesive film
protective layer
package structure
disposed
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PCT/CN2017/072710
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English (en)
French (fr)
Inventor
罗军平
Original Assignee
深圳市汇顶科技股份有限公司
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Filing date
Publication date
Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to PCT/CN2017/072710 priority Critical patent/WO2018137224A1/zh
Priority to EP17894547.3A priority patent/EP3435410B1/en
Priority to CN201780005876.7A priority patent/CN108780782A/zh
Publication of WO2018137224A1 publication Critical patent/WO2018137224A1/zh
Priority to US16/170,847 priority patent/US10727196B2/en

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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G06V40/1329—Protecting the fingerprint sensor against damage caused by the finger
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Definitions

  • Embodiments of the present invention relate to the field of packaging technologies, and in particular, to a chip package structure and a packaging method.
  • fingerprint modules require consumers to have higher and higher requirements on their structural strength, that is, they must withstand certain static external forces and external objects.
  • the external force is slowly applied to the fingerprint module through the spherical indenter, and the steel ball is freely falling from a certain height to the fingerprint module to assess the strength of the fingerprint sensor.
  • the existing fingerprint sensor is also difficult to meet the high-strength demand, and it is easy to cause functional failure under the action of static external force and external object impact, and even the wafer is broken.
  • the object of the embodiments of the present invention is to provide a chip package structure and a packaging method, which can improve the overall impact resistance of the wafer, without changing the structure of the carrier, eliminating the cost of mold opening, and having a simple package structure and easy quantitative production.
  • embodiments of the present invention provide a chip package structure and a package method, including: a wafer, a carrier, an adhesive film, and a plastic package; the adhesive film is disposed on a bottom surface of the wafer.
  • the thickness of the adhesive film is greater than or equal to 40 microns; the wafer is disposed on the carrier through the adhesive film; the molded body is disposed on the carrier, and the wafer is coated Top and multiple sides.
  • Embodiments of the present invention also provide a wafer packaging method comprising: providing an adhesive film on a bottom surface of the at least one wafer; the adhesive film has a thickness greater than or equal to 40 microns; passing the wafer through the adhesive The conjunct film is disposed on the carrier; the wafer is plastically sealed by a molding body; wherein the molding body is disposed on the carrier and covers a top surface and a plurality of sides of the wafer to form a chip package structure.
  • the embodiment of the present invention can increase the impact resistance of the whole wafer by increasing the thickness of the adhesive film, that is, increase the strength of the wafer. Moreover, it is not necessary to change the structure of the carrier, the cost of mold opening is omitted, and the package structure is simple, and it is easy to quantify production.
  • the thickness of the adhesive film is less than or equal to 150 microns.
  • the thickness of the adhesive film is too large, wafer tilting tends to occur when the wafer is wired, the production difficulty is increased, and the package yield is lowered. Therefore, in the present embodiment, by limiting the upper limit of the thickness of the adhesive film, It can ensure the strength of the wafer, reduce the production difficulty and improve the packaging yield.
  • the total thickness of the wafer and the adhesive film is equal to a first predetermined value. This can keep the total thickness of the chip package structure constant, thereby avoiding the influence on the design or manufacture of the electronic device to which the chip package structure is applied after the total thickness of the chip package structure is increased.
  • the chip package structure further includes a protective layer; the protective layer is disposed on a top surface of the wafer and is covered by the molding body.
  • the protective layer can protect the wafer well, better resist external impact damage, and further improve the overall strength.
  • a total thickness of a portion of the molding body covering the protective layer and the protective layer is equal to a second predetermined value. This allows the total height of the protective layer and the molded body above it to be constant, thereby making the performance of the wafer unaffected, and also contributing to keeping the total thickness of the package constant.
  • the bottom surface of the wafer is a smooth surface. This can effectively reduce the scratches, that is, reduce the crack source (when the wafer is subjected to external pressure, the scratch is more likely to crack), thereby improving the wafer strength.
  • FIG. 1 is a schematic view of a wafer package structure in accordance with a first embodiment of the present invention
  • FIG. 2 is a schematic view of a wafer package structure in accordance with a third embodiment of the present invention.
  • FIG. 3 is a flow chart of a wafer packaging method in accordance with a sixth embodiment of the present invention.
  • FIG. 4 is a flow chart of a method of packaging a wafer in accordance with a seventh embodiment of the present invention.
  • FIG. 5 is a flow chart of a wafer packaging method according to an eighth embodiment of the present invention.
  • FIG. 6 is a flow chart of a wafer packaging method in accordance with a ninth embodiment of the present invention.
  • a first embodiment of the present invention relates to a wafer package structure, as shown in FIG. 1, a wafer 1, a carrier 2, an adhesive film 3, and a molded body 4.
  • the adhesive film 3 is disposed on the bottom surface of the wafer 1, and the thickness a of the adhesive film 3 is greater than or equal to 40 micrometers; the wafer 1 is disposed on the carrier 2 through the adhesive film 3; the molded body 4 It is disposed on the carrier 2 and covers the top surface and the plurality of sides of the wafer 1.
  • Both surfaces of the adhesive film 3 may have adhesive glue, one side of the adhesive film 3 is attached to the carrier 2, and the other side is attached to the bottom surface of the wafer 1, so that the wafer 1 can be placed on the carrier 2.
  • the adhesive film 3 may be a soft material, so that the external object is shocked.
  • the wafer 1 is well buffered, and by increasing the thickness a of the adhesive film 3, the overall impact resistance can be improved, that is, the strength of the wafer 1 is improved.
  • the present embodiment can increase the impact resistance of the wafer 1 as a whole by increasing the thickness a of the adhesive film 3, that is, increase the strength of the wafer 1. Moreover, it is not necessary to change the structure of the carrier 2, the cost of mold opening is omitted, and the package structure is simple, and it is easy to quantify production.
  • a second embodiment of the present invention is directed to a chip package structure.
  • the second embodiment is improved on the basis of the first embodiment, and is improved in that, in the present embodiment, a preferred implementation of the adhesive film 3 and the carrier 2 is provided, with reference to FIG.
  • the thickness a of the adhesive film 3 in the present embodiment is greater than or equal to 40 ⁇ m, so that increasing the thickness a of the adhesive film 3 can increase the strength of the wafer 1.
  • the thickness a of the adhesive film 3 is less than or equal to 150 micrometers, that is, the thickness a of the adhesive film 3 is controlled in the range of 40 micrometers to 150 micrometers, so that the strength of the wafer 1 can be ensured, the production difficulty can be reduced, and the package yield can be improved.
  • the total thickness of the wafer 1 and the adhesive film 3 is equal to a first predetermined value (as in FIG. 1, the thickness of the adhesive film 3 is a, the thickness of the wafer 1 is b, and the sum of a and b is equal to the first preset.
  • the value of the first preset value in this embodiment may be determined according to actual needs, for example, the height of the wafer and the adhesive film in the prior art, that is, when the thickness a of the adhesive film 3 is larger.
  • the thickness b of the wafer 1 can be correspondingly reduced, the total thickness of the chip package structure can be kept constant, so that the design of the electronic device to which the chip package structure may be applied after the total thickness of the chip package structure is increased can be avoided. Or the impact of manufacturing and other aspects.
  • the carrier 2 in this embodiment may be a substrate.
  • the carrier 2 may also be a lead frame, which is not limited in this embodiment.
  • This embodiment provides a preferred implementation of the adhesive film 3 and the carrier 2.
  • the strength of the wafer 1 can be ensured, the production difficulty can be reduced, and the package yield can be improved.
  • the total thickness of the chip package structure remains unchanged, thereby avoiding the influence on the design or manufacture of the electronic device to which the chip package structure is applied after the total thickness of the chip package structure is increased.
  • a third embodiment of the present invention relates to a chip package structure.
  • the third embodiment is improved on the basis of the first embodiment.
  • the improvement is that in the embodiment, the wafer 1 package structure further includes a protective layer 5, as shown in FIG. 2:
  • the protective layer 5 in this embodiment may be disposed on the top surface of the wafer 1 and covered by the molding body 4.
  • the protective layer 5 may be a polyimide material, so that the wafer can be 1 plays a very good role in protecting against external impact damage to improve overall strength.
  • the total thickness of the portion of the plastic body 4 covering the protective layer 5 and the protective layer 5 is equal to a second predetermined value (such as the thickness of the protective layer 5 in FIG. 2 is c, and the thickness of the portion of the plastic sealing body 4 covering the protective layer 5)
  • a second predetermined value such as the thickness of the protective layer 5 in FIG. 2 is c, and the thickness of the portion of the plastic sealing body 4 covering the protective layer 5
  • the sum of c and d is a second preset value.
  • the second preset value may be determined according to actual needs.
  • the molded body in the prior art chip package structure corresponds to The height of the portion of the top surface of the wafer.
  • the thickness c of the protective layer 5 may be greater than or equal to 1 micrometer and less than or equal to 20 micrometers.
  • the thickness d of the molding body 4 above the protective layer 5 may be appropriately reduced. So that the sum of the thicknesses of the protective layer 5 and the molded body 4 above it is equal to the second predetermined value, that is, the sum of the thicknesses of the protective layer 5 and the molded body 4 above it can be kept constant, so that the performance of the wafer 1 is not affected. .
  • the protective layer 5 can protect the wafer 1 well, better resist external impact damage, and improve the overall strength.
  • the portion of the plastic body 4 covering the protective layer 5 With the total thickness of the protective layer 5, the total height of the protective layer 5 and the molded body 4 above it can be made constant, so that the performance of the wafer is not affected, and it is also advantageous to keep the total thickness of the package constant.
  • a fourth embodiment of the present invention relates to a chip package structure.
  • the fourth embodiment is improved on the basis of the first embodiment, and the improvement is that in the present embodiment, the bottom surface of the wafer 1 is a smooth surface, referring to FIG. 1:
  • the wafer 1 is ground to a specified thickness in the wafer 1 packaging process, a lot of scratches are left on the bottom of the wafer 1, and these scratches are often the origin of the crack of the wafer 1, when the wafer 1 is subjected to the outside.
  • the wafer 1 is easily broken, so that the bottom surface of the wafer 1 can be polished.
  • the bottom surface of the wafer 1 is a smooth surface, which can effectively reduce the scratches, that is, reduce the crack source, thereby increasing the strength of the wafer 1.
  • This embodiment can effectively reduce scratches, that is, reduce the source of cracks (when the wafer is subjected to external pressure, cracks are more likely to occur at the scratches), thereby increasing the strength of the wafer 1.
  • a fifth embodiment of the present invention relates to a chip package structure.
  • the fifth embodiment is improved on the basis of the first embodiment.
  • the improvement is that in the embodiment, the substrate and the adhesive film 3 can be made of a high modulus material, and referring to FIG. 1:
  • the modulus of the substrate may be greater than 20 GPa, and the modulus of the adhesive film 3 may be greater than 4 MPa, so that the elastic deformation of the substrate and the adhesive film 3 is greatly reduced under a certain stress. Small, that is, the rigidity of the substrate and the adhesive film 3 can be improved.
  • a preferred embodiment of the substrate and the adhesive film 3 is provided in this embodiment, and the rigidity of the substrate and the adhesive film 3 can be improved.
  • a sixth embodiment of the present invention relates to a chip packaging method, the flow of which is shown in FIG. 3, and the details are as follows:
  • an adhesive film is provided on the bottom surface of at least one of the wafers.
  • the thickness of the medium adhesive film is greater than or equal to 40 microns, and both surfaces of the adhesive film may have a viscous glue.
  • step 302 the wafer is placed on the carrier through an adhesive film.
  • one side of the adhesive film can be attached to the carrier, and the other side can be attached to the bottom surface of the wafer so that the wafer can be placed on the carrier.
  • the wafer is molded with a plastic body.
  • the molding body is disposed on the carrier and covers the top surface and the plurality of side surfaces of the wafer to form a chip package structure.
  • the plurality of wafers to be packaged are often connected together, that is, they can be connected wafers.
  • the adhesive film can be attached to the bottom surface of the continuous wafer, and then the individual wafers are cut to obtain a single crystal wafer (at this time, the bottom surface of each of the single crystal wafers is adhered with an adhesive layer), wherein the single crystal wafer That is, the wafer described in the present application; then, a plurality of single-chip wafers are disposed on a carrier (substrate or lead frame), and a plurality of single-crystal wafers are injection-molded; and finally, a single-chip package structure is obtained by cutting.
  • the single chip package structure is the chip package structure described in the present application.
  • the present embodiment can increase the impact resistance of the entire wafer by increasing the thickness of the adhesive film, that is, increase the strength of the wafer. Moreover, it is not necessary to change the structure of the carrier, the cost of mold opening is omitted, and the package structure is simple, and it is easy to quantify production.
  • the embodiment is a method embodiment corresponding to the first embodiment, and the embodiment can be implemented in cooperation with the first embodiment.
  • the related technical details mentioned in the first embodiment are still effective in this embodiment, and are not described herein again in order to reduce repetition. Accordingly, the related art details mentioned in the embodiment can also be applied to the first embodiment.
  • a seventh embodiment of the present invention relates to a wafer packaging method.
  • the seventh embodiment is improved on the basis of the sixth embodiment, and the improvement is that in the embodiment, the bottom surface of the wafer can be ground before the adhesive film is disposed on the bottom surface of the wafer, the wafer of the embodiment
  • the flow of the encapsulation method is shown in Figure 4, as follows:
  • the bottom surface of the wafer is ground; wherein the polished wafer and the adhesive film
  • the total thickness is equal to the first preset value.
  • the height of the wafer can be reduced by grinding the bottom surface of the wafer.
  • the wafer can be ground to the height in the prior art, and then the height is increased to the height in the case, so that the The total thickness of the wafer and the adhesive film is equal to the first predetermined value.
  • the first preset value in this embodiment may be determined according to actual needs.
  • the height of the wafer and the adhesive film in the prior art may also be That is to say, when the thickness of the adhesive film is large, the thickness of the wafer can be correspondingly reduced, so that the total thickness of the package structure can be kept constant, so that the chip package can be packaged after the total thickness of the package structure is increased.
  • the impact of the design or manufacture of electronic devices used in the structure may also be That is to say, when the thickness of the adhesive film is large, the thickness of the wafer can be correspondingly reduced, so that the total thickness of the package structure can be kept constant, so that the chip package can be packaged after the total thickness of the package structure is increased.
  • an adhesive film is disposed on the bottom surface of at least one of the wafers.
  • both surfaces of the adhesive film in the embodiment may have a viscous adhesive, the thickness of the adhesive film being greater than or equal to 40 micrometers and less than or equal to 150 micrometers, and the modulus of the adhesive film may be greater than 4 MPa.
  • the wafer is placed on the carrier through an adhesive film.
  • the carrier in this embodiment may be a substrate, and the modulus of the substrate may be greater than 20 GPa.
  • One side of the adhesive film may be attached to the carrier, and the other side may be attached to the bottom surface of the wafer so that the wafer can be placed on the carrier.
  • the carrier in this embodiment may be a lead frame, which is not limited in this embodiment.
  • the wafer is molded with a molding.
  • the molding body is disposed on the carrier and covers the top surface and the plurality of side surfaces of the wafer to form a chip package structure.
  • the bottom surface of the wafer when the bottom surface of the wafer is polished, the bottom surface of the wafer may be ground.
  • the bottom surface of the wafer may be ground before the adhesive film is disposed on the bottom surface of the wafer, so that the total thickness of the polished wafer and the adhesive film is equal to a first predetermined value, so that the total thickness of the wafer package structure can be maintained. The same is unchanged, so that the influence on the design or manufacture of the electronic device to which the chip package structure is applied may be avoided after the total thickness of the chip package structure is increased. Moreover, by defining the upper limit of the thickness of the adhesive film, both the strength of the wafer and the production can be reduced. Difficulty, improve packaging yield.
  • the present embodiment can be implemented in cooperation with the second embodiment.
  • the technical details mentioned in the second embodiment are still effective in this embodiment, and the technical effects that can be achieved in the second embodiment can also be implemented in the embodiment. To reduce the repetition, details are not described herein again. Accordingly, the related art details mentioned in the embodiment can also be applied to the second embodiment.
  • An eighth embodiment of the present invention relates to a chip packaging method.
  • the eighth embodiment is improved on the basis of the sixth embodiment.
  • the improvement is that in the embodiment, the protective layer can be disposed on the top surface of the wafer before the adhesive film is disposed on the bottom surface of the wafer.
  • the flow of the chip packaging method is shown in Figure 5, as follows:
  • a protective layer is disposed on the top surface of the wafer.
  • a protective layer may be disposed on the top surface of the wafer by spraying or spin coating, and the protective layer may be a polyimide material, so that the wafer can be well protected, and better. Resist external impact damage to increase overall strength.
  • an adhesive film is disposed on a bottom surface of at least one of the wafers.
  • the thickness of the adhesive film in the present embodiment is greater than or equal to 40 ⁇ m, and both surfaces of the adhesive film may have a viscous adhesive.
  • step 503 the wafer is placed on the carrier through an adhesive film.
  • one side of the adhesive film can be attached to the carrier, and the other side can be attached to the bottom surface of the wafer so that the wafer can be placed on the carrier.
  • the wafer is molded with a molding.
  • the molding body is disposed on the carrier and covers the top surface and the plurality of side surfaces of the wafer to form a chip package structure.
  • the total thickness of the portion of the molded body covered with the protective layer and the protective layer is equal to the second predetermined value.
  • the second preset value may be determined according to actual needs, for example, the height of the portion of the prior art wafer package structure corresponding to the top surface of the wafer.
  • the thickness of the protective layer may be greater than or equal to micron And less than or equal to 20 micrometers, such that when the thickness of the protective layer is large, the thickness of the molding body above the protective layer can be appropriately reduced, so that the total thickness of the protective layer and the molded body above it is equal to the second preset value. That is, the sum of the thicknesses of the protective layer and the molded body above it can be kept constant, so that the performance of the wafer is not affected.
  • a protective layer may be disposed on the top surface of the polished wafer.
  • the protective layer can protect the wafer well, better resist external impact damage, and improve the overall strength, by defining a portion of the plastic body covering the protective layer and the total of the protective layer.
  • the thickness is such that the total height of the protective layer and the molded body above it is constant, so that the performance of the wafer is not affected, and it is advantageous to keep the total thickness of the package constant.
  • This embodiment is an embodiment of the method corresponding to the third embodiment. This embodiment can be implemented in cooperation with the third embodiment.
  • the related technical details mentioned in the third embodiment are still effective in this embodiment, and are not described herein again in order to reduce repetition. Accordingly, the related art details mentioned in the embodiment can also be applied to the third embodiment.
  • a ninth embodiment of the invention relates to a wafer packaging method.
  • the ninth embodiment is improved on the basis of the sixth embodiment, and the improvement is that in the embodiment, the bottom surface of the wafer can be polished to form a smooth surface before the adhesive film is disposed on the bottom surface of the wafer.
  • the flow of the wafer packaging method of the embodiment is as shown in FIG. 6, and the details are as follows:
  • step 601 the bottom surface of the wafer is polished to form a smooth surface.
  • an adhesive film is disposed on a bottom surface of at least one of the wafers.
  • the thickness of the adhesive film in the present embodiment is greater than or equal to 40 ⁇ m, and both surfaces of the adhesive film may have a viscous adhesive.
  • step 603 the wafer is placed on the carrier through an adhesive film.
  • one side of the adhesive film may be attached to the carrier, and the other side may be attached to the bottom surface of the wafer, wherein the smooth surface of the wafer faces the adhesive film, so that the wafer can be placed on the carrier.
  • the wafer is molded with a molding.
  • the molding body is disposed on the carrier and covers the top surface and the plurality of side surfaces of the wafer to form a chip package structure.
  • the embodiment may also be improved on the basis of the seventh embodiment, that is, in this embodiment, the bottom surface of the polished wafer may be polished to form a smooth surface.
  • the embodiment can also be improved on the basis of the eighth embodiment, that is, in this embodiment, the bottom surface of the wafer may be polished after the protective layer is disposed on the top surface of the wafer to form a smooth surface.
  • This embodiment can be used for polishing at the bottom of the wafer.
  • the bottom surface of the wafer is a smooth surface, which can effectively reduce scratches, that is, reduce the source of cracks (when the wafer is subjected to external pressure, cracks are more likely to occur at the scratches), thereby increasing the strength of the wafer.
  • This embodiment is an embodiment of the method corresponding to the fourth embodiment. This embodiment can be implemented in cooperation with the fourth embodiment.
  • the related technical details mentioned in the fourth embodiment are still effective in this embodiment, and are not described herein again in order to reduce repetition. Accordingly, the related art details mentioned in the embodiment can also be applied to the fourth embodiment.
  • a program instructing related hardware may be completed by a program instructing related hardware, and the program is stored in a storage medium, and includes a plurality of instructions for making a device (which may be a single chip microcomputer). , a chip, etc. or a processor performs all or part of the steps of the methods described in various embodiments of the present application.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like. .

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Abstract

提供了一种晶片封装结构及封装方法。晶片封装结构包括：晶片（1）、载体（2）、粘结膜（3）以及塑封体（4）；粘结膜（3）设置在晶片（1）的底面上，粘结膜（3）的厚度大于或等于40微米；晶片（1）通过粘结膜（3）设置在载体（2）上；塑封体（4）设置在载体（2）上，且包覆晶片（1）的顶面及多个侧面。还提供了一种晶片封装方法，现对于现有技术，可以提高晶片整体的抗冲击能力，而且无需改变载体的结构，省去开模的费用，且封装结构简单，易于量化生产。

Description

晶片封装结构及封装方法 技术领域
本发明实施例涉及封装技术领域，特别涉及晶片封装结构及封装方法。
背景技术
指纹模组作为手机、平板电脑等电子设备中重要的一个外观元器件，消费者对其结构强度提出越来越高的要求，即需承受一定静压外力和外界物体冲击破坏作用。实际中，会通过球形压头缓慢施加外力在指纹模组上，还有将钢球从一定高度自由落体砸在指纹模组上来考核指纹传感器的强度。
在实现本发明过程中，发明人发现现有技术中至少存在如下问题：
现有指纹传感器还很难满足高强度的需求，很容易在静压外力和外界物体冲击作用下发生功能失效，甚至晶片发生破裂现象。
发明内容
本发明实施例的目的在于提供一种晶片封装结构及封装方法，可以提高晶片整体的抗冲击能力，而且无需改变载体的结构，省去开模的费用，且封装结构简单，易于量化生产。
为解决上述技术问题，本发明的实施例提供了一种晶片封装结构及封装方法，包括：晶片、载体、粘结膜以及塑封体；所述粘结膜设置在所述晶片的底面上，所述粘结膜的厚度大于或等于40微米；所述晶片通过所述粘结膜设置在所述载体上；所述塑封体设置在所述载体上，且包覆所述晶片的 顶面及多个侧面。
本发明的实施例还提供了一种晶片封装方法，包括：在所述至少一晶片的底面设置粘结膜；所述粘结膜的厚度大于或等于40微米；将所述晶片通过所述粘结膜设置在载体上；利用塑封体对所述晶片进行塑封；其中，所述塑封体设置于所述载体且包覆所述晶片的顶面及多个侧面，形成晶片封装结构。
本发明实施例相对于现有技术而言，通过增加粘结膜的厚度可以提高晶片整体的抗冲击能力，即提高晶片的强度。而且无需改变载体的结构，省去开模的费用，且封装结构简单，易于量化生产。
另外，所述粘结膜的厚度小于或等于150微米。由于当粘结膜的厚度过大时，在晶片打线时容易发生晶片倾斜，生产难度加大，使封装良率下降，因此，本实施例中通过限定粘结膜厚度的上限值，既能保证晶片的强度，又可以降低生产难度，提高封装良率。
另外，所述晶片与所述粘结膜的总厚度等于第一预设值。这样可以使得晶片封装结构的总厚度保持不变，从而可以避免晶片封装结构总厚度增大后，可能对该晶片封装结构所应用的电子设备的设计或制造等方面产生的影响。
另外，所述晶片封装结构还包括保护层；所述保护层设置在所述晶片的顶面上，且被所述塑封体包覆在内。通过保护层可以对晶片起到很好的保护作用，更好地抵抗外界冲击损坏，进一步提高整体强度。
另外，所述塑封体中包覆所述保护层的部分与所述保护层的总厚度等于第二预设值。这样可以使保护层和其上方的塑封体的总高度不变，进而使得晶片的性能不受影响，而且，有利于使封装总厚度保持不变。
另外，所述晶片的底面为光滑表面。这样可以有效减少划痕，即减少裂纹源(晶片受到外界压力时，划痕处较容易产生裂纹)，从而提高晶片的 强度。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1是根据本发明第一实施例的晶片封装结构的示意图；
图2是根据本发明第三实施例的晶片封装结构的示意图；
图3是根据本发明第六实施例的晶片封装方法的流程图；
图4是根据本发明第七实施例的晶片封装方法的流程图；
图5是根据本发明第八实施例的晶片封装方法的流程图；
图6是根据本发明第九实施例的晶片封装方法的流程图。
具体实施例
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合附图对本发明的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本发明各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
本发明的第一实施例涉及一种晶片封装结构，如图1所示：晶片1、载体2、粘结膜3以及塑封体4。
具体地说，本实施例中，粘结膜3设置在晶片1的底面上，粘结膜3的厚度a大于或等于40微米；晶片1通过粘结膜3设置在载体2上；塑封体4 设置在载体2上，且包覆晶片1的顶面及多个侧面。
粘结膜3的两个表面均可以具有粘性胶，粘结膜3的一面粘贴在载体2上，另一面粘贴在晶片1的底面上，从而可以将晶片1设置在载体2上。由于在实际应用中，当外界物体冲击晶片1时，晶片1上电路层很容易损坏，甚至整个晶片1出现破裂，本实施例中，粘结膜3可以为软材质，这样在外界物体冲击瞬间，对晶片1起到很好的缓冲作用，而且通过加粘结膜3的厚度a可以提高整体的抗冲击能力，即提高了晶片1的强度。
本实施例相对于现有技术而言，通过增加粘结膜3的厚度a可以提高晶片1整体的抗冲击能力，即提高晶片1的强度。而且无需改变载体2的结构，省去开模的费用，且封装结构简单，易于量化生产。
本发明的第二实施例涉及一种晶片封装结构。第二实施例在第一实施例的基础上作了改进，改进之处在于：在本实施例中，提供了粘结膜3和载体2的一种优选的实现方式，参考图1。
具体地说，本实施例中的粘结膜3的厚度a大于或等于40微米，这样，增大了粘结膜3的厚度a可以提高晶片1的强度。然而，当粘结膜3的厚度a过大时，在晶片1打线时容易发生晶片1倾斜，生产难度加大，使封装良率下降，优选的，粘结膜3的厚度a小于或等于150微米，即将粘结膜3的厚度a控制40微米～150微米范围内，这样，既能保证晶片1的强度，又可以降低生产难度，提高封装良率。
优选的，晶片1与粘结膜3的总厚度等于第一预设值(如图1中粘结膜3的厚度为a，晶片1的厚度为b，a与b的和等于第一预设值)，本实施例中的第一预设值可以根据实际需要而定，比如说：可以为现有技术中晶片与粘结膜的高度，也就是说，当粘结膜3厚度a较大时，可以相应减小晶片1的厚度b，这样可以使得晶片封装结构的总厚度保持不变，从而可以避免晶片封装结构总厚度增大后，可能对该晶片封装结构所应用的电子设备的设计 或制造等方面产生的影响。
其中，本实施例中的载体2可以为基板，当然，载体2也可以为引线框架，本实施例中不做限定。
本实施例提供了粘结膜3和载体2的一种优选的实现方式，通过限定粘结膜3厚度的上限值，既能保证晶片1的强度，又可以降低生产难度，提高封装良率。而且晶片封装结构的总厚度保持不变，从而可以避免晶片封装结构总厚度增大后，可能对该晶片封装结构所应用的电子设备的设计或制造等方面产生的影响。
本发明的第三实施例涉及一种晶片封装结构。第三实施例在第一实施例的基础上作了改进，改进之处在于：在本实施例中，晶片1封装结构还包括保护层5，如图2所示：
具体地说，本实施例中的保护层5可以设置在晶片1的顶面上，且被塑封体4包覆在内，优选的，保护层5可以为聚酰亚胺材料，这样可以对晶片1起到很好的保护作用，更好地抵抗外界冲击损坏，以提高整体强度。
塑封体4中包覆保护层5的部分与保护层5的总厚度等于第二预设值(如图2中保护层5的厚度为c，塑封体4中包覆保护层5的部分的厚度为d的，c与d的和为第二预设值)，具体地说，第二预设值可以根据实际需要而定，比如说：可以为现有技术的晶片封装结构中塑封体对应于晶片顶面的部分的高度。在本实施例中，保护层5的厚度c可以大于或等于1微米且小于或等于20微米，当保护层5的厚度c较大时，可以适当减少保护层5上方的塑封体4的厚度d，以使得保护层5和其上方的塑封体4的厚度总和等于第二预设值，即可以保持保护层5和其上方的塑封体4的厚度总和不变，使得晶片1的性能不受影响。
本实施例中通过保护层5可以对晶片1起到很好的保护作用，更好地抵抗外界冲击损坏，提高整体强度，通过限定塑封体4中包覆保护层5的部分 与保护层5的总厚度，这样可以使保护层5和其上方的塑封体4的总高度不变，进而使得晶片的性能不受影响，而且，也有利于使封装总厚度保持不变。
本发明的第四实施例涉及一种晶片封装结构。第四实施例在第一实施例的基础上作了改进，改进之处在于：在本实施例中，晶片1的底面为光滑表面，参考图1：
具体地说，由于在晶片1封装工艺中，会将晶片1研磨到指定的厚度，这样会在晶片1底部留下很多划痕，这些划痕往往是晶片1破裂的起源，当晶片1受到外界静压力时，晶片1就很容易出现破裂，所以可以在晶片1底部进行抛光使用晶片1的底面为光滑表面，可以有效减少划痕，即减少裂纹源，从而提高晶片1强度。
本实施例可以有效减少划痕，即减少裂纹源(晶片受到外界压力时，划痕处较容易产生裂纹)，从而提高晶片1的强度。
本发明的第五实施例涉及一种晶片封装结构。第五实施例在第一实施例的基础上作了改进，改进之处在于：在本实施例中，基板和粘结膜3可以选用高模量材料，参考图1：
具体地说，在本实施例中，基板的模量可以大于20GPa，粘结膜3的模量可以大于4MPa，这样，在一定应力作用下，基板和粘结膜3发生弹性的变形将大大减小，即可以提高基板和粘结膜3的刚度。
本实施例中提供了基板和粘结膜3的一种优选的实现方式，可以提高基板和粘结膜3的刚度。
本发明第六实施例涉及一种晶片封装方法，其流程如图3所示，具体如下：
在步骤301中，在至少一晶片的底面设置粘结膜。具体地说，本实施例 中粘结膜的厚度大于或等于40微米，且粘结膜的两个表面均可以具有粘性胶。
在步骤302中，将晶片通过粘结膜设置在载体上。具体地说，可以将粘结膜的一面粘贴在载体上，另一面粘贴在晶片的底面上，从而可以将晶片设置在载体上。
在步骤303中，利用塑封体对晶片进行塑封。其中，塑封体设置于载体且包覆晶片的顶面及多个侧面，形成晶片封装结构。
待封装的多个晶片常常是连接在一起的，即可以成为连体晶片。粘结膜可以贴在连体晶片的底面上，然后在对连体晶片进行切割得到单体晶片(此时，各单体晶片的底面均黏贴有黏胶层)，其中，该单体晶片即本申请中所述的晶片；然后再将多个单体晶片设置在载体(基板或引线框架)上，对多个单体晶片进行注塑封装；最后再切割得到单体晶片封装结构，其中，该单体晶片封装结构即本申请所述的晶片封装结构。
本实施例相对于现有技术而言，通过增加粘结膜的厚度可以提高晶片整体的抗冲击能力，即提高晶片的强度。而且无需改变载体的结构，省去开模的费用，且封装结构简单，易于量化生产。
不难发现，本实施例为与第一实施例相对应的方法实施例，本实施例可与第一实施例互相配合实施。第一实施例中提到的相关技术细节在本实施例中依然有效，为了减少重复，这里不再赘述。相应地，本实施例中提到的相关技术细节也可应用在第一实施例中。
本发明第七实施例涉及一种晶片封装方法。第七实施例在第六实施例的基础上作了改进，改进之处在于：在本实施例中，可以在晶片的底面设置粘结膜之前先对晶片的底面进行研磨，本实施例的晶片封装方法的流程如图4所示，具体如下：
在步骤401中，对晶片的底面进行研磨；其中，研磨后的晶片与粘结膜 的总厚度等于第一预设值。具体地说，可以通过对晶片的底面进行研磨以降低晶片的高度，本实施例中，可以先将晶片研磨到现有技术中的高度，再继续研磨到本案中的高度，以使得研磨后的晶片与粘结膜的总厚度等于第一预设值，本实施例中的第一预设值可以根据实际需要而定，比如说：可以为现有技术中晶片与粘结膜的高度，也就是说，当粘结膜厚度较大时，可以相应减小晶片的厚度，这样可以使得晶片封装结构的总厚度保持不变，从而可以避免晶片封装结构总厚度增大后，可能对该晶片封装结构所应用的电子设备的设计或制造等方面产生的影响。
在步骤402中，在至少一晶片的底面设置粘结膜。具体地说，本实施例中粘结膜的两个表面均可以具有粘性胶，粘结膜的厚度大于或等于40微米且小于或等于150微米，且粘结膜的模量可以大于4MPa。
在步骤403中，将晶片通过粘结膜设置在载体上。具体地说，本实施例中的载体可以为基板，该基板的模量可以大于20GPa。可以将粘结膜的一面粘贴在载体上，另一面粘贴在晶片的底面上，从而可以将晶片设置在载体上。
本实施例中的载体可以为引线框架，本实施例中不做限定。
在步骤404中，利用塑封体对晶片进行塑封。其中，塑封体设置于载体且包覆晶片的顶面及多个侧面，形成晶片封装结构。
本实施例中对晶片的底面进行研磨时可以是对连体晶片的底面进行研磨。
本实施例可以在晶片的底面设置粘结膜之前先晶片的底面进行研磨，以使得研磨后的晶片与粘结膜的总厚度等于第一预设值，这样可以使得晶片封装结构的总厚度保持不变，从而可以避免晶片封装结构总厚度增大后，可能对该晶片封装结构所应用的电子设备的设计或制造等方面产生的影响。而且，通过限定粘结膜厚度的上限值，既能保证晶片的强度，又可以降低生产 难度，提高封装良率。
由于第二实施例与本实施例相互对应，因此本实施例可与第二实施例互相配合实施。第二实施例中提到的相关技术细节在本实施例中依然有效，在第二实施例中所能达到的技术效果在本实施例中也同样可以实现，为了减少重复，这里不再赘述。相应地，本实施例中提到的相关技术细节也可应用在第二实施例中。
本发明第八实施例涉及一种晶片封装方法。第八实施例在第六实施例的基础上作了改进，改进之处在于：在本实施例中，可以在晶片的底面设置粘结膜之前先在晶片的顶面设置保护层，本实施例的晶片封装方法的流程如图5所示，具体如下：
在步骤501中，在晶片的顶面设置保护层。具体地说，本实施例中可以使用采用喷涂或旋涂方式在晶片的顶面设置保护层，保护层可以为聚酰亚胺材料，这样可以对晶片起到很好的保护作用，更好地抵抗外界冲击损坏，以提高整体强度。
在步骤502中，在至少一晶片的底面设置粘结膜。具体地说，本实施例中粘结膜的厚度大于或等于40微米，且粘结膜的两个表面均可以具有粘性胶。
在步骤503中，将晶片通过粘结膜设置在载体上。具体地说，可以将粘结膜的一面粘贴在载体上，另一面粘贴在晶片的底面上，从而可以将晶片设置在载体上。
在步骤504中，利用塑封体对晶片进行塑封。其中，塑封体设置于载体且包覆晶片的顶面及多个侧面，形成晶片封装结构。具体地说，本实施例中塑封体中包覆保护层的部分与保护层的总厚度等于第二预设值。第二预设值可以根据实际需要而定，比如说，可以为现有技术的晶片封装结构中塑封体对应于晶片顶面的部分的高度。优选的，保护层的厚度可以大于或等于微米 且小于或等于20微米，这样，当保护层的厚度较大时，可以适当减少保护层上方的塑封体的厚度，以使得保护层和其上方的塑封体的厚度总和等于第二预设值，即可以保持保护层和其上方的塑封体的厚度总和不变，使得晶片的性能不受影响。
需要说明的是，本实施例也可以在第六实施例的基础上做改进，即:本实施例中也可以是在研磨后的晶片的顶面设置保护层。
本实施例中通过保护层可以对晶片起到很好的保护作用，更好地抵抗外界冲击损坏，提高整体强度，通过限定塑封体中包覆所述保护层的部分与所述保护层的总厚度，这样可以使保护层和其上方的塑封体的总高度不变，进而使得晶片的性能不受影响，而且，有利于使封装总厚度保持不变。
本实施例为与第三实施例相对应的方法实施例，本实施例可与第三实施例互相配合实施。第三实施例中提到的相关技术细节在本实施例中依然有效，为了减少重复，这里不再赘述。相应地，本实施例中提到的相关技术细节也可应用在第三实施例中。
本发明第九实施例涉及一种晶片封装方法。第九实施例在第六实施例的基础上作了改进，改进之处在于：在本实施例中，可以在晶片的底面设置粘结膜之前先对晶片的底面进行抛光以形成光滑表面，本实施例的晶片封装方法的流程如图6所示，具体如下：
在步骤601中，对晶片的底面进行抛光以形成光滑表面。
在步骤602中，在至少一晶片的底面设置粘结膜。具体地说，本实施例中粘结膜的厚度大于或等于40微米，且粘结膜的两个表面均可以具有粘性胶。
在步骤603中，将晶片通过粘结膜设置在载体上。具体地说，可以将粘结膜的一面粘贴在载体上，另一面粘贴在晶片的底面上，其中，晶片的光滑表面面对粘结膜，从而可以将晶片设置在载体上。
在步骤604中，利用塑封体对晶片进行塑封。其中，塑封体设置于载体且包覆晶片的顶面及多个侧面，形成晶片封装结构。
需要说明的是，本实施例也可以在第七实施例的基础上做改进，即：本实施例中也可以是对研磨后的晶片的底面进行抛光以形成光滑表面。当然，本实施例也可以在第八实施例的基础上做改进，即：本实施例中也可以是对晶片的顶面设置保护层之后再对晶片的底面进行抛光以形成光滑表面。
本实施例可以在晶片底部进行抛光使用晶片的底面为光滑表面，这样可以有效减少划痕，即减少裂纹源(晶片受到外界压力时，划痕处较容易产生裂纹)，从而提高晶片的强度。
本实施例为与第四实施例相对应的方法实施例，本实施例可与第四实施例互相配合实施。第四实施例中提到的相关技术细节在本实施例中依然有效，为了减少重复，这里不再赘述。相应地，本实施例中提到的相关技术细节也可应用在第四实施例中。
本领域技术人员可以理解实现上述实施例方法中的全部或部分步骤是可以通过程序来指令相关的硬件来完成，该程序存储在一个存储介质中，包括若干指令用以使得一个设备(可以是单片机，芯片等)或处理器(processor)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
本领域的普通技术人员可以理解，上述各实施例是实现本发明的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本发明的精神和范围。

Claims (20)

  1. 一种晶片封装结构，其特征在于，包括：晶片、载体、粘结膜以及塑封体；
    所述粘结膜设置在所述晶片的底面上，所述粘结膜的厚度大于或等于40微米；
    所述晶片通过所述粘结膜设置在所述载体上；
    所述塑封体设置在所述载体上，且包覆所述晶片的顶面及多个侧面。
  2. 根据权利要求1所述的晶片封装结构，其特征在于，所述粘结膜的厚度小于或等于150微米。
  3. 根据权利要求1或2所述的晶片封装结构，其特征在于，所述晶片与所述粘结膜的总厚度等于第一预设值。
  4. 根据权利要求1至3中任一项所述的晶片封装结构，其特征在于，所述晶片封装结构还包括保护层；
    所述保护层设置在所述晶片的顶面上，且被所述塑封体包覆在内。
  5. 根据权利要求4所述的晶片封装结构，其特征在于，所述塑封体中包覆所述保护层的部分与所述保护层的总厚度等于第二预设值。
  6. 根据权利要求4或5所述的晶片封装结构，其特征在于，所述保护层的厚度大于或等于1微米且小于或等于20微米。
  7. 根据权利要求4至6中任一项所述的晶片封装结构，其特征在于，所述保护层为聚酰亚胺材料。
  8. 根据权利要求1至7中任一项所述的晶片封装结构，其特征在于，所述晶片的底面为光滑表面。
  9. 根据权利要求1至8中任一项所述的晶片封装结构，其特征在于， 所述粘结膜的模量大于4MPa。
  10. 根据权利要求1至9中任一项所述的晶片封装结构，其特征在于，所述载体为基板，所述基板的模量大于20GPa。
  11. 一种晶片封装方法，其特征在于，包括：
    在所述至少一晶片的底面设置粘结膜；所述粘结膜的厚度大于或等于40微米；
    将所述晶片通过所述粘结膜设置在载体上；
    利用塑封体对所述晶片进行塑封；其中，所述塑封体设置于所述载体且包覆所述晶片的顶面及多个侧面，形成晶片封装结构。
  12. 根据权利要求11所述的晶片封装方法，其特征在于，所述粘结膜的厚度小于或等于150微米。
  13. 根据权利要求11或12所述的晶片封装方法，其特征在于，所述在所述至少一晶片的底面设置粘结膜之前，还包括：
    对所述晶片的底面进行研磨；其中，研磨后的所述晶片与所述粘结膜的总厚度等于第一预设值。
  14. 根据权利要求11至13中任一项所述的晶片封装方法，其特征在于，所述在所述至少一晶片的底面设置粘结膜之前，还包括：
    对所述晶片的底面进行抛光以形成光滑表面；其中，所述光滑表面面对所述粘结膜。
  15. 根据权利要求11至14中任一项所述的晶片封装方法，其特征在于，所述在所述至少一晶片的底面设置粘结膜之前，还包括：
    在所述晶片的顶面设置保护层。
  16. 根据权利要求15所述的晶片封装结构，其特征在于，所述塑封体 中包覆所述保护层的部分与所述保护层的总厚度等于第二预设值。
  17. 根据权利要求15或16所述的晶片封装方法，其特征在于，所述在所述晶片的顶面设置保护层中，所述保护层的具体设置方式为：喷涂或旋涂方式。
  18. 根据权利要求15至17中任一项所述的晶片封装方法，其特征在于，所述保护层为聚酰亚胺材料。
  19. 根据权利要求11至18中任一项所述的晶片封装方法，其特征在于，所述粘结膜的模量大于4MPa。
  20. 根据权利要求11至19中任一项所述的晶片封装方法，其特征在于，所述载体为基板，所述基板的模量大于20GPa。
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US20190067236A1 (en) 2019-02-28
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EP3435410B1 (en) 2021-07-07
CN108780782A (zh) 2018-11-09

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