WO2018127222A1 - Procédé d'envoi de séquence de synchronisation, et procédé et dispositif de détection synchrone - Google Patents

Procédé d'envoi de séquence de synchronisation, et procédé et dispositif de détection synchrone Download PDF

Info

Publication number
WO2018127222A1
WO2018127222A1 PCT/CN2018/075481 CN2018075481W WO2018127222A1 WO 2018127222 A1 WO2018127222 A1 WO 2018127222A1 CN 2018075481 W CN2018075481 W CN 2018075481W WO 2018127222 A1 WO2018127222 A1 WO 2018127222A1
Authority
WO
WIPO (PCT)
Prior art keywords
sequence
synchronization
synchronization sequence
target
points
Prior art date
Application number
PCT/CN2018/075481
Other languages
English (en)
Chinese (zh)
Inventor
赵铮
任斌
郑方政
马文平
孙韶辉
潘学明
Original Assignee
电信科学技术研究院
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN201710107142.1A external-priority patent/CN108289070B/zh
Application filed by 电信科学技术研究院 filed Critical 电信科学技术研究院
Priority to US16/476,686 priority Critical patent/US10912052B2/en
Publication of WO2018127222A1 publication Critical patent/WO2018127222A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path

Definitions

  • the present disclosure relates to the field of communications technologies, and in particular, to a method for transmitting a synchronization sequence, a method and device for detecting synchronization.
  • the synchronization sequence has a long period.
  • synchronous detection is required to improve the accuracy of one detection as much as possible; for this reason, the synchronization sequence should be as long as possible, and the frequency is synchronous.
  • the bandwidth of the synchronization sequence should be as wide as possible.
  • the user's system bandwidth will range from 180k to 80M. In the same frequency band, different users will have different working bandwidths.
  • the synchronization sequence can work under different bandwidths, that is, in the frequency domain, the synchronization sequence is intercepted, and the synchronization sequence can still have better autocorrelation and cross-correlation characteristics.
  • the synchronization signal when the user moves at high speed, in order to ensure the synchronization detection accuracy, the synchronization signal should have a higher carrier spacing, but in the case where the total bandwidth is constant, the higher carrier spacing reduces the length of the synchronization sequence. Therefore, it is necessary to design a synchronization sequence to support different carrier spacing.
  • the synchronization sequence in the existing Long Term Evolution (LTE) system does not support the use of the bandwidth interception and is still used as the synchronization sequence, and does not support the synchronization sequence of different carrier intervals.
  • LTE Long Term Evolution
  • An object of the present disclosure is to provide a method for transmitting a synchronization sequence, a synchronization detection method, and an apparatus, which solve the problem that the sequence length and the bandwidth width of the synchronization sequence of the related art are mutually limited, resulting in low detection accuracy.
  • an embodiment of the present disclosure provides a method for sending a synchronization sequence, including:
  • the step of setting a target synchronization sequence includes:
  • the plurality of sequence points of the reference synchronization sequence are rearranged according to a preset rule to obtain a target synchronization sequence.
  • the reference synchronization sequence is a generalized sample sequence, and the sequence length of the ZC sequence is an even number,
  • step of reordering the plurality of sequence points of the reference synchronization sequence according to the preset rule to obtain the target synchronization sequence including:
  • sequence points of the reference synchronization sequence are extracted at equal intervals, and the extracted sequence points are successively placed to obtain a target synchronization sequence.
  • the steps of separately extracting sequence points of the reference synchronization sequence and sequentially extracting the extracted sequence points to obtain a target synchronization sequence include:
  • the step of arranging the plurality of first short sequences and the plurality of second short sequences in a preset order to obtain a target synchronization sequence includes:
  • the first short sequence and the second short sequence are alternately placed to obtain a target synchronization sequence.
  • the sequence length of the reference synchronization sequence is divided by 4, the result is even, then the multiple first short sequences are ZC sequences; if the sequence length of the reference synchronization sequence is divided by 4, When the result is an odd number, then the plurality of second short sequences are ZC sequences.
  • the reference synchronization sequence is a ZC sequence
  • the sequence length of the ZC sequence is an odd number, and the sequence length is equal to a square of N
  • step of reordering the plurality of sequence points of the reference synchronization sequence according to the preset rule to obtain the target synchronization sequence including:
  • the extracted target sequence points are successively placed at preset positions of the reference synchronization sequence to obtain a target synchronization sequence; wherein N is an integer greater than or equal to 3.
  • the preset position is a position starting from an integral multiple of N.
  • the sub-synchronization sequence intercepted in the time domain of the target synchronization sequence is a sequence of one-segment X segment of the target synchronization sequence, and
  • the sub-synchronization sequence is a ZC sequence; wherein X is an integer greater than or equal to 2.
  • the reference synchronization sequence is a ZC sequence
  • the sequence length of the ZC sequence is an even number
  • step of reordering the plurality of sequence points of the reference synchronization sequence according to the preset rule to obtain the target synchronization sequence including:
  • the rearrangement sequence is respectively mapped to each subcarrier in the frequency domain, and after the inverse Fourier transform, a target synchronization sequence is obtained.
  • the sub-synchronization sequence intercepted in the frequency domain of the target synchronization sequence is a sequence of a first quarter segment of the target synchronization sequence, and a second sequence of the target synchronization sequence a sequence of a segment, a sequence of a third quarter of the target synchronization sequence, and/or a sequence of a fourth quarter of the target sequence, and the sub-synchronization sequence is ZC sequence.
  • the embodiment of the present disclosure further provides a synchronization detection method, including:
  • Synchronous detection is performed according to the target synchronization sequence.
  • the step of performing synchronization detection according to the target synchronization sequence includes:
  • Synchronous detection is performed based on the intercepted synchronization sequence.
  • the target synchronization sequence is a ZC sequence
  • the sequence length of the ZC sequence is an even number
  • the synchronization sequence intercepted in the time domain or the frequency domain of the target synchronization sequence is one or more first short sequences and/or one or more second short sequences included in the target synchronization sequence; wherein The first short sequence includes a plurality of sequence points, and the second short sequence includes a plurality of sequence points.
  • the step of performing synchronization detection according to the target synchronization sequence includes:
  • Synchronous detection is performed according to the subcarrier spacing and the intercepted synchronization sequence.
  • the target synchronization sequence is a ZC sequence
  • the sequence length of the ZC sequence is an odd number and the sequence length is equal to the square of N
  • the synchronization sequence intercepted in the time domain of the target synchronization sequence is a sequence of one-segment X segment of the target synchronization sequence, and the intercepted synchronization sequence is a ZC sequence; wherein the sequence length of the ZC sequence Is an integer multiple of X, and X is an integer greater than or equal to 2.
  • the step of performing synchronization detection according to the intercepted synchronization sequence includes:
  • Synchronous detection is performed according to the sequence to be detected.
  • the embodiment of the present disclosure further provides a sending device of a synchronization sequence, including:
  • a sequence setting module configured to set a target synchronization sequence; wherein at least one sequence intercepted in a time domain or a frequency domain of the target synchronization sequence is a synchronization sequence;
  • a sequence sending module configured to send the target synchronization sequence to the terminal.
  • sequence setting module includes:
  • a reference acquisition module configured to acquire a reference synchronization sequence
  • a rearrangement module configured to rearrange a plurality of sequence points of the reference synchronization sequence according to a preset rule to obtain a target synchronization sequence.
  • the rearrangement module includes:
  • a first rearrangement submodule configured to: if the reference synchronization sequence is a ZC sequence, and the sequence length of the ZC sequence is an even number, extract the sequence points of the reference synchronization sequence at equal intervals, respectively, and extract the sequence The points are successively placed to obtain the target synchronization sequence.
  • the first rearrangement submodule includes:
  • a first extracting unit configured to respectively extract an even sequence point and an odd sequence point of the reference synchronization sequence
  • a first dividing unit configured to divide the even sequence point into a plurality of first short sequences, and divide the odd sequence points into a plurality of second short sequences; wherein the first short sequence includes multiple a continuous even sequence of points, the second short sequence comprising a plurality of consecutive odd sequence points;
  • a rearrangement unit configured to arrange the plurality of first short sequences and the plurality of second short sequences in a preset order to obtain a target synchronization sequence.
  • the rearrangement unit includes:
  • the sequence length of the reference synchronization sequence is divided by 4, the result is even, then the multiple first short sequences are ZC sequences; if the sequence length of the reference synchronization sequence is divided by 4, When the result is an odd number, then the plurality of second short sequences are ZC sequences.
  • the rearrangement module includes:
  • Extracting a sub-module if the reference synchronization sequence is a ZC sequence, and the sequence length of the ZC sequence is an odd number, and the sequence length is equal to the square of N, starting from the 0th sequence point of the reference synchronization sequence, Extracting one target sequence point in each consecutive N sequence points;
  • a second rearrangement submodule configured to continuously place the extracted target sequence points in a preset position of the reference synchronization sequence to obtain a target synchronization sequence; wherein N is an integer greater than or equal to 3.
  • the preset position is a position starting from an integral multiple of N.
  • the synchronization sequence intercepted in the time domain of the target synchronization sequence is a sequence of one-segment X segment of the target synchronization sequence, and
  • the intercepted synchronization sequence is a ZC sequence; wherein X is an integer greater than or equal to 2.
  • the rearrangement module includes:
  • a second intercepting sub-module configured to: if the reference synchronization sequence is a ZC sequence, and the sequence length of the ZC sequence is an even number, intercept the even sequence point and the odd sequence point of the reference synchronization sequence respectively;
  • a third rearrangement submodule configured to: place an even sequence point of the reference synchronization sequence before an odd sequence point of the reference synchronization sequence to obtain a rearrangement sequence; or place an odd sequence point of the reference synchronization sequence Before the even sequence point of the reference synchronization sequence, a rearrangement sequence is obtained;
  • the frequency domain mapping submodule is configured to map the rearrangement sequence to each subcarrier of the frequency domain, and obtain an object synchronization sequence after performing inverse Fourier transform.
  • the synchronization sequence intercepted in the frequency domain of the target synchronization sequence is a sequence of a first quarter segment of the target synchronization sequence, and a second quarter of the target synchronization sequence a sequence of one segment, a sequence of a third quarter segment of the target synchronization sequence, and/or a sequence of a fourth quarter segment of the target sequence, and the intercepted synchronization sequence is ZC sequence.
  • the embodiment of the present disclosure further provides a synchronization detecting apparatus, including:
  • a sequence receiving module configured to receive a target synchronization sequence sent by the base station
  • a detecting module configured to perform synchronous detection according to the target synchronization sequence.
  • the detecting module includes:
  • An intercepting submodule configured to intercept a sequence in the time domain or the frequency domain of the target synchronization sequence as a synchronization sequence
  • the detecting submodule is configured to perform synchronous detection according to the intercepted synchronization sequence.
  • the target synchronization sequence is a ZC sequence
  • the sequence length of the ZC sequence is an even number
  • the synchronization sequence intercepted in the time domain or the frequency domain of the target synchronization sequence is one or more first short sequences and/or one or more second short sequences included in the target synchronization sequence; wherein The first short sequence includes a plurality of sequence points, and the second short sequence includes a plurality of sequence points.
  • the detecting module includes:
  • a correlation processing submodule configured to perform related processing on the target synchronization sequence by using a preset synchronization sequence
  • An interval determining submodule configured to determine, according to the number of correlation peaks obtained by the correlation process, a subcarrier spacing of the base station transmitting the target synchronization sequence
  • the synchronization detection submodule is configured to perform synchronization detection according to the subcarrier spacing and the intercepted synchronization sequence.
  • the target synchronization sequence is a ZC sequence
  • the sequence length of the ZC sequence is an odd number and the sequence length is equal to the square of N
  • the synchronization sequence intercepted in the time domain of the target synchronization sequence is a sequence of one-segment X segment of the target synchronization sequence, and the intercepted synchronization sequence is a ZC sequence; wherein the sequence length of the ZC sequence is X Integer multiple, X is an integer greater than or equal to 2.
  • the detecting submodule includes:
  • a preprocessing module configured to obtain a p-th power of the intercepted synchronization sequence to obtain a sequence to be detected; wherein p is an integer greater than or equal to 2;
  • a detecting unit configured to perform synchronous detection according to the sequence to be detected.
  • An embodiment of the present disclosure further provides a synchronization sequence sending apparatus, including: a processor, a memory, and a transceiver, where:
  • the processor is configured to read a program in the memory and perform the following process:
  • the transceiver is for receiving and transmitting data
  • the memory is capable of storing data used by the processor in performing operations.
  • the embodiment of the present disclosure further provides a synchronization detecting apparatus, including: a processor, a memory, and a transceiver, wherein:
  • the processor is configured to read a program in the memory and perform the following process:
  • the transceiver is for receiving and transmitting data
  • the memory is capable of storing data used by the processor in performing operations.
  • the base station side presets a target synchronization sequence having good autocorrelation characteristics, and the sequence obtained in the time domain or the frequency domain of the target synchronization sequence is still It can be used as a synchronization sequence, and the obtained sub-synchronization sequence has good autocorrelation property and good cross-correlation property; then, for terminals of different bandwidths or terminals with different carrier spacing, after the base station side transmits the same target synchronization sequence, the terminal The corresponding sub-synchronization sequence can be intercepted according to its own requirements for synchronous detection, which not only ensures the synchronization detection accuracy, but also improves the application range of the target synchronization sequence.
  • FIG. 1 is a flow chart showing the steps of a method for transmitting a synchronization sequence provided in some embodiments of the present disclosure
  • FIG. 2 is a flow chart showing the steps of a synchronization detecting method provided in some embodiments of the present disclosure
  • FIG. 3 is a schematic structural diagram of a transmitting apparatus of a synchronization sequence provided in some embodiments of the present disclosure
  • FIG. 4 is a block diagram showing another apparatus for transmitting a synchronization sequence and a synchronization detecting apparatus provided in some embodiments of the present disclosure
  • FIG. 5 shows a block diagram of another synchronization detecting apparatus provided in some embodiments of the present disclosure.
  • some embodiments of the present disclosure provide a method for sending a synchronization sequence, including:
  • Step 11 Set a target synchronization sequence with good autocorrelation characteristics; wherein at least one sequence intercepted in a time domain or a frequency domain of the target synchronization sequence is a sub-synchronization sequence, and the sub-synchronization sequence has a good self Related characteristics and good cross-correlation properties between the sub-synchronization sequences;
  • Step 12 Send the target synchronization sequence to the terminal.
  • the base station side sets a target synchronization sequence having good sub-correlation characteristics and cross-correlation characteristics.
  • a sequence or a plurality of sequences obtained according to a preset rule in the time domain or the frequency domain of the target synchronization sequence can also be used as a synchronization sequence, which is called a sub-synchronization sequence
  • the sub-synchronization sequence also has good autocorrelation characteristics and Cross-correlation properties.
  • the terminal may intercept the corresponding sub-synchronization sequence according to its own requirements for synchronous detection.
  • step 11 of the embodiment of the present disclosure described above with reference to FIG. 1 includes:
  • Step 111 Obtain a reference synchronization sequence with good autocorrelation properties
  • Step 112 Perform rearrangement of multiple sequence points of the reference synchronization sequence according to a preset rule to obtain a target synchronization sequence with good autocorrelation characteristics.
  • the preset rule may be specifically set according to a characteristic of the reference synchronization sequence; specifically, if the target synchronization sequence is a synchronization sequence that is insensitive to the carrier interval, at least one sequence intercepted in the time domain of the target synchronization sequence If the target synchronization sequence is a bandwidth-insensitive synchronization sequence, at least one sequence intercepted in the frequency domain of the target synchronization sequence is a sub-synchronization sequence.
  • the sub-synchronization sequence in the time domain and the sub-synchronization sequence in the frequency domain are respectively described below.
  • the sequence intercepted in the time domain of the target synchronization sequence is a sub-synchronization sequence.
  • the first reference synchronization sequence is a ZC sequence, and the sequence length of the ZC sequence is an even number
  • the second reference synchronization sequence is a ZC sequence
  • the sequence length of the ZC sequence is It is odd and the sequence length is equal to the square of N
  • the Chinese name of the ZC (Zadoff-Chu) sequence is: a generalized sample sequence.
  • step 112 includes:
  • Step 1123 Extract the sequence points of the reference synchronization sequence at equal intervals, and successively place the extracted sequence points to obtain a target synchronization sequence with good autocorrelation properties.
  • step 1123 includes:
  • Step 11231 extracting even sequence points and odd sequence points of the reference synchronization sequence respectively;
  • Step 11232 dividing the even sequence point into a plurality of first short sequences, and dividing the odd sequence points into a plurality of second short sequences; wherein the first short sequence includes multiple consecutive even sequences Point, the second short sequence includes a plurality of consecutive odd sequence points;
  • Step 11233 the plurality of first short sequences and the plurality of second short sequences are arranged in a preset order to obtain a target synchronization sequence having good autocorrelation characteristics.
  • step 11233 includes:
  • the first short sequence and the second short sequence are alternately placed to obtain a target synchronization sequence having good autocorrelation properties.
  • step 11232 is specifically: dividing the even sequence point into two first short sequences, which are short sequence 1 and short sequence 2, respectively; The sequence points are divided into two second short sequences, which are short sequence 3 and short sequence 4, respectively.
  • the short sequence 1 is the first half of the even sequence point of the reference synchronization sequence
  • the short sequence 2 is the second half of the even sequence point of the reference synchronization sequence
  • the short sequence 3 is the first half of the odd sequence point of the reference synchronization sequence
  • the short sequence 4 is the reference The second half of the odd sequence of the synchronization sequence.
  • the target synchronization sequence is [short sequence 1, short sequence 3, short sequence 2, short sequence 4], or [short sequence 1, short sequence 4, short sequence 2, short sequence 3], Or [short sequence 2, short sequence 3, short sequence 1, short sequence 4], [short sequence 2, short sequence 4, short sequence 1, short sequence 3], similarly, a short sequence consisting of odd points can be placed in The first short sequence position is not listed here.
  • first short sequence and the second short sequence are only a preferred embodiment of the present application, and other placement sequences are equally applicable to the present application.
  • first short sequences are successively placed, and then a plurality of second short sequences are successively continued; or, a plurality of second short sequences are successively placed, and then a plurality of first short sequences are successively placed.
  • the sequence length of the reference synchronization sequence is divided by 4, the result is even, then the plurality of first short sequences are ZC sequences; if the sequence of the reference synchronization sequence is When the result obtained by dividing the length by 4 is an odd number, then the plurality of second short sequences are ZC sequences.
  • the short sequence 1 and the short sequence 2 are ZC sequences; if the reference synchronization sequence is one quarter long
  • short sequence 3 and short sequence 4 are ZC sequences.
  • the step 112 further includes:
  • Step 1121 respectively intercepting even sequence points and odd sequence points of the reference synchronization sequence
  • Step 1122 placing an even sequence point of the reference synchronization sequence before an odd sequence point of the reference synchronization sequence to obtain a target synchronization sequence with good autocorrelation characteristics; or placing an odd sequence point of the reference synchronization sequence A target synchronization sequence having good autocorrelation properties is obtained before the even sequence points of the reference synchronization sequence.
  • the reference synchronization sequence includes ⁇ sequence point 1, sequence point 2, sequence point 3, sequence point 4, sequence point 5, sequence point 6, sequence point 7, sequence point 8 ⁇
  • the target synchronization sequence is ⁇ sequence point 2 Sequence point 4, sequence point 6, sequence point 8, sequence point 1, sequence point 3, sequence point 5, sequence point 7 ⁇
  • target synchronization sequence is ⁇ sequence point 1, sequence point 3, sequence point 5, sequence point 7 , sequence point 2, sequence point 4, sequence point 6, sequence point 8 ⁇ .
  • the target synchronization sequence is ⁇ sequence point 2 Sequence point 4, sequence point 6, sequence point 8, sequence point 1, sequence point 3, sequence point 5, sequence point 7 ⁇ ;
  • the result obtained by the time domain of the target synchronization sequence is the first quarter of the target synchronization sequence.
  • a sequence and/or a sequence of a second quarter of the target synchronization sequence, and the sub-synchronization sequence is a ZC sequence; that is, the sub-synchronization sequence is ⁇ sequence point 2, sequence point 4 ⁇ or a sub-synchronization sequence Is ⁇ sequence point 6, sequence point 8 ⁇ .
  • the sub-synchronization sequence intercepted in the time domain of the target synchronization sequence is the third quarter of the target synchronization sequence.
  • a sequence and/or a sequence of a fourth quarter of the target synchronization sequence, and the sub-synchronization sequence is a ZC sequence;
  • the target synchronization sequence is ⁇ sequence point 1, sequence Point 3, sequence point 5, sequence point 7, sequence point 2, sequence point 4, sequence point 6, sequence point 8 ⁇ ;
  • the result is an odd number
  • the sub-synchronization sequence intercepted in the time domain of the target synchronization sequence is the first quarter of the target synchronization sequence.
  • a sequence and/or a sequence of a second quarter of the target synchronization sequence, and the sub-synchronization sequence is a ZC sequence;
  • the sub-synchronization sequence intercepted in the time domain of the target synchronization sequence is the third quarter of the target synchronization sequence.
  • a sequence and/or a sequence of a fourth quarter of the target synchronization sequence, and the sub-synchronization sequence is a ZC sequence; that is, the sub-synchronization sequence is ⁇ sequence point 2, sequence point 4 ⁇ or a sub-synchronization sequence Is ⁇ sequence point 6, sequence point 8 ⁇ .
  • the even ZC sequence is:
  • z 3 (m) is a ZC sequence in which
  • z 4 (m) is a ZC sequence in which
  • step 112 includes:
  • Step 1123 starting from the 0th sequence point of the reference synchronization sequence, extracting one target sequence point in each consecutive N sequence points;
  • Step 1124 The extracted target sequence points are successively placed in a preset position of the reference synchronization sequence to obtain a target synchronization sequence having good autocorrelation properties; wherein N is an integer greater than or equal to 3.
  • the preset position is a position starting from an integral multiple of N.
  • the reference synchronization sequence includes ⁇ sequence point 1, sequence point 2, sequence point 3, sequence point 4, sequence point 5, sequence point 6, sequence point 7, sequence point 8, sequence point 9 ⁇ , and N is equal to 3;
  • the target synchronization sequence is ⁇ sequence point 1, sequence point 4, sequence point 7, sequence point 2, sequence point 5, sequence point 8, sequence point 3, sequence point 6, sequence point 9 ⁇ .
  • the sub-synchronization sequence intercepted in the time domain of the target synchronization sequence is a sequence of one-segment X segment of the target synchronization sequence, and
  • the subsynchronization sequence is a ZC sequence; wherein X is an integer greater than or equal to 2.
  • the target synchronization sequence is ⁇ sequence point 1, sequence point 3, sequence point 4, sequence point 6, sequence point 2, sequence point 7, sequence point 8, sequence point 9, sequence point 5 ⁇
  • the sequence length of the target synchronization sequence is 9, and 9 is an integer multiple of 3, so the sub-synchronization sequence is a sequence of one-third of the target synchronization sequence, that is, ⁇ sequence point 1, sequence point 3, sequence point 4 ⁇ , or ⁇ Sequence point 6, sequence point 2, sequence point 7 ⁇ , or ⁇ sequence point 8, sequence point 9, sequence point 5 ⁇ .
  • step 112 includes:
  • Step 1125 Intercepting even sequence points and odd sequence points of the reference synchronization sequence respectively;
  • Step 1126 placing an even sequence point of the reference synchronization sequence before an odd sequence point of the reference synchronization sequence to obtain a rearrangement sequence; or placing an odd sequence point of the reference synchronization sequence on the reference synchronization sequence A rearrangement sequence is obtained before the even sequence point;
  • Step 1127 The rearrangement sequence is respectively mapped to each subcarrier in the frequency domain, and after the inverse Fourier transform, a target synchronization sequence with good autocorrelation property is obtained.
  • the sub-synchronization sequence intercepted in the frequency domain of the target synchronization sequence is a sequence of a first quarter segment of the target synchronization sequence, and a second quarter of the target synchronization sequence. a sequence of one segment, a sequence of a third quarter of the target synchronization sequence, and/or a sequence of a fourth quarter of the target sequence, and the subsynchronization sequence is a ZC sequence .
  • the sub-ZC sequence on each carrier can be used as a synchronization sequence according to the formula of the even ZC sequence, that is, it has good autocorrelation property and cross-correlation property. It is not specifically described here.
  • the base station side presets a target synchronization sequence with good autocorrelation characteristics, which is insensitive to carrier spacing and system bandwidth, and can satisfy different system bandwidths and
  • the carrier interval is required by the user; specifically, the sequence obtained in the time domain of the target synchronization sequence or in the frequency domain can still be used as a synchronization sequence, and the obtained sub-synchronization sequence has good autocorrelation property and good cross-correlation.
  • the terminal can intercept the corresponding sub-synchronization sequence according to its own requirements for synchronous detection, which not only ensures the synchronization detection accuracy, but also improves The scope of application of the target synchronization sequence.
  • a synchronization detection method including:
  • Step 21 Receive a target synchronization sequence that is sent by the base station and has good autocorrelation characteristics.
  • Step 22 Perform synchronous detection according to the target synchronization sequence.
  • the terminal side receives the target synchronization sequence transmitted by the base station, and performs synchronization detection according to its own needs and the received target synchronization sequence to implement synchronization timing.
  • step 22 of the embodiment of the present disclosure described above with reference to FIG. 2 includes:
  • Step 221 Intercept a sequence in the time domain or the frequency domain of the target synchronization sequence as a sub-synchronization sequence, where the sub-synchronization sequence has good autocorrelation characteristics; the target synchronization sequence is insensitive to carrier spacing and system bandwidth, and The requirements of different system bandwidths and carrier spacing users are met; in short, the subsequence obtained by the terminal after intercepting in the frequency domain or the time domain of the target synchronization sequence can still be used as the synchronization sequence.
  • Step 222 Perform synchronization detection according to the sub-synchronization sequence.
  • the target synchronization sequence is a ZC sequence, and the sequence length of the ZC sequence is an even number,
  • the sub-synchronization sequence intercepted in the time domain or the frequency domain of the target synchronization sequence is one or more first short sequences and/or one or more second short sequences included in the target synchronization sequence;
  • the first short sequence includes a plurality of sequence points, and the second short sequence includes a plurality of sequence points.
  • the specific first short sequence includes several sequence points and the second short sequence includes several sequence points, and is determined according to the sequence length of the reference synchronization sequence is an integer multiple of several, which is not specifically limited herein.
  • the target synchronization sequence is a ZC sequence
  • the sequence length of the ZC sequence is an even number
  • the sequence length of the ZC sequence is an integer multiple of 4
  • a sub-synchronization sequence intercepted in a time domain or a frequency domain of the target synchronization sequence is a sequence of a first quarter segment of the target synchronization sequence, and a second quarter of the target synchronization sequence a sequence of segments, a sequence of a third quarter of the target synchronization sequence, or a sequence of a fourth quarter of the target synchronization sequence, and the subsynchronization sequence is a ZC sequence.
  • the specific sequence of the first quarter segment can be determined as the sub-synchronization sequence according to whether the result of dividing the sequence length of the target synchronization sequence by 4 is odd or even, and the characteristics of the target synchronization sequence.
  • the characteristics of the target synchronization sequence may be indicated by the base station side, and are not specifically limited herein.
  • step 22 includes:
  • Step 223 Perform correlation processing on the target synchronization sequence by using a preset synchronization sequence.
  • Step 224 Determine, according to the number of correlation peaks obtained by the correlation processing, a subcarrier spacing of the base station to send the target synchronization sequence.
  • Step 225 Perform synchronous detection according to the subcarrier spacing and the sub synchronization sequence.
  • the subcarrier spacing may be determined according to the number of correlation peaks obtained by correlating the synchronization sequence.
  • the target synchronization sequence is exemplified as [short sequence 1, short sequence 3, short sequence 2, short sequence 4].
  • the transmission target synchronization sequence is [short sequence 1, short sequence 3, short sequence 2, short sequence 4].
  • the transmitted target synchronization sequence is [short sequence].
  • 1, short sequence 3] when the subcarrier spacing is 60k Hz, the target synchronization sequence transmitted is [short sequence 1].
  • the transmission terminal carrier interval can be determined according to the number of correlation peaks. For example, if the transmission terminal carrier interval is 15 kHz, the user uses the 60 k Hz preset synchronization sequence [short sequence 1] as the local sequence for correlation, and two peaks are detected; if the transmission terminal carrier interval is 60 kHz, the user uses the 60 k Hz preset. When the synchronization sequence [short sequence 1] is correlated, one peak is detected; if the transmission terminal carrier interval is 30 kHz, the user uses the 60 k Hz preset synchronization sequence [short sequence 1] for correlation, and the user detects only one peak.
  • the user will also detect a peak, but for the case where the transmission terminal carrier spacing is 30 kHz, the short sequence 3 is used, and there is no peak, thereby judging the transmission terminal carrier spacing. , thereby further performing synchronous detection.
  • the target synchronization sequence is a ZC sequence
  • the sequence length of the ZC sequence is an odd number and the sequence length is equal to the square of N
  • the sub-synchronization sequence intercepted in the time domain of the target synchronization sequence is a sequence of one-segment X segment of the target synchronization sequence, and the sub-synchronization sequence is a ZC sequence; wherein the sequence length of the ZC sequence is An integer multiple of X, where X is an integer greater than or equal to two. For example, if the sequence length is 15 and X is 3, the sub-synchronization sequence is any one-third sequence of the target synchronization sequence.
  • the step of performing synchronization detection by the terminal according to the sub-synchronization sequence includes:
  • Synchronous detection is performed according to the sequence to be detected; that is, the pre-processed signal is synchronously detected.
  • the receiving process includes two parts: pre-processing and synchronous detection, and the synchronization detection is an existing algorithm, which is not described here.
  • the terminal side intercepts the corresponding sub-synchronization sequence according to its own requirements for synchronization detection, which not only ensures synchronization detection accuracy, but also improves target synchronization.
  • the application range of the sequence; specifically, the target synchronization sequence is insensitive to carrier spacing and system bandwidth, and can meet the needs of users with different system bandwidths and carrier spacing.
  • a synchronization sequence sending apparatus including:
  • a sequence setting module 31 configured to set a target synchronization sequence with good autocorrelation characteristics; wherein at least one sequence intercepted in a time domain or a frequency domain of the target synchronization sequence is a sub-synchronization sequence, and the sub-synchronization sequence Has good autocorrelation properties and has good cross-correlation properties between the sub-synchronization sequences;
  • the sequence sending module 32 is configured to send the target synchronization sequence to the terminal.
  • sequence setting module in the embodiment described above with reference to FIG. 3 of the present disclosure includes:
  • a reference acquisition module configured to obtain a reference synchronization sequence with good autocorrelation properties
  • the rearrangement module is configured to rearrange the plurality of sequence points of the reference synchronization sequence according to a preset rule to obtain a target synchronization sequence having good autocorrelation characteristics.
  • the rearrangement module in the embodiment described above with reference to FIG. 3 of the present disclosure includes:
  • a first rearrangement submodule configured to: if the reference synchronization sequence is a ZC sequence, and the sequence length of the ZC sequence is an even number, extract the sequence points of the reference synchronization sequence at equal intervals, respectively, and extract the sequence The points are successively placed to obtain a target synchronization sequence with good autocorrelation properties.
  • the first rearrangement sub-module in the embodiment described above with reference to FIG. 3 of the present disclosure includes:
  • a first extracting unit configured to respectively extract an even sequence point and an odd sequence point of the reference synchronization sequence
  • a first dividing unit configured to divide the even sequence point into a plurality of first short sequences, and divide the odd sequence points into a plurality of second short sequences; wherein the first short sequence includes multiple a continuous even sequence of points, the second short sequence comprising a plurality of consecutive odd sequence points;
  • a rearrangement unit configured to arrange the plurality of first short sequences and the plurality of second short sequences in a preset order to obtain a target synchronization sequence having good autocorrelation characteristics.
  • the rearrangement unit includes:
  • the plurality of first short sequences are ZC sequences;
  • the plurality of second short sequences are ZC sequences.
  • the rearrangement module in the embodiment described above with reference to FIG. 3 of the present disclosure includes:
  • a first intercepting submodule configured to: if the reference synchronization sequence is a ZC sequence, and the sequence length of the ZC sequence is an even number, intercept the even sequence point and the odd sequence point of the reference synchronization sequence respectively;
  • a first rearrangement submodule configured to: place an even sequence point of the reference synchronization sequence before an odd sequence point of the reference synchronization sequence to obtain a target synchronization sequence having good autocorrelation characteristics; or synchronize the reference
  • the odd sequence points of the sequence are placed before the even sequence points of the reference synchronization sequence to obtain a target synchronization sequence with good autocorrelation properties.
  • the second half of the target synchronization sequence is an odd sequence point of the reference synchronization sequence.
  • the result obtained by the time domain of the target synchronization sequence is the first quarter of the target synchronization sequence. a sequence and/or a sequence of a second quarter of the target synchronization sequence, and wherein the sub-synchronization sequence is a ZC sequence;
  • the sub-synchronization sequence intercepted in the time domain of the target synchronization sequence is the third quarter of the target synchronization sequence.
  • a sequence and/or a sequence of a fourth quarter of the target synchronization sequence, and the subsynchronization sequence is a ZC sequence.
  • the second half of the target synchronization sequence is an even sequence point of the reference synchronization sequence.
  • the result is an odd number
  • the sub-synchronization sequence intercepted in the time domain of the target synchronization sequence is the first quarter of the target synchronization sequence.
  • the sub-synchronization sequence intercepted in the time domain of the target synchronization sequence is the third quarter of the target synchronization sequence.
  • a sequence and/or a sequence of a fourth quarter of the target synchronization sequence, and the subsynchronization sequence is a ZC sequence.
  • the rearrangement module in the embodiment described above with reference to FIG. 3 of the present disclosure includes:
  • Extracting a submodule if the reference synchronization sequence is a ZC sequence, and the sequence length of the ZC sequence is an odd number and the sequence length is equal to the square of N, starting from the 0th sequence point of the reference synchronization sequence, Extracting one target sequence point from every N consecutive sequence points;
  • a second rearrangement sub-module configured to continuously place the extracted target sequence points in a preset position of the reference synchronization sequence to obtain a target synchronization sequence with good autocorrelation characteristics; wherein N is greater than or equal to 3 The integer.
  • the above-described preset position of the present embodiment described with reference to FIG. 3 is a position starting from an integral multiple of N.
  • the sub-synchronization sequence intercepted in the time domain of the target synchronization sequence is the target.
  • a sequence of one-segment X of the synchronization sequence, and the sub-synchronization sequence is a ZC sequence; wherein X is an integer greater than or equal to two.
  • the rearrangement module includes:
  • a second intercepting sub-module configured to: if the reference synchronization sequence is a ZC sequence, and the sequence length of the ZC sequence is an even number, intercept the even sequence point and the odd sequence point of the reference synchronization sequence respectively;
  • a third rearrangement submodule configured to: place an even sequence point of the reference synchronization sequence before an odd sequence point of the reference synchronization sequence to obtain a rearrangement sequence; or place an odd sequence point of the reference synchronization sequence Before the even sequence point of the reference synchronization sequence, a rearrangement sequence is obtained;
  • the frequency domain mapping sub-module is configured to map the rearrangement sequence to each sub-carrier of the frequency domain, and obtain an object synchronization sequence with good autocorrelation characteristics after performing inverse Fourier transform.
  • the sub-synchronization sequence intercepted in the frequency domain of the target synchronization sequence is the first quarter segment of the target synchronization sequence.
  • a sequence, a sequence of a second quarter of the target synchronization sequence, a sequence of a third quarter of the target synchronization sequence, and/or a fourth quarter of the target sequence is a ZC sequence.
  • the base station side presets a target synchronization sequence with good autocorrelation characteristics, which is insensitive to carrier spacing and system bandwidth, and can satisfy different system bandwidths and
  • the carrier interval is required by the user; specifically, the sequence obtained in the time domain of the target synchronization sequence or in the frequency domain can still be used as a synchronization sequence, and the obtained sub-synchronization sequence has good autocorrelation property and good cross-correlation.
  • the terminal can intercept the corresponding sub-synchronization sequence according to its own requirements for synchronous detection, which not only ensures the synchronization detection accuracy, but also improves The scope of application of the target synchronization sequence.
  • the transmitting apparatus of the synchronization sequence provided by the embodiment described above with reference to FIG. 3 of the present disclosure is a transmitting apparatus capable of executing the transmitting method of the synchronization sequence provided by the embodiment described above with reference to FIG. 1, and the synchronization sequence is All embodiments of the transmitting method are applicable to the transmitting device and both achieve the same or similar benefits.
  • the synchronization sequence transmission apparatus includes: a processor 100; and a memory 120 connected to the processor 100 through a bus interface. And a transceiver 110 coupled to the processor 100 via a bus interface; the memory for storing programs and data used by the processor in performing operations; transmitting control commands and the like through the transceiver 110; When the program calls and executes the programs and data stored in the memory, the following functional modules are implemented:
  • a sequence setting module configured to set a target synchronization sequence having a good autocorrelation property; wherein at least one sequence intercepted in a time domain or a frequency domain of the target synchronization sequence is a sub-synchronization sequence, and the sub-synchronization sequence has Good autocorrelation properties and good cross-correlation properties between the subsynchronous sequences;
  • a sequence sending module configured to send the target synchronization sequence to the terminal.
  • the bus architecture can include any number of interconnected buses and bridges, specifically linked by one or more processors represented by processor 100 and various circuits of memory represented by memory 120.
  • the bus architecture can also link various other circuits such as peripherals, voltage regulators, and power management circuits.
  • the bus interface provides an interface.
  • Transceiver 110 can be a plurality of components, including a transmitter and a transceiver, providing means for communicating with various other devices on a transmission medium.
  • the processor 100 is responsible for managing the bus architecture and general processing, and the memory 120 can store data used by the processor 100 in performing operations.
  • the processor 100 is responsible for managing the bus architecture and general processing, and the memory 920 can store data used by the processor 100 in performing operations.
  • the transmitting apparatus of the synchronization sequence provided by the embodiment described above with reference to FIG. 4 of the present disclosure is a transmitting apparatus capable of executing the transmitting method of the synchronization sequence provided by the embodiment described above with reference to FIG. 1, and the synchronization sequence is All embodiments of the transmitting method are applicable to the transmitting device and both achieve the same or similar benefits.
  • some embodiments of the present disclosure further provide a synchronization detecting apparatus, including:
  • the sequence receiving module 51 is configured to receive a target synchronization sequence that is sent by the base station and has good autocorrelation characteristics
  • the detecting module 52 is configured to perform synchronous detection according to the target synchronization sequence.
  • the detection module in the embodiment described above with reference to FIG. 5 of the present disclosure includes:
  • a intercepting submodule configured to intercept a sequence in the time domain or the frequency domain of the target synchronization sequence as a sub-synchronization sequence, the sub-synchronization sequence having good autocorrelation characteristics
  • the detecting submodule is configured to perform synchronous detection according to the sub synchronization sequence.
  • the target synchronization sequence is a ZC sequence
  • the sequence length of the ZC sequence is an even number
  • the sub-synchronization sequence intercepted in the time domain or the frequency domain of the target synchronization sequence is one or more first short sequences and/or one or more second short sequences included in the target synchronization sequence;
  • the first short sequence includes a plurality of sequence points, and the second short sequence includes a plurality of sequence points.
  • the detecting module includes:
  • a correlation processing submodule configured to perform related processing on the target synchronization sequence by using a preset synchronization sequence
  • An interval determining submodule configured to determine, according to the number of correlation peaks obtained by the correlation process, a subcarrier spacing of the base station transmitting the target synchronization sequence
  • the synchronization detection submodule is configured to perform synchronization detection according to the subcarrier spacing and the sub synchronization sequence.
  • the target synchronization sequence is a ZC sequence
  • the sequence length of the ZC sequence is an even number
  • a sub-synchronization sequence intercepted in a time domain or a frequency domain of the target synchronization sequence is a sequence of a first quarter segment of the target synchronization sequence, and a second quarter of the target synchronization sequence a sequence of segments, a sequence of a third quarter of the target synchronization sequence, or a sequence of a fourth quarter of the target synchronization sequence, and the subsynchronization sequence is a ZC sequence.
  • the target synchronization sequence is a ZC sequence
  • the sequence length of the ZC sequence is an odd number and the sequence length is equal to the square of N
  • the sub-synchronization sequence intercepted in the time domain of the target synchronization sequence is a sequence of one-segment X segment of the target synchronization sequence, and the sub-synchronization sequence is a ZC sequence; wherein the sequence length of the ZC sequence is An integer multiple of X, where X is an integer greater than or equal to two.
  • the detecting submodule in the embodiment described above with reference to FIG. 5 of the present disclosure includes:
  • a pre-processing module configured to obtain a p-th power of the sub-synchronization sequence to obtain a sequence to be detected; p is an integer greater than or equal to 2;
  • a detecting unit configured to perform synchronous detection according to the sequence to be detected.
  • the terminal side intercepts the corresponding sub-synchronization sequence according to its own needs for synchronization detection, which not only ensures synchronization detection accuracy, but also improves target synchronization.
  • the application range of the sequence; specifically, the target synchronization sequence is insensitive to carrier spacing and system bandwidth, and can meet the needs of users with different system bandwidths and carrier spacing.
  • the synchronization detecting apparatus capable of executing the synchronization detecting method provided by the embodiment described above with reference to FIG. 2, all the implementations of the above-described synchronous detecting method The examples are applicable to the synchronous detection device and both achieve the same or similar beneficial effects.
  • another embodiment of the present disclosure further provides another synchronization detecting apparatus, including: a processor 100; a memory 120 connected to the processor 100 through a bus interface, and a bus a transceiver 110 having an interface coupled to the processor 100; the memory for storing programs and data used by the processor when performing operations; transmitting control commands by the transceiver 110, etc.; when the processor calls and executes
  • a processor 100 a memory 120 connected to the processor 100 through a bus interface, and a bus a transceiver 110 having an interface coupled to the processor 100; the memory for storing programs and data used by the processor when performing operations; transmitting control commands by the transceiver 110, etc.; when the processor calls and executes
  • the program and data stored in the memory are implemented, the following functional modules are implemented:
  • a sequence receiving module configured to receive a target synchronization sequence that is sent by the base station and has good autocorrelation characteristics
  • a detecting module configured to perform synchronous detection according to the target synchronization sequence.
  • the bus architecture can include any number of interconnected buses and bridges, specifically linked by one or more processors represented by processor 100 and various circuits of memory represented by memory 120.
  • the bus architecture can also link various other circuits such as peripherals, voltage regulators, and power management circuits.
  • the bus interface provides an interface.
  • Transceiver 110 can be a plurality of components, including a transmitter and a transceiver, providing means for communicating with various other devices on a transmission medium.
  • the processor 100 is responsible for managing the bus architecture and general processing, and the memory 120 can store data used by the processor 100 in performing operations.
  • the processor 100 is responsible for managing the bus architecture and general processing, and the memory 920 can store data used by the processor 100 in performing operations.
  • the synchronization detecting apparatus capable of executing the synchronization detecting method provided by the embodiment described above with reference to FIG. 2, all the implementations of the above-described synchronous detecting method The examples are applicable to the synchronous detection device and both achieve the same or similar beneficial effects.

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

La présente invention concerne un procédé d'envoi de séquence de synchronisation, et un procédé et un dispositif de détection synchrone. Le procédé d'envoi comprend : le réglage d'une séquence de synchronisation cible qui présente une propriété d'auto-corrélation satisfaisante, au moins un segment de séquence intercepté sur un domaine temporel ou un domaine fréquentiel de la séquence de synchronisation cible étant une sous-séquence de synchronisation, les sous-séquences de synchronisation présentant des propriétés d'auto-corrélation satisfaisantes et des propriétés de corrélation croisée satisfaisantes ; et l'envoi de la séquence de synchronisation cible à un terminal.
PCT/CN2018/075481 2017-01-09 2018-02-06 Procédé d'envoi de séquence de synchronisation, et procédé et dispositif de détection synchrone WO2018127222A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/476,686 US10912052B2 (en) 2017-01-09 2018-02-06 Method for transmitting synchronization sequence, and method and device for synchronization detection

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CN201710013632.5 2017-01-09
CN201710013632 2017-01-09
CN201710107142.1A CN108289070B (zh) 2017-01-09 2017-02-06 一种同步序列的发送方法、同步检测方法及装置
CN201710107142.1 2017-02-06

Publications (1)

Publication Number Publication Date
WO2018127222A1 true WO2018127222A1 (fr) 2018-07-12

Family

ID=62789219

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/075481 WO2018127222A1 (fr) 2017-01-09 2018-02-06 Procédé d'envoi de séquence de synchronisation, et procédé et dispositif de détection synchrone

Country Status (1)

Country Link
WO (1) WO2018127222A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101374129A (zh) * 2007-08-20 2009-02-25 中兴通讯股份有限公司 基于正交频分复用的同步序列生成方法、同步方法及系统
CN101465830A (zh) * 2007-12-19 2009-06-24 华为技术有限公司 发送、接收同步信息的方法与系统、装置
CN102255722A (zh) * 2006-01-18 2011-11-23 华为技术有限公司 改进通讯系统中同步和信息传输的方法
CN106559206A (zh) * 2015-09-30 2017-04-05 中兴通讯股份有限公司 同步信号的传输方法及装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102255722A (zh) * 2006-01-18 2011-11-23 华为技术有限公司 改进通讯系统中同步和信息传输的方法
CN101374129A (zh) * 2007-08-20 2009-02-25 中兴通讯股份有限公司 基于正交频分复用的同步序列生成方法、同步方法及系统
CN101465830A (zh) * 2007-12-19 2009-06-24 华为技术有限公司 发送、接收同步信息的方法与系统、装置
CN106559206A (zh) * 2015-09-30 2017-04-05 中兴通讯股份有限公司 同步信号的传输方法及装置

Similar Documents

Publication Publication Date Title
CN101944929B (zh) 基于随机接入过程的检测方法和检测装置
CN101656700B (zh) 长期演进系统小区初始搜索循环前缀类型检测方法及装置
CN101295999B (zh) 一种随机接入前导的检测方法
CN102130883A (zh) 一种用于td-lte系统时频同步的方法
WO2018049931A1 (fr) Procédé et dispositif pour déterminer un signal de synchronisation de liaison latérale dans une communication d2d
RU2008150492A (ru) Обнаружение сигналов в системе беспроводной связи
CN104717174B (zh) 一种复杂多径信道下的ofdm抗干扰同步方法
CN101325450A (zh) 一种同步方法、频偏估计方法、同步装置、频偏估计装置
JP2020519162A (ja) アップリンク同期タイミング偏差を決定するための方法および装置
JP2011193476A (ja) 伝播ラウンドトリップ遅延を推定するための方法及び通信システム
CN108289070B (zh) 一种同步序列的发送方法、同步检测方法及装置
CN104618289A (zh) 用于主同步信号检测的方法及装置
CN104918336A (zh) 一种干扰环境下随机接入信号的检测方法、装置和系统
CN101925172A (zh) 一种时间同步方法及装置
CN102647382B (zh) 整数倍频偏估计方法及装置
CN102104951B (zh) 定时偏移估计方法及装置
CN106230758B (zh) 一种lte-a系统整数倍频偏估计方法
CN106507467A (zh) 一种非实时lte上行链路数据定时同步的方法
WO2018127222A1 (fr) Procédé d'envoi de séquence de synchronisation, et procédé et dispositif de détection synchrone
CN110430156A (zh) 突发ofdm数据传输的帧同步方法及系统
CN114339979A (zh) 小区搜索方法、装置、电子装置和存储介质
CN101702705B (zh) 用于多载波系统的同步方法及系统
CN103108337B (zh) 一种随机接入信号的检测方法、装置及基站
CN103095333A (zh) 一种高速移动环境下定时同步方法
TWI723248B (zh) 一種同步序列的發送方法、同步檢測方法及裝置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18736013

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18736013

Country of ref document: EP

Kind code of ref document: A1