WO2018127041A1 - 速率匹配方法、编码装置和通信装置 - Google Patents

速率匹配方法、编码装置和通信装置 Download PDF

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Publication number
WO2018127041A1
WO2018127041A1 PCT/CN2018/070056 CN2018070056W WO2018127041A1 WO 2018127041 A1 WO2018127041 A1 WO 2018127041A1 CN 2018070056 W CN2018070056 W CN 2018070056W WO 2018127041 A1 WO2018127041 A1 WO 2018127041A1
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Prior art keywords
code length
length
code
bit sequence
mother
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PCT/CN2018/070056
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English (en)
French (fr)
Inventor
张公正
罗禾佳
李榕
陈莹
乔云飞
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华为技术有限公司
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Priority to KR1020197022946A priority Critical patent/KR102243485B1/ko
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP21190257.2A priority patent/EP3996284A1/en
Priority to ES18736283T priority patent/ES2894999T3/es
Priority to RU2019124520A priority patent/RU2761405C2/ru
Priority to AU2018206034A priority patent/AU2018206034B2/en
Priority to JP2019536962A priority patent/JP6817452B2/ja
Priority to EP18736283.5A priority patent/EP3550750B1/en
Publication of WO2018127041A1 publication Critical patent/WO2018127041A1/zh
Priority to US16/223,121 priority patent/US10341044B2/en
Priority to US16/423,173 priority patent/US10700809B2/en
Priority to US16/885,244 priority patent/US10938506B2/en
Priority to US17/174,794 priority patent/US11539457B2/en
Priority to US18/069,379 priority patent/US20230198660A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0009—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the channel coding
    • H04L1/0013—Rate matching, e.g. puncturing or repetition of code symbols
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H03M13/6356—Error control coding in combination with rate matching by repetition or insertion of dummy data, i.e. rate reduction
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H03M13/6362—Error control coding in combination with rate matching by puncturing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H03M13/6362—Error control coding in combination with rate matching by puncturing
    • H03M13/6368—Error control coding in combination with rate matching by puncturing using rate compatible puncturing or complementary puncturing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6502—Reduction of hardware complexity or efficient processing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0054—Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0067—Rate matching
    • H04L1/0068—Rate matching by puncturing

Definitions

  • Embodiments of the present invention relate to the field of communications and, more particularly, to methods and apparatus for rate matching.
  • Polar codes proposed by Turkish professor Arikan are the first good code to theoretically prove that Shannon capacity can be achieved with low coding complexity.
  • the Polar code is a linear block code whose coding matrix is G N and the encoding process is among them Is a binary line vector with a length of N (ie, the length of the mother code); G N is an N ⁇ N matrix, and Defined as the Kronecker product of log 2 N matrices F 2 .
  • G N. (A) is a sub-matrix obtained from those rows corresponding to the index in the set A in G N.
  • G N (A C ) is obtained from the rows corresponding to the indexes in the set A C in G N . Submatrix.
  • the encoded output of the Polar code can be simplified to: Is a K ⁇ N matrix.
  • the construction process of the Polar code is a collection
  • the selection process determines the performance of the Polar code.
  • the construction process of the Polar code is generally: determining that there are N polarized channels in total according to the length N of the mother code, respectively corresponding to N rows of the coding matrix, calculating the reliability of the polarized channel, and the first K polarizations with higher reliability.
  • the index of the channel is the element of set A, and the index corresponding to the remaining (NK) polarized channels is used as the index set of fixed bits.
  • Set A determines the position of the information bits, the set The position of the fixed bit is determined.
  • the original Polar code (parent code) has a code length of 2, which is an integer power of 2, and in practice, a Polar code of arbitrary code length needs to be implemented by rate matching.
  • the prior art implements rate matching using a puncture or shortening scheme.
  • the mother code exceeding the target code length is always punctured to achieve the target code length, and the padding is restored to the mother code length.
  • the cache size, complexity, and delay of the compiled code are related to the length of the mother code.
  • the number of shortened or punctured bits is large (for example, shortened or punctured from 2048 bits to 1200 bits), the overhead caused by puncturing is large.
  • the code rate decreases, which on the one hand can bring coding gain, and on the other hand, the complexity increases as the mother code length increases.
  • the embodiments of the present application provide a rate matching method, an encoding apparatus, a de-rate matching method, a decoding apparatus, and a communication apparatus, which can reduce the complexity of the polar code encoding code.
  • a rate matching method for a Polar code including: acquiring an information bit sequence and a target code length M of a Polar code; and when the target code length M satisfies a preset condition, using a first mother code length N a Polar code of 1 encodes the information bit sequence, outputs a first coded bit sequence, N 1 is less than or equal to M, and N 1 is an integer power of 2; repeating at least a portion of the bits of the first coded bit sequence to obtain a length a first target Polar code of M; when the target code length M does not satisfy the preset condition, encoding the information bit sequence by using a Polar code of the second mother code length N 2 , and outputting the second code a bit sequence, N 2 is greater than or equal to M, and N 2 is an integer power of 2; the second coded bit sequence is shortened or punctured to obtain a second target Polar code of length M.
  • an encoding apparatus including:
  • Encoding means for, when the target code length M satisfies a predetermined condition, using a first code length N Polar mother code 1 of encoding the information bit sequence and outputs a first coded bit sequence, N is equal to less than 1 M, N 1 is an integer power of 2; or when the target code length M does not satisfy the preset condition, the information bit sequence is encoded and outputted by using a Polar code of the second mother code length N 2 a second coded bit sequence, N 2 is greater than or equal to M, and N 2 is an integer power of 2;
  • a rate matching unit configured to repeat at least a part of the bits of the first coded bit sequence to obtain a first target Polar code of length M; or shorten or punctify the second coded bit sequence to obtain a length M The second target Polar code.
  • a communication device including:
  • a transceiver for communicating with other devices
  • a processor configured to execute the program stored in the memory, when the program is executed, the processor is configured to use, when the target code length M of the Polar code satisfies a preset condition,
  • a Polar code of a mother code length N 1 encodes the information bit sequence, outputs a first coded bit sequence, N 1 is less than or equal to M, and N 1 is an integer power of 2; repeating at least a portion of the first coded bit sequence Bits, obtaining a first target Polar code of length M; when the target code length M does not satisfy the preset condition, encoding the information bit sequence by using a Polar code of the second mother code length N 2 Outputting a second coded bit sequence, N 2 is greater than or equal to M, and N 2 is an integer power of 2; shortening or puncturing the second coded bit sequence to obtain a second target Polar code of length M.
  • a method for de-rate matching of a Polar code including:
  • the transmitting end performs rate matching by using a repeated method; determining the position of the repeated bit, and adding and combining the LLRs of the repeated positions in the LLRs of the received M bits to obtain An LLR of a first to-be-decoded bit sequence having a length of the first mother code length N 1 , wherein N 1 is less than or equal to M, and N 1 is an integer power of 2; LLR according to the first bit sequence to be decoded Perform Polar code decoding;
  • the transmitting end performs rate matching by shortening or puncturing, determines the shortening or punching position and its LLR, and recovers the LLR of the received M bits.
  • the second mother code length N 2 Up to the second mother code length N 2 , obtaining an LLR of a second to-be-decoded bit sequence having a length of the second mother code length N 2 , wherein N 2 is greater than or equal to M, and N 2 is an integer power of 2;
  • the LLR of the second bit-decoded bit sequence is subjected to Polar code decoding.
  • a decoding apparatus including:
  • a receiving unit configured to receive a log likelihood ratio LLR of a bit sequence to be decoded of length M, where M is a target code length of the Polar code encoding;
  • a rate matching unit configured to: when the target code length M satisfies a preset condition, determine that the transmitting end uses a repeated method to implement rate matching; determine a position of the repeated bit, and repeat the position in the LLR of the received M bits.
  • the LLR performs addition and combining to obtain an LLR of a first to-be-decoded bit sequence having a length of the first mother code length N 1 , where N 1 is less than or equal to M, and N 1 is an integer power of 2;
  • N 1 is less than or equal to M
  • N 1 is an integer power of 2
  • the transmitting end uses the method of shortening or punching to achieve rate matching, determine the shortening or punching position and its LLR, and restore the LLR of the received M bits to the first
  • the second mother code length N 2 is obtained as an LLR of a second to-be-decoded bit sequence having a length of the second mother code length N 2 , wherein N 2 is greater than or equal to M, and N 2 is an integer power of 2;
  • a decoding unit configured to perform Polar code decoding according to the LLR of the first to-be-decoded bit sequence or the second to-be-decoded bit sequence.
  • a communication device including:
  • a transceiver for communicating with other devices
  • a processor configured to execute the program stored by the memory, when the program is executed, the processor is configured to determine that the transmitting end adopts a repeated method when the target code length M of the Polar code encoding satisfies a preset condition The rate matching is performed, the position of the repeated bit is determined, and the LLRs of the repeated positions in the LLRs of the received M bits are added and combined to obtain an LLR of the first to-be-decoded bit sequence having a length of the first mother code length N 1 . , wherein N 1 is less than or equal to M, and N 1 is an integer power of 2; performing Polar code decoding according to the LLR of the first bit sequence to be decoded; or
  • the second mother code length N 2 is obtained as an LLR of a second to-be-decoded bit sequence having a length of the second mother code length N 2 , wherein N 2 is greater than or equal to M, and N 2 is an integer power of 2;
  • the LLR of the two to-be-decoded bit sequence is subjected to Polar code decoding.
  • the seventh aspect provides a rate matching method for a Polar code, including:
  • R 1 K/N 1
  • K is the number of information bits
  • N 1 2 n
  • n is an integer less than or equal to log 2 M
  • M is Polar The target code length of the code
  • the information bit sequence is encoded by using a Polar code having a mother code length N 1 , and N 1 coded bits are output; the N 1 bits of encoded bits repeated to obtain at least a portion of length M Polar first target code;
  • the information bit sequence is encoded by using a Polar code of a mother code length N 2 , and N 2 coded bits are output, and N 2 is greater than or equal to
  • the target code length M, N 2 is an integer power of 2; shortening or puncturing the N 2 coded bits to obtain a second target Polar code of length M.
  • the eighth aspect provides a rate matching method for a Polar code, the method comprising:
  • N max is an integer power of 2;
  • the information bit sequence is encoded by a Polar code having a mother code length of N max , and N max coded bits are output; the N max codes are encoded. At least a portion of the bits are repeated to obtain a first target Polar code of length M
  • the to-be-coded bit sequence is encoded by using a Polar code having a mother code length of N, and N coded bits are output, where N is greater than or equal to the target code.
  • the length M, N is an integer power of 2; shortening or puncturing the N coded bits to obtain a second target Polar code of length M.
  • a ninth aspect provides a method for rate matching of a Polar code, the method comprising:
  • a first set of values selected from a mother code length N 1 is any one of the following three conditions are satisfied a preset condition as the value of the smallest first mother code length is N 1, the rate matching scheme using repeated; if not If there is a value of the first mother code length N 1 that satisfies any of the following preset conditions, a shortened or punctured rate matching scheme is adopted; wherein the three preset conditions are:
  • the target code length is greater than a preset maximum mother code length N max , and the first mother code length N 1 is N max ;
  • the difference between the target code length M and the first mother code length N 1 is less than a predetermined range, where N 1 is less than or equal to M, and N 1 is an integer power of 2.
  • At least a part of the bits of the first coded bit sequence are repeated according to a predetermined rule, the predetermined The rules include any of the following methods: order from back to front, order from head to back, random, bit reverse order from back to front, bit reverse order from going to the back, or reliability from high to low.
  • the repeated position is determined according to a predetermined rule, where the predetermined rule includes any one of the following manners: the order is from back to front The order is from the beginning to the end, random, bit reverse order from back to front, bit reverse order from the back to the end or reliability from high to low.
  • the first mother code length is a maximum integer less than or equal to log 2 M.
  • the value of the second code rate is 1/4, 1/3, 1/4, 1/5, 1/6, 1/7, 1/8, 1/9, 1/10, 1/11, 1/12, 2/7, 3/8, 2/9, 3/10, 2/11 or 3/11.
  • the preset condition is that the target code length is greater than a preset maximum mother code length N max .
  • the first mother code length is N max .
  • the N max is 8192, 4096, 2048, 1024, 512, 256, 128, or 64.
  • the second mother code length is a minimum power of two equal to or greater than the target code length.
  • the preset condition is that at least one of the following conditions is met, and the determined condition is determined by any one of the following conditions: The smallest value of the set of all values of the first mother code length is taken as the value of the first mother code length:
  • the difference between the target code length M and the first mother code length N 1 is less than a predetermined range.
  • the preset condition is: the difference between the target code length M and the first mother code length N 1 is less than a predetermined range, wherein N 1 is less than or equal to M, and N 1 is an integer power of 2.
  • the difference between the target code length M and the first mother code length N 1 is less than a predetermined range, which is expressed as one of the following:
  • ⁇ is a constant, for example, 1/8, 1/4 or 3/8.
  • the value of ⁇ is a function of the first code rate R 1 , and ⁇ decreases as the R1 increases.
  • ⁇ is a function of the first code rate R 1 as:
  • ⁇ is a function of the first code rate R 1 as:
  • R3 is a code rate threshold, which is a constant, and R 3 can be 1/4, 1/6, 1/3, 1/5, 1/7, 1/8, 1/9, 1/10, 1/11, 1/12, 2/7, 3/8, 2/9, 3/10, 2/11 or 3/ 11 and so on.
  • Yet another aspect of the present application is directed to a computer readable storage medium having instructions stored therein that, when executed on a computer, cause the computer to perform the methods described in the various aspects above.
  • Yet another aspect of the present application provides a computer program product comprising instructions which, when run on a computer, cause the computer to perform the methods described in the various aspects above.
  • Yet another aspect of the present application provides a computer program that, when run on a computer, causes the computer to perform the methods described in the various aspects above.
  • Yet another aspect of the present application provides a communication device, including:
  • a processor configured to execute the program stored in the memory, when the program is executed, the processor is configured to perform the first aspect, the fourth aspect, the seventh aspect, the eighth aspect, or the ninth aspect A method, or any one of the possible implementations of the first aspect, the fourth aspect, the eighth aspect, or the ninth aspect.
  • the rate matching scheme is determined according to the target code length, and the repetition rate-based matching scheme is adopted when the preset condition is met. Since the mother code length is less than or equal to the target code length, the target code length is not 2 When the integer power is used, the scheme that the mother code length is smaller than the shortening or puncturing under the same condition can satisfy the coding gain requirement and reduce the coding complexity, thereby reducing the delay. When the target code length does not satisfy the preset condition, a shortened or punctured rate matching scheme is adopted.
  • the decoding end determines the rate matching scheme adopted by the encoding end according to the corresponding manner, and performs rate matching and decoding. Through the embodiments of the present application, the coding gain loss and complexity are well balanced.
  • FIG. 1 is a schematic diagram of a basic flow of a wireless communication transmitting end and a receiving end;
  • FIG. 2 is a schematic diagram of an encoding apparatus 200 implemented in the present application
  • FIG. 3 is a schematic flow chart of a rate matching method implemented by the present application.
  • FIG. 4 is a schematic diagram of a circular buffer implemented by the present application.
  • FIG. 5 is a performance comparison diagram of determining a performance based on a repetition rate matching scheme and a shortening based rate matching scheme on an AWGN channel by a code rate threshold;
  • FIG. 6 is a performance comparison diagram of a repetition-based rate matching scheme and a shortened-based rate matching scheme determined by a maximum mother code length in an AWGN channel;
  • FIG. 7 is a schematic diagram of a communication device 700 implemented by the present application.
  • FIG. 8 is a schematic diagram of a decoding apparatus 800 implemented by the present application.
  • FIG. 9 is a schematic flow chart of a solution rate matching method implemented by the present application.
  • FIG. 1 is a basic flow of wireless communication.
  • the source is sequentially transmitted after source coding, channel coding, and digital modulation.
  • the destination is outputted by digital demodulation, channel decoding, and source decoding.
  • the channel codec can use a Polar code. Since the code length of the original Polar code (parent code) is an integer power of 2, in practical applications, a Polar code of arbitrary code length needs to be implemented by rate matching. As shown in FIG. 1, rate matching is performed after channel coding at the transmitting end to implement an arbitrary target code length, and at the receiving end, de-rate matching is performed before channel decoding.
  • the technical solution of the embodiment of the present application can be applied to a 5G communication system, and can also be applied to other various communication systems, for example, a Global System of Mobile communication (GSM) system, and Code Division Multiple Access (CDMA).
  • GSM Global System of Mobile communication
  • CDMA Code Division Multiple Access
  • WCDMA Wideband Code Division Multiple Access
  • GPRS General Packet Radio Service
  • LTE Long Term Evolution
  • FDD frequency division duplex
  • Frequency Division Duplex system LTE Time Division Duplex
  • Universal Mobile Telecommunication System UMTS
  • the rate matching method of the Polar code selects the mother code length to be less than or equal to the target code length (greater than the number of information bits), and constructs and encodes the Polar code according to the determined mother code length. The coded bits are repeated to reach the target code length, thereby achieving rate matching of the Polar code.
  • the rate matching and de-rate matching process is as follows:
  • the receiving end acquires the MLR of the M bits, determines the position of the repeated bits, and combines the Log-likelihood Ratio (LLR) of the repeated positions to obtain the LLRs of the N bits to be decoded. To achieve de-rate matching.
  • the decoding is performed according to the LLRs of the N bits to be decoded.
  • the rate matching is implemented by using a repeated method. Since the mother code length is smaller than the target code length, the mother code length is smaller than that of the prior art, which reduces the complexity of the compiled code.
  • a condition can be set for the target code length.
  • the rate matching is implemented by using a repeated scheme, that is, the mother code length is less than the target code length.
  • the complexity is low, and the gain loss due to repetition is also within an acceptable range.
  • the rate matching is implemented by using a repetition or shortening scheme. The length of the selected mother code is greater than the target code length, and the complexity is higher by shortening or punching to the target code length. Loss of gain is avoided.
  • the encoding device 200 shown in FIG. 2 can perform encoding and rate matching. As shown in FIG. 3, encoding and rate matching may include the following processes:
  • This step can be implemented by the obtaining unit 201 of FIG. 2, and the obtaining unit 201 acquires the information bit sequence and the target code length M of the Polar code.
  • the target code length can be determined based on the number of information bits K and the used code rate R. For example, if the number of information bits is 20 and the code rate is 1/8, then the target code length is 160.
  • the encoding unit 202 encodes the information bit sequence by using the Polar code of the first mother code length N 1 , and outputs a first coded bit sequence of length N 1 , N 1 .
  • N 1 is an integer power of 2;
  • the encoding unit 202 encodes the information bit sequence by using a Polar code of the second mother code length N 2 , and outputs a second coded bit of length N 2 .
  • the sequence, N 2 is greater than or equal to M, and N 2 is an integer power of 2.
  • the rate matching unit 203 repeats at least a part of the bits of the first coded bit sequence to obtain the first target of length M.
  • Polar code
  • the mother code length N 2 used in step 402 is greater than or equal to the target code length.
  • the rate matching unit 203 shortens or punctifies the second coded bit sequence to obtain a length M.
  • the second target Polar code is
  • the rate matching is performed by using a repeated scheme, and can be repeated according to a predetermined rule until the target code length M, and the target Polar code is obtained.
  • the predetermined rule may include any one of the following: order from back to front, order from after to go, random, bit reverse order from back to front, bit reverse order from after going to or from high to low according to reliability.
  • Bit reverse order refers to converting a decimal integer (index of coded bits) into a binary form, inverting the order of the binary elements, converting the inverted binary numbers into decimal, and the newly obtained number is the bit reverse order value of the original number. .
  • the reliability here refers to the reliability of the polarized channel corresponding to the coded bits, and is repeated from high to low according to the reliability, indicating that the more important coded bits are preferentially repeated.
  • the N 1 coded bits can be placed in the circular buffer as shown in FIG. 4 according to the above predetermined rule, and the coded bits are sequentially read from the circular buffer at the rate matching until the target code length M. Assuming N 1 is 128 and M is 160, then 32 coded bits need to be repeated.
  • the 128 coded bits are sorted according to reliability and placed in a circular buffer, and the 1-128 bits are sequentially read, and then 32 bits are continuously read to obtain a Polar code having a length of 160.
  • the target code length M in step 302 and step 303 satisfies a preset condition, which may be that the first code rate R 1 determined by the information bit number K and the target code length M is less than or equal to the preset second code.
  • Rate R 2 a preset condition
  • the first code rate R 1 K/N 1
  • K is the number of information bits
  • N 1 2 n
  • n is an integer less than or equal to log 2 M. That is, N 1 is an integer power of 2 and is less than or equal to the target code length M.
  • the second code rate is a code rate threshold used to determine the rate matching scheme.
  • N 1 coded bits are output, and at least a part of the bits of the N 1 coded bits are repeated to obtain a length of M's target Polar code.
  • the second mother code length N 2 encodes the information bit sequence by using a minimum integer power equal to or greater than the target code length, and outputs N 2 coded bits, and performs N 2 coded bits. Shortening or puncturing results in a second target Polar code of length M.
  • the mother code length is determined by comparing the first code rate with the second code rate, and the rate matching scheme is determined correspondingly, and the second code rate may be referred to as a mother code rate threshold.
  • the value of the mother code rate threshold can be set according to the actual application.
  • the mother code rate threshold can be flexibly set to a value between 0 and 1 according to the application scenario, for example, the R 2 value includes But not limited to 1/3, 1/4, 1/5, 1/6, 1/7, 1/8, 1/9, 1/10, 1/11, 1/12, 2/7, 3/8 , 2/9, 3/10, 2/11, 3/11, etc.
  • the value of R 2 is not limited to the example exemplified herein, nor is it limited to the form of the score used here, and may be set to a value such as 0.167 with a decimal point.
  • FIG. 5 shows the performance comparison between the repeated rate matching scheme and the shortening scheme in Additive White Gaussian Noise (AWGN) channels at different bit rates when the number of information bits is 40.
  • the target code length M corresponding to the two solid lines is 224, and the block is marked with a repeated rate matching scheme, encoded to 128 bits (the first mother code length N 1 ), and 224 bits are obtained by repeating 96 bits (target code) Long); the asterisk "*" marks a shortened rate matching scheme, encoding to 256 bits (second mother code length N 2 ), shortening 32 bits to 224 bits (target code length).
  • AWGN Additive White Gaussian Noise
  • Rate matching It can be seen that when the block error rate is 10 -3 , the coding gain loss based on the repeated rate matching scheme is about 0.3 dB. When the code rate is higher, the coding length is smaller, and the coding gain loss is larger, so the first code When the rate is greater than the rate threshold, it is suitable to use a shortening or punching scheme.
  • the target code length corresponding to the two dotted lines in Figure 5 is 288.
  • the asterisk “*” marks the use of a repeated rate matching scheme, encoding to 256 bits (the first mother code length N 1 ), by repeating 32 bits to 288 Bit; the circle “o” is marked with a shortened rate matching scheme, encoded to 512 bits (second mother code length N 2 ), shortening 224 bits to 288 bits. It can be seen that the repetition-based rate matching scheme is equivalent to the coding gain based on the shortened rate matching scheme, but the mother code length is half of the latter, so the delay and complexity of the compiled code are significantly reduced compared to the latter. .
  • the code rate is lower, the coding length is longer and the coding gain is closer, but the repetition rate-based matching scheme can significantly reduce the complexity and reduce the delay.
  • log 2 M is rounded to 7.
  • n can take values from 1 to 7.
  • R 1 > R 2 if N 1 selects a smaller value, then R 1 is larger and R 1 is definitely greater than R 2 . If R 2 is set to 1/6, then R 1 >R 2 . Therefore, in this case, no N 1 value is available to satisfy the repetition-based rate matching scheme.
  • M 288, log 2 M is rounded to 8, and theoretically n can take values from 1 to 8.
  • the code rate threshold R 2 is set to 1/7, the condition of R 1 ⁇ R 2 is not satisfied regardless of whether N 1 is selected to be 256 or 128.
  • a rate matching scheme of shortening or puncturing is employed.
  • N 1 can be 2048, 1024 or 512, and the like.
  • R 1 is 200/2048, 200/1024, 200/512, respectively.
  • the compiler code can be selected to have the lowest complexity, that is, the one with the smallest mother code length.
  • both 2018 and 1024 satisfy the preset condition, then select 1024 is taken as the value of N 1 . That is to say, when it is determined that the repetition-based rate matching scheme is adopted, the lowest length of the candidate mother code length that satisfies the preset condition is selected as the first mother code length.
  • a rate-based matching scheme based on repetition is selected, and only when the value of N 1 does not satisfy R 1 ⁇ R 2 , the shortening or Punching rate matching scheme.
  • the target code length M in step 302 satisfies the preset condition, which may be that the target code length M is determined to be greater than or equal to the preset maximum mother code length N max , and the value of N max may be flexibly set to 2 according to the actual application scenario.
  • the power of an integer such as 2048, 1024, 512, 256, 128, 64, or 32, etc., without limitation.
  • the value of N max has no upper limit, but is determined according to the application scenario. For example, in some application scenarios, such as a data channel, if the target code length reaches 6000 or 12000, the value of N max may be larger, for example, 4096 or 8192.
  • the first mother code length adopts N max , then the sender constructs and encodes a Polar code of length N max , and repeats (MN max ) bits to the first target Polar of the target code length M. code.
  • the receiving end combines the LLR signals of the repeated positions, restores to the mother code length Nmax, and then performs decoding.
  • N max 2048
  • the target code length M 600
  • M ⁇ N max at which time the rate matching is performed by shortening or puncturing
  • the mother code length is selected to be the smallest integer power of 2 greater than 600, that is, 1024.
  • the Polar code is constructed according to the mother code length 1024 and the target code length 600, and the encoding obtains 1024 bits, shortening or puncturing 424 bits to obtain the target 600 bits.
  • N max 1024
  • the target code length M 2400
  • M > N max at which time the rate matching is repeated
  • the mother code length is determined to be 1024.
  • the target code length is 2400.
  • the traditional rate matching scheme needs to be encoded to 4096 and then punctured or shortened to 2400.
  • the scheme of the present application is encoded to 2048/1024 bits from the perspective of coding gain, and then repeated to 2400 bits with little loss of coding gain relative to the conventional rate matching scheme (1024 is within 0.1 dB).
  • the buffer encoded to 2048 or 1024 is reduced to 1/2 or 1/4 with respect to 4096, the computational complexity is significantly reduced, and the decoding delay can be reduced by about 20% or 50%.
  • the target code length M of the solid line group in the figure is 1184
  • the mother code and code length corresponding to the box are 1024
  • 160 bits are repeated to 1184.
  • the mother code length corresponding to the asterisk "*" and the circle “o” are 2048, by shortening to reach 1184 bits.
  • the rate-based matching scheme based on repetition is equivalent to the coding gain based on the shortened rate matching scheme.
  • the target code length of the dashed group in FIG. 6 is 2400, the mother code length corresponding to the block is 1024, the repetition is 1376 bits to 2400 bits, and the mother code length corresponding to the asterisk "*" is 2048, and 352 bits are repeated. 2400 bits, the mother code length corresponding to the circle "o" is 4096 bits, which is shortened to 2400 bits.
  • the 2048-bit repetition is equivalent to the shortening-based coding gain, and the 1024-bit repetition ratio is reduced by 0.05 dB or less based on the shortened coding gain.
  • the target code length is not an integer power of 2
  • the length of the mother code used based on the repeated rate matching scheme is reduced by at least half, which can significantly reduce the required buffer size and reduce the complexity of the encoding and decoding operations. Reduce the delay.
  • the punching in the embodiment of the present application includes Quasi-Uniform Puncture (QUP).
  • the mother code length is an integer power greater than or equal to the target code length of 2
  • the punch mode (punch position) is determined according to the mother code length and the target code length.
  • the puncturing mode can be represented by a binary sequence (00...011...1), wherein it is determined that "0" indicates the punching position and "1" indicates the unpunched position.
  • Set the channel capacity corresponding to the punching position to 0 or set the error probability to 1 or the signal-to-noise ratio SNR to infinity
  • the information bits and fixed bit (freeze bits) locations are determined.
  • the encoding end deletes the bit in the punched position after encoding to obtain a polar code.
  • the scheme of shortening the (Shorten) Polar code described in the present application determines that the mother code length is an integer power of 2 or more greater than or equal to the target code length.
  • the coded bits of the shortened position are only related to fixed bits.
  • the process includes: calculating the reliability of the polarized channel according to the mother code, and then determining the Shorten position, the corresponding polarized channel placing a fixed bit, and determining the information bit and the frozen bit (fixed bit) position according to the reliability from the remaining polarized channels, The bit that is in the shortened position after encoding is deleted to obtain a Polar code, and rate matching is achieved.
  • the communication device 700 includes:
  • a transceiver 701 configured to communicate with other devices
  • a memory 702 configured to store a program
  • a processor 703 configured to execute the program stored by the memory, when the program is executed, the processor is configured to: when the target code length M of the Polar code satisfies a preset condition, The Polar code of the first mother code length N 1 encodes the information bit sequence, and outputs a first coded bit sequence, N 1 is less than or equal to M, and N 1 is an integer power of 2; repeating at least the first coded bit sequence a part of the bits, the first target Polar code of length M is obtained; when the target code length M does not satisfy the preset condition, the information bit sequence is encoded by using a Polar code of the second mother code length N 2 And outputting a second coded bit sequence, N 2 is greater than or equal to M, and N 2 is an integer power of 2; shortening or puncturing the second coded bit sequence to obtain a second target Polar code of length M.
  • the transceiver 701, the memory 702, and the processor 703 are connected by a bus.
  • Whether the target code length M satisfies the preset condition and the corresponding rate matching implementation manner is the same as the foregoing, and whether the mother code rate threshold or the maximum mother code length can be determined by using the repetition rate matching scheme or shortening or Punch scheme to balance coding gain and complexity. Repeated implementations, shortening or puncturing can be implemented in the same way as described above.
  • the communication device has the dual function of compiling the code, performing the encoding and rate matching process when acting as the sender, and performing the de-rate matching and decoding process when acting as the receiver.
  • the communication device includes a baseband chip including an encoder and a decoder, the encoder being operative to perform the same functions as the aforementioned encoding device, and the decoder can perform the same functions as the aforementioned decoding device.
  • Such a communication device includes a device having a two-way wireless communication function such as a base station, a user equipment, and the like.
  • the decoding device 800 shown in Figure 8 can be used to perform the de-rate matching and decoding of the present application.
  • the de-rate matching and decoding process includes the following process:
  • LLR Log-likelihood Ratio
  • the receiving unit 801 receives the log likelihood ratio LLR of the bit sequence to be decoded of length M, and M is consistent with the target code length of the Polar code encoded by the encoding end.
  • the de-rate matching unit 802 determines that the transmitting end performs rate matching by using a repeated method; determines the position of the repeated bit, and performs the LLR of the repeated position in the LLR of the received M bits. Adding and combining to obtain an LLR of a first to-be-decoded bit sequence having a length of the first mother code length N 1 , wherein N 1 is less than or equal to M, and N 1 is an integer power of 2.
  • the de-rate matching unit 802 determines that the encoding end performs rate matching by shortening or puncturing, determines a shortened or punctured position and its LLR, and receives the receiving unit 801.
  • the LLR of the obtained M bits is restored to the second mother code length N 2 , and the LLR of the second to-be-decoded bit sequence having the length of the second mother code code length N 2 is obtained, where N 2 is greater than or equal to M, and N 2 is An integer power of 2.
  • the corresponding decoding end performs de-rate matching according to the predetermined repeated rules of both parties.
  • the rule of the code side repetition is that the order is from the back to the front, and when the rate is matched, the LLRs of the following MN 1 bits of the M bits are added and combined to obtain the LLR of the N 1 bits to be decoded.
  • the de-rate matching unit 802 treats the shortened bit as a known bit, and the corresponding LLR is set to infinity, and returns to the mother code length together with the received LLR of the unshortened position. .
  • the de-rate matching unit 802 treats the bit corresponding to the puncturing position as an unknown bit, and the corresponding log likelihood ratio is set to 0, and the received unpunctured Together with the LLR of the location, it is restored to the length of the mother code.
  • the decoding unit 803 When the target code length M satisfies the preset condition, the decoding unit 803 performs the Polar code decoding according to the LLR of the first to-be-decoded bit sequence.
  • the decoding unit 804 performs Polar code decoding according to the LLR of the second bit sequence to be decoded.
  • the target code length M in steps 902 and 903 satisfies the preset condition, and may mean that the information bit number K and the target code length M determine that the first code rate R 1 is less than or equal to the preset value.
  • the second code rate R 2 .
  • the first code rate R 1 K/N 1
  • K is the number of information bits
  • N 1 2 n
  • n is an integer less than or equal to log 2 M.
  • the selection process of N 1 is the same as that of the encoding end.
  • the second code rate can also be referred to as a mother code rate threshold, which is preset in the code side.
  • the value of R 2 is the same as that of the encoding end and can be 1/4 or 1/6.
  • R 2 of the encoding end is 1/4, and the decoding end is also 1/4.
  • R 1 ⁇ R 2 it is determined that the encoding end adopts a repeated rate matching scheme, and the mother code length used is N 1 .
  • R 1 > R 2 it is determined that the coding end uses a shortening or punching scheme.
  • the preset condition may also be setting a maximum mother code length N max , comparing the target code length M and the maximum mother code length. If M ⁇ N max is satisfied, it is determined that the transmitting end uses a repeated scheme for rate matching, so the decoding end correspondingly Perform rate resolution matching. If M ⁇ N max , it is determined that the transmitting end adopts a shortening or puncturing scheme for rate matching, and the decoding end performs corresponding de-rate matching. Like the encoding end, N max can be set to an integer power of 2, such as 2048, 1024, 512, 256, 128, 64, or 32, etc., without limitation.
  • the coding end can be pre-set to use a rate matching scheme that shortens or puncturing when the target code length M does not satisfy the preset condition. For example, a unified shortening scheme or a uniform punching scheme can be adopted.
  • the communication device shown in FIG. 7 can also be used to perform a de-rate matching and decoding process, the communication device comprising:
  • a transceiver 701 configured to communicate with other devices
  • a memory 702 configured to store a program
  • the processor 703 is configured to execute the program stored by the memory 701. When the program is executed, the processor 703 is configured to determine a sending end when a target code length M of the Polar code encoding meets a preset condition.
  • the rate matching is implemented by using a repeated method, the position of the repeated bits is determined, and the LLRs of the repeated positions in the LLRs of the received M bits are added and combined to obtain a first to-be-decoded length of the first mother code length N 1 .
  • the transmitting end uses the method of shortening or punching to achieve rate matching, determine the shortening or punching position and its LLR, and recover the LLR of the received M bits.
  • the second mother code length N 2 Up to the second mother code length N 2 , obtaining an LLR of a second to-be-decoded bit sequence having a length of the second mother code length N 2 , wherein N 2 is greater than or equal to M, and N 2 is an integer power of 2;
  • the LLR of the second bit-decoded bit sequence is subjected to Polar code decoding.
  • the method for determining whether the target code length M satisfies the preset condition and the corresponding solution rate matching is the same as the foregoing, and the code end rate or the maximum mother code length can be determined by using the repetition rate-based rate matching scheme. It is also a rate matching scheme that shortens or punches.
  • the scheme of the present application can be used for a control channel or a data channel.
  • the control channel needs to send less information bits. Therefore, in an embodiment, when the code is compiled, according to whether the target code length in the present application satisfies a predetermined condition, the code length (matrix code length) and the rate matching scheme in various situations are listed and stored. At the end of the compiled code. That is to say, the coding end does not need to determine whether the target code length satisfies the preset condition, but directly reads the corresponding parameter from the configured parameters for coding, rate matching, and corresponding solution according to the set rule. Rate matching and decoding.
  • the configured coding parameters may be stored in the form shown in Table 1.
  • the number of information bits, the target code length, the mother code length, and the rate matching scheme have been determined according to preset rules.
  • the rate matching scheme may also be unclear. If the mother code length is less than or equal to the target code length, it is determined to be a repeated rate matching scheme; if the mother code length is greater than the target code length, it is determined to adopt a shortening or puncturing scheme.
  • the code side can be uniformly specified to be shortened or punctured, and the corresponding shortening mode or punching mode. Of course, it can also be clearly indicated in the configuration parameters. How to repeat can also do the same configuration on the compiler side.
  • the mother code length and rate matching scheme in each case can be determined.
  • R 2 is taken as 1/6
  • the coding parameters and rate matching schemes in different situations can also be determined.
  • the communication device in the embodiment of the present application may be a wireless communication device such as an access point, a station, a base station, or a user terminal.
  • the Polar code in the embodiment of the present application may also be a CA-Polar code or a PC-Polar code.
  • Arikan Polar refers to the original Polar code, which is not cascaded with other codes, only information bits and frozen bits.
  • the CA-Polar code is a Polar code that is cascaded with a Cyclic Redundancy Check (CRC).
  • the PC-Polar code is a code of a Parity Check (PC). PC-Polar and CA-Polar improve the performance of Polar codes by cascading different codes.
  • the “information bit sequence” in the embodiment of the present application may also be called “bit sequence to be encoded” or “information bit set”.
  • the “number of information bits” may be the number of bits to be encoded in the bit sequence to be encoded. Number, or the number of elements in the information bit set.
  • the target code length M of the present application satisfies the preset condition, and the difference between the target code length M and the first mother code length N 1 is less than a predetermined range, where N 1 is less than or equal to M.
  • N 1 is an integer power of 2.
  • the preset condition may be: M ⁇ N 1 * (1 + ⁇ ). If there is a mother code length N 1 that satisfies the condition, it is determined that a repetition-based rate matching scheme is adopted, and the first mother code length N is adopted. 1 Performing Polar coding to obtain a first coded bit sequence, and repeating at least a part of the bits of the first coded bit to obtain a coded bit sequence of a target code length. If this condition is not met, a rate matching scheme based on shortening or puncturing is employed.
  • the above preset conditions can also be expressed as: Or MN 1 ⁇ N 1 * ⁇ , or
  • ⁇ can be a constant, for example set to 1/8, 1/4 or 3/8.
  • the function of ⁇ with respect to the code rate R 1 can be designed as:
  • ⁇ is a piecewise function determined by R 1 . If R 1 is less than the preset threshold R 3 , ⁇ takes a, a is a constant, and a can also be 1/16, 1/4, 3 /8 or 1/2, etc.; if R 0 is greater than or equal to the threshold R 3 , the value of ⁇ is taken as 0.
  • R 3 may be 1/4 or 1/6, or may be 1/3, 1/4, 1/5, 1/7, 1/8, 1/9, 1/10, 1/11, 1/12. , 2/7, 3/8, 2/9, 3/10, 2/11 or 3/11, etc.
  • the target code length is 128, and a coded bit sequence of length 128 is obtained, and 32 bits in the coded bit sequence are repeated to obtain 160.
  • M 160
  • the performance comparison between the repetition-based scheme and the perforation-based scheme is adopted.
  • the dotted line indicates a repetition-based rate matching scheme
  • the solid line indicates a perforation-based rate matching scheme.
  • the embodiment of the present application provides a plurality of embodiments for determining whether the target code length M satisfies a preset condition.
  • the minimum value may be selected from all values of N 1 respectively satisfying any of the above preset conditions.
  • the target code length is greater than a preset maximum mother code length N max , and N max is 512.
  • the set of values of N 1 obtained by the above three preset conditions is: ⁇ 128, 256, 512 ⁇ , adopting a scheme based on repetition rate matching, and selecting the smallest 128 as the value of the first mother code length, and encoding to obtain a code having a length of 128.
  • the bit sequence repeats the coded bit sequence to obtain a target code length of 576.
  • the unit and method processes of the examples described in the embodiments of the present application can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the solution. The skilled person can use different methods for each particular application to implement the described functionality.
  • the disclosed apparatus and method may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division, and the actual implementation may have another division manner.
  • multiple units or components may be combined or integrated into another system, or some steps may be omitted or not performed.
  • the coupling or direct coupling or communication connection of the various units to each other may be through some interfaces, which may be in electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separate, and may be located in one place or on multiple network elements.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above embodiments it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof.
  • software it may be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions.
  • the computer program instructions When the computer program instructions are loaded and executed on a computer, the processes or functions described in accordance with embodiments of the present invention are generated in whole or in part.
  • the computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable device.
  • the computer instructions can be stored in or transmitted by a computer readable storage medium.
  • the computer instructions can be from a website site, computer, server or data center to another website site by wire (eg, coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (eg, infrared, wireless, microwave, etc.) Transfer from a computer, server, or data center.
  • the computer readable storage medium can be any available media that can be accessed by a computer or a server (eg, a cloud server), a data center, or the like that includes one or more available media.
  • the usable medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape, a USB flash drive, a ROM, a RAM, etc.), an optical medium (eg, a CD, a DVD, etc.), or a semiconductor medium (eg, a solid state hard disk Solid State Disk (SSD) ))Wait.
  • a magnetic medium eg, a floppy disk, a hard disk, a magnetic tape, a USB flash drive, a ROM, a RAM, etc.
  • an optical medium eg, a CD, a DVD, etc.
  • a semiconductor medium eg, a solid state hard disk Solid State Disk (SSD)

Abstract

本申请实施例提供一种速率匹配方法、编译码装置和通信装置。该方法包括：获取信息比特序列和Polar码的目标码长M；当所述目标码长M满足预设条件时，采用第一母码码长N 1的Polar码对所述信息比特序列进行编码，输出第一编码比特序列，N 1小于等于M，N 1为2的整数次幂；重复所述第一编码比特序列的至少一部分比特，得到长度为M的第一目标Polar码；当所述目标码长M不满足所述预设条件时，采用第二母码码长N 2的Polar码对所述信息比特序列进行编码，输出第二编码比特序列，N 2大于等于M，且N 2为2的整数次幂；所述第二编码比特序列进行缩短或打孔，得到长度为M的第二目标Polar码。编码增益损失很小的情况下，采用基于重复的速率匹配方案，降低了编译码的复杂度。

Description

速率匹配方法、编码装置和通信装置
本申请要求于2017年01月5日提交中国专利局、申请号为201710007883.2、申请名称为“速率匹配方法、编码装置和通信装置”和于2017年3月16日提交中国专利局、申请号为201710157341.3、申请名称为“速率匹配方法、编码装置和通信装置”和的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明实施例涉及通信领域，并且更具体地，涉及速率匹配的方法和装置。
背景技术
通信系统通常采用信道编码提高数据传输的可靠性，以保证通信的质量。土耳其教授Arikan提出的极化码(Polar codes)是第一个理论上证明可以达到香农容量且具有低编译码复杂度的好码。Polar码是一种线性块码，其编码矩阵为G N，编码过程为
Figure PCTCN2018070056-appb-000001
其中
Figure PCTCN2018070056-appb-000002
是一个二进制的行矢量，长度为N(即母码长度)；G N是一个N×N的矩阵，且
Figure PCTCN2018070056-appb-000003
定义为log 2N个矩阵F 2的克罗内克(Kronecker)乘积。
上述矩阵
Figure PCTCN2018070056-appb-000004
Polar码的编码过程中，
Figure PCTCN2018070056-appb-000005
中的一部分比特用来携带信息，称为信息比特，这些比特的索引的集合记作
Figure PCTCN2018070056-appb-000006
；另外的一部分比特设置为收发端预先约定的固定值，称之为固定比特或冻结比特(frozen bits)，其索引的集合用
Figure PCTCN2018070056-appb-000007
的补集
Figure PCTCN2018070056-appb-000008
表示。Polar码的编码过程相当于：
Figure PCTCN2018070056-appb-000009
这里，G N.(A)是G N.中由集合A中的索引对应的那些行得到的子矩阵，G N(A C)是G N中由集合A C中的索引对应的那些行得到的子矩阵。
Figure PCTCN2018070056-appb-000010
为
Figure PCTCN2018070056-appb-000011
中的信息比特集合，信息比特个数为K；
Figure PCTCN2018070056-appb-000012
为
Figure PCTCN2018070056-appb-000013
中的固定比特集合，固定比特个数为(N-K)，是已知比特。这些固定比特通常被设置为0，但是只要收发端预先约定，固定比特可以被任意设置。固定比特设置为0时，Polar码的编码输出可简化为：
Figure PCTCN2018070056-appb-000014
是一个K×N的矩阵。
Polar码的构造过程即集合
Figure PCTCN2018070056-appb-000015
的选取过程，决定了Polar码的性能。Polar码的构造过程通常是，根据母码码长N确定共存在N个极化信道，分别对应编码矩阵的N个行，计算极化信道可靠度，将可靠度较高的前K个极化信道的索引作为集合A的元素，剩余(N-K)个极化信道对应的索引作为固定比特的索引集合
Figure PCTCN2018070056-appb-000016
的元素。集合A决定了信息比特的位置，集合
Figure PCTCN2018070056-appb-000017
决定了固定比特的位置。
从编码矩阵可以看出，原始Polar码(母码)的码长为2的整数次幂，在实际应用中需要通过速率匹配实现任意码长的Polar码。
现有技术采用打孔(puncture)或缩短(shorten)的方案实现速率匹配。现有技术在编码时总是通过对超过目标码长的母码进行打孔达到目标码长，译码时填充恢复至母码码长。编译码的缓存大小、复杂度和时延都跟母码长度有关，在缩短或打孔比特比较多时(例如从2048比特缩短或打孔到1200比特)，因打孔造成的额外开销很大。随着目标码长增加，码率降低，一方面可以带来编码增益，另一方面复杂度也随母码长度的增加而增加。
发明内容
本申请实施例提供速率匹配的方法及编码装置、解速率匹配的方法及译码装置、通信装置，能够降低polar码编译码的复杂度。
第一方面，提供一种Polar码的速率匹配方法，包括：获取信息比特序列和Polar码的目标码长M；当所述目标码长M满足预设条件时，采用第一母码码长N 1的Polar码对所述信息比特序列进行编码，输出第一编码比特序列，N 1小于等于M，N 1为2的整数次幂；重复所述第一编码比特序列的至少一部分比特，得到长度为M的第一目标Polar码；当所述目标码长M不满足所述预设条件时，采用第二母码码长N 2的Polar码对所述信息比特序列进行编码，输出第二编码比特序列，N 2大于等于M，且N 2为2的整数次幂；对所述第二编码比特序列进行缩短或打孔，得到长度为M的第二目标Polar码。
第二方面，提供一种编码装置，包括：
获取单元，获取信息比特序列和Polar码的目标码长M；
编码单元，用于当所述目标码长M满足预设条件时，采用第一母码码长N 1的Polar码对所述信息比特序列进行编码，输出第一编码比特序列，N 1小于等于M，N 1为2的整数次幂；或当所述目标码长M不满足所述预设条件时，采用第二母码码长N 2的Polar码对所述信息比特序列进行编码，输出第二编码比特序列，N 2大于等于M，且N 2为2的整数次幂；
速率匹配单元，用于重复所述第一编码比特序列的至少一部分比特，得到长度为M的第一目标Polar码；或对所述第二编码比特序列进行缩短或打孔，得到长度为M的第二目标Polar码。
第三方面，提供一种通信装置，包括：
收发器，用于和其他设备进行通信；
存储器，用于存储程序；
处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，所述处理器用于，所述处理器用于当Polar编码的目标码长M满足预设条件时，采用第一母码码长N 1的Polar码对信息比特序列进行编码，输出第一编码比特序列，N 1小于等于M，N 1为2的整数次幂；重复所述第一编码比特序列的至少一部分比特，得到长度为M的第一目标Polar码；当所述目标码长M不满足所述预设条件时，采用第二母码码长N 2的Polar码对所述信息比特序列进行编码，输出第二编码比特序列，N 2大于等于M， 且N 2为2的整数次幂；对所述第二编码比特序列进行缩短或打孔得到长度为M的第二目标Polar码。
第四方面，提供一种Polar码的解速率匹配的方法，包括：
接收长度为M的待译码比特序列的对数似然比LLR，M为Polar码编码的目标码长；
当所述目标码长M满足预设条件时，确定发送端采用重复的方法进行速率匹配；确定重复比特的位置，将接收到的M个比特的LLR中重复位置的LLR进行相加合并，得到长度为第一母码码长N 1的第一待译码比特序列的LLR，其中，N 1小于等于M，N 1为2的整数次幂；根据所述第一待译码比特序列的LLR进行Polar码译码；
当所述目标码长M不满足所述预设条件时，确定发送端采用缩短或打孔的方法进行速率匹配，确定缩短或打孔位置及其LLR，将接收到的M个比特的LLR恢复至第二母码长度N 2，得到长度为第二母码码长N 2的第二待译码比特序列的LLR，其中，N 2大于等于M，N 2为2的整数次幂；根据所述第二待译码比特序列的LLR进行Polar码译码。
第五方面，提供一种译码装置，包括：
接收单元，用于接收长度为M的待译码比特序列的对数似然比LLR，M为Polar码编码的目标码长；
解速率匹配单元，用于当所述目标码长M满足预设条件时，确定发送端采用重复的方法实现速率匹配；确定重复比特的位置，将接收到的M个比特的LLR中重复位置的LLR进行相加合并，得到长度为第一母码码长N 1的第一待译码比特序列的LLR，其中，N 1小于等于M，N 1为2的整数次幂；或用于当所述目标码长M不满足所述预设条件时，确定发送端采用缩短或打孔的方法实现速率匹配，确定缩短或打孔位置及其LLR，将接收到的M个比特的LLR恢复至第二母码长度N 2，得到长度为第二母码码长N 2的第二待译码比特序列的LLR，其中，N 2大于等于M，N 2为2的整数次幂；
译码单元，用于根据所述第一待译码比特序列或第二待译码比特序列的LLR进行Polar码译码。
第六方面，提供一种通信装置，包括：
收发器，用于和其他设备进行通信；
存储器，用于存储程序；
处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，所述处理器用于在Polar码编码的目标码长M满足预设条件时，确定发送端采用重复的方法实现速率匹配，确定重复比特的位置，将接收到的M个比特的LLR中重复位置的LLR进行相加合并，得到长度为第一母码码长N 1的第一待译码比特序列的LLR，其中，N 1小于等于M，N 1为2的整数次幂；根据所述第一待译码比特序列的LLR进行Polar码译码；或
在所述目标码长M不满足预设条件时，确定发送端采用缩短或打孔的方法实现速率匹配，确定缩短或打孔位置及其LLR，将接收到的M个比特的LLR恢复至第二母码长度N 2，得到长度为第二母码码长N 2的第二待译码比特序列的LLR，其中，N 2大于等于M，N 2为2的整数次幂；根据所述第二待译码比特序列的LLR进行Polar码译码。
第七方面、提供一种Polar码的速率匹配方法，包括：
获得信息比特序列以及第一码率R 1，其中，R 1＝K/N 1，K为所述信息比特个数，N 1＝2 n，n是小于等于log 2M的整数，M为Polar编码的目标码长；
若所述第一码率R 1小于等于预定的第二码率R 2，采用母码码长为N 1的Polar码对所述信息比特序列进行编码，输出N 1个编码比特；对所述N 1个编码比特的至少一部分比特进行重复得到长度为M的第一目标Polar码；
若所述第一码率R 1大于所述第二码率R 2，则采用母码码长N 2的Polar码对所述信息比特序列进行编码，输出N 2个编码比特，N 2大于等于所述目标码长M，N 2为2的整数次幂；对所述N 2个编码比特进行缩短或打孔，得到长度为M的第二目标Polar码。
第八方面、提供一种Polar码的速率匹配方法，该方法包括：
获得预设的最大母码长度N max，N max为2的整数次幂；
若Polar编码的目标码长M大于所述最大母码长度N max，采用母码码长为N max的Polar码对信息比特序列进行编码，输出N max个编码比特；对所述N max个编码比特的至少一部分比特进行重复，得到长度为M的第一目标Polar码
若所述目标码长小于所述最大母码长度N max，则采用母码码长为N的Polar码对所述待信息比特序列进行编码，输出N个编码比特，N大于等于所述目标码长M，N为2的整数次幂；对所述N个编码比特进行缩短或打孔，得到长度为M的第二目标Polar码。
第九方面、提供一种Polar码的速率匹配的方法，该方法包括：
获取信息比特序列和Polar码的目标码长M；
从满足以下三个预设条件的任意一个条件的第一母码长度N 1的取值集合中选择最小的值作为第一母码长度N 1的值，采用重复的速率匹配方案；若均不存在满足以下任意预设条件的第一母码长度N 1的值，则采用缩短或者打孔的速率匹配方案；其中，所述三个预设条件分别为：
由所述信息比特的个数K和所述目标码长M确定的第一码率R 1小于等于预设的第二码率R 2，R 1＝K/N 1；
所述目标码长大于预设的最大母码长度N max，所述第一母码长度N 1为N max；和
所述目标码长M与所述第一母码长度N 1的差值小于预定的范围，其中，N 1小于等于M，N 1为2的整数次幂。
结合第一方面、第二方面、第三方面、第七方面或第八方面，在一种可能的实现方式中，按照预定的规则重复所述第一编码比特序列的至少一部分比特，所述预定的规则包括以下方式中的任意一种：顺序从后往前、顺序从前往后、随机、比特逆序从后往前、比特逆序从前往后或可靠度从高到低。
结合第四方面、第五方面或第六方面，在一种可能的实现方式中，按照预定的规则确定重复的位置，所述预定的规则包括以下方式中的任意一种：顺序从后往前、顺序从前往后、随机、比特逆序从后往前、比特逆序从前往后或可靠度从高到低。
结合第一方面至第六方面的任意一方面，在一种可能的实现方式中，所述预设的 条件为：由所述信息比特个数K和所述目标码长确定的第一码率R 1小于等于预设的第二码率R 2；其中，所述第一码率R 1＝K/N 1，K为待编码的信息比特个数，N 1＝2 n，n是小于等于log 2M的整数。在一种可能的实现方式中，所述第一母码码长为小于等于log 2M的最大整数。在一种可能的实现方式中，所述第二码率的值为1/4、1/3、1/4、1/5、1/6、1/7、1/8、1/9、1/10、1/11、1/12、2/7、3/8、2/9、3/10、2/11或3/11。
结合第一方面至第六方面的任意一方面，在一种可能的实现方式中，所述预设的条件为：所述目标码长大于预设的最大母码长度N max。在一种可能的实现方式中，所述第一母码长度为N max。在一种可能的实现方式中，所述N max为8192、4096、2048、1024、512、256、128或64。
结合以上所有方面，在一种可能的实现方式中，第二母码码长为大于等于目标码长的最小的2的整数次幂。
结合第一方面至第六方面的任意一方面，在一种可能的实现方式中，所述预设的条件为：满足以下条件中的至少一项条件，满足以下条件中任意一项所确定的第一母码长度的所有值的集合中最小的值作为所述第一母码长度的值：
由所述信息比特的个数K和所述目标码长M确定的第一码率R 1小于等于预设的第二码率R 2，R 1＝K/N 1；
所述目标码长大于预设的最大母码长度N max，N 1＝N max；或
所述目标码长M与所述第一母码长度N 1的差值小于预定的范围。
结合第一方面至第六方面的任意一方面，在一种可能的实现方式中，所述预设的条件为：所述目标码长M与所述第一母码长度N 1的差值小于预定的范围，其中，N 1小于等于M，N 1为2的整数次幂。在一种可能的实现方式中，所述目标码长M与所述第一母码长度N 1的差值小于预定的范围表示为以下中的一种：
M≤N 1*(1+δ)；
Figure PCTCN2018070056-appb-000018
M-N 1≤N 1*δ；或
Figure PCTCN2018070056-appb-000019
在一个可能的实现方式中，δ为常数，例如可以取值为1/8，1/4或3/8。
在一个可能的实现方式中，δ的取值是第一码率R 1的函数，δ随着R1的增加递减，其中
Figure PCTCN2018070056-appb-000020
在一个可能的实现方式中，δ与第一码率R 1的函数关系为：
δ＝β*(1-R 1)，或者，δ＝β*(1-R 1) 2，其中β为常数，例如β可以为1/2，3/8，1/4，1/8或1/16等。
在一个可能的实现方式中，δ与第一码率R 1的函数关系为：
Figure PCTCN2018070056-appb-000021
其中，a为常数，可以为1/16，1/4，3/8或1/2等，R3为码率门限，为常数，R 3可以为1/4、1/6、1/3、1/5、1/7、1/8、1/9、1/10、1/11、1/12、2/7、3/8、2/9、3/10、2/11或3/11等。
本申请的又一方面提了供一种计算机可读存储介质，所述计算机可读存储介质中存储有指令，当其在计算机上运行时，使得计算机执行上述各方面所述的方法。
本申请的又一方面提供了一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行上述各方面所述的方法。
本申请的又一方面提供了一种计算机程序，当其在计算机上运行时，使得计算机执行上述各方面所述的方法。
本申请的又一方面提供了一种通信装置，该包括：
存储器，用于存储程序；
处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，所述处理器用于执行第一方面、第四方面、第七方面、第八方面或第九方面所述的方法，或执行第一方面、第四方面、第八方面或第九方面的任意一种可能的实现方式。
本申请实施例中，根据目标码长确定采用何种速率匹配方案，在满足预设的条件时采用基于重复的速率匹配方案，由于母码码长小于等于目标码长，在目标码长不是2的整数次幂的时候，采用的母码码长小于相同条件下的缩短或者打孔的方案，能够满足编码增益的要求，又降低了编译码复杂度，从而减少了时延。在目标码长不满足预设的条件时，采用缩短或者打孔的速率匹配方案。译码端根据相应的方式确定编码端采用的速率匹配方案，并进行解速率匹配和译码。通过本申请的实施例，很好的平衡了编码增益损失与复杂度。
附图说明
图1是无线通信发送端和接收端的基本流程示意图；
图2是本申请实施的编码装置200的示意图；
图3是本申请实施的速率匹配方法的流程示意图；
图4是本申请实施的的循环缓冲器示意图；
图5是通过码率门限确定基于重复的速率匹配方案与基于缩短的速率匹配方案在AWGN信道下的性能对比图；
图6是通过最大母码长度确定的基于重复的速率匹配方案与基于缩短的速率匹配方案在AWGN信道下的性能对比图；
图7是本申请实施的通信装置700的示意图；
图8是本申请实施的译码装置800的示意图；
图9是本申请实施的解速率匹配方法的流程示意图；
图10所示是M＝160，K取不同值时，采用基于重复的方案与基于打孔的方案的性能比较。
具体实施方式
图1是无线通信的基本流程，在发送端，信源依次信源编码、信道编码、数字调制后发出。在接收端，依次通过数字解调、信道解码、信源解码输出信宿。信道编解码可以采用Polar码，由于原始Polar码(母码)的码长为2的整数次幂，在实际应用中需要通过速率匹配实现任意码长的Polar码。图1所示的，在发送端在信道编码后进行速率匹配实现任意的目标码长，在接收端，信道解码之前先进行解速率匹配。
本申请实施例的技术方案可以应用5G通信系统，也可以用于其他各种通信系统，例如：全球移动通讯(GSM，Global System of Mobile communication)系统、码分多址(CDMA，Code Division Multiple Access)系统、宽带码分多址(WCDMA，Wideband Code Division Multiple Access)系统、通用分组无线业务(GPRS，General Packet Radio Service)、长期演进(LTE，Long Term Evolution)系统、LTE频分双工(FDD，Frequency Division Duplex)系统、LTE时分双工(TDD，Time Division Duplex)、通用移动通信系统(UMTS，Universal Mobile Telecommunication System)等。
本申请实施例提供的Polar码的速率匹配方法，选择母码长度为小于等于目标码长(大于信息比特个数)的2的整数次幂，根据确定的母码长度构造和编码Polar码，对编码后的比特进行重复，达到目标码长，从而实现Polar码的速率匹配。速率匹配和解速率匹配过程如下：
(1)选择母码长度N＝2 n为小于等于目标码长M的2的整数次幂(n≤log 2M，n是整数)，目标码长M由信息比特个数K和码率R确定M＝INT(K/R)，INT表示取整；
(2)构造母码长度为N，信息个数为K的Polar码，并进行编码，得到编码比特序列；
(3)将编码比特序列的至少一部分比特按照约定次序进行重复，直到目标码长M，得到速率匹配后的待发送比特；
(4)接收端获取M个比特的LLR，确定重复比特的位置，将重复位置的对数似然比(英文：Log-likelihood Ratio，简称LLR)进行合并，得到N个待译码比特的LLR，从而实现解速率匹配。根据N个待译码比特的LLR进行译码。
采用重复的方法实现速率匹配，由于母码码长小于目标码长，母码长度比现有技术采用的方案小，降低了编译码的复杂度。
母码码长越长，由编码增益带来的性能越好，但是复杂度越高。随着码率降低，增加母码码长，编码增益带来的性能提升越小。因此可以进一步通过编码参数来平衡编码增益与复杂度的问题，例如可以针对目标码长设定一个条件，当条件满足的时候，采用重复的方案实现速率匹配，即母码码长小于目标码长，此时复杂度较低，由于重复带来的增益损失也在可接受范围内。而当设定的条件不满足的时候，采用重复或缩短的方案实现速率匹配，此时选择的母码长度大于目标码长，通过缩短或打孔到目标码长，此时复杂度较高但是避免了增益损失。
如图2所示的编码装置200可以执行编码和速率匹配。如图3所示，编码、速率匹配可以包括以下过程：
301、获取信息比特序列和Polar码的目标码长M。
该步骤可以由图2的获取单元201实施，获取单元201获取信息比特序列和Polar 码的目标码长M。目标码长可以根据信息比特个数K以及采用的码率R确定。例如信息比特个数为20，码率为1/8，那么目标码长为160。
302、根据预设的条件选择母码码长，对所述信息比特序列进行Polar码编码。
具体的，当目标码长M满足预设条件时，编码单元202采用第一母码码长N 1的Polar码对信息比特序列进行编码，输出长度为N 1的第一编码比特序列，N 1小于等于M，N 1为2的整数次幂；
当所述目标码长M不满足所述预设条件时，编码单元202采用第二母码码长N 2的Polar码对所述信息比特序列进行编码，输出长度为N 2的第二编码比特序列，N 2大于等于M，且N 2为2的整数次幂。
303、根据步骤302采用的母码长度确定速率匹配的方案，并进行速率匹配。
当目标码长M满足预设条件时，由于步骤302采用的母码长度N 1小于等于目标码长，速率匹配单元203重复第一编码比特序列的至少一部分比特，得到长度为M的第一目标Polar码；
当目标码长M不满足预设条件时，步骤402采用的母码长度N 2大于等于目标码长，相应的，速率匹配单元203对第二编码比特序列进行缩短或打孔，得到长度为M的第二目标Polar码。
采用重复的方案进行速率匹配，可以按预定的规则进行重复，直到目标码长M，得到目标Polar码。预定的规则可以包括以下中的任意一种：顺序从后往前、顺序从前往后、随机、比特逆序从后往前、比特逆序从前往后或根据可靠度从高到低的顺序等。比特逆序是指把一个十进制整数(编码比特的索引)转换成二进制形式，把二进制元素的顺序取反，把取反后的二进制数转换成十进制，新得到的数即是原数的比特逆序值。这里的可靠度是指编码比特对应的极化信道的可靠度，根据可靠度从高往低进行重复，表示优先重复更重要的编码比特。可以将N 1个编码比特按上述预定的规则放入如图4所示的循环缓冲器，速率匹配时从循环缓冲器顺序读取编码比特，直到目标码长M。假设N 1为128，M为160，则需要重复32个编码比特。将128个编码比特按照可靠度排序后放入循环缓冲器，顺序读取第1-128个比特，接着继续读取32个比特，得到长度为160的Polar码。
步骤302和步骤303所说的目标码长M满足预设的条件，可以是指由所述信息比特个数K和目标码长M确定的第一码率R 1小于等于预设的第二码率R 2。这里的第一码率R 1＝K/N 1，K为信息比特个数，N 1＝2 n，n是小于等于log 2M的整数。也就是说，N 1是2的整数次幂且小于等于目标码长M。第二码率是个码率门限，用于确定速率匹配方案。
也就是说，若R 1≤R 2，采用小于目标码长的第一母码码长N 1进行编码，输出N 1个编码比特，对N 1个编码比特的至少一部分比特进行重复得到长度为M的目标Polar码。若R 1＞R 2，第二母码长度N 2采用大于等于目标码长的最小的2的整数次幂，对信息比特序列进行编码，输出N 2个编码比特，对N 2个编码比特进行缩短或打孔得到长度为M的第二目标Polar码。通过比较第一码率与第二码率确定母码码长，相应的确定了速率匹配方案，第二码率又可以称作母码码率门限。母码码率门限的值可以根据实际运用情况进行设置，在本申请的实施例中，母码码率门限可以考虑应用场景进 行灵活设置为0至1之间的数值，例如R 2取值包括但不限于1/3、1/4、1/5、1/6、1/7、1/8、1/9、1/10、1/11、1/12、2/7、3/8、2/9、3/10、2/11、3/11等。R 2取值并不限于这里举例的例子，也不限于这里采用的分数的形式，也可以设置为诸如0.167等带有小数点的值。
码率门限的确定可以平衡编码增益与复杂度。图5展示了信息比特个数为40时，不同码率下采用重复的速率匹配方案与缩短方案在加性高斯白噪声(Additive White Gaussian Noise，简称AWGN)信道下的性能对比。两条实线对应的目标码长M为224，方框标记的是采用重复的速率匹配方案，编码到128比特(第一母码码长N 1)，通过重复96比特得到224比特(目标码长)；星号“*”标记的是采用缩短的速率匹配方案，编码到256比特(第二母码码长N 2)，缩短32比特到224比特(目标码长)。以码率门限R 2＝1/4为例，此时R 1＝K/N 1＝40/128>1/4，不满足R 1≤R 2的，因此可以采用打孔或者缩短的方案进行速率匹配。可以看出，在误块率为10 -3时，基于重复的速率匹配方案编码增益损失约0.3dB，当码率更高时，编码长度更小，编码增益损失会更大，因此第一码率大于码率门限的时候适合采用缩短或打孔的方案。
图5中两张虚线对应的目标码长为288，星号“*”标记的是采用重复的速率匹配方案，编码到256比特(第一母码码长N 1)，通过重复32比特到288比特；圆圈“o”标记的采用缩短的速率匹配方案，编码到512比特(第二母码码长N 2)，缩短224比特到288比特。可以看出，基于重复的速率匹配方案与基于缩短的速率匹配方案相比编码增益相当，但是母码长度是后者的一半，因此编译码的时延和复杂度相比后者有明显减小。以码率门限R 2＝1/4为例，，此时R 1＝K/N 1＝40/256<1/4，满足预设的条件R 1≤R 2，选择基于重复的速率匹配方案。当码率更低时，编码长度更长，编码增益更加接近，但是基于重复的速率匹配方案却可以明显降低复杂度，减少时延。
根据本申请的实施例，N 1＝2 n，n是小于等于log 2M的整数。例如M＝224时，log 2M取整后为7，理论上n可以取值从1～7。在图5所示的例子中，基于重复的速率匹配方案，n选择了小于等于log 2M的最大整数，即N 1＝2 7＝128。此时R 1>R 2,如果N 1选择更小的数值，那么R 1就更大，R 1肯定大于R 2。如果R 2设置为1/6，则此时R 1>R 2。因此该情况下，没有可用的N 1值能满足基于重复的速率匹配方案。另一个例子中，M＝288，log 2M取整后为8，理论上n可以取值从1～8。在图5所示的例子中，基于重复的速率匹配方案，n选择了小于等于log 2M的最大整数，即2 8＝256，满足R 1≤R 2条件。此时，若N 1选择了128，则不满足R 1≤R 2条件。如果码率门限R 2设置为1/7，则无论是N 1选择256还是128，都不满足R 1≤R 2的条件，此时采用缩短或打孔的速率匹配方案。
再举一个例子。假设信息比特的个数K＝200,目标码长M＝2400，码率门限R 2＝1/4。N 1最大的值可以取2048、1024或512等。R 1分别为200/2048,200/1024，200/512，当N 1取2048和1024时，均满足R 1≤R 2，可以采用基于重复的速率匹配的方案。当有两个以上母码长度均满足预设条件的时候，此时可以选择编译码复杂度最低，也就是母码长度最小的那个，本例子中2018和1024都满足预设的条件，那么选择1024作为N 1的值。也就是说，在确定采用基于重复的速率匹配方案时，优先从满足预设条件的候选母码码长中选择长度最低的作为第一母码长度。
本申请实施例中，只要有N 1取值能够满足满足R 1≤R 2，就选用基于重复的速率匹 配方案，只有N 1的取值全都不满足R 1≤R 2时，才采用缩短或者打孔的速率匹配方案。
步骤302所说的目标码长M满足预设的条件，可以是指所述目标码长M确定大于等于预设的最大母码长度N max，N max的值可以根据实际应用场景灵活设置为2的整数次幂，例如2048、1024、512、256、128、64或32等，没有限制。这里N max的取值并没有上限，而是根据应用场景来决定。例如，在某些应用场景中，例如数据信道上，若目标码长达到6000或12000，此时N max可以取值可以更大，例如取值4096或8192。如确定采用重复方案进行速率匹配，第一母码长度采用N max，则发送端构造和编码的长度为N max的Polar码，重复(M-N max)个比特到目标码长M的第一目标Polar码。接收端将重复位置的LLR信号合并，恢复到母码长度Nmax，然后进行译码。
例如N max＝2048，目标码长M＝600，M<N max，此时采用缩短或者打孔进行速率匹配，母码长度选取为大于600的最小的2的整数次幂，即1024。根据母码长度1024和目标码长600构造Polar码，编码得到1024个比特，缩短或者打孔掉424个比特，得到目标600个比特。
例如N max＝1024，目标码长M＝2400，M>N max，此时采用重复进行速率匹配，母码长度确定为1024。根据母码长度1024构造Polar码，编码得到1024个比特，重复1376个比特，得到2400个比特的目标Polar码。若N max＝2048，仍然满足M>N max，可以根据码长度2048构造Polar码，编码得到2048个比特，重复352个比特，得到2400个比特的目标Polar码。
若系统中最大的信息比特个数是200，最低码率是1/12，此时目标码长是2400，传统的速率匹配方案需要编码到4096然后打孔或者缩短到2400。本申请的方案从编码增益的角度考虑，编码到2048/1024比特，然后重复到2400比特相对于传统的速率匹配方案编码增益几乎没有损失(1024在0.1dB以内)。但是从复杂度的角度来说，编码到2048或1024的缓存相对于4096减少到1/2或1/4，运算复杂度有显著降低，译码时延可以减少20％或50％左右。
图6是基于重复的速率匹配方案与基于缩短的速率匹配方案在AWGN信道下的性能对比，信息比特个数K＝200。图中实线组的目标码长M是1184，方框对应的母码和编码长度为1024，重复160个比特到1184，星号“*”和圆圈“o”对应的母码码长都是2048，通过缩短达到1184个比特。从图6中可以看出，此时基于重复的速率匹配方案与基于缩短的速率匹配方案编码增益相当。
图6中虚线组的目标码长是2400，方框对应的母码码长为1024，重复1376个比特到2400比特，星号“*”对应的母码码长为2048，重复352个比特到2400个比特，圆圈“o“对应的母码码长是4096比特，通过缩短达到2400个比特。从图6中可以看出，通过2048比特重复与基于缩短的编码增益相当，通过1024比特重复比基于缩短的编码增益损失在0.05dB以内。但是与缩短相比，在目标码长不是2的整数次幂时，基于重复的速率匹配方案所使用的母码长度至少下降一半，可以显著降低所需的缓存大小，降低编译码运算复杂度、减少时延。
本申请实施例所说的打孔包括准均匀打孔(Quasi-Uniform Puncture，简称QUP)。 首先确定母码长度为大于等于目标码长的2的整数次幂，然后根据母码长度和目标码长确定打孔模式(打孔位置)。打孔模式可以通过二进制序列(00…011…1)表示，其中，确定“0”表示打孔位置，“1”表示未打孔位置。将打孔位置对应的信道容量设为0(或者错误概率设置为1或信噪比SNR设置为无穷小)，利用密度进化、高斯近似或者线性拟合的方法计算极化信道的可靠度并排序，确定信息比特和固定比特(冻结比特)位置。编码端将编码后处于打孔位置的比特删除得到polar码。
本申请所说的缩短(Shorten)Polar码的方案，确定母码长度为大于等于目标码长的2的整数次幂。缩短(Shorten)位置的编码比特只与固定比特有关。过程包括：根据母码计算极化信道的可靠度，然后确定Shorten位置，对应的极化信道放置固定比特，从余下的极化信道中根据可靠度确定信息比特和冻结比特(固定比特)位置，将编码后处于缩短位置的比特删除得到Polar码，实现速率匹配。基于Shorten的编码和速率匹配方案，由于不需要根据缩短位置重新计算极化信道的可靠度，只是将缩短位置对应的极化信道放置固定比特，大大降低Polar码的构造复杂度。
如图7所示，本申请提供了另一种可以实施编码和速率匹配的通信装置700。该通信装置700包括：
收发器701，用于和其他设备进行通信；
存储器702，用于存储程序；
处理器703，用于执行所述存储器存储的所述程序，当所述程序被执行时，所述处理器用于，所述处理器用于当Polar编码的目标码长M满足预设条件时，采用第一母码码长N 1的Polar码对信息比特序列进行编码，输出第一编码比特序列，N 1小于等于M，N 1为2的整数次幂；重复所述第一编码比特序列的至少一部分比特，得到长度为M的第一目标Polar码；当所述目标码长M不满足所述预设条件时，采用第二母码码长N 2的Polar码对所述信息比特序列进行编码，输出第二编码比特序列，N 2大于等于M，且N 2为2的整数次幂；对所述第二编码比特序列进行缩短或打孔得到长度为M的第二目标Polar码。收发器701、存储器702、处理器703之间通过总线连接。
判断目标码长M是否满足预设条件及对应的速率匹配的实现方式同前面所说的一样，可以通过母码码率门限或最大母码长度确定是采用基于重复的速率匹配方案，还是缩短或者打孔的方案，以平衡编码增益和复杂度。重复的实现方式，缩短或者打孔的实现方式与前面描述的可以一样。
在一些实施例中，通信装置具有编译码的双重功能，当作为发送方的时候执行编码、速率匹配流程，当作为接收方的时候，执行解速率匹配、译码流程。该通信装置中包含有基带芯片，该基带芯片含有编码器和译码器，编码器可以用于执行与前述的编码装置相同的功能，译码器可以执行与前述译码装置相同的功能。这样的通信装置包括基站、用户设备等具有双向无线通信功能的设备。
图8所示的译码装置800可以用来执行本申请的解速率匹配和译码。如图9所示，解速率匹配和译码过程包括以下过程：
901、接收长度为M的待译码比特序列的对数似然比(Log-likelihood Ratio，简称LLR)，M为Polar码编码的目标码长。
接收单元801接收长度为M的待译码比特序列的对数似然比LLR，M与编码端进行Polar编码的目标码长一致。
902、根据目标码长M确定编码端采用的速率匹配方案，并进行解速率匹配。
当所述目标码长M满足预设条件时，解速率匹配单元802确定发送端采用重复的方法进行速率匹配；确定重复比特的位置，将接收到的M个比特的LLR中重复位置的LLR进行相加合并，得到长度为第一母码码长N 1的第一待译码比特序列的LLR，其中，N 1小于等于M，N 1为2的整数次幂。
当所述目标码长M不满足所述预设条件时，解速率匹配单元802确定编码端采用缩短或打孔的方法进行速率匹配，确定缩短或打孔位置及其LLR，将接收单元801接收到的M个比特的LLR恢复至第二母码长度N 2，得到长度为第二母码码长N 2的第二待译码比特序列的LLR，其中，N 2大于等于M，N 2为2的整数次幂。
如果编码端采用重复的方案进行速率匹配，那么相应的解码端就根据双方预先确定的重复规则进行解速率匹配。例如编码端重复的规则是顺序从后往前，则速率匹配的时候就将M个比特中后面的M-N 1个比特的LLR进行相加合并，得到N 1个待译码比特的LLR。
如果编码端采用缩短方案进行速率匹配，则解速率匹配单元802将缩短位置的比特当作已知比特，对应的LLR设为无穷大，与接收到的未缩短位置的LLR一起，恢复至母码长度。
如果编码端采用的打孔的方案进行速率匹配，则解速率匹配单元802将打孔位置对应的比特当作未知比特处理，对应的对数似然比设为0，与接收到的未打孔位置的LLR一起，恢复至母码长度。
903、根据解速率匹配后的待译码比特序列的LLR进行Polar码译码。
当所述目标码长M满足预设条件时，相应的，译码单元803根据所述第一待译码比特序列的LLR进行Polar码译码；
当所述目标码长M不满足预设条件时，相应的，译码单元804根据所述第二待译码比特序列的LLR进行Polar码译码。
跟编码端类似的，步骤902和步骤903所说的目标码长M满足预设的条件，可以是指信息比特个数K和目标码长M确定的第一码率R 1小于等于预设的第二码率R 2。这里的第一码率R 1＝K/N 1，K为信息比特个数，N 1＝2 n，n是小于等于log 2M的整数。N 1的选取过程与编码端一样。第二码率也可以称作母码码率门限，是在编译码端预先设置好的。R 2取值与编码端相同，可以为1/4或1/6。例如编码端的R 2是1/4，译码端也是1/4。当R 1≤R 2，确定编码端采用的是重复的速率匹配方案，且用的母码码长为为N 1。当R 1>R 2，确定编码端采用的是缩短或打孔的方案。
预设条件也可以是设定最大母码长度N max，比较目标码长M与最大母码长度，若满足M≥N max,确定发送端采用重复的方案进行速率匹配的，因此译码端相应的进行解速率匹配。若M<N max，确定发送端采用的是缩短或者打孔方案进行速率匹配的，译码端相应的进行解速率匹配。与编码端相同，N max可以设置为2的整数次幂，例如2048、1024、512、256、128、64或32等，没有限制。
编译码端可以预先设置好在目标码长M不满足预设条件的时候，采用缩短还是打 孔的速率匹配方案。比如统一采用缩短的方案，或者统一采用打孔的方案。
如图7所示的通信装置也可以用于执行解速率匹配和译码过程，该通信装置包括：
收发器701，用于和其他设备进行通信；
存储器702，用于存储程序；
处理器703，用于执行所述存储器701存储的所述程序，当所述程序被执行时，所述处理器703用于在Polar码编码的目标码长M满足预设条件时，确定发送端采用重复的方法实现速率匹配，确定重复比特的位置，将接收到的M个比特的LLR中重复位置的LLR进行相加合并，得到长度为第一母码码长N 1的第一待译码比特序列的LLR，其中，N 1小于等于M，N 1为2的整数次幂；根据所述第一待译码比特序列的LLR进行Polar码译码；或
用于在所述目标码长M不满足预设条件时，确定发送端采用缩短或打孔的方法实现速率匹配，确定缩短或打孔位置及其LLR，将接收到的M个比特的LLR恢复至第二母码长度N 2，得到长度为第二母码码长N 2的第二待译码比特序列的LLR，其中，N 2大于等于M，N 2为2的整数次幂；根据所述第二待译码比特序列的LLR进行Polar码译码。
判断目标码长M是否满足预设条件及对应的解速率匹配的实现方式同前面所说的一样，可以通过母码码率门限或最大母码长度确定编码端是采用基于重复的速率匹配方案，还是缩短或者打孔的速率匹配方案。
本申请的方案可以用于控制信道或者数据信道。控制信道需要发送的信息比特比较少。因此在一个实施例中，编译码的时候可以根据本申请所说的目标码长是否满足预定的条件，列出来各种情形下的编码码长(母码码长)及速率匹配方案，并存储在编译码端。也就是说，编译码端不需要判断目标码长是否满足预设的条件这个步骤，而是直接根据设定的规则，从配置的参数中读取相应的参数进行编码、速率匹配以及对应的解速率匹配及解码。在一个例子中，假设采用母码码率(编码码率)门限的方式，设置码率门限R 2＝1/4，则配置的编码参数可能以表1所示的形式存储。此时已经根据预设的规则确定出来信息比特个数、目标码长、母码码长以及速率匹配方案。速率匹配方案也可以不明示出来，如果母码码长小于等于目标码长，则确定是重复的速率匹配方案；如果母码码长大于目标码长，则确定是采用缩短或者打孔的方案。编译码端可以统一规定是采用缩短的还是打孔的，以及对应的缩短模式或打孔模式。当然也可以在配置参数里明示出来。如何重复也是可以在编译码端做同样的配置。
信息比特个数K 目标码长M 母码码长N(编码码长) 速率匹配方案
…… …… …… ……
40 224 256 缩短或打孔
40 288 256 重复
…… …… …… ……
200 2400 1024 重复
200 1200 1024 重复
200 800 1024 缩短或打孔
表1
只要预设的条件确定，就可以定下来每种情形下的母码长度和速率匹配方案。例如R 2取1/6时也可以确定不同情形下的编码参数和速率匹配方案。
本申请实施例所说的通信装置，可以是接入点、站点、基站或者用户终端等无线通信设备。
本申请实施例所说的的Polar码，包括但不限于Arikan Polar码，还可以是CA-Polar码或者PC-Polar码。Arikan Polar是指原始的Polar码，没有与其它码级联，只有信息比特和冻结比特。CA-Polar码是Polar码级联了循环冗余校验(Cyclic Redundancy Check，简称CRC)的Polar码，PC-Polar码是Polar码级了奇偶校验(Parity Check，简称PC)的码。PC-Polar和CA-Polar是通过级联不同的码来提高Polar码的性能。
本申请实施例所说的“信息比特序列”，也可以叫做“待编码比特序列”或者“信息比特集合”，相应的，“信息比特个数”可以是待编码比特序列中待编码比特的个数，或者信息比特集合中的元素个数。
本申请所说的目标码长M满足预设的条件，还可以是：所述目标码长M与所述第一母码长度N 1的差值小于预定的范围，其中，N 1小于等于M，N 1为2的整数次幂。例如，预设的条件可以为：M≤N 1*(1+δ)，若存在满足该条件的母码长度N 1则确定采用基于重复的速率匹配方案，采用的第一母码码长N 1进行Polar编码得到第一编码比特序列，重复第一编码比特的至少一部分比特得到目标码长的编码比特序列。若不满足该条件则采用基于缩短或者打孔的速率匹配方案。上述预设的条件还可以表示为：
Figure PCTCN2018070056-appb-000022
或者M-N 1≤N 1*δ，或者
Figure PCTCN2018070056-appb-000023
δ可以为常数，例如设置为1/8,1/4或3/8。
可以取与码率相关的值，δ＝FUNCTION(R 1)，即是
Figure PCTCN2018070056-appb-000024
的函数，一般随着R 1的增加递减，其中，K是信息比特个数。也就是说，δ的取值跟信息比特个数以及母码长度有关。
在一个实施方式中，δ关于码率R的函数可以设计为：δ＝β*(1-R 1)，β为预设的常数，例如β可以为1/2，3/8，1/4，1/8或1/16等。也即是说，δ是R 1的线性函数，R 1越大，δ越小，即允许重复比特数量越少。
假设M＝160，K＝80，β＝1/2，取N1＝128，则R 1＝80/128＝0.625，δ＝1/2*(1-80/128)＝0.1875。用M≤N 1*(1+δ)来判断是否采用重复的速率匹配，N 1*(1+δ)＝128*(1+0.1875)＝152，因为M＝160>152，不满足M≤N 1*(1+δ)，因此不采用重复的速率匹配方案，而可以采用其他的方式比如缩短或者打孔。以上参数中，若K＝32，其他参数不变，则R 1＝32/128＝1/4，δ＝1/2*(1-1/4)＝3/8，N 1*(1+δ)＝128*(1+3/8)＝176，M＝160<176，满足M≤N 1*(1+δ)，因此采用基于重复的速率匹配方案，即第 一母码长度为128，编码得到长度为128的编码比特序列，重复该编码比特序列中的32比特得到160的目标码长。
在另一个实施方式中，δ关于码率R的函数可以设计为：δ＝β*(1-R 1) 2，β是常数，例如β可以为1/2。即δ是R 1的两次函数，R 1越大，δ越小，即允许重复比特数量越少。假设M＝160，K＝80，β＝1/2，取N1＝128，则R 1＝80/128＝0.625，δ＝1/2*(1-80/128) 2＝0.0703125。用M≤N 1*(1+δ)来判断是否采用重复的速率匹配，N 1*(1+δ)＝128*(1+0.0703125)＝137，因为M＝160>137，不满足M≤N 1*(1+δ)，因此不采用重复的速率匹配方案，而可以采用其他的方式比如缩短或者打孔。以上参数中，若K＝32，其他参数不变，则R 1＝32/128＝1/4，δ＝1/2*(1-1/4) 2＝9/32，N 1*(1+δ)＝128*(1+9/32)＝164，M＝160<164，满足M≤N 1*(1+δ)，因此采用基于重复的速率匹配方案，即第一母码长度为128，编码得到长度为128的编码比特序列，重复该编码比特序列中的32比特得到160的目标码长。
在另一个实施方式中，δ关于码率R 1的函数可以设计为：
Figure PCTCN2018070056-appb-000025
即，δ是由R 1确定的分段函数，若R 1小于预设的门限R 3时，δ取值a,a为常数，a的取值也可以为1/16，1/4，3/8或1/2等；若R 0大于等于门限R 3时，δ的值取为0。R 3可以为1/4或者1/6，也可以为1/3、1/4、1/5、1/7、1/8、1/9、1/10、1/11、1/12、2/7、3/8、2/9、3/10、2/11或3/11等。假设M＝160，K＝80，R3＝1/4；取N1＝128，则R 1＝80/128＝0.625>1/4，根据公式(1)δ＝0。用M≤N 1*(1+δ)来判断是否采用重复的速率匹配，N 1*(1+δ)＝128*(1+0)＝128，因为M＝160>128，不满足M≤N 1*(1+δ)，因此不采用重复的速率匹配方案，而可以采用其他的方式比如缩短或者打孔。以上参数中，若K＝32，其他参数不变，则R 1＝32/128＝1/4＝R3，δ的取值为0，不采用重复的速率匹配方案。若R 3＝1/6，则R 1＝32/128＝1/4<R 3,δ的取值为1/8，N1*(1+δ)＝128*(1+1/8)＝144，M＝160>144，不满足M≤N 1*(1+δ)，因此不采用重复的速率匹配方案，而可以采用其他的方式比如缩短或者打孔。如果公式(1)中，R 1<R 3，δ的取值为1/2，则N1*(1+δ)＝128*(1+1/2)＝192，M＝160<192，满足M≤N 1*(1+δ)，因此采用基于重复的速率匹配方案，即第一母码长度为128，编码得到长度为128的编码比特序列，重复该编码比特序列中的32比特得到160的目标码长。
如图10所示是M＝160，K取不同值时，采用基于重复的方案与基于打孔的方案的性能比较。其中，虚线表示采用基于重复的速率匹配方案，实线表示的采用基于打孔的速率匹配方案。目标码长设为固定值160，可以由256打孔(实线)得到或者由128重复得到(虚线)目标码长，如果基于128重复，需要重复的比特数量为(160-128)即32，重复比例为32/128＝1/4。从图10中可以看出，信息比特个数不同也即码率不同时，重复和打孔方案的性能表现不同。其中，高码率情况(K比较大，例如K＝80)时，重复相对于打孔有明显的性能损失(0.7dB左右)；而在低码率(K比较小，例如K＝20或K＝40)时，重复的方案性能与打孔的方案性能相当。因此，通过码率确定δ的取值，使得δ随着R 1的增加而减小，在性能损失相当或者不大的情况下采用重复的 速率匹配，较好地平衡了编码增益损失与复杂度。
本申请实施例提供了多种判断目标码长M是否满足预设的条件的实施例，在另一个实施例中，可以从分别从满足以上任意预设条件的N 1的所有取值中选择最小的值作为第一母码长度的值，采用基于重复的速率匹配方案；若均没有满足预设条件的第一母码长度的值，则采用缩短或者打孔的方案。假设M＝576，K＝20，根据不同的预设条件得到允许采用基于重复的速率匹配方案的情况下对应的N 1的值的集合。
预设条件1：由所述信息比特的个数K和所述目标码长M确定的第一码率R 1小于等于预设的第二码率R 2，R 1＝K/N 1。此处R 2取为1/4，根据R 1＝K/N 1，满足R 1<R 2的N 1有512、256、128。
预设条件2：
所述目标码长大于预设的最大母码长度N max，N max为512。根M＝576>512,满足预设条件，采用基于重复的速率匹配方案，N 1＝512。
预设条件3：
所述目标码长M与所述第一母码长度N 1的差值小于预定的范围，表示为M≤N 1*(1+δ)，δ的值通过公示(1)确定，a＝1/8，R 3＝1/6。若N 1＝512，R 1＝20/512<R 3，δ为1/8，N 1*(1+δ)＝576，M＝N 1*(1+δ)，满足预设条件。若N 1＝256，R 1＝20/256<R3，δ为1/8，N 1*(1+δ)＝288，M＞N 1*(1+δ)，不满足预设条件。因此，根据预设条件3确定的允许采用基于重复的速率匹配的方案的N 1为512。
上述三个预设条件得到的N 1的值的集合为：{128,256,512}，采用基于重复的速率匹配的方案，并选择最小的128作为第一母码长度的值，编码得到长度为128的编码比特序列，重复该编码比特序列，得到576的目标码长。以上三个预设条件中的参数可以参考本申请提供的实施例灵活设置。
本申请实施例描述的各示例的单元及方法过程，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能。
在本申请所提供的几个实施例中，应该理解到，所揭露的装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。例如多个单元或组件可以结合或者可以集成到另一个系统，或一些步骤可以忽略，或不执行。此外，各个单元相互之间的耦合或直接耦合或通信连接可以是通过一些接口实现，这些可以是电性、机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，既可以位于一个地方，也可以分布到多个网络单元上。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本发明实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者通过所述计算机可读存储介质进行传输。所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器(如，云服务器)、数据中心、等数据存储设备。所述可用介质可以是磁性介质，(例如，软盘、硬盘、磁带、U盘、ROM、RAM等)、光介质(例如，CD、DVD等)、或者半导体介质(例如固态硬盘Solid State Disk(SSD))等。

Claims (50)

  1. 一种Polar码的速率匹配的方法，其特征在于，包括：
    获取信息比特序列和Polar码的目标码长M；
    从满足以下三个预设条件的任意一个条件的第一母码长度N 1的取值集合中选择最小的值作为第一母码长度N 1的值，采用重复的速率匹配方案；若均不存在满足以下任意预设条件的第一母码长度N 1的值，则采用缩短或者打孔的速率匹配方案；其中，所述三个预设条件分别为：
    由所述信息比特的个数K和所述目标码长M确定的第一码率R 1小于等于预设的第二码率R 2，R 1＝K/N 1；
    所述目标码长大于预设的最大母码长度N max，所述第一母码长度N 1为N max；和
    所述目标码长M与所述第一母码长度N 1的差值小于预定的范围，其中，N 1小于等于M，N 1为2的整数次幂。
  2. 根据权利要求1所述的方法，其特征在于，设N 1＝2 n，n是小于等于log 2M的最大整数。
  3. 根据权利要求1或2所述的方法，其特征在于，所述第二码率的值为1/4、1/3、1/4、1/5、1/6、1/7、1/8、1/9、1/10、1/11、1/12、2/7、3/8、2/9、3/10、2/11或3/11。
  4. 根据权利要求1至3任意一项所述的方法，其特征在于，N max的值为2048、1024或512。
  5. 根据权利要求1至4任意一项所述的方法，其特征在于，所述目标码长M与所述第一母码长度N 1的差值小于预定的范围表示为以下中的一种：
    M≤N 1*(1+δ)；
    Figure PCTCN2018070056-appb-100001
    M-N 1≤N 1*δ；或
    Figure PCTCN2018070056-appb-100002
    其中，δ为常数或为第一码率R 1的函数。
  6. 根据权利要求5所述的方法，其特征在于，δ取值为1/8，1/4或3/8。
  7. 根据权利要求5所述的方法，其特征在于，δ与第一码率R 1的函数关系为：
    δ＝β*(1-R 1)，或者，δ＝β*(1-R 1) 2，其中β为常数。
  8. 根据权利要求7所述的方法，其特征在于，β为1/2，3/8，1/4，1/8或1/16。
  9. 根据权利要求5所述的方法，其特征在于，δ与第一码率R 1的函数关系为：
    Figure PCTCN2018070056-appb-100003
    其中，a，R 3为常数。
  10. 根据权利要求9所述的方法，其特征在于，a为1/16，1/4，3/8或1/2。
  11. 根据权利要求9或10所述的方法，其特征在于，R 3为1/4、1/6、1/3、1/5、1/7、1/8、1/9、1/10、1/11、1/12、2/7、3/8、2/9、3/10、2/11或3/11。
  12. 一种Polar码的速率匹配的方法，包括：
    获取信息比特序列和Polar码的目标码长M；
    当所述目标码长M满足预设条件时，采用第一母码码长N 1的Polar码对所述信息比特序列进行编码，输出第一编码比特序列，N 1小于等于M，N 1为2的整数次幂；重复所述第一编码比特序列的至少一部分比特，得到长度为M的第一目标Polar码；
    当所述目标码长M不满足所述预设条件时，采用第二母码码长N 2的Polar码对所述信息比特序列进行编码，输出第二编码比特序列，N 2大于等于M，N 2为2的整数次幂；对所述第二编码比特序列进行缩短或打孔，得到长度为M的第二目标Polar码。
  13. 根据权利要求12所述的方法，其特征在于，所述预设的条件为：由所述信息比特的个数K和所述目标码长M确定的第一码率R 1小于等于预设的第二码率R 2；其中，所述第一码率R 1＝K/N 1，N 1＝2 n，n是小于等于log 2M的整数。
  14. 根据权利要求13所述的方法，其特征在于，n为小于等于log 2M的最大整数。
  15. 根据权利要求13至14任意一项所述的方法，其特征在于，所述第二码率的值为1/4、1/3、1/4、1/5、1/6、1/7、1/8、1/9、1/10、1/11、1/12、2/7、3/8、2/9、3/10、2/11或3/11。
  16. 根据权利要求12所述的方法，其特征在于，所述预设的条件为：所述目标码长大于预设的最大母码长度N max。
  17. 根据权利要求16所述的方法，其特征在于，所述第一母码长度为N max。
  18. 根据权利要求17任一项所述的方法，其特征在于，N max的值为2048、1024或512。
  19. 根据权利要求12所述的方法，其特征在于，所述预设的条件为：所述目标码长M与所述第一母码长度N 1的差值小于预定的范围，其中，N 1小于等于M，N 1为2的整数次幂。
  20. 根据权利要求19所述的方法，其特征在于，所述目标码长M与所述第一母码长度N 1的差值小于预定的范围表示为以下中的一种：
    M≤N 1*(1+δ)；
    Figure PCTCN2018070056-appb-100004
    M-N 1≤N 1*δ；或
    Figure PCTCN2018070056-appb-100005
    其中，δ为常数或为第一码率R 1的函数。
  21. 根据权利要求20所述的方法，其特征在于，δ取值为1/8，1/4或3/8。
  22. 一种通信装置，其特征在于，包括：
    收发器，用于和其他设备进行通信；
    存储器，用于存储程序；
    处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，所述处理器用于执行如权利要求1-11任意一项所述的方法。
  23. 一种通信装置，其特征在于，包括：
    存储器，用于存储程序；
    处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，所述处理器用于执行如权利要求1-11任意一项所述的方法。
  24. 一种通信装置，用于执行如权利要求1-11所述的方法。
  25. 一种通信装置，其特征在于，包括：
    第一单元，用于获取信息比特序列和Polar码的目标码长M；
    第二单元，从满足以下三个预设条件的任意一个条件的第一母码长度N 1的取值集合中选择最小的值作为第一母码长度N 1的值，采用重复的速率匹配方案；若均不存在满足以下任意预设条件的第一母码长度N 1的值，则采用缩短或者打孔的速率匹配方案；
    其中，所述三个预设条件分别为：
    由所述信息比特的个数K和所述目标码长M确定的第一码率R 1小于等于预设的第二码率R 2，R 1＝K/N 1；
    所述目标码长大于预设的最大母码长度N max，所述第一母码长度N 1为N max；和
    所述目标码长M与所述第一母码长度N 1的差值小于预定的范围，其中，N 1小于等于M，N 1为2的整数次幂。
  26. 一种通信装置，其特征在于，包括：
    用于获取信息比特序列和Polar码的目标码长M的单元；
    用于从满足以下三个预设条件的任意一个条件的第一母码长度N 1的取值集合中选择最小的值作为第一母码长度N 1的值，采用重复的速率匹配方案；若均不存在满足以下任意预设条件的第一母码长度N 1的值，则采用缩短或者打孔的速率匹配方案的单元；
    其中，所述三个预设条件分别为：
    由所述信息比特的个数K和所述目标码长M确定的第一码率R 1小于等于预设的第二码率R 2，R 1＝K/N 1；
    所述目标码长大于预设的最大母码长度N max，所述第一母码长度N 1为N max；和
    所述目标码长M与所述第一母码长度N 1的差值小于预定的范围，其中，N 1小于等于M，N 1为2的整数次幂。
  27. 根据权利要求25或26所述的装置，其特征在于，设N 1＝2 n，n是小于等于log 2M的最大整数。
  28. 根据权利要求25-27任意一项所述的装置，其特征在于，所述第二码率的值为1/4、1/3、1/4、1/5、1/6、1/7、1/8、1/9、1/10、1/11、1/12、2/7、3/8、2/9、3/10、2/11或3/11。
  29. 根据权利要求25-28任意一项所述的装置，其特征在于，N max的值为2048、1024或512。
  30. 根据权利要求25至29任意一项所述的装置，其特征在于，所述目标码长M与所述第一母码长度N 1的差值小于预定的范围表示为以下中的一种：
    M≤N 1*(1+δ)；
    Figure PCTCN2018070056-appb-100006
    M-N 1≤N 1*δ；或
    Figure PCTCN2018070056-appb-100007
    其中，δ为常数或为第一码率R 1的函数。
  31. 根据权利要求30所述的装置，其特征在于，δ取值为1/8，1/4或3/8。
  32. 一种编码装置，其特征在于，包括：
    获取单元，获取信息比特序列和Polar码的目标码长M；
    编码单元，用于当所述目标码长M满足预设条件时，采用第一母码码长N 1的Polar码对所述信息比特序列进行编码，输出第一编码比特序列，N 1小于等于M，N 1为2的整数次幂；或当所述目标码长M不满足所述预设条件时，采用第二母码码长N 2的Polar码对所述信息比特序列进行编码，输出第二编码比特序列，N 2大于等于M，且N 2为2的整数次幂；
    速率匹配单元，用于重复所述第一编码比特序列的至少一部分比特，得到长度为M的第一目标Polar码；或对所述第二编码比特序列进行缩短或打孔，得到长度为M的第二目标Polar码。
  33. 根据权利要求32所述的装置，其特征在于，所述预设的条件为：由所述信息比特个数K和所述目标码长M确定的第一码率R 1小于等于预设的第二码率R 2；其中，所述第一码率R 1＝K/N 1，N 1＝2 n，n是小于等于log 2M的整数。
  34. 根据权利要求33所述的装置，其特征在于，n为小于等于log 2M的最大整数。
  35. 根据权利要求32至34任意一项所述的装置，其特征在于，所述第二码率的值为1/4、1/3、1/4、1/5、1/6、1/7、1/8、1/9、1/10、1/11、1/12、2/7、3/8、2/9、3/10、2/11或3/11。
  36. 根据权利要求32所述的装置，其特征在于，所述预设的条件为：所述目标码长大于预设的最大母码长度N max。
  37. 根据权利要求36所述的装置，其特征在于，所述第一母码长度为N max。
  38. 根据权利要求36或37任一项所述的装置，其特征在于，N max为2048、1024或512。
  39. 根据权利要求32所述的装置，其特征在于，所述预设的条件为：所述目标码长M与所述第一母码长度N 1的差值小于预定的范围，其中，N 1小于等于M，N 1为2的整数次幂。
  40. 根据权利要求39所述的装置，其特征在于，所述目标码长M与所述第一母码长度N 1的差值小于预定的范围表示为以下中的一种：
    M≤N 1*(1+δ)；
    Figure PCTCN2018070056-appb-100008
    M-N 1≤N 1*δ；或
    Figure PCTCN2018070056-appb-100009
    其中，δ为常数或为第一码率R 1的函数。
  41. 根据权利要求40所述的装置，其特征在于，δ取值为1/8，1/4或3/8。
  42. 一种通信装置，其特征在于，包括：
    收发器，用于和其他设备进行通信；
    存储器，用于存储程序；
    处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，所述处理器用于执行12-21任意一项所述的方法。
  43. 一种通信装置，其特征在于，包括：
    存储器，用于存储程序；
    处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，所述处理器用于执行12-21任意一项所述的方法。
  44. 一种计算机可读存储介质，包括指令，当其在计算机上运行时，使得计算机执行如权利要求1-21任意一项所述的方法。
  45. 一种Polar码的解速率匹配的方法，其特征在于，包括：
    接收长度为M的待译码比特序列的对数似然比LLR，M为Polar码编码的目标码长；
    从满足以下三个预设条件的任意一个条件的第一母码长度N 1的取值集合中选择最小的值作为第一母码长度N 1的值，确定发送端采用重复的方法进行速率匹配，确定重复比特的位置，将接收到的M个比特的LLR中重复位置的LLR进行相加合并，得到长度为第一母码码长N 1的第一待译码比特序列的LLR，其中，N 1小于等于M，N 1为2的整数次幂；根据所述第一待译码比特序列的LLR进行Polar码译码；
    若均不存在满足以下任意预设条件的第一母码长度N 1的值，确定发送端采用缩短或打孔的方法进行速率匹配，确定缩短或打孔位置及其LLR，将接收到的M个比特的LLR恢复至第二母码长度N 2，得到长度为第二母码码长N 2的第二待译码比特序列的LLR，其中，N 2大于等于M，N 2为2的整数次幂；根据所述第二待译码比特序列的LLR进行Polar码译码；
    其中，所述三个预设条件分别为：
    由所述信息比特的个数K和所述目标码长M确定的第一码率R 1小于等于预设的第二码率R 2，R 1＝K/N 1；
    所述目标码长大于预设的最大母码长度N max，所述第一母码长度N 1为N max；和
    所述目标码长M与所述第一母码长度N 1的差值小于预定的范围，其中，N 1小于等于M，N 1为2的整数次幂。
  46. 一种Polar码的解速率匹配的方法，其特征在于，包括：
    接收长度为M的待译码比特序列的对数似然比LLR，M为Polar码编码的目标码长；
    当所述目标码长M满足预设条件时，确定发送端采用重复的方法进行速率匹配；确定重复比特的位置，将接收到的M个比特的LLR中重复位置的LLR进行相加合并，得到长度为第一母码码长N 1的第一待译码比特序列的LLR，其中，N 1小于等于M，N 1为2的整数次幂；根据所述第一待译码比特序列的LLR进行Polar码译码；
    当所述目标码长M不满足所述预设条件时，确定发送端采用缩短或打孔的方法进行速率匹配，确定缩短或打孔位置及其LLR，将接收到的M个比特的LLR恢复至第二母码长度N 2，得到长度为第二母码码长N 2的第二待译码比特序列的LLR，其中，N 2大于等于M，N 2为2的整数次幂；根据所述第二待译码比特序列的LLR进行Polar码译码。
  47. 一种译码装置，其特征在于，包括：
    接收单元，用于接收长度为M的待译码比特序列的对数似然比LLR，M为Polar码编码的目标码长；
    解速率匹配单元，用于当所述目标码长M满足预设条件时，确定发送端采用重复 的方法实现速率匹配；确定重复比特的位置，将接收到的M个比特的LLR中重复位置的LLR进行相加合并，得到长度为第一母码码长N 1的第一待译码比特序列的LLR，其中，N 1小于等于M，N 1为2的整数次幂；或用于当所述目标码长M不满足所述预设条件时，确定发送端采用缩短或打孔的方法实现速率匹配，确定缩短或打孔位置及其LLR，将接收到的M个比特的LLR恢复至第二母码长度N 2，得到长度为第二母码码长N 2的第二待译码比特序列的LLR，其中，N 2大于等于M，N 2为2的整数次幂；
    译码单元，用于根据所述第一待译码比特序列或第二待译码比特序列的LLR进行Polar码译码。
  48. 提供一种通信装置，包括：
    存储器，用于存储程序；
    处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，所述处理器用于在Polar码编码的目标码长M满足预设条件时，确定发送端采用重复的方法实现速率匹配，确定重复比特的位置，将接收到的M个比特的LLR中重复位置的LLR进行相加合并，得到长度为第一母码码长N 1的第一待译码比特序列的LLR，其中，N 1小于等于M，N 1为2的整数次幂；根据所述第一待译码比特序列的LLR进行Polar码译码；或
    在所述目标码长M不满足预设条件时，确定发送端采用缩短或打孔的方法实现速率匹配，确定缩短或打孔位置及其LLR，将接收到的M个比特的LLR恢复至第二母码长度N 2，得到长度为第二母码码长N 2的第二待译码比特序列的LLR，其中，N 2大于等于M，N 2为2的整数次幂；根据所述第二待译码比特序列的LLR进行Polar码译码。
  49. 一种通信装置，其特征在于，所述通信装置用于：
    接收长度为M的待译码比特序列的对数似然比LLR，M为Polar码编码的目标码长；
    从满足以下三个预设条件的任意一个条件的第一母码长度N 1的取值集合中选择最小的值作为第一母码长度N 1的值，确定发送端采用重复的方法进行速率匹配，确定重复比特的位置，将接收到的M个比特的LLR中重复位置的LLR进行相加合并，得到长度为第一母码码长N 1的第一待译码比特序列的LLR，其中，N 1小于等于M，N 1为2的整数次幂；根据所述第一待译码比特序列的LLR进行Polar码译码；
    若均不存在满足以下任意预设条件的第一母码长度N 1的值，确定发送端采用缩短或打孔的方法进行速率匹配，确定缩短或打孔位置及其LLR，将接收到的M个比特的LLR恢复至第二母码长度N 2，得到长度为第二母码码长N 2的第二待译码比特序列的LLR，其中，N 2大于等于M，N 2为2的整数次幂；根据所述第二待译码比特序列的LLR进行Polar码译码；
    其中，所述三个预设条件分别为：
    由所述信息比特的个数K和所述目标码长M确定的第一码率R 1小于等于预设的第二码率R 2，R 1＝K/N 1；
    所述目标码长大于预设的最大母码长度N max，所述第一母码长度N 1为N max；和
    所述目标码长M与所述第一母码长度N 1的差值小于预定的范围，其中，N 1小于 等于M，N 1为2的整数次幂。
  50. 一种通信装置，其特征在于，包括：
    接收单元，用于接收长度为M的待译码比特序列的对数似然比LLR，M为Polar码编码的目标码长；
    解速率匹配单元，从满足以下三个预设条件的任意一个条件的第一母码长度N 1的取值集合中选择最小的值作为第一母码长度N 1的值，确定发送端采用重复的方法进行速率匹配，确定重复比特的位置，将接收到的M个比特的LLR中重复位置的LLR进行相加合并，得到长度为第一母码码长N 1的第一待译码比特序列的LLR，其中，N 1小于等于M，N 1为2的整数次幂；或用于若均不存在满足以下任意预设条件的第一母码长度N 1的值，确定发送端采用缩短或打孔的方法进行速率匹配，确定缩短或打孔位置及其LLR，将接收到的M个比特的LLR恢复至第二母码长度N 2，得到长度为第二母码码长N 2的第二待译码比特序列的LLR，其中，N 2大于等于M，N 2为2的整数次幂；
    译码单元，用于根据所述第一待译码比特序列或第二待译码比特序列的LLR进行Polar码译码。
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