WO2018121371A1 - 开关电源及其电压采样电路 - Google Patents

开关电源及其电压采样电路 Download PDF

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Publication number
WO2018121371A1
WO2018121371A1 PCT/CN2017/117396 CN2017117396W WO2018121371A1 WO 2018121371 A1 WO2018121371 A1 WO 2018121371A1 CN 2017117396 W CN2017117396 W CN 2017117396W WO 2018121371 A1 WO2018121371 A1 WO 2018121371A1
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Prior art keywords
voltage
sampling
control
unit
output
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Ceased
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PCT/CN2017/117396
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English (en)
French (fr)
Inventor
蒋幸福
王文情
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BYD Co Ltd
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BYD Co Ltd
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Priority to US16/474,975 priority Critical patent/US20190339309A1/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/22—Conversion of DC power input into DC power output with intermediate conversion into AC
    • H02M3/24—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters
    • H02M3/28—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC
    • H02M3/325—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33507—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
    • G01R19/2503—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques for measuring voltage only, e.g. digital volt meters (DVM's)
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/18—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using conversion of DC into AC, e.g. with choppers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
    • G01R19/2506—Arrangements for conditioning or analysing measured signals, e.g. for indicating peak values ; Details concerning sampling, digitizing or waveform capturing
    • G01R19/2509—Details concerning sampling, digitizing or waveform capturing
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/22—Conversion of DC power input into DC power output with intermediate conversion into AC
    • H02M3/24—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters
    • H02M3/28—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC
    • H02M3/325—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33507—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
    • H02M3/33523—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters with galvanic isolation between input and output of both the power stage and the feedback loop
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0009—Devices or circuits for detecting current in a converter

Definitions

  • the present invention relates to the field of switching power supplies, and in particular, to a voltage sampling circuit and a switching power supply having the same.
  • the voltage sampling circuit of the switching power supply generally samples the voltage change of the feedback coil through the voltage feedback pin, and controls the operating frequency of the power switch tube and the duty ratio of the conduction according to the sampled voltage value to adjust the secondary coil. The output voltage.
  • the related art has the disadvantage that the load size affects the voltage of the voltage feedback pin, causing the sampled voltage value to change, and cannot accurately represent the magnitude of the output voltage. Therefore, the output voltage of the secondary coil is difficult to maintain stable and lower. The constant voltage accuracy of the switching power supply.
  • the present invention aims to solve at least one of the technical problems in the related art to some extent. Accordingly, it is an object of the present invention to provide a voltage sampling circuit that can improve the constant voltage accuracy of a switching power supply.
  • Another object of the present invention is to provide a switching power supply.
  • a voltage sampling circuit includes: a sample and hold module, the sample and hold module has a sampling input terminal, a sampling output terminal, and a sampling control terminal, and the sampling input terminal and the voltage sampling point.
  • the sample and hold module is configured to sample the voltage of the voltage sampling point in a sampling phase, so that the sampling voltage of the sampling output follows the voltage of the voltage sampling point, and keep the said after the sampling phase ends a sampling voltage of the sampling output;
  • the control module is respectively connected to the voltage sampling point and the control end and the sampling output end of the sample and hold module, and the control module is used for the voltage at the sampling point according to the voltage
  • the sampling and holding module is controlled to enter the sampling phase, and the voltage sampling is determined according to the voltage of the voltage sampling point and the sampling voltage of the sampling output end.
  • the sampling phase of the sample-and-hold module is controlled to end. The sampled voltage at the sampling output is maintained at a voltage corresponding to the voltage inflection point.
  • the control module controls the sampling and holding module to enter the sampling phase when the voltage of the voltage sampling point is in the sampleable voltage segment, so that the sampling voltage of the sampling output end follows the voltage of the voltage sampling point, and the voltage is
  • the sampling phase of the sampling and holding module is controlled to end, so that the sampling voltage of the sampling output end is maintained at the voltage corresponding to the voltage inflection point, so that the voltage of the inflection point of the sampling voltage can accurately reflect the magnitude of the output voltage and avoid the switch.
  • the load variation of the power supply affects the sampling voltage, improves the stability and accuracy of the control system, improves the constant voltage accuracy of the output voltage of the switching power supply, and improves the user experience.
  • a switching power supply includes the above voltage sampling circuit.
  • the voltage of the voltage inflection point is sampled by the voltage sampling circuit, and the output voltage can be accurately reflected, and the load variation of the switching power supply is prevented from affecting the sampling voltage, thereby improving the stability and accuracy of the control system.
  • Sexuality improves the constant voltage accuracy of the switching power supply output voltage and improves the user experience.
  • 1 is a waveform diagram of a voltage sampling circuit in the related art
  • FIG. 2 is a block schematic diagram of a voltage sampling circuit in accordance with an embodiment of the present invention.
  • FIG. 3 is a waveform diagram of a voltage sampling circuit in accordance with an embodiment of the present invention.
  • FIG. 4 is a circuit schematic diagram of a voltage sampling circuit in accordance with an embodiment of the present invention.
  • FIG. 5 is a block schematic diagram of a switching power supply in accordance with an embodiment of the present invention.
  • FIG. 6 is a circuit schematic diagram of a switching power supply in accordance with an embodiment of the present invention.
  • Fig. 7 is a block diagram showing the power control chip of the switching power supply shown in Fig. 6.
  • a trigger 201 a trigger 201, a first control unit 202 and a second control unit 203;
  • the voltage sampling circuit performs filtering processing by RC to filter out high frequency interference in the voltage V1' waveform of the voltage sampling point.
  • a preset threshold for example, 0.1V
  • the output signal of the comparator of the voltage sampling circuit jumps from a low level to a high level, due to the initial presence of the voltage of the voltage sampling point V1' waveform Resonance fluctuation, the output signal of the comparator can be delayed by a delay time by a preset delay time T' to avoid sampling the voltage of the resonance fluctuation region, and after the preset delay time T' is delayed, the voltage sampling point can be sampled.
  • Voltage V1' The voltage in the middle of the voltage platform, which is closer to the average of the voltage V1' of the voltage sampling point. Further, the leading edge blanking LEB module generates a PWM signal SH' with a small pulse according to the output signal after the delay, and the PWM signal SH' controls the transmission gate TR. When the PWM signal SH' is at a high level, the transmission gate TR is turned on. The voltage sampling circuit enters the sampling phase to obtain the current voltage value; when the PWM signal SH' is low, the transmission gate TR is closed, the sampling phase of the voltage sampling circuit ends, and enters the holding phase, and the timing logic of the entire sampling process is as shown in FIG. Shown.
  • the voltage platform of the voltage V1' waveform of the voltage sampling point is not completely equal in one cycle time, and there is a downward trend. Therefore, when the preset delay time of the delay circuit is different, The voltage V1' sampled by the voltage sampling circuit may be different.
  • the voltage platform time of the voltage sampling point actually corresponds to the length of the secondary winding degaussing time, and the load of the switching power supply is different, the voltage platform time of the voltage sampling point changes, when the load of the switching power supply is heavy.
  • the voltage platform of the voltage sampling point takes a long time; when the load of the switching power supply is light, the voltage platform time of the voltage sampling point is short.
  • the voltage of the voltage sampling point may not accurately represent the magnitude of the output voltage, and the sampling voltage V2' output by the voltage sampling circuit is not accurate.
  • the error amplifier receives the sampling voltage V2' deviation, which causes the control of the power control chip to fail.
  • the voltage outputted by the system is deviated, that is, the voltage output by the switching power supply is not a preset voltage value, resulting in a decrease in the constant voltage accuracy of the switching power supply.
  • an embodiment of the present invention provides a switching power supply and a voltage sampling circuit thereof.
  • the voltage sampling circuit includes a sample and hold module 10 and a control module 20.
  • the voltage sampling circuit can be disposed on the power control chip of the switching power supply.
  • the sample and hold module 10 has a sampling input terminal IN, a sampling output terminal OUT and a sampling control terminal P.
  • the sampling input terminal IN is connected to the voltage sampling point M.
  • the sampling and holding module 10 is configured to sample the voltage V1 of the voltage sampling point M in the sampling phase. So that the sampling voltage V2 of the sampling output follows the voltage V1 of the voltage sampling point M, and maintains the sampling voltage V2 of the sampling output after the sampling phase ends; the control module 20 and the voltage sampling point M and the sampling control end of the sample and hold module 10, respectively P is connected to the sampling output terminal OUT.
  • the control module 20 is configured to control the sample and hold module 10 to enter the sampling phase and determine the voltage according to the voltage V1 of the voltage sampling point M when the voltage V1 of the voltage sampling point M is in the sampleable voltage segment.
  • the sampling phase of the sample-and-hold module 10 is controlled to end so that the sampling voltage V2 of the sampling output terminal is maintained at the voltage corresponding to the voltage inflection point. .
  • the control module 20 receives the voltage V1 of the voltage sampling point M and determines whether the voltage V1 of the voltage sampling point M is in a sampleable voltage segment.
  • the control module The output control signal SH is, for example, high level to the sampling control terminal P of the sample and hold module 10, and the sample and hold module 10 enters the sampling phase when receiving the turn-on control signal SH.
  • the sample and hold module 10 samples the voltage sampling point M.
  • the voltage V1 is such that the sampling voltage V2 at the sampling output follows the voltage V1 of the voltage sampling point M.
  • the control module 20 When the voltage V1 of the voltage sampling point M changes to the voltage inflection point, the control module 20 outputs a shutdown control signal SH, for example, a low level to the sampling control terminal P of the sample and hold module 10, and the sample and hold module 10 receives the shutdown control signal SH. At the end of the sampling phase and enter the holding phase, at this time, the sampling voltage V2 of the sampling output terminal is maintained at the voltage corresponding to the voltage inflection point.
  • a shutdown control signal SH for example, a low level to the sampling control terminal P of the sample and hold module 10
  • the voltage sampling point M may be the voltage feedback terminal Q of the feedback coil in the switching power supply, that is, the voltage feedback pin VFB (voltage feed back) of the power control chip shown in FIG.
  • the length of the voltage platform time of the voltage sampling point M actually corresponds to the length of the degaussing time of the secondary winding.
  • the decoupling of the secondary coil ends, the current flowing through the secondary coil is 0.
  • no pressure is generated on the secondary coil.
  • the output line of the secondary coil does not produce a voltage drop, and the feedback coil can accurately map the output voltage of the secondary coil. If the voltage sampling circuit samples the voltage of the feedback coil at the voltage feedback pin VFB, the voltage sampling point can be passed.
  • the voltage of M accurately maps the magnitude of the output voltage. As shown in Fig. 3, at time t3, the degaussing of the secondary coil ends, and the voltage of the voltage feedback pin VFB starts to drop, that is, the voltage inversion of the voltage V1 of the voltage sampling point M appears. Thus, regardless of the voltage platform time of the voltage sampling point M, regardless of light load or heavy load, the final sampled voltage is the voltage corresponding to the voltage inflection point, and the magnitude of the output voltage of the secondary coil can be accurately mapped.
  • the sample and hold module 10 can sample the voltage corresponding to the voltage inflection point, and output the voltage corresponding to the voltage inflection point as the final sampling voltage to the error amplifier, and adjust the control signal output by the power control chip according to the sampling voltage to adjust the power switch tube.
  • the operating frequency and the duty ratio of the conduction keep the output voltage of the secondary coil stable, thereby preventing the load variation of the switching power supply from affecting the sampling voltage, improving the stability and accuracy of the control system, and improving the switching power supply.
  • the constant voltage accuracy of the output voltage improves the user experience.
  • the control module 20 includes a trigger 201, a first control unit 202, and a second control unit 203.
  • the flip-flop 201 has a set terminal S, a reset terminal R and an output terminal O.
  • the output terminal O of the flip-flop 201 is connected to the sampling control terminal P of the sample-and-hold module 10; the input terminal IN1 of the first control unit 202 and the voltage sampling The point M is connected, the output terminal OUT1 of the first control unit 202 is connected to the set terminal S of the flip-flop 201, and the first control unit 202 is configured to control the flip-flop 201 when determining that the voltage V1 of the voltage sampling point M is in the sampleable voltage segment.
  • the input terminal IN2 of the second control unit 203 is respectively connected to the voltage sampling point M and the sampling output terminal, and the output terminal OUT2 of the second control unit 203 and the reset terminal R of the flip-flop 201 Connected, the second control unit 203 is configured to control the reset of the flip-flop 201 when the voltage of the voltage sampling point M is determined to be at a voltage inflection point to control the sampling phase of the sample-and-hold module 10 to end.
  • the output terminal OUT1 of the first control unit 202 outputs a sampling signal, for example, a high level to the set terminal S of the flip-flop 201 to control the flip-flop 201.
  • the flip-flop 201 When set, the flip-flop 201 outputs the turn-on control signal SH to the sampling control terminal P of the sample-and-hold module 10 to control the sample-and-hold module 10 to enter the sampling phase; when the voltage of the voltage sampling point M is at the voltage inflection point, the second control unit 203
  • the output terminal OUT2 outputs a sampling end signal, for example, a high level to the reset terminal R of the flip-flop 201 to control the reset of the flip-flop 201, and the flip-flop 201 outputs a turn-off control signal SH to the sampling control terminal P of the sample-and-hold module 10 to control sampling.
  • the hold phase At the end of the sampling phase of the hold module 10, the hold phase is entered.
  • the sampleable voltage segment may refer to the voltage platform middle segment of the voltage V1 of the voltage sampling point M.
  • the voltage V1 of the voltage sampling point M is compared with the preset voltage V0, and the voltage is sampled. After the voltage V1 of the point M is greater than the preset voltage V0, the preset delay time is delayed to determine that the voltage V1 of the voltage sampling point M is in the middle of the voltageable platform, which is the sampleable voltage segment.
  • the first control unit 202 includes: a first comparator CMP1 and a delay unit 210, wherein the first input of the first comparator CMP1 is connected to the voltage sampling point M.
  • the second input end of the first comparator CMP1 is connected to the preset voltage supply terminal Vref, and the first comparator CMP1 is configured to output the sampling signal when the voltage V1 of the voltage sampling point M is greater than the preset voltage V0 (for example, provided by Vref).
  • One end of the delay unit 210 is connected to the output end of the first comparator CMP1, and the other end of the delay unit 210 is connected to the set end S of the flip-flop 201.
  • the delay unit 210 is configured to delay the sampling signal by a predetermined delay.
  • the time T is output to the flip-flop 201 to control the flip-flop 201 to be set.
  • the power terminal of the first comparator CMP1 is connected to the preset power source VCC, and the ground terminal of the first comparator CMP1 is grounded.
  • the preset voltage V0 provided by the preset voltage supply terminal Vref may be 0.1V, and when the voltage V1 of the voltage sampling point M is less than or equal to 0.1V, the first comparator CMP1 outputs a first sampling signal, for example, a low level; When the voltage V1 of the voltage sampling point M is greater than 0.1 V, the output of the first comparator CMP1 is inverted to output a second sampling signal such as a high level.
  • the delay circuit 210 delays the sampling signal outputted by the first comparator CMP1 by a preset delay time T, and outputs it to the set terminal S of the flip-flop 201, thereby delaying the preset after the first comparator CMP1 outputs a high level.
  • the delay time T control flip-flop 201 is set and the sample-and-hold module 10 enters the sampling phase.
  • the delay circuit 210 delays the sampling signal by the preset delay time T to avoid the sampling and holding module. 10 samples to the voltage platform with high initial interference.
  • the second control unit 203 includes: a second comparator CMP2, the first input of the second comparator CMP2 is connected to the sampling output, and the second comparator CMP2
  • the two input terminals are connected to the voltage sampling point M, the output end of the second comparator CMP2 and the reset terminal R of the flip-flop 201, and the second comparator CMP2 is used for the sampling voltage V2 outputted at the sampling output terminal and the voltage of the voltage sampling point M.
  • the difference between V1 is greater than the preset threshold
  • the sampling end signal is output to the flip-flop 201 to control the flip-flop 201 to reset.
  • the power terminal of the second comparator CMP2 is connected to the preset power source VCC, and the ground terminal of the second comparator CMP2 is grounded.
  • the second comparator CMP2 may be a comparator having a slight mismatch at the input, that is, when the difference between the first input and the second input of the second comparator CMP2 is small. The level output by the second comparator CMP2 is not inverted.
  • the sampling voltage V2 outputted by the sampling output terminal lags behind the voltage V1 of the voltage sampling point M, as shown in FIG. 3, in the middle of the voltage platform of the voltage sampling point M, the voltage sampling point M The voltage V1 changes relatively slowly.
  • the difference between the sampling voltage V2 outputted by the sampling output and the voltage V1 of the voltage sampling point M is less than a preset threshold, that is, the first input and the second of the second comparator CMP2.
  • the voltage difference of the input terminal is less than the preset threshold, and the second comparator CMP2 outputs a first sampling end signal, for example, a low level to the reset terminal R of the flip-flop 201, and the flip-flop 201 remains set to continue to output a high level. As shown in FIG.
  • the voltage V1 of the voltage sampling point M suddenly decreases, and the sampling voltage V2 outputted by the sampling output terminal lags behind the voltage V1 of the voltage sampling point M, so
  • the difference between the sampling voltage V2 outputted by the sampling output terminal and the voltage V1 of the voltage sampling point M is greater than a preset threshold, that is, the voltage difference between the first input end and the second input end of the second comparator CMP2 is greater than a preset threshold.
  • the second comparator CMP2 outputs a second sampling end signal, for example, a high level to the reset terminal R of the flip-flop 201, and the flip-flop 201 resets to output a low level.
  • the sample and hold module 10 includes a sample and hold unit 101, a switch unit 102, and a trigger unit 103.
  • the sample and hold unit 101 is connected to the voltage sampling point M and the control module 20, respectively, and the sample and hold unit 101 includes a transmission gate TR, wherein the control module 20 controls the transmission gate TR to be controlled to control the sample and hold module 10 to enter the sampling phase, and The sampling unit is controlled to be closed by controlling the transmission gate TR to be turned off; the switching unit 102 is connected in parallel with the sample and hold unit 101; the trigger unit 103 is connected to the control module 20 and the switching unit 102, respectively, and the trigger unit 103 is used to enter the sampling in the sample and hold module 10.
  • a trigger signal is generated at the stage to trigger the switch unit 102 to be turned on for a preset time, so that the output end of the sample and hold module 10 first follows the voltage of the voltage sampling point M through the switch unit 102, and then follows by the sample and hold unit 101 after the preset time.
  • the voltage at the voltage sampling point M is generated at the stage to trigger the switch unit 102 to be turned on for a preset time, so that the output end of the sample and hold module 10 first follows the voltage of the voltage sampling point M through the switch unit 102, and then follows by the sample and hold unit 101 after the preset time. The voltage at the voltage sampling point M.
  • the sample and hold unit 101 further includes: a first resistor R1, a first capacitor C1, a second resistor R2, and a second capacitor C2, wherein the first resistor R1 is first The terminal is connected to the voltage sampling point M.
  • the second end of the first resistor R1 is connected to one end of the transmission gate TR, and the control end of the transmission gate TR is connected to the control module 20; one end of the first capacitor C1 is connected to the other end of the transmission gate TR.
  • the other end of the first capacitor C1 is grounded, and the first capacitor C1 and the transfer gate TR have a first node; the first end of the second resistor R2 is connected to the first node, and the second end of the second resistor R2 is connected to the control module. 20 is connected; one end of the second capacitor C2 is connected to the second end of the second resistor R2, the other end of the second capacitor C2 is grounded, and the second node C2 has a second node between the second resistor R2.
  • the first resistor R1 and the first capacitor C1 may constitute a first-stage RC filter circuit
  • the second resistor R2 and the second capacitor C2 may constitute a second-stage RC filter circuit, wherein the first end of the first resistor R1
  • the control terminal of the transmission gate TR can serve as the sampling control terminal P of the sample and hold module 10
  • the first node can serve as the first sampling output terminal OUT' of the sample and hold module 10
  • second The node can be used as the second sampling output terminal OUT'' of the sample and hold module 10, wherein the sampling voltage can be output to the error amplifier of the switching power supply through the first sampling output terminal OUT', and can be output through the second sampling output terminal OUT''
  • the sampled voltage is output to the control module 20.
  • sampling voltage can also be output to the error amplifier of the switching power supply through the second sampling output terminal OUT''.
  • the switching unit 102 includes: a first MOS transistor MOS1 and a second MOS transistor MOS2, wherein the source S of the first MOS transistor MOS1 and the first resistor R1 are respectively One end is connected to the voltage sampling point M, the drain D of the first MOS transistor MOS1 is connected to the first node, the gate G of the first MOS transistor MOS1 is connected to the trigger unit 103; the source S of the second MOS transistor MOS2 is A node is connected, the drain D of the first MOS transistor MOS1 is connected to the second node, and the gate G of the second MOS transistor MOS2 is connected to the gate G of the first MOS transistor MOS1 and the trigger unit 103, respectively.
  • the trigger unit 103 includes a leading edge blanking circuit 110.
  • the voltage V1 of the voltage sampling point M is greater than the preset voltage V0, for example, 0.1 V, and the voltage platform of the voltage sampling point M during the period from t1 to t3.
  • the voltage waveform of the initial stage has oscillation fluctuations, and then the voltage platform of the voltage sampling point M has a slow downward trend.
  • the voltage of the voltage sampling point M has a rapid decreasing trend, that is, at time t3, the voltage sampling point M The voltage is at the voltage inflection point.
  • sampling can be performed at time t2, that is, at time t2, the delay unit 210 outputs the sampling signal to the set terminal S of the flip-flop 201, and the voltage sampling circuit starts to enter the sampling phase to avoid sampling.
  • the voltage V1 of the voltage sampling point M is greater than 0.1V
  • the first comparator CMP1 outputs a sampling signal such as a high level
  • the delay unit 210 outputs the sampling signal to the trigger at time t2 shown in FIG.
  • the set terminal S of the device 201, the output of the flip-flop 201 is set high, that is, the output terminal O of the flip-flop 201 outputs an open control signal SH such as a high level.
  • the transmission gate TR is turned on when receiving the turn-on control signal SH to control the sample-and-hold module 10 to enter the sampling phase.
  • the trigger unit 103 receives the turn-on control signal SH to generate a trigger signal such as a PWM signal SHFA with a small pulse, which is triggered.
  • the pulse width of the signal SHFA is smaller than the pulse width of the turn-on control signal SH.
  • the PWM signal SHFA is high, the first MOS transistor MOS1 and the second MOS transistor MOS2 are turned on, and the switching unit 102 is turned on for a preset time to keep the sample hold.
  • the transmission gate TR, the first resistor R1, the first capacitor C1, the second resistor R2, and the second capacitor C2 in the unit 101 are short-circuited for a preset time.
  • the sampling voltage V2 outputted by the sampling output terminal OUT does not pass through the RC filter circuit.
  • the sampling voltage V2 quickly follows the voltage V1 of the voltage sampling point M through the switching unit 102.
  • the voltage platform time of the voltage sampling point M is short, the voltage platform of the voltage sampling point M can be avoided and the sampling output of the sampling output terminal OUT can be avoided.
  • the voltage V2 has not yet caught up with the voltage V1 of the voltage sampling point M, thereby ensuring that the voltage sampling circuit samples the voltage at the voltage inflection point.
  • the transmission gate TR is turned on under the control of the turn-on control signal SH, and the transfer gate TR and the first-stage RC filter circuit process the voltage V1 of the voltage sampling point M, and then output the sampling voltage V2 to the error amplifier of the switching power supply, and
  • the transmission gate TR, the first-stage RC filter circuit and the second-stage RC filter circuit process the voltage V1 of the voltage sampling point M and output the sampling voltage V2 to the first input terminal of the second comparator CMP2. Since the time constant of the RC filter circuit is large, the variation of the sampling voltage V2 outputted by the sampling output terminal OUT lags behind the voltage V1 of the voltage sampling point M.
  • the voltage V1 of the voltage sampling point M changes relatively slowly, and the difference between the sampling voltage V2 and the voltage V1 of the voltage sampling point M is less than a preset threshold, and the second comparator CMP2 outputs the end of the first sampling.
  • the signal is, for example, low level to the reset terminal R of the flip-flop 201, the flip-flop 201 remains set to continue to output a high level, the control transfer gate TR remains turned on to continue sampling, and the sampling voltage V2 follows the voltage V1 of the voltage sampling point M. . If the voltage V1 of the voltage sampling point M changes greatly, a difference is generated between the sampling voltage V2 and the voltage V1 of the voltage sampling point M.
  • the voltage V1 of the voltage sampling point M has a tendency to rapidly decrease, that is, voltage sampling.
  • the voltage V1 of the point M is at a voltage inflection point.
  • the difference between the sampling voltage V2 outputted by the sampling output terminal and the voltage V1 of the voltage sampling point M is greater than a preset threshold, and the second comparator CMP2 outputs a second sampling end signal, for example.
  • High level to the reset terminal R of the flip-flop 201 the flip-flop 201 resets to output a low level, controls the transfer gate TR to turn off to control the end of the sampling phase, enters the hold phase, and the sampling voltage V2 maintains the voltage corresponding to the voltage inflection point.
  • the control module controls the sample-and-hold module to enter the sampling phase when the voltage of the voltage sampling point is in the sampleable voltage segment, so that the sampling voltage of the sampling output end follows the voltage of the voltage sampling point.
  • the sampling phase of the sampling and holding module is controlled to end, so that the sampling voltage of the sampling output end is maintained at the voltage corresponding to the voltage inflection point, so that the voltage of the inflection point of the sampling voltage can accurately reflect the magnitude of the output voltage.
  • FIG. 5 is a block schematic diagram of a switching power supply in accordance with an embodiment of the present invention.
  • the switching power supply 200 includes a voltage sampling circuit 100.
  • the switching power supply 200 includes a rectifier module 30, a power control chip 40, a power switching transistor Q1, and a transformer assembly 50.
  • the voltage sampling circuit 100 is integrated in the power control chip 40.
  • the transformer assembly 50 includes a primary coil 501, a secondary coil 502, and a feedback coil 503. One end of the secondary coil 502 is connected to the first output terminal V+ of the switching power supply 200. The other end of the stage coil 502 is connected to the second output terminal V- of the switching power supply 200.
  • One end of the feedback coil 503 is connected to the power control chip 40, and the other end of the feedback coil 503 is connected to the rectifier module 30.
  • the power control chip 40 is configured to output a control signal to control the turning on or off of the power switch tube Q1 (eg, Q1 may be a MOS tube) to implement primary and secondary energy transfer of the transformer assembly 50, and to control The operating frequency of the power switch tube Q1 and the duty ratio of the conduction control the output voltage and output current of the secondary coil 502.
  • the power control chip 40 is further configured to sample the output voltage of the secondary coil 502 through the feedback coil 503, thereby adjusting the output frequency and duty ratio of the control signal to stabilize the output voltage of the secondary coil 502.
  • the power control chip 40 includes the following ports: a power supply pin VDD, a ground pin VSS, a current input pin CS, an output pin OUT, and a voltage feedback pin VFB.
  • the power supply pin VDD is used as the power supply terminal of the power control chip 40 for supplying power to the control chip;
  • the current input pin CS is used for detecting the current flowing through the primary coil of the transformer assembly 50; and
  • the output pin OUT is for outputting the control signal for control.
  • the power switch Q1 is turned on or off; the sampling pin VFB is used to sample the feedback voltage of the feedback coil, that is, the voltage feedback pin VFB is the voltage sampling point of the voltage sampling circuit in the above embodiment.
  • the power control chip 40 may further include: a reference bias module 401, a startup module 402, a time sampling circuit 403, an error amplifier 404, a pulse modulation module 405, and a logic processing module 406.
  • the input end of the voltage sampling circuit 100 is connected to the voltage feedback pin VFB, and the output end of the voltage sampling circuit 100 (such as OUT' in the embodiment of FIG. 4) is connected to the first input end of the error amplifier 404; the error amplifier 404 The second input terminal is connected to the reference voltage supply terminal; the input terminal of the time sampling circuit 403 is connected to the voltage feedback pin VFB, the output terminal of the time sampling circuit 403 is connected to the output terminal of the error amplifier 404, and the output terminal of the time sampling circuit 403 is The output of the error amplifier 404 has a third node; the first input of the pulse modulation module 405 is connected to the third node, and the second input of the pulse modulation module 405 is connected to the output of the time sampling circuit 403; the logic processing module The first input end of the 406 is connected to the output end of the pulse modulation module 405; the input end of the drive module 407 is connected to the output end of the logic processing module 406, and the output end of the drive module 407 is connected to the output pin
  • the reference bias module 401 is configured to provide a voltage reference and a current bias required inside the power control chip 40; the startup module 402 is configured to control startup and shutdown of the source control chip 40; and the voltage sampling circuit 100 is configured to sample The winding voltage V1 is fed out and the sampling voltage V2 is output; the time sampling circuit 403 is used to sample the voltage platform time of the voltage sampling point to perform constant current control on the switching power supply; the error amplifier 404 is used to compare the sampling voltage V2 with the reference voltage, and Error amplification is performed; the pulse modulation module 405 is configured to perform pulse width modulation and pulse frequency modulation to convert the analog signal output output by the error amplifier 404 into a PWM signal, and output the PWM signal to the logic processing module 406, and the logic processing module 406 The PWM signal is logically processed to generate a corresponding control signal, the driving module 407 is configured to generate a driving control signal to drive the power switching transistor Q1, and the overcurrent protection module 408 is configured to detect a peak current of the primary
  • the switching power supply can sample the output voltage of the secondary coil through the feedback coil, wherein the voltage sampling circuit generates a corresponding sampling voltage V2 according to the voltage V1 of the voltage sampling point M, and outputs the sampling voltage V2 to the error amplifier, and the error amplifier 404
  • the sampling voltage V2 is processed, and the entire system loop is adjusted according to the sampling voltage V2, and the control signal outputted by the power control chip 40 is adjusted according to the sampling voltage V2 to adjust the operating frequency of the power switch tube Q1 and the duty ratio of the conduction, so that The output voltage of the secondary coil remains stable.
  • the voltage of the voltage inflection point is sampled by the voltage sampling circuit, and the output voltage can be accurately reflected, and the load variation of the switching power supply is prevented from affecting the sampling voltage, thereby improving the stability of the control system.
  • Sexuality and accuracy improve the constant voltage accuracy of the switching power supply output voltage and improve the user experience.
  • first and second are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated.
  • features defining “first” or “second” may include at least one of the features, either explicitly or implicitly.
  • a plurality means at least two, for example two, three, etc., unless specifically defined otherwise.
  • the terms “installation”, “connected”, “connected”, “fixed” and the like shall be understood broadly, and may be either a fixed connection or a detachable connection, unless explicitly stated and defined otherwise. , or integrated; can be mechanical or electrical connection; can be directly connected, or indirectly connected through an intermediate medium, can be the internal communication of two elements or the interaction of two elements, unless otherwise specified Limited.
  • the specific meanings of the above terms in the present invention can be understood on a case-by-case basis.
  • the first feature "on” or “under” the second feature may be a direct contact of the first and second features, or the first and second features may be indirectly through an intermediate medium, unless otherwise explicitly stated and defined. contact.
  • the first feature "above”, “above” and “above” the second feature may be that the first feature is directly above or above the second feature, or merely that the first feature level is higher than the second feature.
  • the first feature “below”, “below” and “below” the second feature may be that the first feature is directly below or obliquely below the second feature, or merely that the first feature level is less than the second feature.

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Abstract

一种开关电源及其电压采样电路，电压采样电路包括：采样保持模块（10），具有采样输入端（IN）、采样输出端（OUT）和采样控制端（P），用于在采样阶段采样电压采样点（M）的电压（V1），以使采样输出端（OUT）的采样电压（V2）跟随电压采样点（M）的电压（V1），并在采样阶段结束后保持采样输出端（OUT）的采样电压（V2）；控制模块（20），用于在根据电压采样点（M）的电压（V1）判断电压采样点（M）的电压（V1）处于可采样电压段时，控制采样保持模块（10）进入采样阶段，以及在根据电压采样点（M）的电压（V1）和采样输出端（OUT）的采样电压（V2）判断电压采样点（M）的电压（V1）处于电压拐点时，控制采样保持模块（10）的采样阶段结束以使采样输出端（OUT）的采样电压（V2）保持在电压拐点对应的电压，从而通过采样电压拐点的电压，能够准确反映输出电压的大小，提高了开关电源的恒压精度。

Description

开关电源及其电压采样电路 技术领域
本发明涉及开关电源技术领域，特别涉及一种电压采样电路和一种具有该电路的开关电源。
背景技术
开关电源由于体积小、效率高且电流大的等优点，被广泛应用于手机充电器和适配器等电源方案中。相关技术中开关电源的电压采样电路通常通过电压反馈引脚采样反馈线圈的电压变化，并根据采样到的电压值控制功率开关管的工作频率和导通的占空比，以调整次级线圈的输出电压。
但是，相关技术存在的缺点是，负载大小会影响电压反馈引脚的电压，导致采样到的电压值发生变化，不能准确表示输出电压的大小，因此，次级线圈的输出电压难以保持稳定，降低了开关电源的恒压精度。
因此，相关技术需要进行改进。
发明内容
本发明旨在至少在一定程度上解决相关技术中的技术问题之一。为此，本发明的一个目的在于提出一种电压采样电路，该电路能够提高开关电源的恒压精度。
本发明的另一个目的在于提出一种开关电源。
为达到上述目的，本发明一方面实施例提出的电压采样电路，包括：采样保持模块，所述采样保持模块具有采样输入端、采样输出端和采样控制端，所述采样输入端与电压采样点相连,所述采样保持模块用于在采样阶段采样所述电压采样点的电压，以使所述采样输出端的采样电压跟随所述电压采样点的电压，并在所述采样阶段结束后保持所述采样输出端的采样电压；控制模块，所述控制模块分别与所述电压采样点以及所述采样保持模块的控制端和采样输出端相连，所述控制模块用于在根据所述电压采样点的电压判断所述电压采样点的电压处于可采样电压段时，控制所述采样保持模块进入所述采样阶段，以及在根据所述电压采样点的电压和所述采样输出端的采样电压判断所述电压采样点的电压处于电压拐点时，控制所述采样保持模块的采样阶段结束以使所述采样输出端的采样电压保持在所述电压拐点对应的电压。
根据本发明实施例提出的电压采样电路，控制模块在电压采样点的电压处于可采样电压段时控制采样保持模块进入采样阶段，以使采样输出端的采样电压跟随电压采样点的电压，并在电压采样点的电压处于电压拐点时控制采样保持模块的采样阶段结束，以使采样输出端的采样电压保持在电压拐点对应的电压，从而通过采样电压拐点的电压，能够准确反映输出电压的大小，避免开关电源的负载变化对采样电压产生影响，改善了控制系统的稳定性和准确性，提高了开关电源输出电压的恒压精度，提升了用户体验。
为达到上述目的，本发明另一方面实施例提出的一种开关电源，包括上述的电压采样电路。
根据本发明实施例提出的开关电源，通过上述电压采样电路采样电压拐点的电压，能够准确反映输出电压的大小，避免开关电源的负载变化对采样电压产生影响，改善了控制系统的稳定性和准确性，提高了开关电源输出电压的恒压精度，提升了用户体验。
附图说明
图1是相关技术中的电压采样电路的波形示意图；
图2是根据本发明实施例的电压采样电路的方框示意图；
图3是根据本发明一个具体实施例的电压采样电路的波形示意图；
图4是根据本发明一个具体实施例的电压采样电路的电路原理图；
图5是根据本发明实施例的开关电源的方框示意图；
图6是根据本发明一个具体实施例的开关电源的电路原理图；以及
图7是图6所示的开关电源的电源控制芯片的方框示意图。
附图标记：
采样保持模块10和控制模块20；
触发器201、第一控制单元202和第二控制单元203；
第一比较器CMP1、第二比较器CMP2和延时单元210；
采样保持单元101、开关单元102和触发单元103；
第一电阻R1、第一电容C1、第二电阻R2和第二电容C2；
第一MOS管MOS1和第二MOS管MOS2；前沿消隐电路110。
具体实施方式
下面详细描述本发明的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，旨在用于解释本发明，而不能理解为对本发明的限制。
为便于理解，先简单介绍相关技术中的电压采样电路的工作原理。
在相关技术中，电压采样电路通过RC进行滤波处理，以滤除电压采样点的电压V1＇波形中的高频干扰。当电压采样点的电压V1＇上升超过预设阈值例如0.1V时，电压采样电路的比较器的输出信号从低电平跳变为高电平，由于电压采样点的电压V1＇波形的初期存在谐振波动，可通过延时电路将比较器的输出信号延时预设延时时间T＇以避免采样谐振波动区域的电压，延时预设延时时间T＇后，可采样到电压采样点的电压V1＇电压平台中段的电压，该电压更接近电压采样点的电压V1＇的平均值。进一步地，前沿消隐LEB模块根据延时后的输出信号生成脉冲很小的PWM信号SH＇，PWM信号SH＇控制传输门TR，当PWM信号SH＇为高电平时，传输门TR导通，电压采样电路进入采样阶段，以获取当前的电压值；当PWM信号SH＇为低电平时，传输门TR关 闭，电压采样电路采样阶段结束，并进入保持阶段，整个采样过程的时序逻辑如图1所示。
如图1所示，在一个周期时间内，电压采样点的电压V1＇波形的电压平台并不是完全相等的，而存在下降趋势的，因此，当延时电路的预设延时时间不同时，电压采样电路采样到的电压V1＇可能不同。另外，由于电压采样点的电压平台时间的长短实际对应的是次级绕组消磁时间的长短，开关电源的负载不同，则电压采样点的电压平台时间长短发生变化，当开关电源的负载较重时，电压采样点的电压平台时间较长；当开关电源的负载较轻时，电压采样点的电压平台时间较短。因此，当开关电源的负载不同时，延时电路延时预设延时时间后，电压采样点的电压可能并不能准确表示输出电压的大小，电压采样电路输出的采样电压V2＇不准确，则误差放大器接收到采样电压V2＇存在偏差，导致电源控制芯片的控制失效，系统输出的电压出现偏差即开关电源输出的电压并非预设电压值，导致开关电源的恒压精度降低。
基于此，本发明实施例提出了一种开关电源及其电压采样电路。
下面参考附图来描述本发明实施例提出的开关电源及其电压采样电路。
图2是根据本发明实施例的电压采样电路的方框示意图。如图2所示，该电压采样电路包括：采样保持模块10和控制模块20。其中，电压采样电路可设置于开关电源的电源控制芯片。
其中，采样保持模块10具有采样输入端IN、采样输出端OUT和采样控制端P，采样输入端IN与电压采样点M相连,采样保持模块10用于在采样阶段采样电压采样点M的电压V1，以使采样输出端的采样电压V2跟随电压采样点M的电压V1，并在采样阶段结束后保持采样输出端的采样电压V2；控制模块20分别与电压采样点M以及采样保持模块10的采样控制端P和采样输出端OUT相连，控制模块20用于在根据电压采样点M的电压V1判断电压采样点M的电压V1处于可采样电压段时，控制采样保持模块10进入采样阶段，以及在根据电压采样点M的电压V1和采样输出端的采样电压V2判断电压采样点M的电压V1处于电压拐点时，控制采样保持模块10的采样阶段结束以使采样输出端的采样电压V2保持在电压拐点对应的电压。
也就是说，控制模块20接收电压采样点M的电压V1并判断电压采样点M的电压V1是否处于可采样的电压段，当电压采样点M的电压V1处于可采样的电压段时，控制模块20输出开通控制信号SH例如高电平至采样保持模块10的采样控制端P，采样保持模块10在接收到开通控制信号SH时进入采样阶段，此时，采样保持模块10采样电压采样点M的电压V1，以使采样输出端的采样电压V2跟随电压采样点M的电压V1。当电压采样点M的电压V1变化至电压拐点时，控制模块20输出关断控制信号SH例如低电平至采样保持模块10的采样控制端P，采样保持模块10在接收到关断控制信号SH时结束采样阶段并进入保持阶段，此时，采样输出端的采样电压V2保持在电压拐点对应的电压。
需要说明的是，结合图6的实施例，电压采样点M可为开关电源中反馈线圈的电 压反馈端Q即图6所示的电源控制芯片的电压反馈引脚VFB(voltage feed back)，由于电压采样点M的电压平台时间的长短实际对应的是次级绕组消磁时间的长短，当次级线圈消磁结束时，流过次级线圈的电流为0，此时，次级线圈上不产生压降，次级线圈的输出线路也不产生压降，反馈线圈可以准确映射次级线圈的输出电压，如果电压采样电路此时采样反馈线圈的电压反馈引脚VFB的电压，则可通过电压采样点M的电压准确映射输出电压的大小，如图3所示，在t3时刻，次级线圈消磁结束，电压反馈引脚VFB的电压即将开始下降即电压采样点M的电压V1波形出现电压拐点。由此，无论电压采样点M的电压平台时间长短，不管轻载还是重载，最终采样到的电压均是电压拐点对应的电压，能够准确映射次级线圈的输出电压的大小。
由此，采样保持模块10可采样电压拐点对应的电压，并将电压拐点对应的电压作为最终的采样电压输出至误差放大器，以及根据采样电压调整电源控制芯片输出的控制信号，以调整功率开关管的工作频率和导通的占空比，使次级线圈的输出电压保持稳定，从而能够避免开关电源的负载变化对采样电压产生影响，改善了控制系统的稳定性和准确性，提高了开关电源输出电压的恒压精度，提升了用户体验。
下面结合图3和图4来具体描述本发明实施例的电压采样电路的电路结构和工作原理。
根据本发明的一个实施例，如图4所示，控制模块20包括：触发器201、第一控制单元202和第二控制单元203。
其中，触发器201具有置位端S、复位端R和输出端O，触发器201的输出端O与采样保持模块10的采样控制端P相连；第一控制单元202的输入端IN1与电压采样点M相连，第一控制单元202的输出端OUT1与触发器201的置位端S相连，第一控制单元202用于在判断电压采样点M的电压V1处于可采样电压段时控制触发器201置位以控制采样保持模块10进入采样阶段；第二控制单元203的输入端IN2分别与电压采样点M以及采样输出端相连，第二控制单元203的输出端OUT2与触发器201的复位端R相连，第二控制单元203用于在判断电压采样点M的电压处于电压拐点时控制触发器201复位，以控制采样保持模块10的采样阶段结束。
具体来说，当电压采样点M的电压V1处于可采样电压段时，第一控制单元202的输出端OUT1输出采样信号例如高电平至触发器201的置位端S，以控制触发器201置位，触发器201输出开通控制信号SH至采样保持模块10的采样控制端P，以控制采样保持模块10进入采样阶段；当电压采样点M的电压处于电压拐点时，第二控制单元203的输出端OUT2输出采样结束信号例如高电平至触发器201的复位端R，以控制触发器201复位，触发器201输出关断控制信号SH至采样保持模块10的采样控制端P，以控制采样保持模块10的采样阶段结束即进入保持阶段。
需要说明的是，可采样电压段可指电压采样点M的电压V1的电压平台中段，在本发明实施例中，将电压采样点M的电压V1与预设电压V0进行比较，并在电压采样点M的电压V1大于预设电压V0后延时预设延时时间判断电压采样点M的电压V1处于 可采样电压段即电压平台中段。
根据本发明的一个实施例，如图4所示，第一控制单元202包括：第一比较器CMP1和延时单元210，其中，第一比较器CMP1的第一输入端与电压采样点M相连，第一比较器CMP1的第二输入端与预设电压提供端Vref相连，第一比较器CMP1用于在电压采样点M的电压V1大于预设电压V0(例如由Vref提供)时输出采样信号；延时单元210的一端与第一比较器CMP1的输出端相连，延时单元210的另一端与触发器201的置位端S相连，延时单元210用于将采样信号延时预设延时时间T后输出至触发器201以控制触发器201置位。另外，第一比较器CMP1的电源端与预设电源VCC相连，第一比较器CMP1的接地端接地。
具体来说，预设电压提供端Vref提供的预设电压V0可为0.1V，当电压采样点M的电压V1小于等于0.1V时，第一比较器CMP1输出第一采样信号例如低电平；当电压采样点M的电压V1大于0.1V时，第一比较器CMP1的输出发生翻转即输出第二采样信号例如高电平。延时电路210将第一比较器CMP1输出的采样信号延时预设延时时间T后输出至触发器201的置位端S，从而在第一比较器CMP1输出高电平后延时预设延时时间T控制触发器201置位，采样保持模块10进入采样阶段。
需要说明的是，如图3所示，由于电压采样点M的电压V1在一个周期内的初始阶段存在振荡波动，延时电路210将采样信号延时预设延时时间T能够避免采样保持模块10采样到电压平台初期干扰较大的电压。
根据本发明的一个实施例，如图4所示，第二控制单元203包括：第二比较器CMP2，第二比较器CMP2的第一输入端与采样输出端相连，第二比较器CMP2的第二输入端与电压采样点M相连，第二比较器CMP2的输出端与触发器201的复位端R，第二比较器CMP2用于在采样输出端输出的采样电压V2与电压采样点M的电压V1之间的差值大于预设阈值时，输出采样结束信号至触发器201以控制触发器201复位。另外，第二比较器CMP2的电源端与预设电源VCC相连，第二比较器CMP2的接地端接地。
根据本发明的一个具体实施例，第二比较器CMP2可为输入端存在微小失配的比较器，也就是说，当第二比较器CMP2的第一输入端和第二输入端的差值较小时第二比较器CMP2输出的电平不翻转。
具体来说，在电压采样阶段，采样输出端输出的采样电压V2变化滞后于电压采样点M的电压V1变化，如图3所示，在电压采样点M的电压平台的中段，电压采样点M的电压V1变化比较缓慢，此时，采样输出端输出的采样电压V2与电压采样点M的电压V1之间的差值小于预设阈值，即第二比较器CMP2的第一输入端和第二输入端的电压差值小于预设阈值，第二比较器CMP2输出第一采样结束信号例如低电平至触发器201的复位端R，触发器201保持置位即继续输出高电平。如图3所示，在电压采样点M的电压处于电压拐点时，电压采样点M的电压V1突然减小，采样输出端输出的采样电压V2变化滞后于电压采样点M的电压V1变化，因此，采样输出端输出的采样电压V2与电压采样点M的电压V1之间的差值大于预设阈值，即第二比较器CMP2的第一 输入端和第二输入端的电压差值大于预设阈值，第二比较器CMP2输出第二采样结束信号例如高电平至触发器201的复位端R，触发器201复位即输出低电平。
根据本发明的一个实施例，如图4所示，采样保持模块10包括：采样保持单元101、开关单元102和触发单元103。
其中，采样保持单元101分别与电压采样点M和控制模块20相连，采样保持单元101包括传输门TR，其中，控制模块20通过控制传输门TR导通以控制采样保持模块10进入采样阶段，并通过控制传输门TR关断以控制采样阶段结束；开关单元102与采样保持单元101并联连接；触发单元103分别与控制模块20和开关单元102相连，触发单元103用于在采样保持模块10进入采样阶段时生成触发信号以触发开关单元102导通预设时间，以使采样保持模块10的输出端先通过开关单元102跟随电压采样点M的电压，再在预设时间后通过采样保持单元101跟随电压采样点M的电压。
由此，能够避免电压采样点M的电压平台已经结束而采样输出端OUT输出的采样电压V2还未跟上电压采样点M的电压V1的情况出现，从而可保证电压采样电路采样到电压拐点的电压。
根据本发明的一个实施例，如图4所示，采样保持单元101还包括：第一电阻R1、第一电容C1、第二电阻R2和第二电容C2，其中，第一电阻R1的第一端与电压采样点M相连，第一电阻R1的第二端与传输门TR的一端相连，传输门TR的控制端与控制模块20相连；第一电容C1的一端与传输门TR的另一端相连，第一电容C1的另一端接地，第一电容C1与传输门TR之间具有第一节点；第二电阻R2的第一端与第一节点相连，第二电阻R2的第二端与控制模块20相连；第二电容C2的一端与第二电阻R2的第二端相连，第二电容C2的另一端接地，第二电容C2与第二电阻R2之间具有第二节点。
具体来说，第一电阻R1和第一电容C1可构成第一级RC滤波电路，第二电阻R2和第二电容C2可构成第二级RC滤波电路，其中，第一电阻R1的第一端可作为采样保持模块10的采样输入端IN，传输门TR的控制端可作为采样保持模块10的采样控制端P，第一节点可作为采样保持模块10的第一采样输出端OUT＇，第二节点可作为采样保持模块10的第二采样输出端OUT＇＇，其中，可通过第一采样输出端OUT＇将采样电压输出至开关电源的误差放大器，可通过第二采样输出端OUT＇＇将采样电压输出至控制模块20。
应当理解的是，也可通过第二采样输出端OUT＇＇将采样电压输出至开关电源的误差放大器。
根据本发明的一个实施例，如图4所示，开关单元102包括：第一MOS管MOS1和第二MOS管MOS2，其中，第一MOS管MOS1的源极S分别与第一电阻R1的第一端和电压采样点M相连，第一MOS管MOS1的漏极D与第一节点相连，第一MOS管MOS1的栅极G与触发单元103相连；第二MOS管MOS2的源极S与第一节点相连，第一MOS管MOS1的漏极D与第二节点相连，第二MOS管MOS2的栅极G分别与第 一MOS管MOS1的栅极G和触发单元103相连。
根据本发明的一个实施例，如图4所示，触发单元103包括前沿消隐电路110。
根据本发明的一个具体实施例，如图3所示，在t1时刻，电压采样点M的电压V1大于预设电压V0例如0.1V，在t1至t3时间段内，电压采样点M的电压平台初始阶段的电压波形存在振荡波动，随后电压采样点M的电压平台存在缓慢下降趋势，在t3时刻，电压采样点M的电压有快速下降趋势，也就是说，在t3时刻，电压采样点M的电压处于电压拐点。在本发明的实施例中，可在t2时刻进行采样，即，在t2时刻，延时单元210将采样信号输出至触发器201的置位端S，电压采样电路开始进入采样阶段，以避免采样到振荡波动，此时，延时单元210的预设延时时间T＝t2-t1。
具体来说，在t1时刻，电压采样点M的电压V1大于0.1V，第一比较器CMP1输出采样信号例如高电平，延时单元210在图3所示的t2时刻将采样信号输出至触发器201的置位端S，触发器201的输出置高即触发器201的输出端O输出开通控制信号SH例如高电平。传输门TR在接收到开通控制信号SH时导通以控制采样保持模块10进入采样阶段，在采样开始阶段，触发单元103接收开通控制信号SH以生成触发信号例如脉冲很小的PWM信号SHFA，触发信号SHFA的脉冲宽度小于开通控制信号SH的脉冲宽度，当PWM信号SHFA为高电平时，第一MOS管MOS1和第二MOS管MOS2导通，开关单元102导通预设时间，以使采样保持单元101中的传输门TR、第一电阻R1、第一电容C1、第二电阻R2和第二电容C2均短路预设时间，此时，采样输出端OUT输出的采样电压V2不经过RC滤波电路，采样电压V2通过开关单元102迅速跟随电压采样点M的电压V1，在电压采样点M的电压平台时间较短时，能够避免电压采样点M的电压平台已经结束而采样输出端OUT输出的采样电压V2还未跟上电压采样点M的电压V1的情况出现，从而可保证电压采样电路采样到电压拐点的电压。
在PWM信号SHFA变为低电平时，第一MOS管MOS1和第二MOS管MOS2关断，采样输出端OUT输出的采样电压V2通过采样保持单元101跟随电压采样点M的电压V1。具体地，传输门TR在开通控制信号SH的控制下导通，传输门TR和第一级RC滤波电路对电压采样点M的电压V1进行处理后输出采样电压V2至开关电源的误差放大器，且传输门TR、第一级RC滤波电路和第二级RC滤波电路对电压采样点M的电压V1进行处理后输出采样电压V2至第二比较器CMP2的第一输入端。由于RC滤波电路的时间常数较大，因此，采样输出端OUT输出的采样电压V2的变化滞后于电压采样点M的电压V1的变化。
在t2-t3时间段内，电压采样点M的电压V1变化比较缓慢，采样电压V2与电压采样点M的电压V1之间的差值小于预设阈值，第二比较器CMP2输出第一采样结束信号例如低电平至触发器201的复位端R，触发器201保持置位即继续输出高电平，控制传输门TR保持导通以持续进行采样，采样电压V2跟随电压采样点M的电压V1。如果电压采样点M的电压V1变化较大，则在采样电压V2与电压采样点M的电压V1之间产生差值，在t3时刻，电压采样点M的电压V1有迅速下降的趋势即电压采样点M的 电压V1处于电压拐点，此时，采样输出端输出的采样电压V2与电压采样点M的电压V1之间的差值大于预设阈值，第二比较器CMP2输出第二采样结束信号例如高电平至触发器201的复位端R，触发器201复位即输出低电平，控制传输门TR关断以控制采样阶段结束，进入保持阶段，采样电压V2保持在电压拐点对应的电压。
综上，根据本发明实施例提出的电压采样电路，控制模块在电压采样点的电压处于可采样电压段时控制采样保持模块进入采样阶段，以使采样输出端的采样电压跟随电压采样点的电压，并在电压采样点的电压处于电压拐点时控制采样保持模块的采样阶段结束，以使采样输出端的采样电压保持在电压拐点对应的电压，从而通过采样电压拐点的电压，能够准确反映输出电压的大小，避免开关电源的负载变化对采样电压产生影响，改善了控制系统的稳定性和准确性，提高了开关电源输出电压的恒压精度，提升了用户体验。
图5是根据本发明实施例提出的开关电源的方框示意图。如图5所示，开关电源200包括电压采样电路100。
根据本发明的一个实施例，如图6所示，开关电源200包括整流模块30、电源控制芯片40、功率开关管Q1和变压器组件50。其中，电压采样电路100集成在电源控制芯片40内部；变压器组件50包括初级线圈501、次级线圈502和反馈线圈503，次级线圈502的一端与开关电源200的第一输出端V+相连，次级线圈502的另一端与开关电源200的第二输出端V-相连，反馈线圈503的一端与电源控制芯片40相连，反馈线圈503的另一端与整流模块30相连。
具体来说，电源控制芯片40用于输出控制信号以控制功率开关管Q1(例如Q1可为MOS管)的导通或关断，以实现变压器组件50的初、次级能量传递，并通过控制功率开关管Q1的工作频率和导通的占空比控制次级线圈502的输出电压和输出电流。电源控制芯片40还用于通过反馈线圈503采样次级线圈502的输出电压，进而调节控制信号的输出频率和占空比，以使次级线圈502的输出电压保持稳定。
根据本发明的一个具体实施例，如图7所示，电源控制芯片40包括以下端口：供电引脚VDD、接地引脚VSS、电流输入引脚CS、输出引脚OUT和电压反馈引脚VFB。其中，供电引脚VDD作为电源控制芯片40供电端用于给控制芯片供电；电流输入引脚CS用于检测流过变压器组件50的初级线圈的电流；输出引脚OUT用于输出控制信号以控制功率开关管Q1的导通或关断；采样引脚VFB用于采样反馈线圈的反馈电压，即，电压反馈引脚VFB为上述实施例中电压采样电路的电压采样点。
在本发明的实施例中，如图7所示，电源控制芯片40可进一步包括：基准偏置模块401、启动模块402、时间采样电路403、误差放大器404、脉冲调制模块405、逻辑处理模块406、驱动模块407和过流保护模块408。
其中，电压采样电路100的输入端与电压反馈引脚VFB相连，电压采样电路100的输出端(例如图4实施例中的OUT’)与误差放大器404的第一输入端相连；误差放大器404的第二输入端与基准电压提供端相连；时间采样电路403的输入端与电压反馈 引脚VFB相连，时间采样电路403的输出端与误差放大器404的输出端相连，时间采样电路403的输出端与误差放大器404的输出端之间具有第三节点；脉冲调制模块405的第一输入端与第三节点相连，脉冲调制模块405的第二输入端与时间采样电路403的输出端相连；逻辑处理模块406的第一输入端与脉冲调制模块405的输出端相连；驱动模块407的输入端与逻辑处理模块406的输出端相连，驱动模块407的输出端与输出引脚OUT相连；过流保护模块408的第一输入端与电流输入引脚CS相连，过流保护模块408的第二输入端与基准电流提供端相连，过流保护模块408的输出端与逻辑处理模块406的第二输入端相连。
具体来说，基准偏置模块401用于提供电源控制芯片40内部所需的电压基准和电流偏置；启动模块402用于控制源控制芯片40的启动和关断；电压采样电路100用于采样反馈绕组的电压V1并输出采样电压V2；时间采样电路403用于采样电压采样点的电压平台时间以对开关电源进行恒流控制；误差放大器404用于将采样电压V2和基准电压进行比较，并进行误差放大；脉冲调制模块405用于进行脉冲宽度调制和脉冲频率调制，以将误差放大器404输出的模拟信号输出转化为PWM信号，并将PWM信号输出至逻辑处理模块406，逻辑处理模块406对PWM信号进行逻辑处理以生成相应的控制信号，驱动模块407用于生成驱动控制信号以驱动功率开关管Q1；过流保护模块408用于检测初级电流的峰值电流，当初级电流的峰值电流超过预设电流阈值时生成功率开关管关断信号，以对开关电源进行过流保护。
这样，开关电源可通过反馈线圈采样次级线圈的输出电压，其中，电压采样电路根据电压采样点M的电压V1生成相应的采样电压V2，并将采样电压V2输出至误差放大器，误差放大器404对采样电压V2进行处理，并根据采样电压V2调节整个系统环路，以及根据采样电压V2调整电源控制芯片40输出的控制信号，以调整功率开关管Q1的工作频率和导通的占空比，使次级线圈的输出电压保持稳定。
综上，根据本发明实施例提出的开关电源，通过上述电压采样电路采样电压拐点的电压，能够准确反映输出电压的大小，避免开关电源的负载变化对采样电压产生影响，改善了控制系统的稳定性和准确性，提高了开关电源输出电压的恒压精度，提升了用户体验。
在本发明的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”“内”、“外”、“顺时针”、“逆时针”、“轴向”、“径向”、“周向”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。在本发明的描述中，“多个”的含义是至少 两个，例如两个，三个等，除非另有明确具体的限定。
在本发明中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”、“固定”等术语应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或成一体；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系，除非另有明确的限定。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本发明中的具体含义。
在本发明中，除非另有明确的规定和限定，第一特征在第二特征“上”或“下”可以是第一和第二特征直接接触，或第一和第二特征通过中间媒介间接接触。而且，第一特征在第二特征“之上”、“上方”和“上面”可是第一特征在第二特征正上方或斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”可以是第一特征在第二特征正下方或斜下方，或仅仅表示第一特征水平高度小于第二特征。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
尽管上面已经示出和描述了本发明的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本发明的限制，本领域的普通技术人员在本发明的范围内可以对上述实施例进行变化、修改、替换和变型。

Claims (9)

  1. 一种电压采样电路，其特征在于，包括：
    采样保持模块，所述采样保持模块具有采样输入端、采样输出端和采样控制端，所述采样输入端与电压采样点相连,所述采样保持模块用于在采样阶段采样所述电压采样点的电压，以使所述采样输出端的采样电压跟随所述电压采样点的电压，并在所述采样阶段结束后保持所述采样输出端的采样电压；
    控制模块，所述控制模块分别与所述电压采样点以及所述采样保持模块的控制端和采样输出端相连，所述控制模块用于在根据所述电压采样点的电压判断所述电压采样点的电压处于可采样电压段时，控制所述采样保持模块进入所述采样阶段，以及在根据所述电压采样点的电压和所述采样输出端的采样电压判断所述电压采样点的电压处于电压拐点时，控制所述采样保持模块的采样阶段结束以使所述采样输出端的采样电压保持在所述电压拐点对应的电压。
  2. 根据权利要求1所述的电压采样电路，其特征在于，所述控制模块包括：
    触发器，所述触发器具有置位端、复位端和输出端，所述触发器的输出端与所述采样保持模块的采样控制端相连；
    第一控制单元，所述第一控制单元的输入端与所述电压采样点相连，所述第一控制单元的输出端与所述触发器的置位端相连，所述第一控制单元用于在判断所述电压采样点的电压处于可采样电压段时控制所述触发器置位以控制所述采样保持模块进入所述采样阶段；
    第二控制单元，所述第二控制单元的输入端与所述电压采样点以及所述采样输出端相连，所述第二控制单元的输出端与所述触发器的复位端相连，所述第二控制单元用于在判断所述电压采样点的电压处于电压拐点时控制所述触发器复位，以控制所述采样保持模块的采样阶段结束。
  3. 根据权利要求2所述的电压采样电路，其特征在于，所述第一控制单元包括：
    第一比较器，所述第一比较器的第一输入端与所述电压采样点相连，所述第一比较器的第二输入端与预设电压提供端相连，所述第一比较器用于在所述电压采样点的电压大于所述预设电压时输出采样信号；
    延时单元，所述延时单元的一端与所述第一比较器的输出端相连，所述延时单元的另一端与所述触发器的置位端相连，所述延时单元用于将所述采样信号延时预设延时时间后输出至所述触发器以控制所述触发器置位。
  4. 根据权利要求2或3所述的电压采样电路，其特征在于，所述第二控制单元包括：
    第二比较器，所述第二比较器的第一输入端与所述采样输出端相连，所述第二比较器的第二输入端与所述电压采样点相连，所述第二比较器的输出端与所述触发器的复位端,所述第二比较器用于在所述采样输出端输出的采样电压与所述电压采样点的电压之间的差值大于预设阈值时，输出采样结束信号至所述触发器以控制所述触发器复位。
  5. 根据权利要求1-4中任一项所述的电压采样电路，其特征在于，所述采样保持模块包括：
    采样保持单元，所述采样保持单元分别与所述电压采样点和所述控制模块相连，所述采样保持单元包括传输门，其中，所述控制模块通过控制所述传输门导通来控制所述采样保持模块进入所述采样阶段，并通过控制所述传输门关断来控制所述采样阶段结束；
    开关单元，所述开关单元与所述采样保持单元并联连接，且所述开关单元被触发单元控制；
    触发单元，所述触发单元分别与所述控制模块和所述开关单元相连，所述触发单元用于在所述采样保持模块进入所述采样阶段时生成触发信号以触发所述开关单元导通预设时间，以使所述采样保持模块的输出端先通过所述开关单元跟随所述电压采样点的电压，再在所述预设时间后通过采样保持单元跟随所述电压采样点的电压。
  6. 根据权利要求5所述的电压采样电路，其特征在于，所述采样保持单元还包括：
    第一电阻，所述第一电阻的第一端与所述电压采样点相连，所述第一电阻的第二端与所述传输门的一端相连，所述传输门的控制端与控制模块相连；
    第一电容，所述第一电容与所述传输门的另一端相连，所述第一电容的另一端接地，所述第一电容与所述传输门之间具有第一节点；
    第二电阻，所述第二电阻的第一端与所述第一节点相连，所述第二电阻的第二端与所述控制模块相连；
    第二电容，所述第二电容的一端与所述第二电阻的第二端相连，所述第二电容的另一端接地，所述第二电容与所述第二电阻之间具有第二节点。
  7. 根据权利要求6所述的电压采样电路，其特征在于，所述开关单元包括：
    第一MOS管，所述第一MOS管的源极分别与所述第一电阻的第一端和所述电压采样点相连，所述第一MOS管的漏极与所述第一节点相连，所述第一MOS管的栅极与所述触发单元相连；
    第二MOS管，所述第二MOS管的源极与所述第一节点相连，所述第一MOS管的漏极与所述第二节点相连，所述第二MOS管的栅极分别与所述第一MOS管的栅极和所述触发单元相连。
  8. 根据权利要求5所述的电压采样电路，其特征在于，所述触发单元包括前沿消隐电路。
  9. 一种开关电源，其特征在于，包括根据权利要求1-8中任一项所述的电压采样电路。
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