WO2018120934A1 - Lte基站基带处理板主备信号处理方法 - Google Patents

Lte基站基带处理板主备信号处理方法 Download PDF

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WO2018120934A1
WO2018120934A1 PCT/CN2017/102521 CN2017102521W WO2018120934A1 WO 2018120934 A1 WO2018120934 A1 WO 2018120934A1 CN 2017102521 W CN2017102521 W CN 2017102521W WO 2018120934 A1 WO2018120934 A1 WO 2018120934A1
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standby
bpu
active
bpus
data
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PCT/CN2017/102521
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English (en)
French (fr)
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邵忠军
王云峰
吉荣新
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南京泰通科技股份有限公司
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Publication of WO2018120934A1 publication Critical patent/WO2018120934A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/25—Arrangements specific to fibre transmission
    • H04B10/2575—Radio-over-fibre, e.g. radio frequency signal modulated onto an optical carrier
    • H04B10/25752—Optical arrangements for wireless networks
    • H04B10/25758—Optical arrangements for wireless networks between a central unit and a single remote unit by means of an optical fibre
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/03—Arrangements for fault recovery
    • H04B10/032—Arrangements for fault recovery using working and protection systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W24/00—Supervisory, monitoring or testing arrangements
    • H04W24/04—Arrangements for maintaining operational condition

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  • the present invention relates to the field of LTE-R wireless mobile communication base stations, and in particular to a method for processing active and standby signals of an LTE base station baseband processing board.
  • China Railway is developing an LTE-R technical standard system and adopts the latest LTE technology as the next-generation railway mobile communication system.
  • LTE-R carries the railway traffic, operation and maintenance services, public safety communication services and passenger information system services.
  • the driving business includes train dispatching communication, dispatching communication, vehicle dispatching communication, power dispatching communication, comprehensive maintenance dispatching communication and emergency communication. These services place extremely high requirements on the stability and reliability of the railway communication system.
  • the active and standby redundancy design of the entire communication system must be considered when networking. That is to use two sets of communication systems, one set of main use, one set of standby, when the main system fails, quickly switch to the standby system, so as to ensure the normal operation of the communication service.
  • the LTE wireless communication system consists of a terminal, a base station, and a core network (EPC).
  • the base station is composed of a baseband processing unit (BBU) and a radio remote unit (RRU).
  • the BBU is generally a multi-slot rack-mounted device with a central control board (CCU), a baseband processing board (BPU), a switch board, etc., installed in the equipment room.
  • the BBU board-level master/slave is difficult to implement because it is subject to the rack structure, hardware solution, power consumption, weight, cost, and operability, or can only achieve the active/standby redundancy of some boards.
  • the BPU is the most important board in the BBU.
  • the panel uses a high-performance multi-core DSP chip to complete the physical layer, MAC layer and Layer 3 protocol functions.
  • the panel outputs CPRI optical interfaces and RRU communication.
  • the general BPU master-slave redundancy synchronizes the basic configuration of the user and control plane of the primary BPU to the standby BPU through the network port of the backplane, a large number of users and control data, and a large amount of physics.
  • Layer and link layer data cannot be synchronized due to huge overhead.
  • services are interrupted during active/standby switchover.
  • the terminal re-initiates the random access request, and is established through radio resource control (RRC) and radio access bearer (E-RAB).
  • RRC radio resource control
  • E-RAB radio access bearer
  • the present invention provides a master/slave signal processing method for an LTE base station baseband processing board.
  • the high-speed synchronous bus based on the DSP chip adds timing synchronization processing to not only solve the upper layer configuration when the active and standby BPU switches. Synchronization of parameters enables the original service to be uninterrupted when the active and standby BPUs are switched.
  • the BPU active/standby switching device used in the present invention is composed of two parts:
  • the optical path switching part implements CPRI optical fiber protection switching and optical division of the BPU and the RRU interface, and can be physically inserted into the BBU chassis.
  • the optical protection board uses the FPGA, does not use the CPU, does not install the operating system, and the software and hardware are as simple as possible to ensure the reliability of the software and hardware.
  • the CPRI optical signal sent by the RRU to the BPU is sent to the primary and backup BPUs by the optical splitter, and is received by the BPU optical module, so that the two BPUs of the active and standby BPUs receive the same RRU signal.
  • the optical protection board controls the two BPU states by controlling the two BPU states, so that the CPRI optical signal received by the RRU is switched to the primary BPU.
  • BBU chassis The active and standby BPUs are inserted into the BBU chassis in the form of boards.
  • the backplane of the chassis is designed with four buses to support fast switching between the BPU master and backup. Including: 1, BPU active and standby status bus: detecting the peer BPU in position and active and standby state; 2, DSP beat synchronous bus: synchronous internal beat of the DSP chip on the active and standby BPU, by calculating the phase difference to make the DSP internal processing phase consistent or constant 3, Ethernet synchronous bus: use SGMII bus to synchronize the basic configuration of the user and control plane of the active and standby BPU; 4, high-speed synchronous bus: use the high-speed serdes bus synchronization of the DSP chip, the active and standby BPU massive user data, control data, Physical layer data and link layer data.
  • the signal processing method provided by the present invention includes the following steps:
  • the upstream data is sent to the active and standby BPUs. After the physical layer, the link layer, and the network layer are processed, the data is not uploaded to the EPC through the S1 interface of the BBU until the main switch is used.
  • Downlink data The downlink data sent by the EPC via the S1 interface is sent to the primary BPU through the switching network of the BBU.
  • the BPU is normally processed and sent to the RRU via the CPRI optical interface.
  • the DSP chip of the primary BPU sends the downlink data received by the primary BPU to the DSP chip of the standby BPU in real time through the high-speed data synchronization port, and is sent by the standby BPU through the CPRI interface, because the optical protection board detects the work of the active and standby BPUs. State, the optical path is switched to the primary BPU, so the RRU does not receive the CPRI optical signal from the standby BPU;
  • Active/standby switchover The standby BPU immediately sets itself to the active use, and sets the peer BPU as standby to complete the active/standby switchover of the BPU.
  • the optical protection board monitors the status of the active and standby BPUs in real time, and finds that the BPU controls the light after switching. The switch quickly switches to the new active BPU;
  • the master-slave state synchronization bus includes an Ethernet synchronous bus connecting the main and standby BPUs and a high-speed synchronous bus based on the DSP chip.
  • the Ethernet synchronous bus uses the SGMII bus to synchronize the basic configuration of the user and control plane of the active and standby BPUs.
  • the DSP chip inside the BPU is connected to the high-speed synchronous bus through the high-speed interface, directly transmitting the underlying data and register status of the chip, and synchronizing a large amount of user data, control data, physical layer data and link layer data to the standby BPU through the high-speed interface. ;
  • DSP beat synchronization The backplane of the active and standby BPUs uses the DSP beat synchronization signal connection to perform DSP beat synchronization, and the auxiliary synchronization calculation is performed by the 1PPS and TOD signals on the backplane.
  • This patent uses a high-speed synchronous bus based on DSP chip.
  • the timing synchronization processing not only solves the synchronization of upper layer configuration parameters when the active and standby BPUs are switched, but also solves the massive user data, control data, physical layer data and link layer data synchronization. Since the integrity of the user and the control data is ensured, the original service is not interrupted when the active/standby BPU is switched, and the user is not aware of the instantaneous switching;
  • optical protection board design of the optical switch + optical splitter is used, so that the RRU does not have to be switched when the BPU is switched. This saves the RRU investment, and also eliminates the RRU handover and service setup time, and also ensures the user's non-aware handover.
  • Figure 1 is a schematic diagram of a BPU active/standby switchover device.
  • FIG. 2 is a schematic diagram of a method for switching between active and standby according to the present invention.
  • the BPU active/standby switching device used in the present invention is composed of two parts as shown in FIG.
  • the optical path switching part implements CPRI optical fiber protection switching and optical division of the BPU and the RRU interface, and can be physically inserted into the BBU chassis.
  • the optical protection board uses the FPGA, does not use the CPU, does not install the operating system, and the software and hardware are as simple as possible to ensure the reliability of the software and hardware.
  • the CPRI optical signal sent by the RRU to the BPU is sent to the primary and backup BPUs by the optical splitter, and is received by the BPU optical module, so that the two BPUs of the active and standby BPUs receive the same RRU signal.
  • the optical protection board controls the two BPU states by controlling the two BPU states, so that the CPRI optical signal received by the RRU is switched to the primary BPU.
  • BBU chassis part The main and standby BPUs are inserted in the BBU chassis in the form of boards, and the four boards of the chassis backplane are designed. It is used to support fast switching between the BPU master and backup. Including: 1, BPU active and standby status bus: detecting the peer BPU in position and active and standby state; 2, DSP beat synchronous bus: synchronous internal beat of the DSP chip on the active and standby BPU, by calculating the phase difference to make the DSP internal processing phase consistent or constant 3, Ethernet synchronous bus: use SGMII bus to synchronize the basic configuration of the user and control plane of the active and standby BPU; 4, high-speed synchronous bus: use the high-speed serdes bus synchronization of the DSP chip, the active and standby BPU massive user data, control data, Physical layer data and link layer data.
  • the signal processing method provided by the present invention is as shown in FIG. 2, and includes the following steps:
  • Upstream data The uplink data sent by the RRU is split into two bundles and sent to the active and standby BPUs (the model of the BPU used in the embodiment is TCI6638). After the main BPU is processed according to the normal process, the BBU is passed through the BBU. The network port is sent to the core network, and the backup BPU is processed normally according to the basic configuration of the user and control plane of the active BPU. After the physical layer, the link layer, and the network layer are processed, the data is not uploaded to the S1 interface of the BBU. EPC, until it is switched to the main use and then uploaded;
  • Downlink data The downlink data sent by the EPC via the S1 interface is sent to the primary BPU through the switching network of the BBU.
  • the BPU is normally processed and sent to the RRU via the CPRI optical interface.
  • the DSP chip of the primary BPU sends the downlink data received by the primary BPU to the DSP chip of the standby BPU in real time through the high-speed data synchronization port, and is sent by the standby BPU through the CPRI interface, because the optical protection board detects the work of the active and standby BPUs. State, the optical path is switched to the primary BPU, so the RRU does not receive the CPRI optical signal from the standby BPU;
  • Active/standby switchover The standby BPU immediately sets itself to the active use, and sets the peer BPU as standby to complete the active/standby switchover of the BPU.
  • the optical protection board monitors the status of the active and standby BPUs in real time, and finds that the BPU controls the light after switching. The switch quickly switches to the new active BPU;
  • the master-slave state synchronization bus includes an Ethernet synchronous bus connecting the main and standby BPUs and a high-speed synchronous bus based on the DSP chip.
  • the Ethernet synchronous bus uses the SGMII bus to synchronize the basic configuration of the user and control plane of the active and standby BPUs.
  • the DSP chip inside the BPU is connected to the high-speed synchronous bus through the high-speed interface, directly transmitting the underlying data and register status of the chip, and synchronizing a large amount of user data, control data, physical layer data and link layer data to the standby BPU through the high-speed interface. ;
  • DSP beat synchronization The backplane of the active and standby BPUs uses the DSP beat synchronization signal connection to perform DSP beat synchronization, and the auxiliary synchronization calculation is performed by the 1PPS and TOD signals on the backplane.
  • the BPU implementation process is as follows:
  • TCI6638 is a multi-core DSP+ARM KeyStone architecture high-performance processor designed by TI.
  • the system architecture is shown in Figure 2.
  • TCI6638 is used for high-speed processing and calculation of large-flow data and is widely used on LTE base stations.
  • TCI6638 has 8 TMS320C66x processors, each operating frequency 1G ⁇ 1.2GHz, there are 4 Cortex A15ARM processors, each working frequency is 1.4GHz, there are 4 Turbo decoders, 8 Viterbi decoders, 4
  • a variety of dedicated processors such as WCDA coprocessor, 6 FFT coprocessor, bit processing accelerator, etc., are especially suitable for base station applications.
  • the HyperLink interface consists of four sets of transceiver serdes buses with a maximum speed of 50 Gbps, which can be used to transmit user data, control data, physical layer data and link layer data.
  • the TPU6638 is used to build the BPU system: 1.
  • the AIF interface of the TCI6638 is configured in CPRI mode, and the optical module is connected to the RRU through the optical module.
  • the HyperLink is configured as a 50G, and is connected to the HyperLink interface of the TCI6638 through the backplane and the peer TCI6638 through four sets of serdes differential lines as a high-speed data synchronous backup channel.
  • the network port of the TCI6638 is relatively large.
  • a Gigabit Ethernet port is connected to the corresponding network port of the peer BPU through the SGMII mode through the SGMII mode, and the basic configuration of the user and control plane of the active and standby BPUs is synchronized. 4.
  • the IO port of the TCI6638 is used as the active/standby state detection and DSP timing synchronization signal of the active and standby BPUs.
  • the primary BPU sends the in-position and primary signals of the board to the standby BPU, and simultaneously sends a timing heartbeat signal to the standby BPU.
  • the standby BPU determines whether the active BPU works normally by detecting the presence, active/standby status, and heartbeat signals of the active BPU board. Once an abnormality is found, the board is used as a master and the baseband data processing function is performed.

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Abstract

本发明提供了一种LTE基站基带处理板LTE基站基带处理板主备信号处理方法，主备BPU之间有一组主备状态信号，包括板卡在位、主备状态、心跳信号，档备用BPU检测到主用BPU不在位、切换成备用或心跳超时，备用BPU立即将自己设成主用，同时将对端BPU设成备用，完成BPU的主备切换，并完成主备状态同步和DSP节拍同步。

Description

LTE基站基带处理板主备信号处理方法 技术领域
本发明涉及LTE-R无线移动通信基站领域，具体是一种LTE基站基带处理板主备信号处理方法。
背景技术
随着中国铁路移动通信带宽需求迅猛增长，原有的GSM-R系统不再适应新的市场需求，而且随着GSM产业链的逐渐消亡，迫切需要对原有的GSM-R通信体制进行升级换代。参照GSM-R技术规范中国铁路正在制定LTE-R技术标准体系，采用最新的LTE技术作为下一代铁路移动通信体制。
LTE-R承载铁路的行车业务、运营维护业务、公共安全通信业务和旅客信息系统业务。行车业务包括了列车调度通信、机务调度通信、车辆调度通信、供电调度通信、综合维修调度通信和应急通信等，这些业务对铁路通信系统的稳定性、可靠性提出了极高的要求。为提高通信系统的可靠性，组网时必须考虑整个通信系统主备冗余设计。即采用两套通信系统，一套主用，一套备用，当主用系统故障时迅速切换到备用系统，这样来保证通信业务正常工作。
LTE无线通讯系统由终端、基站和核心网(EPC)组成。基站由基带处理单元(BBU)和射频拉远单元(RRU)构成。BBU一般是多槽位机架式设备，内插中央控制板(CCU)、基带处理板(BPU)、交换板等，安装在机房内。BBU板卡级主备因为受制于机架结构、硬件方案、功耗、重量、成本、可操作性等，很难实现，或者只能实现部分板卡的主备冗余。BPU是BBU中最重要的板卡，采用高性能多核DSP芯片，完成物理层、MAC层和三层协议功能，面板出CPRI光接口和RRU通信。因为BPU的数据处理量巨大，一般的BPU主备冗余都是通过背板的网口将主用BPU的用户和控制面基本配置同步到备用BPU上，大量的用户和控制数据以及海量的物理层、链路层数据由于开销巨大无法同步，这样导致主备切换时业务中断，终端要重新发起随机接入申请，经过无线资源控制(RRC)建立、无线接入承载(E-RAB)建立等流程才能重新继续原来的业务。所以一旦BPU主备切换，重新建立业务耗时很长，对于某些时间敏感的业务可能无法接受。
发明内容
本发明为了解决现有技术的问题，提供了一种LTE基站基带处理板主备信号处理方法，基于DSP芯片的高速同步总线，在加上时序同步处理不仅解决主备BPU切换时上层配置 参数同步，实现了主备BPU切换时原有业务不中断，瞬时切换，用户无感知。
本发明使用的BPU主备切换设备由两部分构成：
(1)光路切换部分：光路切换部分实现BPU和RRU接口的CPRI光纤保护切换和光分，物理上可以做成一块光保护板插在BBU机箱中。光保护板使用FPGA，不使用CPU，不安装操作系统，软硬件尽量简单，保证软硬件的可靠性。RRU发送给BPU的CPRI光信号经光分器，1：1分给主备两块BPU，接到BPU光模块的接收上，使主备两块BPU收到同样的RRU信号。光保护板通过判断主备两块BPU状态，控制二选一光开关使RRU接收的CPRI光信号切换到主用BPU上。
(2)BBU机箱部分：主备BPU以板卡形式插在BBU机箱中，机箱背板设计4条总线用以支持BPU主备快速切换。包括：1、BPU主备状态总线：检测对端BPU在位及主备状态；2、DSP节拍同步总线：同步主备BPU上DSP芯片的内部节拍，通过计算相位差使DSP内部处理相位一致或恒定；3、以太网同步总线：使用SGMII总线同步主备BPU的用户和控制面基本配置；4、高速同步总线：使用DSP芯片自带的高速serdes总线同步，主备BPU海量用户数据、控制数据、物理层数据及链路层数据。
本发明提供的信号处理方法包括以下步骤：
1)正常工作时，LTE基站基带处理板信号处理如下：
1.1)上行数据：RRU发出的上行数据经光分器后分成两束同时发给主备两块BPU，主用BPU按正常流程处理后，通过BBU的网口发送给核心网，备用BPU按照同步过来的主用BPU的用户和控制面基本配置正常处理，物理层、链路层和网络层处理完后，数据不再通过BBU的S1接口上传给EPC，直到切换成主用后再上传；
1.2)下行数据：EPC经S1接口下发的下行数据经过BBU的交换网发给主用BPU，BPU正常处理后经CPRI光接口发送给RRU。同时主用BPU的DSP芯片通过高速数据同步端口将主用BPU收到的下行数据实时发给备用BPU的DSP芯片，备用BPU处理后经CPRI接口发出，由于光保护板检测到主备BPU的工作状态，将光路切向主用BPU，所以RRU收不到备用BPU发出的CPRI光信号；
2)主备BPU之间有一组主备状态信号，包括板卡在位、主备状态、心跳信号，档备用BPU检测到主用BPU不在位、切换成备用或心跳超时，LTE基站基带处理板进行如下切换：
2.1)主备切换：备用BPU立即将自己设成主用，同时将对端BPU设成备用，完成BPU的主备切换，光保护板实时监视主备BPU的状态，发现BPU发生切换后控制光开关迅速切换到新的主用BPU上；
2.2)主备状态同步：主备状态同步总线包括连接主备BPU的以太网同步总线和基于DSP芯片的高速同步总线，以太网同步总线使用SGMII总线，同步主备BPU的用户和控制面基本配置，BPU内部的DSP芯片通过高速接口和高速同步总线相连，直接传输芯片的底层数据和寄存器状态，将大量的用户数据、控制数据、物理层数据及链路层数据通过高速接口同步到备用BPU上；
2.3)DSP节拍同步：主备BPU的背板采用DSP节拍同步信号连接，进行DSP节拍同步，并通过背板上的1PPS和TOD信号进行辅助同步计算。
本发明有益效果在于：
1、本专利使用基于DSP芯片的高速同步总线，在加上时序同步处理不仅解决主备BPU切换时上层配置参数同步，也解决海量用户数据、控制数据、物理层数据及链路层数据同步。由于保证了用户和控制数据的完整性，实现了主备BPU切换时原有业务不中断，瞬时切换，用户无感知；
2、采用光开关+光分器的光保护板设计，使BPU切换时RRU不必切换。这样节省RRU投资，也省去了RRU的切换和业务建立时间，也保证了用户的无感知切换。
附图说明
图1为BPU主备切换设备示意图。
图2为本发明主备切换方法示意图。
图中：1、RRU CPRI接收；2、2:1光开关；3、BPU(主用)；4、BPU主备状态；5、DSP节拍同步；6、以太网同步；7、高速数据同步；8、背板；9、BPU(备用)；10、光分器；11、RRU CPRI发送；12、CPRI光口。
具体实施方式
下面结合附图对本发明作进一步说明。
本发明使用的BPU主备切换设备如图1所示，由两部分构成：
(1)光路切换部分：光路切换部分实现BPU和RRU接口的CPRI光纤保护切换和光分，物理上可以做成一块光保护板插在BBU机箱中。光保护板使用FPGA，不使用CPU，不安装操作系统，软硬件尽量简单，保证软硬件的可靠性。RRU发送给BPU的CPRI光信号经光分器，1：1分给主备两块BPU，接到BPU光模块的接收上，使主备两块BPU收到同样的RRU信号。光保护板通过判断主备两块BPU状态，控制二选一光开关使RRU接收的CPRI光信号切换到主用BPU上。
(2)BBU机箱部分：主备BPU以板卡形式插在BBU机箱中，机箱背板设计4条总线 用以支持BPU主备快速切换。包括：1、BPU主备状态总线：检测对端BPU在位及主备状态；2、DSP节拍同步总线：同步主备BPU上DSP芯片的内部节拍，通过计算相位差使DSP内部处理相位一致或恒定；3、以太网同步总线：使用SGMII总线同步主备BPU的用户和控制面基本配置；4、高速同步总线：使用DSP芯片自带的高速serdes总线同步，主备BPU海量用户数据、控制数据、物理层数据及链路层数据。
本发明提供的信号处理方法如图2所示，包括以下步骤：
1)正常工作时，LTE基站基带处理板信号处理如下：
1.1)上行数据：RRU发出的上行数据经光分器后分成两束同时发给主备两块BPU(实施例中使用的BPU板型号为TCI6638)，主用BPU按正常流程处理后，通过BBU的网口发送给核心网，备用BPU按照同步过来的主用BPU的用户和控制面基本配置正常处理，物理层、链路层和网络层处理完后，数据不再通过BBU的S1接口上传给EPC，直到切换成主用后再上传；
1.2)下行数据：EPC经S1接口下发的下行数据经过BBU的交换网发给主用BPU，BPU正常处理后经CPRI光接口发送给RRU。同时主用BPU的DSP芯片通过高速数据同步端口将主用BPU收到的下行数据实时发给备用BPU的DSP芯片，备用BPU处理后经CPRI接口发出，由于光保护板检测到主备BPU的工作状态，将光路切向主用BPU，所以RRU收不到备用BPU发出的CPRI光信号；
2)主备BPU之间有一组主备状态信号，包括板卡在位、主备状态、心跳信号，档备用BPU检测到主用BPU不在位、切换成备用或心跳超时，LTE基站基带处理板进行如下切换：
2.1)主备切换：备用BPU立即将自己设成主用，同时将对端BPU设成备用，完成BPU的主备切换，光保护板实时监视主备BPU的状态，发现BPU发生切换后控制光开关迅速切换到新的主用BPU上；
2.2)主备状态同步：主备状态同步总线包括连接主备BPU的以太网同步总线和基于DSP芯片的高速同步总线，以太网同步总线使用SGMII总线，同步主备BPU的用户和控制面基本配置，BPU内部的DSP芯片通过高速接口和高速同步总线相连，直接传输芯片的底层数据和寄存器状态，将大量的用户数据、控制数据、物理层数据及链路层数据通过高速接口同步到备用BPU上；
2.3)DSP节拍同步：主备BPU的背板采用DSP节拍同步信号连接，进行DSP节拍同步，并通过背板上的1PPS和TOD信号进行辅助同步计算。
以TCI6638系统为例，BPU实现过程如下：
TCI6638是TI公司设计的多核DSP+ARM KeyStone架构高性能处理器，系统架构如图2所示。 TCI6638用于大流量数据的高速处理、计算，在LTE基站上大量使用。TCI6638有8个TMS320C66x处理器，每个工作频率1G～1.2GHz，有4个Cortex A15ARM处理器，每个工作频率1.4GHz，内部还有4个Turbo译码器、8个Viterbi译码器、4个WCDA协处理器、6个FFT协处理器、位处理加速器等多种专用处理器，特别适合基站应用。有6个CPRI接口、2个HyperLink接口、2个10G以太网、4个千兆以太网接口方便外接RRU、交换机、EPC等设备。其中HyperLink接口由4组收发serdes总线组成，最高速率达50Gbps，可以用来传输用户数据、控制数据、物理层数据及链路层数据。
用TCI6638搭建BPU系统：1、TCI6638的AIF接口配成CPRI模式，通过光模块使用光纤和RRU连接。2、HyperLink配置成50G，通过4组serdes差分线经过背板和对端TCI6638的HyperLink接口连接，作为高速数据同步备份通道。3、TCI6638的网口比较多，取一个千兆网口通过SGMII模式经过背板与对端BPU的对应网口连接，同步主备BPU的用户和控制面基本配置。4、TCI6638的IO端口用作主备BPU的主备状态检测和DSP时序同步信号，主用BPU将本板的在位和主用信号发给备用BPU，同时向备用BPU发送定时的心跳信号，备用BPU通过检测主用BPU板卡在位、主备状态、心跳信号来判断主用BPU工作是否正常，一旦发现异常，将本板置为主用，执行基带数据的处理功能。两块BPU的主备数据同步过程中，尤其是用户数据、控制数据、物理层数据及链路层数据同步过程中，涉及到大量的关键时序相位同步，两片TCI6638时序同步信号用来保证数据处理中相位同相。CCU通过背板过来1PPS和TOD信号也可以辅助两片TCI6638的相位同步。
本发明具体应用途径很多，以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以作出若干改进，这些改进也应视为本发明的保护范围。

Claims (1)

  1. 一种LTE基站基带处理板主备信号处理方法，其特征在于包括以下步骤：
    1)正常工作时，LTE基站基带处理板信号处理如下：
    1.1)上行数据：RRU发出的上行数据经光分器后分成两束同时发给主备两块BPU，主用BPU按正常流程处理后，通过BBU的网口发送给核心网，备用BPU按照同步过来的主用BPU的用户和控制面基本配置正常处理，物理层、链路层和网络层处理完后，数据不再通过BBU的S1接口上传给EPC，直到切换成主用后再上传；
    1.2)下行数据：EPC经S1接口下发的下行数据经过BBU的交换网发给主用BPU，BPU正常处理后经CPRI光接口发送给RRU；
    同时主用BPU的DSP芯片通过高速数据同步端口将主用BPU收到的下行数据实时发给备用BPU的DSP芯片，备用BPU处理后经CPRI接口发出，由于光保护板检测到主备BPU的工作状态，将光路切向主用BPU，所以RRU收不到备用BPU发出的CPRI光信号；
    2)主备BPU之间有一组主备状态信号，包括板卡在位、主备状态、心跳信号，档备用BPU检测到主用BPU不在位、切换成备用或心跳超时，LTE基站基带处理板进行如下切换：
    2.1)主备切换：备用BPU立即将自己设成主用，同时将对端BPU设成备用，完成BPU的主备切换，光保护板实时监视主备BPU的状态，发现BPU发生切换后控制光开关迅速切换到新的主用BPU上；
    2.2)主备状态同步：主备状态同步总线包括连接主备BPU的以太网同步总线和基于DSP芯片的高速同步总线，以太网同步总线使用SGMII总线，同步主备BPU的用户和控制面基本配置，BPU内部的DSP芯片通过高速接口和高速同步总线相连，直接传输芯片的底层数据和寄存器状态，将大量的用户数据、控制数据、物理层数据及链路层数据通过高速接口同步到备用BPU上；
    2.3)DSP节拍同步：主备BPU的背板采用DSP节拍同步信号连接，进行DSP节拍同步，并通过背板上的1PPS和TOD信号进行辅助同步计算。
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