WO2018120133A1 - 一种阵列基板及显示面板 - Google Patents

一种阵列基板及显示面板 Download PDF

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Publication number
WO2018120133A1
WO2018120133A1 PCT/CN2016/113763 CN2016113763W WO2018120133A1 WO 2018120133 A1 WO2018120133 A1 WO 2018120133A1 CN 2016113763 W CN2016113763 W CN 2016113763W WO 2018120133 A1 WO2018120133 A1 WO 2018120133A1
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electrode
pixel
pixel sub
disposed
array substrate
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PCT/CN2016/113763
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English (en)
French (fr)
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彭海波
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武汉华星光电技术有限公司
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Priority to US15/328,458 priority Critical patent/US20180336829A1/en
Publication of WO2018120133A1 publication Critical patent/WO2018120133A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the invention relates to a liquid crystal display technology, in particular to an array substrate and a display panel.
  • the panel aperture ratio becomes lower and lower, resulting in lower and lower penetration rates.
  • the cost is increased
  • the power consumption of the display screen is increased, thereby reducing the mobile display device such as mobile phones.
  • Single charge usage time How to improve the transmittance of the panel and reduce the power consumption of the product has become the direction that the industry has been working hard.
  • the present invention provides an array substrate and a display panel to improve the transmittance.
  • the present invention provides an array substrate including a pixel electrode disposed on an array substrate, the pixel electrode including a first pixel sub-electrode and a second pixel sub-electrode distributed up and down, the first pixel sub-electrode including at least two a first main portion that is disposed parallel to each other and obliquely disposed, and is respectively disposed at a first bent portion of each of the first trunk portions away from one end of the second pixel sub-electrode; the second pixel sub-electrode includes at least three parallel and obliquely disposed The second trunk portion is respectively connected to the second bent portion on each end of the second trunk portion away from the first pixel sub-electrode.
  • first trunk portion and the second trunk portion are opposite to each other in an oblique direction.
  • a gap is provided between the first pixel sub-electrode and the second pixel sub-electrode, and an end opposite to the first pixel sub-electrode is connected to each other through a first connection portion, the second main One end of the cador opposite to the first pixel sub-electrode is connected to each other through a second connecting portion, and the first connecting portion is disposed in parallel with the second connecting portion.
  • first pixel sub-electrode provided on the outermost side of the first trunk portion and the second pixel sub-electrode is respectively disposed on the outermost two trunk portions and the second sub-pixel sub-electrode An opposite end of the one pixel sub-electrode is connected, and the first pixel sub-electrode and the second pixel sub-electrode are connected to each other by a third connection portion.
  • the two ends of the third connecting portion are respectively connected to the connection between the two outermost first trunk portions and the second trunk portion and the second main portion of the second pixel sub-electrode One end of the opposite side of the pixel sub-electrode is connected.
  • first pixel sub-electrode is disposed at an upper portion of the pixel electrode
  • second pixel sub-electrode is disposed at a lower portion of the pixel electrode
  • first pixel sub-electrodes of the adjacent two pixel electrodes are disposed at opposite positions.
  • the second pixel sub-electrode is disposed at an upper portion of the pixel electrode, and the first pixel sub-electrode is disposed at a lower portion of the pixel electrode.
  • first pixel sub-electrodes of the adjacent two pixel electrodes are disposed at opposite positions.
  • the present invention also provides a display panel comprising a CF substrate, and further comprising the array substrate, the array substrate being disposed opposite to the CF substrate.
  • the present invention adopts two pixel sub-electrodes arranged one above the other, one of the two pixel sub-electrodes is provided with two trunk portions, and the other is provided with three trunk portions, which are connected or separated, thereby The transmittance of the pixel electrode is improved, and the overall transmittance of the display panel is improved, thereby reducing power consumption.
  • Embodiment 1 is a schematic structural view of Embodiment 1 of the present invention.
  • Embodiment 2 is a schematic structural view of Embodiment 2 of the present invention.
  • Embodiment 3 is a schematic structural view of Embodiment 3 of the present invention.
  • Figure 4 is a schematic illustration of an arrangement of the present invention.
  • An array substrate of the present invention includes a pixel electrode 1 disposed on an array substrate. Since the improvement of the present invention lies in the pixel electrode 1 itself, only the pixel electrode 1 portion will be described in detail below.
  • the pixel electrode 1 is Slit electrode.
  • an array substrate includes a pixel electrode 1 disposed on an array substrate, the pixel electrode including a first pixel sub-electrode 2 and a second pixel sub-electrode distributed up and down 3, wherein the first pixel sub-electrode 2 includes two first trunk portions 21 that are parallel to each other and are disposed obliquely, and first bends respectively disposed at one end of each of the first trunk portions 21 away from the second pixel sub-electrode 3
  • the second pixel sub-electrode 3 includes three second trunk portions 31 that are parallel to each other and are disposed obliquely, and second bent portions respectively connected to one end of each of the second trunk portions 31 away from the first pixel sub-electrode 2 32.
  • the spacing of the three second trunk portions 31 is equal; the first trunk portion 21 is opposite to the oblique direction of the second trunk portion 31; and a gap is provided between the first pixel sub-electrode 2 and the second pixel sub-electrode 3, One end of the first trunk portion 21 opposite to the second pixel sub-electrode 3 is connected to each other by a first connecting portion 23, and one end of the second trunk portion 31 opposite to the first pixel sub-electrode 3 is connected to each other by a second connecting portion 33.
  • the first connecting portion 23 Arranging in parallel with the second connecting portion 33, finally forming a slit electrode, in the first embodiment, the second pixel sub-electrode 3 is disposed in the middle of a second trunk portion 21, the first pixel sub-electrode 2 and the second pixel sub-
  • the outer contour of the electrode 3 is a symmetrically arranged pattern, and the first bent portion 22 and the second bent portion 32 are bent toward the same side, and the right side in the figure is a clip between the bent portion and the trunk portion.
  • the angle is less than 180 degrees.
  • the first pixel sub-electrode 2 in the first embodiment may be disposed in the upper or lower portion of the pixel electrode 1, and correspondingly, the second pixel sub-electrode 3 is disposed in the lower or upper portion of the pixel electrode 1.
  • the transmittance is 4.3%, and the driving voltage is 4.35V.
  • the first pixel sub-electrode 2 (transmittance 4%, driving voltage 4V) or the upper and lower symmetry is disposed symmetrically only in the pixel electrode.
  • a second pixel sub-electrode 3 (transmission rate of 4.5%, driving voltage of 4.8V) has been greatly improved in transmittance, and its driving voltage has also been improved.
  • the array substrate of the second embodiment includes a pixel electrode 1 disposed on the array substrate, the pixel electrode including a first pixel sub-electrode 2 and a second pixel sub-electrode 3 distributed up and down, the first pixel
  • the sub-electrode 2 is disposed at a lower portion of the pixel electrode 1
  • the second sub-electrode 3 is disposed at an upper portion of the pixel electrode 1
  • the first sub-electrode 2 includes two first trunk portions 21 that are parallel to each other and are disposed obliquely.
  • the first bending portion is disposed at each end of each of the first trunk portions 21 away from the second pixel sub-electrode 3
  • the second pixel sub-electrode 3 includes three second trunk portions 31 that are parallel to each other and are disposed obliquely, and second bent portions 32 respectively connected to one end of each of the second trunk portions 31 away from the first pixel sub-electrode 2
  • the spacing of the three second trunk portions 31 is equal; the inclination direction of the first trunk portion 21 and the second trunk portion 31 is opposite; and the two first trunk portions 21 of the first pixel sub-electrode 2 are disposed at the outermost side.
  • One end opposite to the second pixel sub-electrode 3 is respectively connected to one end of the second pixel sub-electrode 3 opposite to the first pixel sub-electrode 2, forming a clockwise 90-degree rotation.
  • the first pixel sub-electrode 2 and the second pixel sub-electrode 3 are connected to each other by a third connecting portion 4, and the first bent portion 22 and the second bent portion 32 are bent toward the same side. In the right side of the figure, the angle between the bent portion and the trunk portion is less than 180 degrees; finally, the slit electrode is formed.
  • the two ends of the third connecting portion 4 are respectively connected to the connection between the two outermost first trunk portions 21 and the second trunk portion 31 and the second trunk portion 31 disposed in the middle of the second pixel sub-electrode 3
  • the upper end opposite to the first pixel sub-electrode 2 is connected.
  • the third embodiment differs from the second embodiment in that the second pixel sub-electrode 3 is disposed at a lower portion of the pixel electrode 1, and the second pixel electrode 2 is disposed at an upper portion of the pixel electrode 1.
  • the present invention also discloses a display panel comprising a CF substrate and an array substrate according to any of the above embodiments.
  • the array substrate is disposed opposite to the CF substrate, and the liquid crystal layer is disposed between the array substrate and the CF substrate.
  • the invention is applicable to display panels of FFS technology.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Geometry (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
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Abstract

一种显示面板，包括CF基板，与CF基板相对设置的阵列基板。其中阵列基板包括设置在阵列基板上的像素电极（1），像素电极（1）包括上下分布的第一像素子电极（2）和第二像素子电极（3），第一像素子电极（2）包括至少两条相互平行并且倾斜设置的第一主干部（21）、分别设于每条第一主干部（21）远离第二像素子电极（3）一端的第一弯折部（22）；第二像素子电极（3）包括至少三条相互平行并且倾斜设置的第二主干部（31）以及分别连接在每条第二主干部（31）远离第一像素子电极（2）一端上的第二弯折部（32）。使像素电极（1）的穿透率得到提升，提高显示面板的整体穿透率，从而降低功耗。

Description

一种阵列基板及显示面板 技术领域
本发明涉及一种液晶显示技术，特别是一种阵列基板及显示面板。
背景技术
随着手机产品解析度的提高，面板开口率越来越低，导致穿透率越来越低。为了使显示屏达到满足正常视觉需求的亮度水准,我们一般需要增加背光的LED颗数，一方面成本提升，另一方面也会使显示屏功耗变大，从而降低如手机类移动显示设备的单次充电使用时间。如何提升面板的穿透率，降低产品的功耗，已成为业者一直在努力的方向。
发明内容
为克服现有技术的不足，本发明提供一种阵列基板及显示面板，从而提高穿透率。
本发明提供了一种阵列基板，包括设置在阵列基板上的像素电极，所述像素电极包括上下分布的第一像素子电极和第二像素子电极，所述第一像素子电极包括至少两条相互平行并且倾斜设置的第一主干部、分别设于每条第一主干部远离第二像素子电极一端的第一弯折部；所述第二像素子电极包括至少三条相互平行并且倾斜设置的第二主干部以及分别连接在每条第二主干部远离第一像素子电极一端上的第二弯折部。
进一步地，所述第一主干部与第二主干部的倾斜方向相反。
进一步地，所述第一像素子电极与第二像素子电极之间设有间隙，所述第一主干部与第二像素子电极相对的一端通过第一连接部相互连接，所述第二主干部与第一像素子电极相对的一端通过第二连接部相互连接，所述第一连接部与第二连接部平行设置。
进一步地，所述第一像素子电极中设于最外侧的两条第一主干部与第二像素子电极相对的一端分别与第二像素子电极中设于最外侧的两条主干部与第 一像素子电极相对的一端连接，所述第一像素子电极与第二像素子电极之间通过第三连接部相互连接。
进一步地，所述第三连接部的两端分别与设于最外侧的两条第一主干部以及第二主干部的连接处以及第二像素子电极中设置中间的第二主干部上与第一像素子电极相对的一端连接。
进一步地，所述第一像素子电极设置在像素电极的上部，第二像素子电极设置在像素电极的下部。
进一步地，相邻两个像素电极中第一像素子电极的设置位置相反。
进一步地，所述第二像素子电极设置在像素电极的上部，第一像素子电极设置在像素电极的下部。
进一步地，相邻两个像素电极中第一像素子电极的设置位置相反。
本发明还提供了一种显示面板，包括CF基板，还包括所述的阵列基板，所述阵列基板与CF基板相对设置。
本发明与现有技术相比，通过上下设置的两个像素子电极，两个像素子电极中其中一个设有两条主干部，另一个设有三条主干部，采用相连或分离的设置，从而使像素电极的穿透率得到提升，提高显示面板的整体穿透率，从而降低功耗。
附图说明
图1是本发明实施例一的结构示意图；
图2是本发明实施例二的结构示意图；
图3是本发明实施例三的结构示意图；
图4是本发明的一种排列方式的示意图。
具体实施方式
下面结合附图和实施例对本发明作进一步详细说明。
本发明的一种阵列基板，包括设置在阵列基板上的像素电极1，由于本发明的改进点在于像素电极1本身，因此以下仅对像素电极1部分进行详细描述，本发明中像素电极1为狭缝电极。
如图1所示，为发明实施例一的结构示意图，一种阵列基板，包括设置在阵列基板上的像素电极1，该像素电极包括上下分布的第一像素子电极2和第二像素子电极3，其中，所述第一像素子电极2包括两条相互平行并且倾斜设置的第一主干部21、分别设于每条第一主干部21远离第二像素子电极3一端的第一弯折部22；所述第二像素子电极3包括三条相互平行并且倾斜设置的第二主干部31以及分别连接在每条第二主干部31远离第一像素子电极2一端上的第二弯折部32，三条第二主干部31的间距相等；所述第一主干部21与第二主干部31的倾斜方向相反；在第一像素子电极2与第二像素子电极3之间设有间隙，第一主干部21与第二像素子电极3相对的一端通过第一连接部23相互连接，所述第二主干部31与第一像素子电极3相对的一端通过第二连接部33相互连接，所述第一连接部23与第二连接部33平行设置，最终构成狭缝电极，本实施例1中将第二像素子电极3设置在中间的一条第二主干部21撇开，第一像素子电极2和第二像素子电极3的外部轮廓为对称设置的图形，所述第一弯折部22与第二弯折部32朝相同的一侧弯折，图中右侧，使得弯折部与主干部之间的夹角小于180度。
实施例一中第一像素子电极2的设置位置可以为像素电极1的上部或下部中，相应地，第二像素子电极3的设置位置为像素电极1的下部或上部中。
实施例一中其穿透率为4.3％，驱动电压为4.35V，其与在像素电极中仅上下对称设置一个第一像素子电极2(穿透率4％、驱动电压4V)或上下对称设置一个第二像素子电极3(穿透率4.5％、驱动电压4.8V)来说穿透率依旧得到了很大幅度的提升，同时其驱动电压也得到了改善。
如图2所示，实施例二的阵列基板，包括设置在阵列基板上的像素电极1，该像素电极包括上下分布的第一像素子电极2和第二像素子电极3，所述第一像素子电极2设于像素电极1的下部，第二像素子电极3设于像素电极1的上部，其中，所述第一像素子电极2包括两条相互平行并且倾斜设置的第一主干部21、分别设于每条第一主干部21远离第二像素子电极3一端的第一弯折部 22；所述第二像素子电极3包括三条相互平行并且倾斜设置的第二主干部31以及分别连接在每条第二主干部31远离第一像素子电极2一端上的第二弯折部32，三条第二主干部31的间距相等；所述第一主干部21与第二主干部31的倾斜方向相反；所述第一像素子电极2中设于最外侧的两条第一主干部21与第二像素子电极3相对的一端分别与第二像素子电极3中设于最外侧的两条主干部31与第一像素子电极2相对的一端连接，形成一个顺时针旋转90度的V字形，所述第一像素子电极2与第二像素子电极3之间通过第三连接部4相互连接，所述第一弯折部22与第二弯折部32朝相同的一侧弯折，图中右侧，使得弯折部与主干部之间的夹角小于180度；最终构成狭缝电极。
具体地，第三连接部4的两端分别与设于最外侧的两条第一主干部21以及第二主干部31的连接处以及第二像素子电极3中设置中间的第二主干部31上与第一像素子电极2相对的一端连接。
如图3所示，实施例三与实施例二的区别在于，第二像素子电极3设置在像素电极1的下部，第二像素电极2设置在像素电极1的上部。
如图4所示，作为本发明的一种排布方式，在实际应用中，在整个像素电极中会有不同穿透率出现,为了避免面板出现亮暗条纹斑,这样就需要采用将相邻两个像素电极中具有两个第二像素子电极3相反设置排布，如图4所示，即若左边的这个像素电极中第二像素子电极3是设置在像素电极的上部(实施例二)，则右边和它相邻的这个像素电极中的第二像素子电极3设置在像素电极1的下部(实施例三)，即在排布中相邻两个像素电极中第二像素子电极3不可落在同一侧上(如全部都设置在上部或全部都设置在下部)。
本发明还公开了一种显示面板，包括CF基板以及上述任意一种实施例的阵列基板，阵列基板与CF基板相对设置，液晶层设置在阵列基板与CF基板之间。
本发明适用于FFS技术的显示面板。
虽然已经参照特定实施例示出并描述了本发明，但是本领域的技术人员将理解：在不脱离由权利要求及其等同物限定的本发明的精神和范围的情况下，可在此进行形式和细节上的各种变化。

Claims (18)

  1. 一种阵列基板，包括设置在阵列基板上的像素电极，其中：所述像素电极包括上下分布的第一像素子电极和第二像素子电极，所述第一像素子电极包括至少两条相互平行并且倾斜设置的第一主干部、分别设于每条第一主干部远离第二像素子电极一端的第一弯折部；所述第二像素子电极包括至少三条相互平行并且倾斜设置的第二主干部以及分别连接在每条第二主干部远离第一像素子电极一端上的第二弯折部。
  2. 根据权利要求1所述的阵列基板，其中：所述第一主干部与第二主干部的倾斜方向相反。
  3. 根据权利要求2所述的阵列基板，其中：所述第一像素子电极与第二像素子电极之间设有间隙，所述第一主干部与第二像素子电极相对的一端通过第一连接部相互连接，所述第二主干部与第一像素子电极相对的一端通过第二连接部相互连接，所述第一连接部与第二连接部平行设置。
  4. 根据权利要求2所述的阵列基板，其中：所述第一像素子电极中设于最外侧的两条第一主干部与第二像素子电极相对的一端分别与第二像素子电极中设于最外侧的两条主干部与第一像素子电极相对的一端连接，所述第一像素子电极与第二像素子电极之间通过第三连接部相互连接。
  5. 根据权利要求4所述的阵列基板，其中：所述第三连接部的两端分别与设于最外侧的两条第一主干部以及第二主干部的连接处以及第二像素子电极中设置中间的第二主干部上与第一像素子电极相对的一端连接。
  6. 根据权利要求3所述的阵列基板，其中：所述第一像素子电极设置在像素电极的上部，第二像素子电极设置在像素电极的下部，或所述第二像素子电极设置在像素电极的上部，第一像素子电极设置在像素电极的下部。
  7. 根据权利要求5所述的阵列基板，其中：所述第一像素子电极设置在像素电极的上部，第二像素子电极设置在像素电极的下部，或所述第二像素子电极设置在像素电极的上部，第一像素子电极设置在像素电极的下部。
  8. 根据权利要求6所述的阵列基板，其中：相邻两个像素电极中第一像 素子电极的设置位置相反。
  9. 根据权利要求7所述的阵列基板，其中：相邻两个像素电极中第一像素子电极的设置位置相反。
  10. 一种显示面板，包括CF基板，其中：还包括阵列基板，所述阵列基板与CF基板相对设置，所述阵列基板包括设置在阵列基板上的像素电极，所述像素电极包括上下分布的第一像素子电极和第二像素子电极，所述第一像素子电极包括至少两条相互平行并且倾斜设置的第一主干部、分别设于每条第一主干部远离第二像素子电极一端的第一弯折部；所述第二像素子电极包括至少三条相互平行并且倾斜设置的第二主干部以及分别连接在每条第二主干部远离第一像素子电极一端上的第二弯折部。
  11. 根据权利要求10所述的阵列基板，其中：所述第一主干部与第二主干部的倾斜方向相反。
  12. 根据权利要求11所述的阵列基板，其中：所述第一像素子电极与第二像素子电极之间设有间隙，所述第一主干部与第二像素子电极相对的一端通过第一连接部相互连接，所述第二主干部与第一像素子电极相对的一端通过第二连接部相互连接，所述第一连接部与第二连接部平行设置。
  13. 根据权利要求11所述的阵列基板，其中：所述第一像素子电极中设于最外侧的两条第一主干部与第二像素子电极相对的一端分别与第二像素子电极中设于最外侧的两条主干部与第一像素子电极相对的一端连接，所述第一像素子电极与第二像素子电极之间通过第三连接部相互连接。
  14. 根据权利要求13所述的阵列基板，其中：所述第三连接部的两端分别与设于最外侧的两条第一主干部以及第二主干部的连接处以及第二像素子电极中设置中间的第二主干部上与第一像素子电极相对的一端连接。
  15. 根据权利要求12所述的阵列基板，其中：所述第一像素子电极设置在像素电极的上部，第二像素子电极设置在像素电极的下部，或所述第二像素子电极设置在像素电极的上部，第一像素子电极设置在像素电极的下部。
  16. 根据权利要求14所述的阵列基板，其中：所述第一像素子电极设置 在像素电极的上部，第二像素子电极设置在像素电极的下部，或所述第二像素子电极设置在像素电极的上部，第一像素子电极设置在像素电极的下部。
  17. 根据权利要求15所述的阵列基板，其中：相邻两个像素电极中第一像素子电极的设置位置相反。
  18. 根据权利要求16所述的阵列基板，其中：相邻两个像素电极中第一像素子电极的设置位置相反。
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