WO2018119654A1 - 薄膜晶体管及具有薄膜晶体管的设备 - Google Patents

薄膜晶体管及具有薄膜晶体管的设备 Download PDF

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WO2018119654A1
WO2018119654A1 PCT/CN2016/112348 CN2016112348W WO2018119654A1 WO 2018119654 A1 WO2018119654 A1 WO 2018119654A1 CN 2016112348 W CN2016112348 W CN 2016112348W WO 2018119654 A1 WO2018119654 A1 WO 2018119654A1
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thin film
auxiliary electrode
film transistor
gate
drain
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PCT/CN2016/112348
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English (en)
French (fr)
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陈小明
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深圳市柔宇科技有限公司
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Priority to PCT/CN2016/112348 priority Critical patent/WO2018119654A1/zh
Priority to CN201680042736.2A priority patent/CN107980177B/zh
Publication of WO2018119654A1 publication Critical patent/WO2018119654A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

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  • the present invention relates to the field of thin film transistor technologies, and in particular, to a high voltage type thin film transistor and a device having the same.
  • High-voltage thin film transistors can be used in printing and scanning equipment, and have potential applications in MEMS and planar X-ray sources.
  • the offset drain structure is a basic high-voltage thin film transistor structure in which a certain offset between the gate and the drain is caused, so that the high voltage on the drain mainly falls on the offset structure, thereby improving the thin film transistor. Breakdown voltage.
  • the offset length has a significant effect on the breakdown voltage of the offset drain structure thin film transistor.
  • the problem with this structure is that the resistance of the semiconductor layer in the offset region is high, which seriously affects its current driving capability.
  • Embodiments of the present invention provide a thin film transistor that can improve current drive without seriously affecting breakdown voltage.
  • a thin film transistor as described in the present application includes a substrate, a gate, at least one auxiliary electrode, an insulating layer, a semiconductor layer, a source and a drain, and the gate and the at least one auxiliary electrode are disposed on the lining
  • the bottom surface is spaced apart, the insulating layer covers the substrate, the gate and the at least one auxiliary electrode, the semiconductor layer is located on the insulating layer, and the orthographic projection covers the gate and the at least one auxiliary electrode,
  • the source and the drain are connected to opposite sides of the semiconductor layer to form a channel region, and the at least one auxiliary electrode is connected to the drain.
  • the size of the spacing between the at least one auxiliary electrode and the gate is negatively correlated with the output current.
  • the auxiliary electrode is one, and a separation distance between the auxiliary electrode and the gate is greater than zero.
  • the auxiliary electrodes are plural and spaced apart from the gate side.
  • the width dimension of the auxiliary electrode adjacent to the gate is positively correlated with the amount of output current.
  • the at least one auxiliary electrode is formed in the same process step as the gate.
  • the at least one auxiliary electrode is connected to the drain through a via.
  • the thin film crystal is provided with a circuit for supplying power to the at least one auxiliary electrode.
  • An apparatus having a thin film transistor as described herein includes the thin film transistor.
  • the thin film transistor described in the present application is provided with an auxiliary electrode in an offset region and is connected to a drain, and the auxiliary electrode induces a free charge in the semiconductor layer, thereby reducing the resistance of the semiconductor in the drain offset region and optimizing the electric field distribution, thereby increasing Current drive capability.
  • FIG. 1 is a schematic structural view of a thin film transistor provided by the present application.
  • FIG. 2 is another schematic structural view of a thin film transistor provided by the present application.
  • FIG. 3 is a current transfer graph of the thin film transistor shown in FIG. 2.
  • FIG. 4 is a graph showing electric field distribution in the source and drain directions of the gate surface of the thin film transistor shown in FIG. 2.
  • the application provides a thin film transistor and an apparatus having the same.
  • the thin film transistor is a high voltage shaped offset drain structure.
  • the device having a thin film transistor includes, but is not limited to, a printing, scanning device, a microelectromechanical system, a planar X-ray source, and the like.
  • the thin film transistor described in the present application includes a substrate 10 , a gate electrode 11 , at least one auxiliary capacitor 12 , an insulating layer 13 , a semiconductor layer 14 , a source 15 , and a drain 16 .
  • the at least one auxiliary electrode 12 is disposed on the surface of the substrate 10, and the insulating layer 13 covers the substrate 10, the gate electrode 11 and the at least one auxiliary electrode 12, and the semiconductor layer 14 is located on the insulating layer 13.
  • the orthographic projection covers the gate 11 and the at least one auxiliary electrode 12, the source A semiconductor region 14 is connected to the drain electrode 16 to form a channel region on opposite sides thereof, and the at least one auxiliary electrode 12 is connected to the drain electrode 16.
  • the thin film transistor of the present application is an offset drain structure under the semiconductor layer 14, and the gate 11 is located at a position where the channel region is biased from the source 15 and between the gate 11 and the drain 16. The distance is longer; the auxiliary electrode 12 is located in the offset region near the drain 16.
  • the gate 11 is in the same layer as the at least one auxiliary electrode 12.
  • the at least one auxiliary electrode is connected to the drain 16 through a via, and the via is disposed at a periphery of the channel region.
  • a circuit (not shown) for supplying power to the auxiliary electrode may be disposed on the thin film crystal.
  • the size of the spacing between the at least one auxiliary electrode 12 and the gate 11 is negatively correlated with the output current.
  • the auxiliary electrode 12 is one, and the distance S between the auxiliary electrode 12 and the gate 11 is greater than zero. That is to say, there is a need for a spacing between the auxiliary electrode 12 and the gate electrode 11.
  • the smaller the spacing S the larger the electric field in the channel region, the larger the current, but the lower the breakdown voltage. The best S value can be determined according to the specific application.
  • the high-voltage thin-film transistor offset region semiconductor layer has a large resistance
  • the high voltage on the drain mainly falls on the offset structure
  • the offset region has a large degree between the gate and the drain, and the semiconductor layer
  • the resistance is high; and the thin film transistor of the present application is provided with the auxiliary electrode 12 in the offset region.
  • the auxiliary electrode 12 induces a free charge in the semiconductor layer 14, thereby reducing the resistance of the semiconductor in the offset region of the drain 16.
  • the current driving capability of the thin film transistor is improved.
  • the auxiliary electrodes are plural and spaced apart from the gate 11 side.
  • the auxiliary electrode includes a first auxiliary electrode 121, a second auxiliary electrode 122, and a third auxiliary electrode 123.
  • the provision of a plurality of auxiliary electrodes in the offset region facilitates the high output current and breakdown voltage of the thin film transistor.
  • the width dimension of the auxiliary electrode 121 adjacent to the gate electrode 11 is positively correlated with the amount of output current.
  • the first auxiliary electrode 121, the second auxiliary electrode 122, and the third auxiliary electrode 123 are spaced apart and have a pitch S1, S2.
  • the vertical spacing between the third auxiliary electrode 123 and the drain is S3, and the first is close to the gate 11.
  • the smaller the distance between the auxiliary electrode 121 and the gate 11, the larger the current; and the first auxiliary power The opposing area between the pole 121 and the gate 11 is small, so the parasitic capacitance is very small.
  • FIG. 3 and FIG. 4 are current transfer curves and electric field distribution curves of the gate surface in the source and drain directions in the case of the above plurality of auxiliary electrodes, wherein the novel structure 1-5 described in the figure is Different embodiments of the invention and embodiments which are simply modified according to the invention, such as a change in the number of auxiliary electrodes.
  • the drain current ID of the thin film transistor using the offset drain structure of the present application is two orders of magnitude smaller than the ID of the thin film transistor of the conventional structure; as can be seen from FIG. 4, the thin film transistor with the drain structure is shifted.
  • the highest electric field (located near the right edge of the gate determines the breakdown voltage of the high voltage thin film transistor) is nearly an order of magnitude smaller than that of a conventional thin film transistor structured thin film transistor.
  • the introduction of the auxiliary electrode greatly increases the I D of the high voltage thin film transistor, and the corresponding maximum electric field does not change significantly, which indicates that the breakdown voltage and offset leakage of the thin film transistor of the present application
  • the ultra-structured high-voltage thin film transistor is almost uniform, and the current driving capability is greatly increased, thus ensuring the current driving capability of the thin film transistor and maintaining a high breakdown voltage.
  • the at least one auxiliary electrode 12 and the gate 11 are formed in the same process step. Since the auxiliary electrode 12 is prepared simultaneously with the gate electrode 11, the signal line and the preparation steps of the thin film transistor are not increased.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种薄膜晶体管，包括衬底(10)、栅极(11)、至少一个辅助电极(12)、绝缘层(13)、半导体层(14)、源极(15)及漏极(16)，所述栅极(11)和所述至少一个辅助电极(12)设于所述衬底(10)表面间隔设置，所述绝缘层(13)覆盖所述衬底(10)、栅极(11)及至少一个辅助电极(12)，所述半导体层(14)位于所述绝缘层(13)上，且正投影覆盖所述栅极(11)和所述至少一个辅助电极(12)，所述源极(15)与漏极(16)连接所述半导体层(14)相对两侧形成沟道区域，并且所述至少一个辅助电极(12)与所述漏极(16)连接。同时提供一种具有所述薄膜晶体管的设备。

Description

薄膜晶体管及具有薄膜晶体管的设备 技术领域
本发明涉及薄膜晶体管技术领域，尤其涉及一种高压型的薄膜晶体管及具有薄膜晶体管的设备。
背景技术
高压型薄膜晶体管可应用于打印、扫描设备中，并在微机电系统、平面型X射线源中有应用前景。偏移漏极结构是一种基本的高压薄膜晶体管结构，其中，栅极和漏极之间有一定偏移量，使得漏极上的高电压主要落在偏移结构上，从而提高薄膜晶体管的击穿电压。偏移长度对偏移漏极结构薄膜晶体管的击穿电压有显著影响。但是该结构的问题在于，偏移区的半导体层的电阻很高，严重影响其电流驱动能力。
发明内容
本发明实施例提供一薄膜晶体管，可以在不严重影响击穿电压同时提高电流驱动。
本申请所述的一种薄膜晶体管，包括衬底、栅极、至少一个辅助电极、绝缘层、半导体层、源极及漏极，所述栅极和所述至少一个辅助电极设于所述衬底表面间隔设置，所述绝缘层覆盖所述衬底、栅极及至少一个辅助电极，所述半导体层位于所述绝缘层上，且正投影覆盖所述栅极和所述至少一个辅助电极，所述源极与漏极连接所述半导体层相对两侧形成沟道区域，并且所述至少一个辅助电极与所述漏极连接。
其中，所述至少一个辅助电极与所述栅极之间的间距的尺寸与输出电流负相关。
其中，所述辅助电极为一个，并且所述辅助电极与所述栅极之间的间隔距离大于零。
其中，所述辅助电极为多个且间隔设置与所述栅极一侧。
其中，与所述栅极相邻的辅助电极的宽度尺寸与输出电流量正相关。
其中，所述至少一个辅助电极与所述栅极为同一工艺步骤形成。
其中，所述至少一个辅助电极与所述漏极通过过孔连接。
其中，所述薄膜晶体上设有为所述至少一个辅助电极供电的电路。
本申请所述的具有薄膜晶体管的设备，包括所述的薄膜晶体管。
本申请所述的薄膜晶体管在偏移区域设置辅助电极并与漏极连接，辅助电极在半导体层中诱导出自由电荷，从而降低漏极偏移区的半导体的电阻并优化电场分布，进而增加了电流驱动能力。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请提供的薄膜晶体管的一种结构示意图。
图2是本申请提供的薄膜晶体管的另一种结构示意图。
图3是图2所示的薄膜晶体管的电流转移曲线图。
图4是图2所示的薄膜晶体管的栅极表面在源漏极方向上的电场分布曲线图。
具体实施方式
下面将结合本发明实施方式中的附图，对本发明实施方式中的技术方案进行清楚、完整地描述。
本申请提供一种薄膜晶体管及具有薄膜晶体管的设备。所述薄膜晶体管为高压形的偏移漏极结构。所述具有薄膜晶体管的设备包括但不限于打印、扫描设备、微机电系统、平面型X射线源等。
请参阅图1，本申请所述的薄膜晶体管包括衬底10、栅极11、至少一个辅助电12、绝缘层13、半导体层14、源极15及漏极16，所述栅极11和所述至少一个辅助电极12设于所述衬底10表面间隔设置，所述绝缘层13覆盖所述衬底10、栅极11及至少一个辅助电极12，所述半导体层14位于所述绝缘层13上，且正投影覆盖所述栅极11和所述至少一个辅助电极12，所述源极 15与漏极16连接所述半导体层14相对两侧形成沟道区域，并且所述至少一个辅助电极12与所述漏极16连接。
具体的，本申请的薄膜晶体管为偏移漏极结构，位于半导体层14下方，所述栅极11位于沟道区域偏于所述源极15所处位置，栅极11到漏极16之间的距离较长；辅助电极12位于所述偏移区域内靠近漏极16。栅极11与至少一个辅助电极12位于同一层。所述至少一个辅助电极与所述漏极16通过过孔连接，所述过孔设于所述沟道区域外围。根据设计需要，所述薄膜晶体上可以设有为所述辅助电极供电的电路(图未示)。
进一步的，所述至少一个辅助电极12与所述栅极11之间的间距的尺寸与输出电流负相关。本实施例中，所述辅助电极12为一个，并且所述辅助电极12与所述栅极11之间的间隔S距离大于零。也就说，所述辅助电极12与所述栅极11之间需要有间距，在通电后，该间距S越小，沟道区域电场越大，电流也就增大，但击穿电压减小，可根据具体的应用确定最佳的S值。
现有技术中的高压型薄膜晶体管偏移区半导体层的电阻很大，漏极上的高电压主要落在偏移结构上，偏移区栅极与漏极之间程度较大，半导体层的电阻很高；而本申请的薄膜晶体管在偏移区设置了辅助电极12，在正常工作时，辅助电极12在半导体层14中诱导出自由电荷，从而降低漏极16偏移区的半导体的电阻并优化电场分布，进而增加了电流，那么薄膜晶体管的电流驱动能力得到提升。同时，由于辅助电极12与漏极16相连，因此两者之间并没有寄生电容。
请参阅图2，另一实施方式中，所述辅助电极为多个且间隔设置与所述栅极11一侧。具体为，所述辅助电极包括第一辅助电极121、第二辅助电极122及第三辅助电极123。偏移区内设置多个辅助电极有利于提薄膜晶体管的高输出电流和击穿电压。
进一步的，与所述栅极11相邻的辅助电极121的宽度尺寸与输出电流量正相关。本实施例中，靠近栅极11的第一辅助电极121的宽度越大，输出电流越大。
第一辅助电极121、第二辅助电极122及第三辅助电极123间隔设置且具有间距S1、S2，所述第三辅助电极123与漏极之间的垂直间距为S3，靠近栅极11的第一辅助电极121与栅极11的距离越小，电流越大；而且第一辅助电 极121与栅极11之间相对的面积较小，故寄生电容非常小。
请参阅图3与图4，为上述多个辅助电极情况下电流转移曲线图及栅极表面在源漏极方向上的电场分布曲线图，其中，图中所述的新型结构1-5是本发明所述的不同实施例以及根据本发明简单改变的实施方式，比如辅助电极的个数的改变。从图3可见，采用了本申请偏移漏极结构的薄膜晶体管的漏极电流ID比普通结构的薄膜晶体管的ID小了两个数量级以上；从图4可见，偏移漏极结构的薄膜晶体管的最高电场(位于栅极右侧边沿附近，决定高压薄膜晶体管的击穿电压)比普通薄膜晶体管结构薄膜晶体管小将近一个数量级。从图3、4可看出，辅助电极的引入，使高压薄膜晶体管的ID大大增加，而相应的最高电场却没有明显改变，这说明，本申请的薄膜晶体管的击穿电压与偏移漏极结构高压薄膜晶体管几乎一致，而电流驱动能力确大大增加，如此保证了薄膜晶体管的电流驱动能力，并维持较高的击穿电压。
进一步的，所述至少一个辅助电极12与所述栅极11为同一工艺步骤形成。由于辅助电极12与栅极11同时制备，因此，薄膜晶体管的信号线及制备步骤没有增加。
以上所述是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本发明的保护范围。

Claims (9)

  1. 一种薄膜晶体管，其特征在于，包括衬底、栅极、至少一个辅助电极、绝缘层、半导体层、源极及漏极，所述栅极和所述至少一个辅助电极设于所述衬底表面间隔设置，所述绝缘层覆盖所述衬底、栅极及至少一个辅助电极，所述半导体层位于所述绝缘层上，且正投影覆盖所述栅极和所述至少一个辅助电极，所述源极与漏极连接所述半导体层相对两侧形成沟道区域，并且所述至少一个辅助电极与所述漏极连接。
  2. 如权利要求1所述的薄膜晶体管，其特征在于，所述至少一个辅助电极与所述栅极之间的间距的尺寸与输出电流负相关。
  3. 如权利要求2所述的薄膜晶体管，其特征在于，所述辅助电极为一个，并且所述辅助电极与所述栅极之间的间隔距离大于零。
  4. 如权利要求2所述的薄膜晶体管，其特征在于，所述辅助电极为多个且间隔设置于所述栅极一侧。
  5. 如权利要求2所述的薄膜晶体管，其特征在于，与所述栅极相邻的辅助电极的宽度尺寸与输出电流量正相关正相关。
  6. 如权利要求1所述的薄膜晶体管，其特征在于，所述至少一个辅助电极与所述栅极为同一工艺步骤形成。
  7. 如权利要求1所述的薄膜晶体管，其特征在于，所述至少一个辅助电极与所述漏极通过过孔连接。
  8. 如权利要求7所述的薄膜晶体管，其特征在于，所述薄膜晶体上设有为所述至少一个辅助电极供电的电路。
  9. 一种具有薄膜晶体管的设备，其特征在于，该设备包括权利要求1-8任一项所述的薄膜晶体管。
PCT/CN2016/112348 2016-12-27 2016-12-27 薄膜晶体管及具有薄膜晶体管的设备 WO2018119654A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5952677A (en) * 1997-12-27 1999-09-14 Lg Semicon Co., Ltd. Thin film transistor and method for manufacturing the same
CN1242608A (zh) * 1998-06-16 2000-01-26 日本电气株式会社 场效应晶体管
US20100276686A1 (en) * 2009-04-29 2010-11-04 Samsung Electronics Co., Ltd. Thin film transistor substrate and method of fabricating the same
CN102280489A (zh) * 2010-06-08 2011-12-14 三星移动显示器株式会社 具有偏移结构的薄膜晶体管
CN103681673A (zh) * 2012-09-14 2014-03-26 瑞萨电子株式会社 半导体器件和半导体器件制造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5952677A (en) * 1997-12-27 1999-09-14 Lg Semicon Co., Ltd. Thin film transistor and method for manufacturing the same
CN1242608A (zh) * 1998-06-16 2000-01-26 日本电气株式会社 场效应晶体管
US20100276686A1 (en) * 2009-04-29 2010-11-04 Samsung Electronics Co., Ltd. Thin film transistor substrate and method of fabricating the same
CN102280489A (zh) * 2010-06-08 2011-12-14 三星移动显示器株式会社 具有偏移结构的薄膜晶体管
CN103681673A (zh) * 2012-09-14 2014-03-26 瑞萨电子株式会社 半导体器件和半导体器件制造方法

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