WO2018113132A1 - 一种半导体器件及其制造方法 - Google Patents

一种半导体器件及其制造方法 Download PDF

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Publication number
WO2018113132A1
WO2018113132A1 PCT/CN2017/078829 CN2017078829W WO2018113132A1 WO 2018113132 A1 WO2018113132 A1 WO 2018113132A1 CN 2017078829 W CN2017078829 W CN 2017078829W WO 2018113132 A1 WO2018113132 A1 WO 2018113132A1
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Prior art keywords
end structure
cavity
semiconductor device
forming
active end
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PCT/CN2017/078829
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English (en)
French (fr)
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梁凯智
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上海新微技术研发中心有限公司
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Publication of WO2018113132A1 publication Critical patent/WO2018113132A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4817—Conductive parts for containers, e.g. caps

Definitions

  • the present application relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor device and a method of fabricating the same.
  • Miniaturized mechanical sensors developed by semiconductor manufacturing processes such as accelerometers, gyroscopes, oscillators, silicon wheat, pressure gauges, etc., when subjected to external physical disturbances, such as vibration, drop, impact, etc., microstructure Movement of the body in a three-dimensional space will result in deformation of the structure, and sometimes the surfaces of the structures will contact each other.
  • the surface will be peeled off due to wear, and the particles that are peeled off will cause interference in the future operating environment and electrical environment, and even cause temporary or permanent failure of the device, thereby affecting the product. Quality and longevity.
  • the structural rigidity design is made tougher as much as possible to reduce the collision to the surface of another structure, but the sensitivity of the sensor is lost.
  • the choice of material for the contact surface the choice of strong hardness and non-brittle materials is another way.
  • the interface modification method is adopted, and the two surfaces are touched, and a layer of organic material with hydrophobicity and low surface energy is applied to greatly reduce the surface energy during the collision process.
  • the resulting covalent bond which sticks together.
  • the contact surface area of the collision between the two is reduced, and the small bump design is adopted to greatly reduce the contact area of the collision, and the contact area range of the covalent bond can be greatly reduced.
  • the spring restoring force of the structure is greater than the bonding force of the surface energy, and the situation of sticking failure can be avoided, but it will directly affect the sensitivity of the sensor and the design of the dynamic range.
  • the present application provides a semiconductor device having a cavity surrounded by a conductive material, the cavity capable of buffering a force when the active end structure and the passive end structure are in contact with each other, and
  • the conductive material can guide the static electricity generated by the contact to avoid the electrostatic effect, thereby avoiding the stickiness and the production caused by the impact and impact. Product failure.
  • a semiconductor device having an active end structure and a passive end structure, wherein the active end structure and the passive end structure are capable of relative movement and contact with each other, characterized in that ,
  • At least one of the active end structure and the passive end structure has a cavity
  • the cavity is formed as an accommodation space
  • the cavity is surrounded by a bottom portion and an outer wall, the outer wall protruding toward the relative movement direction relative to the bottom portion,
  • the outer wall and the bottom are both electrically conductive materials.
  • a portion of the active end structure and the passive end structure that is in contact due to the relative movement is located on an outer surface of the outer wall.
  • the conductive material is a metal material.
  • the cavity is a sealed cavity or is in communication with the outside.
  • the accommodating space is vacuum or filled with a medium.
  • the medium is a gas and/or a polymeric material.
  • the direction of the relative motion is parallel or perpendicular to the surface of the substrate of the semiconductor device.
  • a method of fabricating a semiconductor device having an active end structure and a passive end structure, the active end structure and the passive end structure being relatively movable and Contact with each other characterized in that
  • the manufacturing method includes:
  • the cavity is formed in at least one of the active end structure and the passive end structure, and the cavity is formed as an accommodation space.
  • the cavity is surrounded by a bottom portion and an outer wall, the outer wall protruding toward the relative movement direction relative to the bottom portion,
  • the outer wall and the bottom are both electrically conductive materials.
  • a portion of the active end structure and the passive end structure that is in contact due to the relative movement is located on an outer surface of the outer wall.
  • the cavity is formed
  • the step of forming the cavity includes: (corresponding to relative motion in a vertical direction)
  • the step of forming the cavity includes: (corresponding to relative motion in the horizontal direction)
  • a hole is formed in a region of the conductive material corresponding to the active end structure and/or the passive end structure, the inside of the hole serving as the cavity.
  • the step of forming the cavity further includes:
  • An insulating dielectric layer is covered at the opening of the hole.
  • the utility model has the beneficial effects that the force when the active end structure body and the passive end structure body are in contact with each other can be buffered, and the static electricity generated by the contact can be guided away to avoid the electrostatic effect, thereby avoiding contact and impact.
  • FIG. 1 is a schematic view of a semiconductor device of the present embodiment
  • FIG 2 is another schematic view of the semiconductor device of the present embodiment
  • FIG 3 is still another schematic view of the semiconductor device of the present embodiment.
  • FIG. 4 is a schematic view showing a method of forming a cavity in a passive end structure according to the embodiment
  • Fig. 5 is a schematic view showing a method of forming a semiconductor device of the present embodiment.
  • the substrate of the semiconductor device may be a wafer commonly used in the field of semiconductor fabrication, such as a silicon wafer, a silicon-on-insulator (SOI) wafer, a silicon germanium wafer, or a germanium wafer. a glass wafer (Quartz) or a gallium nitride (GaN) wafer, etc.; and the wafer may be a wafer that has not been subjected to a semiconductor process, or a wafer that has been processed, for example Wafers processed by processes such as ion implantation, etching, and/or diffusion are not limited in this application or on a flexible flexible substrate, processing methods performed by semiconductor-related processing equipment, and the like.
  • a wafer commonly used in the field of semiconductor fabrication such as a silicon wafer, a silicon-on-insulator (SOI) wafer, a silicon germanium wafer, or a germanium wafer. a glass wafer (Quartz) or a gallium nitride (GaN)
  • the active end structure and/or the passive end structure may be moved in the vertical direction (Z) and/or the horizontal direction (X-Y).
  • Embodiment 1 of the present application provides a semiconductor device
  • FIG. 1 is a schematic view of the semiconductor device of the present embodiment.
  • the semiconductor device may have an active end structure and a passive end structure, and the active end structure and the passive end structure can be moved relative to each other touch.
  • At least one of the active end structure and the passive end structure has a cavity 1 formed in the cavity as an accommodation space, and the cavity may be enclosed by the bottom and the outer wall.
  • the outer wall and the bottom are both electrically conductive materials, wherein the outer wall is the upper conductive layer in the figure, and the bottom is the lower conductive layer in the figure. Wherein, the outer wall protrudes in a direction of relative movement with respect to the bottom, and a portion of the active end structure and the passive end structure that is in contact due to the relative movement is located on an outer surface of the outer wall.
  • the cavity can buffer the force when the active end structure and the passive end structure are in contact with each other, and the conductive material can guide the static electricity generated by the contact to avoid the electrostatic effect, thereby avoiding the collision. Stickiness and product failure caused by impact.
  • the conductive material may be a metal material.
  • the cavity may be a sealed cavity or in communication with the outside.
  • the accommodating space may be vacuum or filled with a medium, wherein the filled medium may be a gas and/or a polymer material, and the polymer material is as described in FIG. 1 .
  • the direction of relative motion is indicated by an arrow, which may be perpendicular to the surface of the substrate of the semiconductor device.
  • the embodiment is not limited thereto, and the direction of relative motion may be parallel to the surface of the substrate of the semiconductor device.
  • FIG. 2 is another schematic view of the semiconductor device of the present embodiment
  • FIG. 3 is still another schematic view of the semiconductor device of the present embodiment.
  • the direction of the relative movement (the direction of the arrow) is parallel to the surface of the substrate of the semiconductor device.
  • the conductors of the passive end structure constitute the outer wall and the bottom of the cavity 1, and the cavity may be filled with a polymer material.
  • the active end structure may also have an electrical conductor; the surface of the substrate may Set whether or not to have conductive media.
  • the opening of the cavity 1 may be covered with or without the conductive medium 2.
  • the active end structure and the passive end structure may be formed first, and then the cavity is formed on the active end structure and/or the passive end structure.
  • the step of forming a cavity may include:
  • Step 101 forming a patterned first conductive material layer on the surface of the active end structure and/or the passive end structure as the bottom portion;
  • Step 102 forming a dielectric layer on a surface of the bottom.
  • Step 103 Form a patterned second conductive material layer on the surface of the dielectric layer as the outer wall, wherein the outer wall and the bottom are enclosed to form the cavity.
  • FIG. 4 is a schematic view showing a method of forming a cavity in a passive end structure according to the present embodiment.
  • the materials represented by the respective patterns in FIG. 4 are the same as those in FIG.
  • the method includes:
  • a patterned lower conductive layer on the substrate above the substrate, a prior art process such as a CMOS front transistor and a rear metal pull wire may be provided; in this step, evaporation or sputtering may be performed.
  • the lower conductive layer is laid and patterned, and the lower conductive layer may be a metal material such as titanium nitride (TiN) or silicon carbide (SiC) or titanium nitride (TiN) and aluminum-copper alloy (AlCu).
  • the thickness can be in the range of 50 to 1000 angstroms.
  • a dielectric layer is formed, which may be, for example, a polymer layer.
  • polymer coating can be carried out by coating or gasification, such as a light-sensitive polymer material, which can be a high viscosity coefficient photoresist, etc., which is generally coated, exposed, developed, and UV-cured.
  • a series of process steps, such as baking, define a polymer pattern whose area size can vary from 1 micron square to 10,000 micron square.
  • the hole is defined by conventional semiconductor lithography and etching to facilitate the next step of releasing the polymer material.
  • the polymer material is released by plasma etching to form a film body cavity.
  • the active end structure may be formed by a series of surface micromachining or decent micromachining, and the active end structure may include at least one or more movable structures, springs, and fixed end points.
  • the semiconductor device can also be fabricated in other ways.
  • a cavity may be formed in a region corresponding to the active end structure and the passive end structure, and then an active end structure and a passive end structure are formed, wherein The step of the cavity may include forming a hole in a region of the conductive material corresponding to the active end structure and/or the passive end structure, the inside of the hole serving as the cavity.
  • FIG. 5 is a schematic view of a method of forming a semiconductor device of the present embodiment, corresponding to FIG. 3, and the materials represented by the respective patterns in FIG. 5 are the same as those of FIG. As shown in FIG. 5, the method includes:
  • the thickness of the main structure is defined, and the thickness thereof may be from 1 micrometer to 100 micrometers, which is modulated in thickness according to the application of the microsensor device.
  • the thickness of the main structure can be pre-determined by processes such as surface micromachining or bulk micromachining.
  • One or more holes are defined by photolithography etching and are designed to be near the edge of the collision of the rear side wall structure, about 2 microns to 10 microns.
  • the holes which fall in diameter from 5 microns to 100 microns, are not etched to the bottom.
  • the non-conductive medium may be a composite material of silicon oxide and silicon nitride or silicon nitride, and the thickness thereof is about 500-3000 angstroms, according to The final step is adjusted by the etch selection ratio when the sensor assembly is released.
  • steps (3)-(6) may be optional steps.

Abstract

一种半导体器件及其制造方法，该半导体器件具有由导电材料围合而成的腔体（1），该腔体能够缓冲主动端结构体和被动端结构体彼此接触时的作用力，并且，该导电材料能够将接触产生的静电导走，避免静电效应产生，由此，避免碰触与撞击所导致的粘黏和产品失效问题。

Description

一种半导体器件及其制造方法 技术领域
本申请涉及半导体制造技术领域，尤其涉及一种半导体器件及其制造方法。
背景技术
采用半导体制造工艺所开发制造的微型化机械式传感器，例如加速度计、陀螺仪、震荡器、硅麦、压力计等，在受到外在物理量扰动时，例如受到振动、跌落、冲击等，微结构体在立体空间中运动，将产生结构体的形变，有时结构体的表面会彼此接触。
其中，存在两者或两者以上的微结构体之间碰撞而接触到彼此表面时，其中一者称主动端结构体，另一者称被动端结构体。因为在微观尺度内，除了存在着接触时间内所产生的摩擦作用力之外，彼此间还存在着相互吸引的范德华力(van der Waals'force)。
对于摩擦作用力而言，将潜在因磨耗而产生表面剥离，而剥离下来的粒子，将造成日后操作环境与电性上的干扰源，甚至造成器件短暂性或永久性的失效，进而影响产品的质量与寿命。为改善磨耗情境，除了透过结构体的设计，尽可能将结构刚性设计更具强韧，以减少碰撞到另一结构体的表面，但失去的却是传感器的灵敏度。除此之外，接触面的材质选择，选择强硬度与非脆性材料亦是另一种方式。
对于范德华力而言，由于在微观尺度下，是不可避免的作用力，当碰触时间长久时，因表面能的提升，而产生微焊接行为，使得两者 结构体之间形成永久键结，即为粘黏的背后主因，导致最终器件永久失效。
一般做法，多采取界面改质方式，将两者存在碰触的表面上，涂布上一层疏水性及低表面能的有机材质，以大幅降低表面能在两者碰撞过程时，长时间接触下而产生的共价键结，而黏附一起。除此之外，减少两者碰撞的接触表面积，采小凸块设计，以大幅降低碰撞的接触面积，亦可大幅降低共价键结的接触面积范围。与此同时，结构体的弹簧回复力大于表面能的键结力，亦可避免粘黏失效的情境，但直接将影响到传感器灵敏度与动态范围设计之限度。摩擦力与表面能的存在是不可避免的基本物理能量，除了透过结构体的设计、接触面材质的选择与表面改质等方式。另外，透过软弹簧的设计概念于被动端结构体之上及碰触机率高的地方处，设计一组或一组以上的弹簧结构，作为缓冲与吸收能量之用途等。
应该注意，上面对技术背景的介绍只是为了方便对本申请的技术方案进行清楚、完整的说明，并方便本领域技术人员的理解而阐述的。不能仅仅因为这些方案在本申请的背景技术部分进行了阐述而认为上述技术方案为本领域技术人员所公知。
发明内容
在现有技术中，尽管采用了多种方法，仍然难以避免机械结构体因长时间碰触与撞击所导致的粘黏，进而导致产品永久失效问题。
本申请提供一种半导体器件及其制造方法，该半导体器件具有由导电材料围合而成的腔体，该腔体能够缓冲主动端结构体和被动端结构体彼此接触时的作用力，并且，该导电材料能够将接触产生的静电导走，避免静电效应产生，由此，避免碰触与撞击所导致的粘黏和产 品失效问题。
根据本申请实施例的一个方面，提供一种半导体器件，其具有主动端结构体和被动端结构体，所述主动端结构体和所述被动端结构体能够相对运动并彼此接触，其特征在于，
所述主动端结构体和所述被动端结构体的至少一者具有腔体，
所述腔体内形成为容置空间，
所述腔体由底部和外壁围合而成，所述外壁相对于所述底部而向所述相对运动的方向突起，
所述外壁和所述底部均为导电材料，
所述主动端结构体和所述被动端结构体由于所述相对运动而接触的部分位于所述外壁的外表面。
根据本申请实施例的一个方面，其中，
所述导电材料为金属材料。
根据本申请实施例的一个方面，其中，
所述腔体为密封腔体或与外部连通。
根据本申请实施例的一个方面，其中，
所述容置空间内为真空或填充有介质。
根据本申请实施例的一个方面，其中，
所述介质为气体和/或高分子材料。
根据本申请实施例的一个方面，其中，
所述相对运动的方向平行或垂直于所述半导体器件的基底表面。
根据本申请实施例的一个方面，提供一种半导体器件的制造方法，所述半导体器件具有主动端结构体和被动端结构体，所述主动端结构体和所述被动端结构体能够相对运动并彼此接触，其特征在于，
该制造方法包括：
形成主动端结构体和被动端结构体；以及
形成腔体，
其中，所述腔体形成于所述主动端结构体和所述被动端结构体的至少一者，所述腔体内形成为容置空间，
所述腔体由底部和外壁围合而成，所述外壁相对于所述底部而向所述相对运动的方向突起，
所述外壁和所述底部均为导电材料，
所述主动端结构体和所述被动端结构体由于所述相对运动而接触的部分位于所述外壁的外表面。
根据本申请实施例的一个方面，其中，
在形成主动端结构体和被动端结构体之后，形成所述腔体，
并且，形成所述腔体的步骤包括：(对应于垂直方向的相对运动)
在所述主动端结构体和/或所述被动端结构体的表面形成图形化的第一导电材料层，以作为所述底部；
在所述底部的表面形成介质层；以及
在所述介质层表面形成图形化的第二导电材料层，以作为所述外壁；
其中，所述外壁和所述底部围合以形成所述腔体。
根据本申请实施例的一个方面，其中，
在形成主动端结构体和被动端结构体之前，形成所述腔体，
并且，形成所述腔体的步骤包括：(对应于水平方向的相对运动)
在与所述主动端结构体和/或所述被动端结构体对应的导电材料的区域中形成孔洞，所述孔洞内部作为所述腔体。
根据本申请实施例的一个方面，其中，
形成所述腔体的步骤还包括：
在所述孔洞中填充介质材料；以及
在所述孔洞的开口处覆盖绝缘介质层。
本申请的有益效果在于：能够缓冲主动端结构体和被动端结构体彼此接触时的作用力，并且，能够将接触产生的静电导走，避免静电效应产生，由此，避免碰触与撞击所导致的粘黏和产品失效问题。
参照后文的说明和附图，详细公开了本申请的特定实施方式，指明了本申请的原理可以被采用的方式。应该理解，本申请的实施方式在范围上并不因而受到限制。在所附权利要求的精神和条款的范围内，本申请的实施方式包括许多改变、修改和等同。
针对一种实施方式描述和/或示出的特征可以以相同或类似的方式在一个或更多个其它实施方式中使用，与其它实施方式中的特征相组合，或替代其它实施方式中的特征。
应该强调，术语“包括/包含”在本文使用时指特征、整件、步骤或组件的存在，但并不排除一个或更多个其它特征、整件、步骤或组件的存在或附加。
附图说明
所包括的附图用来提供对本申请实施例的进一步的理解，其构成了说明书的一部分，用于例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是本实施例的半导体器件的一个示意图；
图2是本实施例的半导体器件的另一个示意图；
图3是本实施例的半导体器件的又一个示意图
图4是本实施例的在被动端结构体形成腔体的方法一个示意图；
图5是本实施例的形成半导体器件的方法的一个示意图。
具体实施方式
参照附图，通过下面的说明书，本申请的前述以及其它特征将变得明显。在说明书和附图中，具体公开了本申请的特定实施方式，其表明了其中可以采用本申请的原则的部分实施方式，应了解的是，本申请不限于所描述的实施方式，相反，本申请包括落入所附权利要求的范围内的全部修改、变型以及等同物。
在本申请中，半导体器件的基片可以是半导体制造领域中常用的晶圆，例如硅晶圆、绝缘体上的硅(Silicon-On-Insulator，SOI)晶圆、锗硅晶圆、锗晶圆、玻璃晶圆(Quartz)或氮化镓(Gallium Nitride，GaN)晶圆等；并且，该晶圆可以是没有进行过半导体工艺处理的晶圆，也可以是已经进行过处理的晶圆，例如进行过离子注入、蚀刻和/或扩散等工艺处理过的晶圆，本申请对此并不限制或是在软性可挠性基材上，采半导体相关制程设备所进行的加工方式等等。
在本申请中，主动端结构体和/或被动端结构体可以在垂直方向(Z)和/或水平方向(X-Y)运动。
实施例1
本申请实施例1提供一种半导体器件，图1是本实施例的半导体器件的一个示意图。
如图1所示，该半导体器件可以具有主动端结构体和被动端结构体，所述主动端结构体和所述被动端结构体能够相对运动并彼此接 触。
在本实施例中，如图1所示，主动端结构体和所述被动端结构体的至少一者具有腔体1，腔体内形成为容置空间，该腔体可以由底部和外壁围合而成，外壁和底部均为导电材料，其中，所述外壁为图中的上导电层，所述底部为图中的下导电层。其中，外壁相对于底部而向相对运动的方向突起，主动端结构体和被动端结构体由于所述相对运动而接触的部分位于所述外壁的外表面。
根据本实施例，该腔体能够缓冲主动端结构体和被动端结构体彼此接触时的作用力，并且，该导电材料能够将接触产生的静电导走，避免静电效应产生，由此，避免碰触与撞击所导致的粘黏和产品失效问题。
在本实施例中，所述导电材料可以为金属材料。
在本实施例中，腔体可以为密封腔体或与外部连通。
在本实施例中，容置空间内可以是真空或填充有介质，其中，填充的该介质可以为气体和/或高分子材料，所述高分子材料如图1所述。
在本实施例中，如图1所示，相对运动的方向为箭头所示，该方向可以垂直于半导体器件的衬底表面。
但是，本实施例并不限于此，相对运动的方向也可以平行于半导体器件的基底表面。
图2是本实施例的半导体器件的另一个示意图，图3是本实施例的半导体器件的又一个示意图。如图2和图3所示，相对运动的方向(箭头方向)平行于半导体器件的衬底表面。在图2和图3中，被动端结构体的导电体构成腔体1的外壁和底部，并且腔体中可以填充有高分子材料。此外，主动端结构体也可以具有导电体；衬底表面可以 设置有无导电介质。此外，在图3中，腔体1的开口处可以覆盖有无导电介质2。
下面，对本实施例的半导体器件的制造方法进行说明。
在本实施例中，可以先形成主动端结构体和被动端结构体，然后将腔体形成于主动端结构体和/或被动端结构体。
例如，该形成腔体的步骤可以包括：
步骤101、在所述主动端结构体和/或所述被动端结构体的表面形成图形化的第一导电材料层，以作为所述底部；
步骤102、在所述底部的表面形成介质层；以及
步骤103、在所述介质层表面形成图形化的第二导电材料层，以作为所述外壁，其中，所述外壁和所述底部围合以形成所述腔体。
图4是本实施例的在被动端结构体形成腔体的方法一个示意图，与图1对应，图4中各图案所代表的材料与图1相同。如图4所示，该方法包括：
(1)在衬底上形成图形化的下导电层：在该衬底之上，可以具备有CMOS前段晶体管与后段金属拉线等先前工艺流程；在本步骤中，可以以蒸镀或溅镀等方式，进行下导电层的铺设与图形化，下导电层可以为氮化钛(TiN)或碳化硅(SiC)或氮化钛(TiN)与铝铜合金的(AlCu)复合等金属材质等，厚度可在50至1000埃等级。
(2)形成介质层，该介质层例如可以是高分子层。例如，可以以涂布或气项化实行高分子涂布，如对光敏感的高分子材料，可以是高黏滞系数光阻等，经一般涂布、曝光、显影、紫外光再加以修护及烘烤等一系列制程步骤，定义出高分子图形，其面积尺寸可以在1微米平方至10000微米平方不等。
(3)形成外壁。例如，实施上导电层覆盖于高分子材料之上并 加以图形化。
(4)使用常用的半导体光刻与刻蚀定义洞口以方便进行下一步骤将高分子材料释放出。
(5)以电浆刻蚀方式，将高分子材料释放出来，成为一个薄膜体空腔。
(6)后续可接连一连串之表面微加工或体面微加工等方式，形成主动端结构体，该主动端结构体例如可以至少含有一个或一个以上可动结构体、弹簧以及固定端点。
在上述步骤中，(4)和(5)是可选的步骤。
在本实施例中，也可以采用其他方式来制造半导体器件。例如，可以在主动端结构体和被动端结构体形成之前，在主动端结构体和被动端结构体所对应的区域先形成腔体，然后形成主动端结构体和被动端结构体，其中，形成所述腔体的步骤可以包括：在与所述主动端结构体和/或所述被动端结构体对应的导电材料的区域中形成孔洞，所述孔洞内部作为所述腔体。
图5是本实施例的形成半导体器件的方法的一个示意图，与图3对应，图5中各图案所代表的材料与图3相同。如图5所示，该方法包括：
(1)始于衬底定义主结构体厚度，其厚度可以为1微米至100微米，依照微传感器件应用而有所厚度上的调变。其主结构体厚度可以是表面微加工或是体型微加工等工艺所预先制定完成。
(2)以光刻刻蚀定义一个或一个以上的孔洞并设计于靠近日后侧壁结构体碰撞处之边缘，约2微米至10微米处。其孔洞，直径落于5微米至100微米，但刻蚀深度并未到穿底。
(3)高分子材料填充，如对光敏感的高分子材料，可于一般涂 布、曝光、显影、紫外光再加以修护及烘烤等一系列制程步骤。
(4)进行上层无导电介质沉积与图形化，将高分子材质之顶层覆盖，该无导电介质可以为氧化硅与氮化硅之复合材料或氮化硅，其厚度约500-3000埃，依照最后步骤进行释放为传感器组件时之刻蚀选择比来进行调整。
(5)将上层无导电介质至少开一个孔洞，以利后续释放高分子材料的工艺需求。
(6)以电浆激活方式，将高分子材料释放。
(7)形成主动端结构体，该主动端结构体至少含有一个或一个以上可动结构体、弹簧以及固定端点。
(8)以气化干法将主动端结构体和被动端结构体下方的无导电介质去除，使得主动端结构体得以释放；或者，主动端结构体对应的区域中预先有定义好的前沟槽，由此，无须步骤(8)。
在本实施例中，步骤(3)-(6)可以是可选的步骤。
以上结合具体的实施方式对本申请进行了描述，但本领域技术人员应该清楚，这些描述都是示例性的，并不是对本申请保护范围的限制。本领域技术人员可以根据本申请的精神和原理对本申请做出各种变型和修改，这些变型和修改也在本申请的范围内。

Claims (10)

  1. 一种半导体器件，其具有主动端结构体和被动端结构体，所述主动端结构体和所述被动端结构体能够相对运动并彼此接触，其特征在于，
    所述主动端结构体和所述被动端结构体的至少一者具有腔体，
    所述腔体内形成为容置空间，
    所述腔体由底部和外壁围合而成，所述外壁相对于所述底部而向所述相对运动的方向突起，
    所述外壁和所述底部均为导电材料，
    所述主动端结构体和所述被动端结构体由于所述相对运动而接触的部分位于所述外壁的外表面。
  2. 如权利要求1所述的半导体器件，其中，
    所述导电材料为金属材料。
  3. 如权利要求1所述的半导体器件，其中，
    所述腔体为密封腔体或与外部连通。
  4. 如权利要求1所述的半导体器件，其中，
    所述容置空间内为真空或填充有介质。
  5. 如权利要求4所述的半导体器件，其中，
    所述介质为气体和/或高分子材料。
  6. 如权利要求1所述的半导体器件，其中，
    所述相对运动的方向平行或垂直于所述半导体器件的基底表面。
  7. 一种半导体器件的制造方法，所述半导体器件具有主动端结构体和被动端结构体，所述主动端结构体和所述被动端结构体能够相对运动并彼此接触，其特征在于，
    该制造方法包括：
    形成主动端结构体和被动端结构体；以及
    形成腔体，
    其中，所述腔体形成于所述主动端结构体和所述被动端结构体的至少一者，所述腔体内形成为容置空间，
    所述腔体由底部和外壁围合而成，所述外壁相对于所述底部而向所述相对运动的方向突起，
    所述外壁和所述底部均为导电材料，
    所述主动端结构体和所述被动端结构体由于所述相对运动而接触的部分位于所述外壁的外表面。
  8. 如权利要求7所述的半导体器件的制造方法，其中，
    在形成主动端结构体和被动端结构体之后，形成所述腔体，
    并且，形成所述腔体的步骤包括：
    在所述主动端结构体和/或所述被动端结构体的表面形成图形化的第一导电材料层，以作为所述底部；
    在所述底部的表面形成介质层；以及
    在所述介质层表面形成图形化的第二导电材料层，以作为所述外壁；
    其中，所述外壁和所述底部围合以形成所述腔体。
  9. 如权利要求7所述的半导体器件的制造方法，其中，
    在形成主动端结构体和被动端结构体之前，形成所述腔体，
    并且，形成所述腔体的步骤包括：
    在与所述主动端结构体和/或所述被动端结构体对应的导电材料的区域中形成孔洞，所述孔洞内部作为所述腔体。
  10. 如权利要求9所述的半导体器件的制造方法，其中，
    形成所述腔体的步骤还包括：
    在所述孔洞中填充介质材料；以及
    在所述孔洞的开口处覆盖绝缘介质层。
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