WO2018113058A1 - 阵列基板、阵列基板制造方法及液晶显示屏 - Google Patents

阵列基板、阵列基板制造方法及液晶显示屏 Download PDF

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WO2018113058A1
WO2018113058A1 PCT/CN2017/071154 CN2017071154W WO2018113058A1 WO 2018113058 A1 WO2018113058 A1 WO 2018113058A1 CN 2017071154 W CN2017071154 W CN 2017071154W WO 2018113058 A1 WO2018113058 A1 WO 2018113058A1
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oxide semiconductor
ips
electrode
insulating layer
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韦显旺
刘洋
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background

Definitions

  • the present invention relates to the field of liquid crystal display manufacturing technology, and in particular, to an array substrate, an array substrate manufacturing method, and a liquid crystal display.
  • TFT LCD Thin-Film-Transistor Liquid Crystal Display
  • TN the fastest response, but the worst color, relatively small viewing angle, low cost, mainly used in displays and small TV fields.
  • the IPS mode TFT substrate is a wide viewing angle display technology with relatively high viewing angle, fast response speed, accurate color and moderate cost.
  • the IPS (In-Plane Switching) mode requires a higher driving voltage.
  • the driving voltage is applied to the IPS panel electrode, the liquid crystal molecules near the electrode obtain a larger power, but the upper liquid crystal molecules away from the electrode. It is impossible to obtain the same power, and the movement is slow. Only by increasing the driving voltage, the liquid crystal molecules far from the electrode can obtain a small power, so the driving voltage is high.
  • the power consumption of the coplanar conversion mode is increased, and it is difficult to match the TFT.
  • the electric field driving of the liquid crystal molecules near the substrate is weakened, resulting in a decrease in light transmittance.
  • the invention provides an array substrate and a manufacturing method thereof, which can improve the driving uniformity of liquid crystal molecules.
  • the array substrate of the present application the method for fabricating an array substrate, wherein the method comprises sequentially forming a gate electrode, a gate insulating layer and an oxide semiconductor layer on a substrate; wherein the oxide semiconductor layer comprises opposite the gate electrode a first oxide semiconductor portion connected to the first oxide semiconductor portion a second oxide semiconductor portion on both sides and a plurality of third oxide semiconductor portions spaced apart from the second oxide semiconductor portion;
  • Forming an insulating layer on the first oxide semiconductor portion, the second conductor portion, the first IPS electrode, and the common electrode, and forming a source and a drain on the insulating layer, the source and the drain and the first a channel layer formed by the oxide semiconductor portion constitutes a semiconductor device;
  • a second IPS electrode corresponding to the first IPS electrode is formed on the passivation layer, and the second IPS electrode is connected to the first IPS electrode through the via hole.
  • the step of sequentially forming a gate electrode, a gate insulating layer, and an oxide semiconductor layer on the substrate includes: physically depositing an oxide semiconductor layer on the gate insulating layer, and then patterning the oxide semiconductor layer The first oxide semiconductor portion, the second oxide semiconductor portion, and the third oxide semiconductor portion.
  • the step of forming an insulating layer on the first oxide semiconductor portion, the second conductor portion, the first IPS electrode, and the common electrode and forming a source and a drain on the insulating layer includes forming on the insulating layer
  • the via hole communicating with the first oxide semiconductor portion is then deposited on the insulating layer to form a metal layer, and the metal layer is patterned to form the source and drain electrodes to form the channel layer.
  • the step of connecting the second IPS electrode to the first IPS electrode through the via hole comprises: forming an ITO layer on the passivation layer, patterning the The ITO layer forms the second IPS electrode, and the second IPS electrode fills the via to be connected to the first IPS electrode.
  • the source and the drain are respectively connected to the second conductor portions on both sides of the first oxide semiconductor portion through through holes provided in the insulating layer.
  • the array substrate described in the present application includes a substrate, and sequentially forms a gate and a gate of the surface of the substrate. a very insulating layer, a channel layer, an insulating layer and a passivation layer,
  • the insulating layer covers the oxide semiconductor layer and the plurality of first IPS electrodes,
  • the passivation layer covers the channel layer and is formed with a trench, and the trench is located between one side of each first IPS electrode and extends to the gate insulating layer;
  • a second IPS electrode corresponding to the first IPS electrode is formed on the passivation layer, and the second IPS electrode is connected to the first IPS electrode.
  • the second IPS electrode and the first IPS electrode are connected by a via.
  • the plurality of the second IPS electrodes includes a first group of electrodes and a second group of electrodes arranged at intervals, and each of the first group of electrodes is located at each of the second group of electrodes Between the second IPS.
  • the liquid crystal display of the present invention includes a color filter substrate, an array substrate, and a liquid crystal layer.
  • the color film substrate and the array substrate form a receiving space for accommodating the liquid crystal.
  • the array substrate includes a substrate, and the substrate surface is sequentially formed. a gate electrode, a gate insulating layer, a channel layer, an insulating layer, and a passivation layer, wherein the gate insulating layer further includes an oxide semiconductor layer constituting the channel layer and a plurality of regions spaced apart from the oxide semiconductor layer a first IPS electrode; the insulating layer covers the oxide semiconductor layer and a plurality of first IPS electrodes, the passivation layer covers the channel layer and is formed with a trench, and the trench is located at each first Between the one side of the IPS electrode and extending onto the gate insulating layer; a second IPS electrode corresponding to the first IPS electrode is formed on the passivation layer, and the second IPS electrode is connected to the first IPS electrode; The trench of the array substrate is in communication with
  • the array substrate of the liquid crystal display panel of the present invention has a first IPS electrode and a second IPS electrode.
  • the voltages of the two electrodes are the same, forming a double IPS driving structure array substrate, and the liquid crystal located in the bottom trench is also the same. It can be driven by a sufficient voltage to ensure efficient driving of the liquid crystal layer and achieve high transmittance of the liquid crystal.
  • FIG. 1 is a flow chart of a method for fabricating an array substrate according to the present invention.
  • FIG. 2 to FIG. 6 are schematic diagrams showing respective steps of the method for fabricating the array substrate illustrated in FIG. 1.
  • Figure 7 is a schematic view of an array substrate of the present invention.
  • FIG. 8 is a schematic view showing the arrangement of a first group of electrodes and a second group of electrodes in the method for fabricating the array substrate of FIG. 1.
  • the present invention provides a method for fabricating an array substrate, the method comprising
  • Step S1 sequentially forming a gate electrode 11, a gate insulating layer 12, and an oxide semiconductor layer on the substrate 10; wherein the oxide semiconductor layer includes a first oxide semiconductor portion 131 opposite to the gate electrode 11 and is connected to the A second oxide semiconductor portion 132 on both sides of the first oxide semiconductor portion 131 and a plurality of third oxide semiconductor portions 133 spaced apart from the second oxide semiconductor portion 132.
  • the oxide semiconductor layer is physically vapor-deposited on the gate insulating layer 12, and then the first oxide semiconductor portion 131 and the second oxide semiconductor are patterned by patterning the oxide semiconductor layer. Portion 132 and third oxide semiconductor portion 133.
  • step S2 the oxide semiconductor layer is irradiated with ultraviolet rays on the surface of the substrate 10 facing away from the surface of the gate electrode 11, so that the second oxide semiconductor portion 132 and the plurality of The third oxide semiconductor portion 133 becomes a second conductor portion 134 and a plurality of third conductor portions, respectively, wherein the plurality of third conductor portions are divided into a first IPS electrode 135 and a common electrode 136.
  • ultraviolet rays illuminate the oxide semiconductor layer, the first oxide semiconductor portion 131 is blocked by the gate electrode 11, and other portions are turned into a conductor by ultraviolet light.
  • the first IPS electrode 135 and the common electrode 136 are both arranged in a plurality of intersecting insulation arrangements.
  • step S3 at the first oxide semiconductor portion 131 and the second guide.
  • An insulating layer 14 is formed on the body portion 134 and the plurality of first IPS electrodes 135 and the common electrode 136, and a source 15 and a drain 16 are formed on the insulating layer 14.
  • the source 15 and the drain 16 are connected to the first oxide.
  • the semiconductor portion 131 is formed to form a channel layer.
  • the source 15 and the drain 16 are respectively connected to the second conductor portions 134 on both sides of the first oxide semiconductor portion 131 through through holes provided in the insulating layer 14.
  • the via hole communicating with the first oxide semiconductor portion 131 is formed on the insulating layer 14, and then a metal layer is deposited on the insulating layer 14, and the metal layer is patterned to form a The source 15 and the drain 16 are described.
  • a passivation layer 17 is formed on the source 15 , the drain 16 , the channel layer and the insulating layer 14 , and via holes 171 and trenches 172 are formed on the passivation layer 17 .
  • the trench 172 is on one side of each of the first IPS electrodes 135 and extends to the gate insulating layer 12, and the via 171 communicates with the first IPS electrode 135.
  • the groove bottom of the trench 172 is recessed on the gate insulating layer 12 on the side of the first IPS electrode 135.
  • a second IPS electrode 18 corresponding to the first IPS electrode 135 is formed on the passivation layer 17 , and the second IPS electrode 18 is connected to the first IPS electrode 135 .
  • an ITO layer is formed on the passivation layer, the ITO layer is patterned to form the second IPS electrode 18, and the second IPS electrode fills the via hole and is connected to the first IPS electrode.
  • the array substrate formed by the method has a first IPS electrode and a second IPS electrode having an upper and lower layer structure, and the bottom trench is filled with liquid crystal. When the liquid crystal is driven by the current, the voltages of the two electrodes are uniform, and the liquid crystal located in the bottom trench It can also be driven by a sufficient voltage to ensure efficient driving of the liquid crystal layer.
  • a plurality of the second IPS electrodes 18 include a first group of electrodes A and a second group of electrodes B arranged in a column, and each of the first group of electrodes A is a second IPS electrode. Between each of the second IPSs of the second set of electrodes B. It can be understood that a plurality of the second IPS electrodes 18 are arranged in multiple columns and are connected to one side of the first IPS electrode provided with a via, while the second IPS electrode and the second group B of the first group A are The second IPS electrode is cross-insulated. In this way, the opening position of the via hole 171 can be shifted to avoid the occurrence of a plurality of via holes 171 on the same straight line and affect the strength of the substrate.
  • the present invention further provides an array substrate manufactured by the above manufacturing method, the array substrate comprising a substrate 10, and sequentially forming a gate electrode 11, a gate insulating layer 12, and a channel layer 19 on the surface of the substrate.
  • the gate insulating layer 12 is further provided with a channel layer An oxide semiconductor layer and a plurality of first IPS electrodes 135 spaced apart from the oxide semiconductor layer; the insulating layer 14 covering the oxide semiconductor layer and the plurality of first IPS electrodes 135, the passivation layer 17 covering the a channel layer formed with a trench 172 on one side of each of the first IPS electrodes 135 and extending onto the gate insulating layer 12; the passivation layer 17 is formed with a plurality of An IPS electrode 135 corresponds to a second IPS electrode 18, and the second IPS electrode 18 is connected to the first IPS electrode 18 through a via.
  • the method for fabricating the array substrate of the present invention does not need to add complicated steps, only needs the back ultraviolet light to conduct the semiconductor conductor, and can realize the double electrode effect of the array substrate, and is the first formation of the array substrate including the oxide semiconductor layer.
  • the IPS electrode and the second IPS electrode made of ITO are connected to the first IPS electrode and the second IPS electrode through the hole to ensure that the voltages of the two electrodes are uniform, and the array substrate of the double IPS driving structure is formed, thereby effectively reducing the driving voltage of the liquid crystal.
  • a common electrode 136 disposed to intersect with the first IPS electrode 135 is further disposed on the gate insulating layer 12.
  • the present invention also provides a liquid crystal display panel (not shown), which includes a color filter substrate, the array substrate, and a liquid crystal layer.
  • the color film substrate and the array substrate form a receiving space for accommodating liquid crystal, and the array substrate
  • the trench is in communication with the receiving space, and the liquid crystal is distributed in the liquid crystal space and the trench.
  • the array substrate of the liquid crystal display panel of the present invention has a first IPS electrode and a second IPS electrode.
  • the voltages of the two electrodes are the same, forming a double IPS driving structure array substrate, and the liquid crystal located in the bottom trench is also the same. It can be driven by a sufficient voltage to ensure efficient driving of the liquid crystal layer and achieve high transmittance of the liquid crystal.

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  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
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  • Optics & Photonics (AREA)
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Abstract

一种阵列基板、阵列基板制造方法及液晶显示屏，所述阵列基板包括基板（10），依次形成所述基板（10）表面的栅极（11）、栅极绝缘层（12）、沟道层、绝缘层（14）及钝化层（17），所述栅极绝缘层（12）上还设有构成沟道层的氧化物半导体层及与氧化物半导体层间隔设置的多个第一IPS电极（135）；所述绝缘层（14）覆盖所述氧化物半导体层及多个第一IPS电极（135），所述钝化层（17）覆盖所述沟道层并形成有沟槽（172），所述沟槽（172）位于每个第一IPS电极（135）一侧间并延伸至所述栅极绝缘层（12）上；所述钝化层（17）上形成与第一IPS电极（135）对应的第二IPS电极（18），所述第二IPS电极（18）与所述第一IPS电极连接（135）。

Description

阵列基板、阵列基板制造方法及液晶显示屏
本发明要求2016年12月23日递交的发明名称为“阵列基板、阵列基板制造方法及液晶显示屏”的申请号2016112150263的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及液晶显示屏制造技术领域，尤其涉及阵列基板、阵列基板制造方法及液晶显示屏。
背景技术
TFT LCD(Thin-Film-Transistor Liquid Crystal Display，薄膜晶体管液晶显示器)由于其高速度、高亮度、高对比度等优点，目前已经得到普遍的应用。TFT基板的模式有很多，较常见的有TN、IPS、MVA等。TN模式，响应速度最快，但色彩最差，可视角度相对较小，成本低，主要应用在显示器和小型电视领域。IPS模式的TFT基板，是一种宽视角显示技术，可视角度相对较高，响应速度较快，色彩准确，成本适中。
然而，传统技术中IPS(In-Plane Switching)模式需要较高的驱动电压，当驱动电压加到IPS面板电极上后，靠近电极的液晶分子会获得较大的动力，但是远离电极的上层液晶分子就无法获得一样的动力，运动较慢，只用增加驱动电压才能使远离电极的液晶分子也获得不小的动力，所以驱动电压会较高。使得共面转换模式功耗升高，难以和TFT相匹配。同时在靠近基板附近的液晶分子电场驱动减弱，导致光透过率降低。
发明内容
本发明提供一种阵列基板及其制造方法，可以提高液晶分子驱动均匀性。
本申请所述阵列基板、一种阵列基板制造方法，其中，所述方法包括在基板依次形成栅极、栅极绝缘层及氧化物半导体层；其中，氧化物半导体层包括与所述栅极相对的第一氧化物半导体部分、连接于所述第一氧化物半导体部分 两侧的第二氧化物半导体部分以及与所述第二氧化物半导体部分间隔设置的多个第三氧化物半导体部分；
于所述基板背向所述栅极的表面方通过紫外线光罩所述氧化物半导体层，使所述第二氧化物半导体部分及多个所述第三氧化物半导体部分分别变成第二导体部分及多个第三导体部分，其中，所述多个第三导体部分分为第一IPS电极及公共电极；
在所述第一氧化物半导体部分、第二导体部分、第一IPS电极及公共电极上形成绝缘层并在绝缘层上形成源极及漏极，所述源极及漏极与所述第一氧化物半导体部分形成的沟道层构成半导体器件；
在所述源极、漏极、沟道层及绝缘层上形成钝化层，并在所述钝化层上形成与所述第一IPS电极连通的过孔及沟槽，所述沟槽位于每个第一IPS电极一侧并延伸至所述栅极绝缘层上；
在所述钝化层上形成与所述第一IPS电极对应的第二IPS电极，且所述第二IPS电极通过所述过孔与第一IPS电极连接。
其中，在基板依次形成栅极、栅极绝缘层及氧化物半导体层的步骤包括，在所述栅极绝缘层上物理气相沉积氧化物半导体层，然后对所述氧化物半导体层图案化形成所述的第一氧化物半导体部分、第二氧化物半导体部分及第三氧化物半导体部分。
其中，在所述第一氧化物半导体部分、第二导体部分、第一IPS电极及公共电极上形成绝缘层并在绝缘层上形成源极及漏极的步骤，包括在所述绝缘层上形成与所述第一氧化物半导体部分连通的所述通孔，然后在绝缘层上沉积形成金属层，图案化所述金属层形成所述源极及漏极以形成所述沟道层。
其中，在所述钝化层上形成第二IPS电极，所述第二IPS电极通过所述过孔与第一IPS电极连接步骤包括，在所述钝化层上形成ITO层，图案化所述ITO层形成所述第二IPS电极，并且第二IPS电极填满所述过孔与所述第一IPS电极连接。
其中，所述源极与漏极通过设于绝缘层的通孔分别与所述第一氧化物半导体部分两侧的第二导体部分连接。
本申请所述的阵列基板，包括基板，依次形成所述基板表面的栅极、栅 极绝缘层、沟道层、绝缘层及钝化层，
所述绝缘层覆盖所述氧化物半导体层及多个第一IPS电极，
所述钝化层覆盖所述沟道层并形成有沟槽，所述沟槽位于每个第一IPS电极一侧间并延伸至所述栅极绝缘层上；
所述钝化层上形成与第一IPS电极对应的第二IPS电极，所述第二IPS电极与所述第一IPS电极连接。
其中，所述第二IPS电极与所述第一IPS电极通过过孔连接。
其中，多个所述第二IPS电极包括呈间隔排列的第一组电极及第二组电极，所述第一组电极中的每个第二IPS电位于所述第二组电极中的每两个第二IPS之间。
本申请所述的液晶显示屏，包括彩膜基板、阵列基板及液晶层，所述彩膜基板与阵列基板之间形成收容液晶的收容空间，所述阵列基板包括基板，依次形成所述基板表面的栅极、栅极绝缘层、沟道层、绝缘层及钝化层，所述栅极绝缘层上还设有构成沟道层的氧化物半导体层及与氧化物半导体层间隔设置的多个第一IPS电极；所述绝缘层覆盖所述氧化物半导体层及多个第一IPS电极，所述钝化层覆盖所述沟道层并形成有沟槽，所述沟槽位于每个第一IPS电极一侧间并延伸至所述栅极绝缘层上；所述钝化层上形成与第一IPS电极对应的第二IPS电极，所述第二IPS电极与所述第一IPS电极连接；所述阵列基板的沟槽与所述收容空间连通，液晶分布于所述液晶空间及沟槽内。
本发明的液晶显示屏的阵列基板具有第一IPS电极及第二IPS电极，当通电驱动液晶时，两个电极的电压是一致，形成双IPS驱动结构阵列基板，位于底部沟槽内的液晶同样可以被足够电压驱动，进而保证液晶层的有效驱动并实现液晶的高透过率。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明所述的阵列基板制造方法流程图。
图2至图6为图1所述的阵列基板制造方法各个步骤示意图。
图7为本发明阵列基板示意图。
图8为图1所述的阵列基板制造方法中第一组电极及第二组电极的排布示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1、图2与图3，本发明提供一种阵列基板制造方法，所述方法包括
步骤S1，在基板10依次形成栅极11、栅极绝缘层12及氧化物半导体层；其中，氧化物半导体层包括与所述栅极11相对的第一氧化物半导体部分131、连接于所述第一氧化物半导体部分131两侧的第二氧化物半导体部分132以及与所述第二氧化物半导体部分132间隔设置的多个第三氧化物半导体部分133。
本步骤中，包括，在所述栅极绝缘层12上物理气相沉积氧化物半导体层，然后对所述氧化物半导体层图案化形成所述的第一氧化物半导体部分131、第二氧化物半导体部分132及第三氧化物半导体部分133。
请一并参阅图4，步骤S2，于所述基板10背向所述栅极11的表面方通过紫外线光照所述氧化物半导体层，使所述第二氧化物半导体部分132及多个所述第三氧化物半导体部分133分别变成第二导体部分134及多个第三导体部分，其中，所述多个第三导体部分分为第一IPS电极135及公共电极136。本步骤中，紫外线光照所述氧化物半导体层，所述第一氧化物半导体部分131被所述栅极11遮挡，其他部分被紫外线光照变成导体。第一IPS电极135及公共电极136均为多个且交叉绝缘排布。
请一并参阅图5，步骤S3，在所述第一氧化物半导体部分131、第二导 体部分134及多个第一IPS电极135、公共电极136上形成绝缘层14并在绝缘层14上形成源极15及漏极16，所述源极15及漏极16与所述第一氧化物半导体部分131以形成沟道层。其中，所述源极15与漏极16通过设于绝缘层14的通孔分别与所述第一氧化物半导体部分131两侧的第二导体部分134连接。
本步骤中，包括在所述绝缘层14上形成与所述第一氧化物半导体部分131连通的所述通孔，然后在绝缘层14上沉积形成金属层，图案化所述金属层以形成所述源极15及漏极16。
请参阅图6，步骤S4，在所述源极15、漏极16、沟道层及绝缘层14上形成钝化层17，并在所述钝化层17上形成过孔171及沟槽172，所述沟槽172于每个第一IPS电极135一侧并延伸至所述栅极绝缘层12上，所述过孔171连通所述第一IPS电极135。所述沟槽172的槽底凹陷于位于所述第一IPS电极135一侧的栅极绝缘层12上。
请参阅图7，步骤S5，在所述钝化层17上形成与第一IPS电极135对应的第二IPS电极18，所述第二IPS电极18与所述第一IPS电极135连接。具体为，在所述钝化层上形成ITO层，图案化所述ITO层形成所述第二IPS电极18，并且第二IPS电极填满所述过孔与所述第一IPS电极连接。本方法形成的阵列基板具有上下层结构的第一IPS电极及第二IPS电极，位于底部沟槽内充满液晶，当通电驱动液晶时，两个电极的电压是一致，位于底部沟槽内的液晶同样可以被足够电压驱动，进而保证液晶层的有效驱动。
如图8，需要说明的是，多个所述第二IPS电极18包括呈列排列的第一组电极A及第二组电极B，所述第一组电极A中的每个第二IPS电极于所述第二组电极B中的每两个第二IPS之间。可以理解为多个所述第二IPS电极18分为多列设置并且与第一IPS电极设有过孔一侧相连接，同时第一组电极A中第二IPS电极与第二组电极B的第二IPS电极交叉绝缘排列。如此可以错开过孔171的开设位置，避免同一直线上出现多个过孔171而影响基板强度。
如图7所示，本发明还提供一种通过上述制造方法制造的阵列基板，所述阵列基板包括基板10，依次形成所述基板表面的栅极11、栅极绝缘层12、沟道层19、绝缘层14及钝化层17。所述栅极绝缘层12上还设有构成沟道层的 氧化物半导体层及与氧化物半导体层间隔设置的多个第一IPS电极135；所述绝缘层14覆盖所述氧化物半导体层及多个第一IPS电极135，所述钝化层17覆盖所述沟道层并形成有沟槽172，所述沟槽172位于每个第一IPS电极135一侧并延伸至所述栅极绝缘层12上；所述钝化层17上形成多个与第一IPS电极135对应的第二IPS电极18，所述第二IPS电极18与所述第一IPS电极18通过过孔连接。
本发明所述的阵列基板制造方法不需要增加复杂的步骤只需要背部紫外线光照将半导体导体化，既可以实现阵列基板的双电极效果，是阵列基板包括氧化物半导体层变导体化形成的第一IPS电极和ITO制作的第二IPS电极，并通过孔连接第一IPS电极及第二IPS电极，保证两个电极电压一致，形成双IPS驱动结构的阵列基板，有效降低液晶的驱动电压。所述栅极绝缘层12上还设有与第一IPS电极135交叉设置的公共电极136。
本发明还提供一种液晶显示屏(图未示)，其包括彩膜基板、所述阵列基板及液晶层，所述彩膜基板与阵列基板之间形成收容液晶的收容空间，所述阵列基板的沟槽与所述收容空间连通，液晶分布于所述液晶空间及沟槽内。
本发明的液晶显示屏的阵列基板具有第一IPS电极及第二IPS电极，当通电驱动液晶时，两个电极的电压是一致，形成双IPS驱动结构阵列基板，位于底部沟槽内的液晶同样可以被足够电压驱动，进而保证液晶层的有效驱动并实现液晶的高透过率。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (9)

  1. 一种阵列基板制造方法，其中，所述方法包括在基板依次形成栅极、栅极绝缘层及氧化物半导体层；其中，氧化物半导体层包括与所述栅极相对的第一氧化物半导体部分、连接于所述第一氧化物半导体部分两侧的第二氧化物半导体部分以及与所述第二氧化物半导体部分间隔设置的多个第三氧化物半导体部分；
    于所述基板背向所述栅极的表面方通过紫外线光照所述氧化物半导体层，使所述第二氧化物半导体部分及多个所述第三氧化物半导体部分分别变成第二导体部分及多个第三导体部分，其中，所述多个第三导体部分分为第一IPS电极及公共电极；
    在所述第一氧化物半导体部分、第二导体部分、第一IPS电极及公共电极上形成绝缘层并在绝缘层上形成源极及漏极，所述源极及漏极与所述第一氧化物半导体部分形成的沟道层构成半导体器件；
    在所述源极、漏极、沟道层及绝缘层上形成钝化层，并在所述钝化层上形成与所述第一IPS电极连通的过孔及沟槽，所述沟槽位于每个第一IPS电极一侧并延伸至所述栅极绝缘层上；
    在所述钝化层上形成与所述第一IPS电极对应的第二IPS电极，且所述第二IPS电极通过所述过孔与第一IPS电极连接。
  2. 如权利要求1所述的一种阵列基板制造方法，其中，在基板依次形成栅极、栅极绝缘层及氧化物半导体层的步骤包括，在所述栅极绝缘层上物理气相沉积氧化物半导体层，然后对所述氧化物半导体层图案化形成所述的第一氧化物半导体部分、第二氧化物半导体部分及第三氧化物半导体部分。
  3. 如权利要求1所述的一种阵列基板制造方法，其中，在所述第一氧化物半导体部分、第二导体部分、第一IPS电极及公共电极上形成绝缘层并在绝缘层上形成源极及漏极的步骤，包括在所述绝缘层上形成与所述第一氧化物半导体部分连通的所述通孔，然后在绝缘层上沉积形成金属层，图案化所述金属层形成所述源极及漏极以形成所述沟道层。
  4. 如权利要求1所述的一种阵列基板制造方法，其中，在所述钝化层上形成第二IPS电极，所述第二IPS电极通过所述过孔与第一IPS电极连接步骤 包括，在所述钝化层上形成ITO层，图案化所述ITO层形成所述第二IPS电极，并且第二IPS电极填满所述过孔与所述第一IPS电极连接。
  5. 如权利要求1所述的一种阵列基板制造方法，其中，所述源极与漏极通过设于绝缘层的通孔分别与所述第一氧化物半导体部分两侧的第二导体部分连接。
  6. 一种阵列基板，其中，所述阵列基板包括基板，依次形成所述基板表面的栅极、栅极绝缘层、沟道层、绝缘层及钝化层，
    所述栅极绝缘层上还设有构成沟道层的氧化物半导体层及与氧化物半导体层间隔设置的多个第一IPS电极；
    所述绝缘层覆盖所述氧化物半导体层及多个第一IPS电极，
    所述钝化层覆盖所述沟道层并形成有沟槽，所述沟槽位于每个第一IPS电极一侧并延伸至所述栅极绝缘层上；
    所述钝化层上形成与第一IPS电极对应的第二IPS电极，所述第二IPS电极与所述第一IPS电极连接。
  7. 如权利要求6所述的一种阵列基板，其中，所述第二IPS电极与所述第一IPS电极通过过孔连接。
  8. 如权利要求6所述的一种阵列基板，其中，多个所述第二IPS电极包括呈间隔排列的第一组电极及第二组电极，所述第一组电极中的每个第二IPS电位于所述第二组电极中的每两个第二IPS之间。
  9. 一种液晶显示屏，其中，包括彩膜基板、阵列基板及液晶层，所述彩膜基板与阵列基板之间形成收容液晶的收容空间，所述阵列基板包括基板，依次形成所述基板表面的栅极、栅极绝缘层、沟道层、绝缘层及钝化层，所述栅极绝缘层上还设有构成沟道层的氧化物半导体层及与氧化物半导体层间隔设置的多个第一IPS电极；所述绝缘层覆盖所述氧化物半导体层及多个第一IPS电极，所述钝化层覆盖所述沟道层并形成有沟槽，所述沟槽位于每个第一IPS电极一侧间并延伸至所述栅极绝缘层上；所述钝化层上形成与第一IPS电极对应的第二IPS电极，所述第二IPS电极与所述第一IPS电极连接；所述阵列基板的沟槽与所述收容空间连通，液晶分布于所述液晶空间及沟槽内。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020089631A1 (en) * 2000-07-10 2002-07-11 Dong-Hoon Lee In-plane switching liquid crystal display device and method for fabricating the same
CN101216627A (zh) * 2007-01-05 2008-07-09 群康科技(深圳)有限公司 多域垂直配向型液晶显示面板
CN102237411A (zh) * 2010-05-05 2011-11-09 元太科技工业股份有限公司 氧化物薄膜晶体管及其制造方法
CN103777418A (zh) * 2014-01-27 2014-05-07 京东方科技集团股份有限公司 一种阵列基板、液晶显示面板及显示装置
CN105549278A (zh) * 2016-01-11 2016-05-04 深圳市华星光电技术有限公司 Ips型tft-lcd阵列基板的制作方法及ips型tft-lcd阵列基板

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI545380B (zh) * 2006-05-16 2016-08-11 半導體能源研究所股份有限公司 液晶顯示裝置和半導體裝置
JP5235363B2 (ja) * 2007-09-04 2013-07-10 株式会社ジャパンディスプレイイースト 液晶表示装置
WO2013181166A1 (en) * 2012-05-26 2013-12-05 Cbrite Inc. Mask level reduction for mofet
JP2016148760A (ja) * 2015-02-12 2016-08-18 株式会社ジャパンディスプレイ 液晶表示装置
CN106371253A (zh) * 2016-08-26 2017-02-01 武汉华星光电技术有限公司 阵列基板、液晶显示面板以及制造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020089631A1 (en) * 2000-07-10 2002-07-11 Dong-Hoon Lee In-plane switching liquid crystal display device and method for fabricating the same
CN101216627A (zh) * 2007-01-05 2008-07-09 群康科技(深圳)有限公司 多域垂直配向型液晶显示面板
CN102237411A (zh) * 2010-05-05 2011-11-09 元太科技工业股份有限公司 氧化物薄膜晶体管及其制造方法
CN103777418A (zh) * 2014-01-27 2014-05-07 京东方科技集团股份有限公司 一种阵列基板、液晶显示面板及显示装置
CN105549278A (zh) * 2016-01-11 2016-05-04 深圳市华星光电技术有限公司 Ips型tft-lcd阵列基板的制作方法及ips型tft-lcd阵列基板

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