WO2018103685A1 - 一种nand闪存设备的操作指令调度方法及装置 - Google Patents

一种nand闪存设备的操作指令调度方法及装置 Download PDF

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WO2018103685A1
WO2018103685A1 PCT/CN2017/114939 CN2017114939W WO2018103685A1 WO 2018103685 A1 WO2018103685 A1 WO 2018103685A1 CN 2017114939 W CN2017114939 W CN 2017114939W WO 2018103685 A1 WO2018103685 A1 WO 2018103685A1
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task
nand
queue
arbitration queue
read
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PCT/CN2017/114939
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English (en)
French (fr)
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王凤海
夏杰旭
王嵩
杨骥
张建涛
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北京得瑞领新科技有限公司
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Priority to EP17877644.9A priority Critical patent/EP3553646A4/en
Priority to US16/467,107 priority patent/US11112998B2/en
Publication of WO2018103685A1 publication Critical patent/WO2018103685A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0611—Improving I/O performance in relation to response time
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
    • G06F3/0652—Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Definitions

  • the present invention relates to the field of data storage technologies, and in particular, to an operation instruction scheduling method and apparatus for a NAND flash memory device.
  • NAND flash is a better storage solution than hard drives, which is evident in low-volume applications up to 4GB. NAND is proving to be attractive as people continue to pursue lower power, lighter weight and better performance. At present, NAND flash memory technology is widely used in solid-state hard disk and other fields. Compared with traditional mechanical hard disks, solid-state hard disks have greatly improved access speed. Today's NAND interfaces are getting faster and faster, from the original asynchronous mode to the current DDR (Double Data Rate) mode. The latest NAND flash granules can reach 667MB per second. At the same time, in order to increase the storage capacity, the page size of the NAND flash memory has become larger and larger, and the time for accessing a page has increased.
  • DDR Double Data Rate
  • one NAND interface will connect multiple NAND particles, so the order of the NAND instructions needs to be scheduled.
  • the scheduling strategy must ensure correctness, ensure that the instruction sequence for operating NAND particles meets the requirements, and on the other hand, make full use of the performance of the NAND interface and NAND particles.
  • the operation command scheduling schemes of the existing NAND flash memory devices are mostly scheduled by software. There are two main reasons: on the one hand, the scheduling strategy is more complicated, and the demand may change. The software solution is easy to modify and has higher flexibility. On the other hand, the performance requirements of the original NAND interface are not high, and the software has the ability. To meet performance requirements. However, with the rapid development of large-capacity high-speed solid-state drives, the performance of IOPS (Input/Output Operations Per Second) has reached millions of levels and the latency is getting lower and lower. The use of software to implement operational command scheduling for NAND flash devices has failed to meet performance requirements.
  • IOPS Input/Output Operations Per Second
  • the invention provides an operation instruction scheduling method and device for a NAND flash memory device, which can efficiently implement operation instruction scheduling of a NAND flash memory device, improve flexibility of operation instruction scheduling of the NAND flash memory device, and improve overall performance of the NAND flash memory device.
  • One aspect of the present invention provides a method for scheduling an operation instruction of a NAND flash memory device, including:
  • the task decomposition of the operation instructions of the NAND flash memory device includes:
  • the NAND particle corresponds to a unique task queue to store tasks obtained after the task is decomposed.
  • the method further includes: after performing task decomposition on the operation instruction of the NAND flash memory device, the method further includes:
  • the task type includes a non-IO task, a write IO task, and a read IO task.
  • the write IO task and the read IO task have the same priority, and the non-IO task has a higher priority than the write IO task and read.
  • the method further includes:
  • the priority of the arbitration queue is determined according to the task priority stored in the arbitration queue.
  • the task to be executed is extracted from the write IO arbitration queue corresponding to the write IO task or the read IO arbitration queue corresponding to the read IO task according to the preset task execution policy, and the NAND interface is scheduled for the task to be executed.
  • the method further includes: before the extracting the task to be executed from the write IO arbitration queue corresponding to the write IO task or the read IO arbitration queue corresponding to the IO task, according to the preset task execution policy, the method further includes:
  • the task header information further includes a read status task enable identifier
  • the method further includes:
  • the read status task enable identifier is read.
  • a timer is started, a read status task is triggered after a preset timing time, and the read status task is sent to the corresponding The arbitration queue triggers an operation of sending the next task in the task queue to the corresponding arbitration queue when the read status task enable flag is off.
  • the task header information further includes an interface exclusive license identifier
  • the method further includes:
  • the task header information further includes a task identifier ID
  • the method further includes:
  • the task execution result is monitored and returned, and the task execution result carries the task identification ID of the to-be-executed task.
  • an operation instruction scheduling apparatus for a NAND flash memory device includes:
  • a task generation module configured to perform task decomposition on an operation instruction of the NAND flash device, and send the obtained task to a corresponding task queue
  • a task management module configured to send the current task to a corresponding arbitration queue according to a task type of a current task in the task queue;
  • the task arbiter is configured to schedule a NAND interface for the to-be-executed task in the arbitration queue according to the priority information of the arbitration queue.
  • the task generation module is further configured to configure task header information for each task after performing task decomposition on the operation instructions of the NAND flash memory device, where the task header information includes a task type identifier;
  • the task management module is specifically configured to determine a task type of the current task according to the task type identifier included in the task header information of the current task, and send the current task to a corresponding arbitration queue according to the task type. .
  • the invention decomposes an operation instruction into a plurality of tasks by performing task decomposition on the operation instruction of the NAND flash memory device, and sends the obtained task to the corresponding task queue, and then sends the task to the corresponding task according to the task type of the current task in the queue.
  • the embodiments of the present invention can efficiently implement the operation instruction scheduling of the NAND flash memory device, improve the flexibility of the operation instruction scheduling of the NAND flash memory device, and improve the overall performance of the NAND flash memory device.
  • FIG. 1 is a sequence diagram of a block erase operation instruction according to an embodiment of the present invention.
  • FIG. 2 is a sequence diagram of a page programming operation instruction according to an embodiment of the present invention.
  • FIG. 3 is a sequence diagram of a page read operation instruction according to an embodiment of the present invention.
  • FIG. 4 is a sequence diagram of a read status operation instruction according to an embodiment of the present invention.
  • FIG. 5 is a flowchart of a method for scheduling an operation instruction of a NAND flash memory device according to an embodiment of the present invention
  • FIG. 6 is a schematic diagram of an implementation of an arbitration queue in an operation instruction scheduling method of a NAND flash memory device according to an embodiment of the present invention
  • FIG. 7 is a schematic diagram of an implementation method of an operation instruction scheduling method of a NAND flash memory device according to an embodiment of the present invention.
  • FIG. 8 is a specific implementation flow of an operation instruction scheduling method of a NAND flash memory device according to an embodiment of the present invention.
  • FIG. 9 is a specific implementation flow of an operation instruction scheduling method of a NAND flash memory device according to another embodiment of the present invention.
  • FIG. 10 is a structural block diagram of an operation instruction scheduling apparatus of a NAND flash memory device according to an embodiment of the present invention.
  • NAND flash There are four basic operational instructions for NAND flash: the first is block erase, which performs an erase operation on the entire block in block units.
  • the sequence of operations on the NAND interface is shown in Figure 1. Referring to FIG. 1, first, the 60 command is sent on the NAND interface, and then the address is 3, and then the D0 command is issued to start the NAND particle to perform the erase operation. When this operation is performed, the state of the NAND particles becomes busy (SR[6] in the figure goes low), and waits for the t BERS time to become free again. When the state is busy, this NAND particle cannot receive other read and write commands, but can accept read status operations.
  • the second is page program, which programs the entire page in page units.
  • the sequence of operations on the NAND interface is shown in Figure 2. Referring to Figure 2, first send 80 commands on the NAND interface, then 5 beat addresses, and then transfer data, usually full page data, now NAND particles are mostly 16KB, and then send 10 commands to confirm the startup NAND particles to perform programming operations. When this operation is performed, the state of the NAND pellet becomes busy (RDY in the figure goes low), and waits for the t PROG time to become free again. When the state is busy, this NAND particle cannot receive other read and write commands, but can accept read status operations.
  • the third is page read, which reads the data in the page in units of pages. Its sequence of operations on the NAND interface is shown in Figure 3. Referring to Figure 3, first send a 00 command on the NAND interface, then 5 beats the address, and then issue a 30 command to confirm that the NAND particles are being read. The NAND particles will read the data from the internal memory location to its internal cache register (cache). Register). When this operation is performed, the state of the NAND pellet becomes busy (RDY in the figure goes low), and waits for the t R time before it becomes idle again. When the state is busy, this NAND particle cannot receive other read and write commands, but can accept read status operations. When the state changes from busy to idle (RDY in the figure changes from low to high), the data can be read from the cache register through the NAND interface.
  • the fourth is a read state operation that is used to query the state of the NAND particles.
  • the NAND particles are in a busy time and vary from operation to operation. Even for the same operation, different NAND particles, even different states of the same NAND particle, can affect the length of the busy time, so the read status operation is generally used to query when the NAND particles become idle.
  • the read state operation has different forms.
  • the simplest 70 command is taken as an example, and its operation sequence on the NAND interface is as shown in FIG. 4 . Referring to FIG. 4, the 70 command is first sent on the NAND interface, and after waiting for a short time t WHR , the state of one byte can be read through the NAND interface.
  • the characteristics of block erasing are as follows: 1. The time occupied by the NAND interface is relatively short and should be in the microsecond level. 2. NAND particles take a long time to perform erasing, and the latest flash granules may take more than 10 milliseconds.
  • the page programming features are as follows: 1.
  • the NAND interface takes a long time because the entire page of data needs to flow through the NAND interface in one shot and one beat.
  • NAND particles perform programming operations shorter than erase, and the latest flash granules are on the order of 1 millisecond.
  • the page read characteristics are as follows: 1.
  • the occupation of the NAND interface time is determined by the amount of data read. For block devices, it may be an integer multiple of 512B or 4KB. In general, it takes up much longer than the block erase time, but may be shorter than the page programming operation. 2.
  • the time required for NAND particles to perform read operations is relatively short, and the latest flash memory particles are typically within 100 microseconds.
  • the read status operation features are as follows: 1.
  • the NAND interface takes a short time and should be in the microsecond level. 2.
  • NAND particle execution time is very short.
  • the operation instruction scheduling method of the NAND flash memory device of the present invention is proposed to efficiently implement the operation instruction scheduling of the NAND flash memory device, and improve the NAND flash memory.
  • the flexibility of the device's operational instruction scheduling increases the overall performance of the NAND flash device.
  • FIG. 5 is a flow chart schematically showing an operation instruction scheduling method of a NAND flash memory device according to an embodiment of the present invention.
  • the operation instruction scheduling method of the NAND flash memory device of the embodiment of the present invention specifically includes the following steps:
  • each operation instruction of the NAND flash memory device corresponds to at least one execution object, that is, a target NAND particle, and each NAND particle maintains a task queue, and the task generation module performs a task on the operation instruction of the NAND flash memory device.
  • the task for this NAND particle is sent to the corresponding task queue.
  • the task obtained by the decomposition is implemented by using a queue, which can effectively reduce the delay of the task.
  • the task type includes a non-IO task, a write IO task, and a read IO task. Specifically, after the task is decomposed, tasks of different task types are obtained, and then the current task is sent to the corresponding arbitration queue according to the task type of the current task in the task queue.
  • the operation instruction scheduling method of the NAND flash memory device decomposes an operation instruction into a plurality of tasks by performing task decomposition on the operation instructions of the NAND flash memory device, and sends the obtained task to the corresponding task queue, and then The task is sent to the corresponding arbitration queue according to the task type of the current task in the queue, so that the task arbiter dispatches the NAND interface for the task to be executed in the arbitration queue according to the priority of the arbitration queue.
  • the embodiments of the present invention can efficiently implement the operation instruction scheduling of the NAND flash memory device, improve the flexibility of the operation instruction scheduling of the NAND flash memory device, and improve the overall performance of the NAND flash memory device.
  • the operation instruction of the NAND flash memory device in step S11 is subjected to task decomposition, which is specifically implemented by: updating NAND particles corresponding to the operation instruction from idle state to busy during execution of the operation instruction.
  • the time point of the state is used as a demarcation point, and the operation instruction is task-decomposed; wherein the NAND particle corresponds to a unique task queue to store the task obtained after the task is decomposed.
  • the task arbiter in order to ensure that the instruction sequence for operating the NAND particles meets the requirements, the task arbiter needs to follow the following principles when arbitrating the NAND interface:
  • the NAND interface can be arbitrated to the granule for operation only when the NAND particle is in an idle state
  • the time point at which the NAND particle is updated from the idle state to the busy state during the execution of the operation instruction is used as a demarcation point, and the NAND read/write operation instruction is decomposed into Multiple tasks, the specific implementation is as follows:
  • the erase operation break it down into 2 tasks.
  • the first task is the erase cmd task, which sends 60 commands on the NAND interface, then 3 beat addresses, then D0 commands to start NAND particles for erase operations;
  • the second task is the read status task, which is actually Read state operation, this task is used to query the state of the NAND particles until the NAND particles become free and return the pass/fail status returned by the NAND to the upper layer.
  • the first task is to write the IO task, which is to send 80 commands on the NAND interface, then 5 beat addresses, then transfer the entire page data on the NAND interface, and then send 10 commands to start the NAND particles for programming operations;
  • the second task Is the read status task, this task is used to query the state of the NAND particles until the NAND particles become free, and return the pass/fail status returned by the NAND to the upper layer.
  • the first task is the load task, which sends a 00 command on the NAND interface, then 5 beats the address, then sends 30 commands to start the NAND pellet for reading operations;
  • the second task is the read status task, which is used to query The state of the NAND particles until the NAND particles become idle; the third task is to read the IO task and transfer the read data back on the NAND interface.
  • the erase cmd task and the load task occupy the NAND interface for a very short time, and can start the NAND particles to start working, so they should have a higher priority to occupy the NAND interface.
  • the read status task takes up very little time on the NAND interface, and its early return status helps to give the NAND granule an operation, so it also has a higher priority.
  • the embodiments of the present invention refer to these three tasks as non-io tasks.
  • the method further includes: configuring task header information for each task, where the task header information includes a task type identifier task type For details, see Table 1.
  • the sending the current task to the corresponding arbitration queue according to the task type of the current task in the task queue in step S12 includes: determining, according to the task type identifier included in the task header information of the current task, The task type of the current task, and sending the current task to the corresponding arbitration queue according to the task type.
  • each NAND particle is provided with a task management module for maintaining its own state machine module, and the state machine module is responsible for taking the task and the corresponding header information from the task queue, and applying the application to the NAND task arbitrator. After the NAND interface is arbitrated, it waits for the NAND interface controller to complete the task.
  • the task When the granular state machine makes an application to the NAND task arbiter, the task is pushed into a different arbitration queue according to the task type in the header information. There are a total of three arbitration queues, which are non-IO arbitration queues, write IO arbitration queues and read IO arbitration queues, as shown in Figure 6.
  • the particle state opportunity pushes the erase cmd task sent by the software, and the load task is pushed into the non-IO queue.
  • the particle state opportunity automatically generates a read status task, which is also pushed into the non-IO queue.
  • the write IO task sent by the software will be pushed into the write IO queue, and the read IO task sent by the software will be pushed into the read IO queue.
  • each NAND particle has its own independent state machine, which is responsible for managing the state of the NAND particle, and automatically initiates a read status operation according to the timer value of the software configuration, and does not need to separately initiate a read status task to implement the operation efficiently.
  • the scheduling of instructions effectively improves the overall performance of NAND flash devices.
  • scheduling the NAND interface for the task to be executed in the arbitration queue according to the priority information of the arbitration queue further includes the following steps:
  • the non-IO arbitration queue is non-empty, extract the to-be-executed task from the non-IO arbitration queue, and schedule a NAND interface for the to-be-executed task;
  • the non-IO arbitration queue is empty, it is determined whether the task is stored in the write IO arbitration queue and the read IO arbitration queue. If the task is stored in both the write IO arbitration queue and the read IO arbitration queue, the task is executed according to the preset task.
  • the policy extracts the to-be-executed task from the write IO arbitration queue corresponding to the write IO task or the read IO arbitration queue corresponding to the read IO task, and schedules the NAND interface for the to-be-executed task; otherwise, directly extracts from the non-empty arbitration queue Perform the task.
  • the task type includes a non-IO task, a write IO task, and a read IO task
  • the write IO task and the read IO task have the same priority
  • the non-IO task has a higher priority than the write IO task.
  • the operation instruction scheduling method of the NAND flash memory device provided by the embodiment of the present invention further includes the step of determining the priority of the arbitration queue according to the task priority stored in the arbitration queue.
  • the task execution strategy preset in the embodiment of the present invention configures them to occupy the weight of the NAND interface.
  • registers can be employed to configure the weight they occupy on the NAND interface.
  • the task arbitrator of the NAND flash memory device is responsible for initiating arbitration for the task of the NAND granularity application, and its interface is three arbitration queues.
  • the non-IO arbitration queues in these three queues have the highest priority, and the write IO arbitration queue and the read arbitration IO queue have the same priority, but they can be configured to register their weights on the NAND interface.
  • FIG. 7 is a schematic diagram of an implementation of an operation instruction scheduling method of a NAND flash memory device according to an embodiment of the present invention.
  • the CPU interface is mainly an interface used by the task generation module to send a NAND task to the task management module, and a state in which the task arbiter returns a task execution result.
  • the task generation module can be implemented by software, and the NAND task sent is used to control the operation of the NAND interface controller on the one hand, and a task header information on the other hand.
  • the header information is mainly for the software to flexibly control the scheduling of the NAND task arbiter. Strategy.
  • the format and meaning of the task header information are shown in the following table:
  • Table 1 The format and meaning of the task header information
  • the task generation module is responsible for decomposing a NAND read and write operation into one or more tasks.
  • the software sends the erase cmd task to the hardware.
  • the task type is set to a non-io task, and the poll status enable is set to 1, and the timer value is filled in accordingly (for example, set to 15 milliseconds).
  • the task generation module does not need to separately send the read status task, because the read status task is initiated by the task management module itself.
  • the task generation module only needs to set the poll status enable to 1 in the task header information, and set the timer.
  • the task management module will automatically start the timer after completing the erase cmd task.
  • the read status task will be automatically started.
  • the task generation module sends a write IO task to the task management module.
  • set the task type to the write IO task set the poll status enable to 1, and fill in the timer value accordingly (for example, set to 1 millisecond).
  • the poll status enable is 1 in the task header information of the task just completed, the module will start a timer according to the timer value, and when the timer expires, a read status task is automatically generated and directed to the NAND.
  • the task arbitrator submits an application.
  • the operation is divided into two software tasks, the first task is the load task, the additional header information is set to the non-io task, and the poll status enable is set to 1, and the timer is filled accordingly. Value (for example, set to 80 microseconds).
  • the second task is to read the IO task.
  • the task type is set to read the IO task, and the poll status enable is set to 0, indicating that the hardware does not need to automatically initiate the read status task.
  • the task header information further includes a read status task enable identifier poll status enable.
  • the method further includes: after performing the task to be executed, determining the to-be-determined Whether the execution task is a read status task; if yes, determining a usage status of the corresponding NAND particle according to the execution result of the read status task, and when the usage status is busy, starting a timer, triggering reading after the preset timing time a status task, and sending the read status task to a corresponding arbitration queue, and when the usage status is idle, returning to the usage status to trigger sending the next task in the task queue to the corresponding arbitration queue.
  • the root when the task queue corresponding to the NAND particle is non-empty, the root extracts the task header information of the current task to be executed in the task queue, determines the task type in the header information, and according to the task type, The task to be executed is pushed into the corresponding arbitration queue, and waits for the NAND task arbiter to arbitrate the NAND interface to the task to be executed, waiting for the task to complete the execution of the NAND interface, and determining whether the task that has just been executed is a read state task, and if it is a read state task, And determining, according to the execution result of the read state task, a usage state of the corresponding NAND particle, when the usage state is busy, starting a timer timer, automatically triggering a read state task after the preset timing time timer, and the reading is performed The status task is sent to the corresponding non-IO arbitration queue.
  • the status task reads the read status task enable identifier poll status enable, when the read status task enable identifier
  • the poll status enable is 1
  • the timer timer is started
  • the read status task is triggered after the preset timing time timer, and the read status task is sent to the corresponding non-IO arbitration queue, when the read status task
  • the enable flag is disabled, that is, when the poll status enable is 0, the operation of sending the next task in the task queue to the corresponding arbitration queue is triggered.
  • the task header information further includes an interface exclusive license identifier.
  • the method further includes: reading the interface exclusive license after executing the to-be-executed task Identifying, when the interface exclusive license identifier is turned on, masking tasks corresponding to other NAND particles other than the current NAND particles, otherwise unblocking tasks corresponding to other NAND particles, and/or triggering the task queue The next task in the operation is sent to the corresponding arbitration queue.
  • the task header information includes an interface exclusive permission identifier (continue flag), and the continue flag is set to increase scheduling flexibility. For example, for multi-plane operation, a task that may require a granularity is completed as much as possible. Atomic. Setting the continue flag to 1 ensures that as long as the particle is dispatched, these tasks can be completed as quickly as possible, and other particles are masked out and not involved in arbitration.
  • the arbitration queue of the NAND particle when the arbitration queue of the NAND particle is not empty, it is first determined whether the non-IO arbitration queue is non-empty. If the non-IO arbitration queue is not empty, the task is removed from the non-IO arbitration queue arbitration.
  • the NAND interface controller executes, and waits for the task to read the exclusive flag of the interface in the task header information after the execution of the NAND interface is completed.
  • the interface exclusive license flag is enabled, that is, when the continue flag is set to 1, the current location is blocked.
  • the task corresponding to other NAND particles other than NAND particles otherwise, if other NAND particles are masked, the shielding of tasks corresponding to other NAND particles is released, and the next task in the task queue is triggered to be sent to the corresponding arbitration.
  • the operation of the queue if no NAND particles are masked, directly triggers the operation of sending the next task in the task queue to the corresponding arbitration queue. If the non-IO arbitration queue is empty, it is determined whether the task is stored in both the write IO arbitration queue and the read IO arbitration queue. If the task is stored in both the write IO arbitration queue and the read IO arbitration queue, the execution strategy is based on the preset task execution strategy.
  • the task header information further includes a task identifier ID.
  • the method further includes: monitoring and returning the task execution result after executing the to-be-executed task,
  • the task execution result carries the task identification ID of the to-be-executed task.
  • the task header information further includes a task identifier ID, that is, task no, and the task identifier ID is a task number assigned by the task generation module for the task, and is used for software management.
  • the task arbiter monitors and returns the task execution result, and returns the task identification ID at the same time.
  • the operation instruction scheduling method of the NAND flash memory device decomposes the NAND read/write operation into multiple tasks by using the time point when the NAND becomes busy, and performs scheduling by task.
  • the device task management module automatically initiates a read status task according to the timer value configured by the task generation module. Different tasks are divided into three types according to the needs of the scheduling policy, wherein non-IO tasks have the highest priority, while the read and write IO tasks are scheduled according to the software configuration they occupy the weight of the NAND interface.
  • the embodiment of the invention greatly reduces the load of the software and efficiently implements flexible scheduling of operation instructions of the NAND flash memory device.
  • the embodiment of the present invention specifically limits the number of NAND particles connected on one NAND interface, and can be set according to actual application requirements.
  • For each NAND particle it is not limited to only one timer, and the simple expansion of the technical solution of the present invention by using multiple timers also belongs to the spirit and scope of the technical solution of the embodiment of the present invention.
  • For the continue flag in the header information it is not limited to only one bit, and the use of multiple bits to represent different levels to achieve a simple extension of the present invention also belongs to the spirit and scope of the technical solutions of the embodiments of the present invention.
  • Fig. 10 is a block diagram showing the structure of an operation command scheduling device of a NAND flash memory device in accordance with an embodiment of the present invention.
  • the operation instruction scheduling apparatus of the NAND flash memory device of the embodiment of the present invention specifically includes a task generation module 201, a task management module 202, and a task arbiter 203, wherein: the task generation module 201 is configured to use a NAND flash memory device.
  • the operation instruction performs task decomposition, and sends the obtained task to the corresponding task queue.
  • the task management module 202 is configured to send the current task to the corresponding arbitration according to the task type of the current task in the task queue.
  • the task arbiter 203 is configured to schedule a NAND interface for the task to be executed in the arbitration queue according to the priority information of the arbitration queue.
  • the task generating module 201 is specifically configured to use, as a boundary, a time point at which the NAND particle corresponding to the operation instruction is updated from an idle state to a busy state during execution of the operation instruction. Pointing on task decomposition of the operation instruction;
  • the NAND particle corresponds to a unique task queue to store tasks obtained after the task is decomposed.
  • the task generation module 201 is further configured to configure task header information for each task after performing task decomposition on the operation instructions of the NAND flash memory device, where the task header information includes Have a task type identifier;
  • the task management module 202 is specifically configured to determine a task type of the current task according to the task type identifier included in the task header information of the current task, and send the current task to a corresponding arbitration according to the task type. queue.
  • the task type includes a non-IO task, a write IO task, and a read IO task, the write IO task and the read IO task have the same priority, and the priority of the non-IO task Higher than the write IO task and the read IO task;
  • the task arbiter 203 is further configured to determine a priority of the arbitration queue according to the task priority stored in the arbitration queue.
  • the task arbiter 203 includes a first determining unit and an arbitration unit, where the first determining unit is configured to determine whether a non-IO arbitration queue corresponding to the non-IO task is non-empty; When the result of the determination by the first determining unit is that the non-IO arbitration queue is non-empty, the task to be executed is extracted from the non-IO arbitration queue, and the NAND interface is scheduled for the task to be executed, when the first determining unit determines When the result is that the non-IO arbitration queue is empty, the task to be executed is extracted from the write IO arbitration queue corresponding to the write IO task or the read IO arbitration queue corresponding to the read IO task according to the preset task execution policy, and is the task to be executed. Dispatched the NAND interface.
  • the task arbiter 203 further includes: a second determining unit, configured to: when the arbitration unit performs a policy according to a preset task execution strategy, corresponding to a write IO arbitration queue or a read IO task corresponding to the write IO task Before extracting the to-be-executed task in the read IO arbitration queue, determining whether the task is stored in the write IO arbitration queue and the read IO arbitration queue;
  • the arbitration unit performs the operation of extracting the to-be-executed task from the write IO arbitration queue corresponding to the write IO task or the read IO arbitration queue corresponding to the read IO task according to the preset task execution policy. Otherwise, the arbitration The unit extracts the task to be executed directly from the non-empty arbitration queue.
  • the task header information further includes a read status task enable identifier.
  • the task management module 202 further includes a third determining unit and a task triggering unit, wherein: the third determining unit is configured to: in the arbitration queue, the priority information according to the arbitration queue After the NAND interface is scheduled to be executed, and after the task to be executed is executed, it is determined whether the task to be executed is a read state task; and the task triggering unit is configured to: when the determination result of the third determining unit is the When the task to be executed is a read state task, determining a usage state of the corresponding NAND particle according to the execution result of the read state task, when the usage state is busy, starting a timer, and triggering the read state task after the preset timing time And sending the read status task to the corresponding arbitration queue, and when the use status is idle, returning to the use status to trigger an operation of sending the next task in the task queue to the corresponding arbitration queue;
  • the task triggering unit is further configured to: when the determination result of the third determining unit is that the to-be-executed task is not a read-state task, read the read-state task enable identifier, and when the read-state task enable identifier is enabled
  • the timer is started, the read status task is triggered after the preset timing time, and the read status task is sent to the corresponding arbitration queue.
  • the read status task enable identifier is closed, the trigger is performed in the task queue. The next task is sent to the corresponding arbitration queue.
  • the task header information further includes an interface exclusive license identifier.
  • the task arbiter 203 further includes an exclusive control unit, configured to: after scheduling the NAND interface for the task to be executed in the arbitration queue according to the priority information of the arbitration queue, and After the task to be executed is performed, the interface exclusive license identifier is read, and when the interface exclusive license identifier is turned on, the task corresponding to the other NAND particles except the current NAND particle is masked, otherwise the other NAND is released. The masking of the tasks corresponding to the particles, and/or the operation of triggering the next task in the task queue to be sent to the corresponding arbitration queue.
  • the task header information further includes a task identifier ID.
  • the task arbiter 203 further includes an execution result monitoring unit, configured to: after scheduling the NAND interface for the task to be executed in the arbitration queue according to the priority information of the arbitration queue, After the execution of the to-be-executed task, the task execution result is monitored and returned, and the task execution result carries the task identification ID of the to-be-executed task.
  • the operation instruction scheduling method and device of the NAND flash memory device of the present invention decomposes an operation instruction into a plurality of tasks by performing task decomposition on an operation instruction of the NAND flash memory device, and sends the obtained task to a corresponding task queue, and then according to The task type of the current task in the queue sends the task to the corresponding arbitration queue, so that the task arbiter can schedule the NAND interface for the task to be executed in the arbitration queue according to the priority of the arbitration queue.
  • the embodiment of the present invention performs scheduling in units of tasks, can efficiently implement operation instruction scheduling of the NAND flash memory device, improve flexibility of operation instruction scheduling of the NAND flash memory device, and improve overall performance of the NAND flash memory device.
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

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Abstract

一种NAND闪存设备的操作指令调度方法及装置，所述方法包括：对NAND闪存设备的操作指令进行任务分解，并将得到的任务发送到对应的任务队列（S11）；根据所述任务队列中当前任务的任务类型将所述当前任务发送到对应的仲裁队列（S12）；根据所述仲裁队列的优先级信息为所述仲裁队列中的待执行任务调度NAND接口（S13）。该方法及装置能够高效地实现NAND闪存设备的操作指令调度，提高NAND闪存设备的操作指令调度的灵活性，提升NAND闪存设备的总体性能。

Description

一种NAND闪存设备的操作指令调度方法及装置 技术领域
本发明涉及数据存储技术领域，尤其涉及一种NAND闪存设备的操作指令调度方法及装置。
背景技术
NAND闪存是一种比硬盘驱动器更好的存储方案，这在不超过4GB的低容量应用中表现得犹为明显。随着人们持续追求功耗更低、重量更轻和性能更佳的产品，NAND正被证明极具吸引力。目前NAND闪存技术广泛应用于固态硬盘等领域，与传统机械硬盘相比，固态硬盘在存取速度上有了大幅的提升。现在的NAND接口速度越来越快，由原来的异步模式变为现在的DDR(Double Data Rate，双倍速率同步动态随机存储器)模式，最新的NAND闪存颗粒已经能达到每秒667MB的速度。而与此同时，为了提高存储容量，NAND闪存的页尺寸变得越来越大，访问一页的时间反而增加了。因此，为了充分利用NAND接口的带宽，同时也是为了增加存储容量，一条NAND接口会连接多个NAND颗粒，这样就需要对NAND指令的顺序进行调度。调度策略一方面要保证正确性，保证操作NAND颗粒的指令序列符合要求，另一方面要尽可能充分利用NAND接口与NAND颗粒的性能。
现有的NAND闪存设备的操作指令调度方案大多是采用软件进行调度。主要有两方面原因：一方面是调度策略比较复杂，而且需求可能会变化，使用软件方案方便修改，有更高的灵活性；另一方面是原来NAND接口的性能要求并不高，软件有能力来满足性能要求。但是，随着当前大容量高速固态硬盘发展迅速，IOPS(Input/Output Operations Per Second，每秒进行读写I/O操作的次数)性能已经达到百万级，而且延迟也越来越低，因此，使用软件来实现NAND闪存设备的操作指令调度已经无法满足性能要求。
发明内容
本发明提出了一种NAND闪存设备的操作指令调度方法及装置，能够高效地实现NAND闪存设备的操作指令调度，提高NAND闪存设备的操作指令调度的灵活性，提升NAND闪存设备的总体性能。
为解决上述技术问题，本发明采用如下技术方案：
本发明的一个方面，提供了一种NAND闪存设备的操作指令调度方法，包括：
对NAND闪存设备的操作指令进行任务分解，并将得到的任务发送到对应的任务队列；
根据所述任务队列中当前任务的任务类型将所述当前任务发送到对应的仲裁队列；
根据所述仲裁队列的优先级信息为所述仲裁队列中的待执行任务调度NAND接口。
其中，所述对NAND闪存设备的操作指令进行任务分解，包括：
将所述操作指令对应的NAND颗粒在执行所述操作指令过程中由空闲状态更新为繁忙状态的时间点作为分界点，对所述操作指令进行任务分解；
其中，所述NAND颗粒对应有唯一的任务队列，以存放任务分解后得到的任务。
其中，在所述对NAND闪存设备的操作指令进行任务分解之后，所述方法还包括：
为每一任务配置任务头信息，所述任务头信息中包含有任务类型标识；
所述根据所述任务队列中当前任务的任务类型将所述当前任务发送到对应的仲裁队列，包括：
根据所述当前任务的任务头信息中包含的任务类型标识确定所述当前任务的任务类型，并根据所述任务类型将所述当前任务发送到对应的仲裁队列。
其中，所述任务类型包括非IO任务、写IO任务和读IO任务，所述写IO任务和读IO任务的优先级相同，所述非IO任务的优先级高于所述写IO任务和读IO任务；
所述方法还包括：
根据所述仲裁队列中存放的任务优先级确定仲裁队列的优先级。
其中，所述根据所述仲裁队列的优先级信息为所述仲裁队列中的待执行任务调度NAND接口，包括：
判定非IO任务对应的非IO仲裁队列是否为非空；
若是，则从所述非IO仲裁队列中提取待执行任务，并为所述待执行任务调度NAND接口；
否则，根据预先设置的任务执行策略从写IO任务对应的写IO仲裁队列或读IO任务对应的读IO仲裁队列中提取待执行任务，并为所述待执行任务调度NAND接口。
其中，在所述根据预先设置的任务执行策略从写IO任务对应的写IO仲裁队列或读IO任务对应的读IO仲裁队列中提取待执行任务之前，所述方法还包括：
判定所述写IO仲裁队列和读IO仲裁队列中是否都存放有任务；
若是，则执行所述根据预先设置的任务执行策略从写IO任务对应的写IO仲裁队列或读IO任务对应的读IO仲裁队列中提取待执行任务的步骤，否则，直接从非空的仲裁队列中提取待执行任务。
其中，所述任务头信息中还包含有读状态任务使能标识；
在所述根据所述仲裁队列的优先级信息为所述仲裁队列中的待执行任务调度NAND接口之后，所述方法还包括：
在执行完所述待执行任务之后，判定所述待执行任务是否为读状态任务；
若是，则根据所述读状态任务的执行结果确定对应的NAND颗粒的使用状态，当所述使用状态为繁忙时，启动定时器，在预设定时时间后触发读状态任务，并将该读状态任务发送到对应的仲裁队列，当所述使用状态为空闲时，返回所述使用状态，以触发将所述任务队列中的下一任务发送到对应的仲裁队列的操作；
否则，读取所述读状态任务使能标识，当所述读状态任务使能标识开启时，启动定时器，在预设定时时间后触发读状态任务，并将该读状态任务发送到对应的仲裁队列，当所述读状态任务使能标识关闭时，触发将所述任务队列中的下一任务发送到对应的仲裁队列的操作。
其中，所述任务头信息中还包含有接口独占许可标识；
在所述根据所述仲裁队列的优先级信息为所述仲裁队列中的待执行任务调度NAND接口之后，所述方法还包括：
在执行完所述待执行任务之后，读取所述接口独占许可标识，当所述接口独占许可标识开启时，屏蔽当前的所述NAND颗粒之外的其他NAND颗粒对应的任务，否则解除对其他NAND颗粒对应的任务的屏蔽，和/或触发将所述任务队列中的下一任务发送到对应的仲裁队列的操作。
其中，所述任务头信息中还包含有任务标识ID；
在所述根据所述仲裁队列的优先级信息为所述仲裁队列中的待执行任务调度NAND接口之后，所述方法还包括：
在执行完所述待执行任务之后，监测并返回任务执行结果，所述任务执行结果中携带有所述待执行任务的任务标识ID。
本发明的又一个方面，提供了一种NAND闪存设备的操作指令调度装置，包括：
任务生成模块，用于对NAND闪存设备的操作指令进行任务分解，并将得到的任务发送到对应的任务队列；
任务管理模块，用于根据所述任务队列中当前任务的任务类型将所述当前任务发送到对应的仲裁队列；
任务仲裁器，用于根据所述仲裁队列的优先级信息为所述仲裁队列中的待执行任务调度NAND接口。
其中，所述任务生成模块，还用于在对NAND闪存设备的操作指令进行任务分解之后，为每一任务配置任务头信息，所述任务头信息中包含有任务类型标识；
所述任务管理模块，具体用于根据所述当前任务的任务头信息中包含的任务类型标识确定所述当前任务的任务类型，并根据所述任务类型将所述当前任务发送到对应的仲裁队列。
与现有技术相比，本发明技术方案主要的优点如下：
本发明通过对NAND闪存设备的操作指令进行任务分解，将一条操作指令分解为多条任务，并将得到的任务发送到对应的任务队列，然后根据队列中当前任务的任务类型将任务发送到对应的仲裁队列，以供任务仲裁器根据仲裁队列的优先级为仲裁队列中的待执行任务调度NAND接口。本发明实施例能够高效地实现NAND闪存设备的操作指令调度，提高NAND闪存设备的操作指令调度的灵活性，提升NAND闪存设备的总体性能。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在所写的说明书、权利要求书、以及附图中所特别指出的结构来实现和获得。
下面通过附图和实施例，对本发明的技术方案做进一步的详细描述。
附图说明
通过阅读下文优选实施方式的详细描述，各种其他的优点和益处对于本领域普通技术人员将变得清楚明了。附图仅用于示出优选实施方式的目的，而并不认为是对本发明的限制。而且在整个附图中，用相同的参考符号表示相同的部件。在附图中：
图1为本发明实施例提出的块擦除操作指令的序列示意图；
图2为本发明实施例提出的页编程操作指令的序列示意图；
图3为本发明实施例提出的页读取操作指令的序列示意图；
图4为本发明实施例提出的读状态操作指令的序列示意图；
图5为本发明实施例一种NAND闪存设备的操作指令调度方法的流程图；
图6为本发明实施例一种NAND闪存设备的操作指令调度方法中仲裁队列的实现原理图；
图7为本发明实施例一种NAND闪存设备的操作指令调度方法的实现原理图；
图8为本发明实施例一种NAND闪存设备的操作指令调度方法的具体实现流程；
图9为本发明另一实施例一种NAND闪存设备的操作指令调度方法的具体实现流程；
图10为本发明实施例一种NAND闪存设备的操作指令调度装置的结构框图。
具体实施方式
下面将参照附图更详细地描述本公开的示例性实施例。虽然附图中显示了本公开的示例性实施例，然而应当理解，可以以各种形式实现本公开而不应被这里阐述的实施例所限制。相反，提供这些实施例是为了能够更透彻地理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。
为了更好地理解本发明技术方案，首先对NAND闪存的操作指令进行简单的说明。
NAND闪存有四种基本操作指令：第一种是块擦除(block erase)，它以块为单位，对整个块执行擦除操作，它在NAND接口上的操作序列如图1所示。参见图1，首先在NAND接口上发送60命令，然后3拍地址，再发D0命令，即可启动NAND颗粒执行擦除操作。执行该操作时NAND颗粒的状态变为繁忙(图中的SR[6]变为低)，等待t BERS时间以后，才重新变为空闲。在状态为繁忙时，这个NAND颗粒不能接收其他读写命令，但可以接受读状态操作。
第二种是页编程(page program)，它以页为单位，对整页进行编程操作，它在NAND接口上的操作序列如图2所示。参见图2，首先在NAND接口上发送80命令，然后5拍地址，再传送数据，一般是整页数据，现在NAND颗粒多为16KB，然后发10命令确认启动NAND颗粒执行编程操作。执行该操作时NAND颗粒的状态变为繁忙(图中的RDY变为低)，等待t PROG时间以后，才重新变为空闲。在状态为繁忙时，这个NAND颗粒不能接收其他读写命令，但可以接受读状态操作。
第三种是页读(page read)，它以页为单位，将页里的数据读出来，它在NAND接口上的操作序列如图3所示。参见图3，首先在NAND接口上发送00命令，然后5拍地址，再发 30命令确认启动NAND颗粒执行读操作，NAND颗粒会将数据从内部的存储单元读取到它内部的缓存寄存器(cache register)中。执行该操作时NAND颗粒的状态变为繁忙(图中的RDY变为低)，等待t R时间以后，才重新变为空闲。在状态为繁忙时，这个NAND颗粒不能接收其他读写命令，但可以接受读状态操作。当状态由繁忙变为空闲(图中的RDY由低变为高)时，才可以通过NAND接口来从缓存寄存器读取数据。
第四种是读状态操作，它用于查询NAND颗粒的状态。NAND颗粒处于繁忙的时间随操作的不同而不同。即使对于同一操作，不同的NAND颗粒，甚至同一NAND颗粒的不同状态也会影响繁忙时间的长短，因此一般使用读状态(read status)操作来查询NAND颗粒什么时候变为空闲。读状态操作有不同的形式，本发明实施例中以最简单的70命令为例进行说明，它在NAND接口上的操作序列如图4所示。参见图4，首先在NAND接口上发送70命令，稍等一小段时间t WHR，即可通过NAND接口读取一个字节的状态。
可理解的是，除了这4种基本操作指令以外，还有其他一些操作指令，比如reset操作，read id操作，set feature操作等等，但这些操作多是低频操作，或者执行时间比较短，对于实际应用来说，不会是性能的瓶颈。本发明实施例仅以NAND闪存设备的基本读写操作为例对本发明技术方案进行解释说明，但本发明并不局限于这些简单操作，对于NAND闪存设备的复杂操作序列，比如multi-plane操作，cache操作，interleaved die操作等等，均属于本发明的简单扩展，均可通过本发明实施例的技术方案实现。
从调度策略来说，有两种资源需要管理：一是NAND接口；二是NAND颗粒。下面从这两个资源的角度来看上述的4种基本操作指令。
块擦除的特点如下：1.占用NAND接口时间比较短，应该在微秒级。2.NAND颗粒执行擦除需要的时间比较长，最新的闪存颗粒可能需要10毫秒以上。
页编程特点如下：1.占用NAND接口时间比较长，因为整页数据需要一拍一拍地顺序流过NAND接口。2.NAND颗粒执行编程操作需要的时间比擦除要短一些，最新的闪存颗粒大概在1毫秒的量级。
页读特点如下：1.占用NAND接口时间由读取数据的数量决定。对于块设备来说，可能是512B或4KB的整数倍。一般来说，它占用NAND接口时间比块擦除时间长得多，但可能比页编程操作短。2.NAND颗粒执行读操作需要的时间相对较短，最新的闪存颗粒一般在100微秒以内。
读状态操作特点如下：1.占用NAND接口时间短，应该在微秒级。2.NAND颗粒执行时 间很短。
由于NAND接口的带宽大于NAND颗粒的带宽，因此多个NAND颗粒共享同一个NAND接口，因此提出本发明NAND闪存设备的操作指令调度方法，以高效地实现NAND闪存设备的操作指令调度，提高NAND闪存设备的操作指令调度的灵活性，提升NAND闪存设备的总体性能。下面结合附图对对本申请实施例技术方案的主要实现原理、具体实施方式及其对应能够达到的有益效果进行详细的阐述。
图5示意性示出了本发明一个实施例的NAND闪存设备的操作指令调度方法的流程图。参照图5，本发明实施例的NAND闪存设备的操作指令调度方法具体包括以下步骤：
S11、对NAND闪存设备的操作指令进行任务分解，并将得到的任务发送到对应的任务队列。
本发明实施例中，NAND闪存设备的每一操作指令均对应有至少一个执行对象，即目标NAND颗粒，每一个NAND颗粒都维护有一个任务队列，任务生成模块对NAND闪存设备的操作指令进行任务分解之后，把针对这个NAND颗粒的任务发送到对应的任务队列。本发明实施例采用队列的方式实现分解后得到的任务的存放，可以有效地减少任务的延时。
S12、根据所述任务队列中当前任务的任务类型将所述当前任务发送到对应的仲裁队列。
本发明实施例中，所述任务类型包括非IO任务、写IO任务和读IO任务。具体的，任务分解后，得到不同任务类型的任务，然后可根据任务队列中当前任务的任务类型将所述当前任务发送到对应的仲裁队列。
S13、根据所述仲裁队列的优先级信息为所述仲裁队列中的待执行任务调度NAND接口。
本发明实施例提供的NAND闪存设备的操作指令调度方法，通过对NAND闪存设备的操作指令进行任务分解，将一条操作指令分解为多条任务，并将得到的任务发送到对应的任务队列，然后根据队列中当前任务的任务类型将任务发送到对应的仲裁队列，以供任务仲裁器根据仲裁队列的优先级为仲裁队列中的待执行任务调度NAND接口。本发明实施例能够高效地实现NAND闪存设备的操作指令调度，提高NAND闪存设备的操作指令调度的灵活性，提升NAND闪存设备的总体性能。
本发明实施例中，步骤S11中的对NAND闪存设备的操作指令进行任务分解，具体通过以下步骤实现：将所述操作指令对应的NAND颗粒在执行所述操作指令过程中由空闲状态更新为繁忙状态的时间点作为分界点，对所述操作指令进行任务分解；其中，所述NAND颗粒对应有唯一的任务队列，以存放任务分解后得到的任务。
本发明实施例中，为了确保操作NAND颗粒的指令序列符合要求，任务仲裁器在对NAND接口进行仲裁时需要遵循以下原则：
1.只有NAND颗粒处于空闲状态时，才能将NAND接口仲裁给该颗粒进行操作；
2.当NAND接口正被某个颗粒占用时，要等该颗粒至少完成当前任务才能将接口仲裁给其他颗粒；
3.尽可能让更多的NAND颗粒同时工作起来，这样才能充分利用NAND接口的带宽；
4.对于同一个NAND颗粒的访问，必须保证操作的前后顺序；
5.对于不同NAND颗粒的访问，不保证他们之间的操作顺序，如果对操作有顺序要求，由更上一层的机制来保证。
根据这些原则以及上述四种NAND基本操作的特点，本发明实施例中以NAND颗粒在执行操作指令过程中由空闲状态更新为繁忙状态的时间点作为分界点，将NAND的读写操作指令分解为多个任务，具体实现如下：
1.对于擦除操作，将它分解为2个任务。第1个任务是erase cmd任务，它是在NAND接口上发送60命令，然后3拍地址，再发D0命令，启动NAND颗粒进行擦除操作；第2个任务是read status任务，它实际上就是读状态操作，这个任务用来查询NAND颗粒的状态，直到NAND颗粒变得空闲，并将NAND返回的pass/fail状态返回给上层。
2.对于编程操作，将它分解为2个任务。第1个任务是写IO任务，它是在NAND接口上发送80命令，然后5拍地址，然后在NAND接口上传输整页数据，再发10命令，启动NAND颗粒进行编程操作；第2个任务是read status任务，这个任务用来查询NAND颗粒的状态，直到NAND颗粒变得空闲，并将NAND返回的pass/fail状态返回给上层。
3.对于页读操作，将它分解为3个任务。第1个任务是load任务，它是在NAND接口上发送00命令，然后5拍地址，再发30命令，启动NAND颗粒进行读取操作；第2个任务是read status任务，这个任务用来查询NAND颗粒的状态，直到NAND颗粒变得空闲；第3个任务是读IO任务，在NAND接口上传输读取回来的数据。
其中，erase cmd任务和load任务占用NAND接口的时间非常短，而且能够启动NAND颗粒开始工作，因此他们应该具有比较高的优先级来占用NAND接口。read status任务占用NAND接口时间也非常短，而且它早点返回状态有助于给这个NAND颗粒发下一个操作，因此它也具有比较高的优先级。本发明实施例将这3个任务称为非io任务。
在本发明实施例中，在所述对NAND闪存设备的操作指令进行任务分解之后，所述方法还包括：为每一任务配置任务头信息，所述任务头信息中包含有任务类型标识task type，具体可参见表1。
相应的，步骤S12中的根据所述任务队列中当前任务的任务类型将所述当前任务发送到对应的仲裁队列，包括：根据所述当前任务的任务头信息中包含的任务类型标识确定所述当前任务的任务类型，并根据所述任务类型将所述当前任务发送到对应的仲裁队列。
本发明实施例中，每个NAND颗粒都设置有任务管理模块，用于维护自己的状态机模块，状态机模块负责从任务队列中取出任务及相应的头信息，向NAND任务仲裁器提起申请占据NAND接口，得到仲裁以后，等待NAND接口控制器将任务完成。
颗粒状态机向NAND任务仲裁器提起申请时，会根据头信息中的任务类型将任务压入不同的仲裁队列。一共有3个仲裁队列，分别是非IO仲裁队列，写IO仲裁队列和读IO仲裁队列，如图6所示。参见图6，颗粒状态机会将软件发过来的erase cmd任务，load任务压入非IO队列，当timer到时以后，颗粒状态机会自动产生一个read status任务，将它也压入非IO队列。软件发过来的写IO任务会压入写IO队列，软件发过来的读IO任务会压入读IO队列。本发明实施例中，每个NAND颗粒有自己独立的状态机，它负责管理NAND颗粒的状态，并根据软件配置的timer值自动发起read status操作，不需要单独发起read status任务，高效地实现操作指令的调度，有效地提升了NAND闪存设备的总体性能。
进一步地，所述根据所述仲裁队列的优先级信息为所述仲裁队列中的待执行任务调度NAND接口，进一步包括以下步骤：
判定非IO任务对应的非IO仲裁队列是否为非空；
若非IO仲裁队列为非空，则从所述非IO仲裁队列中提取待执行任务，并为所述待执行任务调度NAND接口；
若非IO仲裁队列为空，则判定所述写IO仲裁队列和读IO仲裁队列中是否都存放有任务，若写IO仲裁队列和读IO仲裁队列中都存放有任务，则根据预先设置的任务执行策略从写IO任务对应的写IO仲裁队列或读IO任务对应的读IO仲裁队列中提取待执行任务，并为所述待执行任务调度NAND接口；否则，直接从非空的仲裁队列中提取待执行任务。
本发明实施例中，任务类型包括非IO任务、写IO任务和读IO任务，所述写IO任务和读IO任务的优先级相同，所述非IO任务的优先级高于所述写IO任务和读IO任务。本发明实施例提供的NAND闪存设备的操作指令调度方法，还包括根据所述仲裁队列中存放的任务 优先级确定仲裁队列的优先级的步骤。
需要说明的是，由于写IO任务和读IO任务都需要占据NAND接口较长的时间，因此处于较低的优先级。理论上来说，他们具有同样的重要性，但是为了增加灵活性，允许上层调节读写的比例，本发明实施例预先设置的任务执行策略配置他们占据NAND接口的权重。在一个具体示例中，可采用寄存器来配置他们占据NAND接口的权重。因为一般来说写IO传输的数据量是一整页，而读IO传输的数据可能是一页的一部分，因此可以配置寄存器来设置一次写IO任务以后允许传输几次读IO任务，如果没有读IO任务的话，则继续仲裁写IO任务。本发明实施例中，NAND闪存设备的任务仲裁器负责对NAND颗粒申请的任务发起仲裁，它的接口是3个仲裁队列。这3个队列中非IO仲裁队列优先级最高，写IO仲裁队列和读仲裁IO队列拥有同样的优先级，但可以通过寄存器配置他们占据NAND接口的权重。
图7为本发明实施例提供的NAND闪存设备的操作指令调度方法的实现原理图。参见图7，其中CPU接口主要是任务生成模块用来给任务管理模块发送NAND任务，以及接收任务仲裁器返回任务执行结果的状态的接口。任务生成模块可由软件实现，其发送的NAND任务一方面用于控制NAND接口控制器进行操作，另一方面还包含一个任务头信息，这个头信息主要是为了软件灵活地控制NAND任务仲裁器的调度策略。任务头信息的格式及含义如下表所示：
表1任务头信息的格式及含义
Figure PCTCN2017114939-appb-000001
Figure PCTCN2017114939-appb-000002
其中，任务生成模块负责将一个NAND读写操作分解为一个或多个任务。对于块擦除操作，软件发送erase cmd任务给硬件，附加的头信息中将task type设为非io任务，并将poll status enable置1，并相应地填好timer value(比如设置为15毫秒)。本实施例中，任务生成模块不用单独发送read status任务，这是因为read status任务是由任务管理模块自己发起的。任务生成模块只需在任务头信息中将poll status enable置1，并设置好timer，任务管理模块会在完成erase cmd任务之后自动启动timer，等待timer到时以后，会自动发起read status任务。对于页编程操作，任务生成模块发送写IO任务给任务管理模块。附加的头信息中将task type设为写IO任务，并将poll status enable置1，并相应地填好timer value(比如设置为1毫秒)。在实际应用中，当刚完成任务的任务头信息中poll status enable为1时，则该模块会根据timer value来启动一个timer，等timer到时以后，会自动产生一个read status任务，并向NAND任务仲裁器提出申请。对于页读操作，将操作分为2个软件任务，第一个任务是load任务，附加的头信息中将task type设为非io任务，并将poll status enable置1，并相应地填好timer value(比如设置为80微秒)。第二个任务是读IO任务，附加的头信息中将task type设为读IO任务，并将poll status enable置0，表示不需要硬件自动发起read status任务。
在本发明的一个可选实施例中，所述任务头信息中还包含有读状态任务使能标识poll status enable。相应的，在所述根据所述仲裁队列的优先级信息为所述仲裁队列中的待执行任务调度NAND接口之后，所述方法还包括：在执行完所述待执行任务之后，判定所述待执行任务是否为读状态任务；若是，则根据所述读状态任务的执行结果确定对应的NAND颗粒的使用状态，当所述使用状态为繁忙时，启动定时器，在预设定时时间后触发读状态任务，并将该读状态任务发送到对应的仲裁队列，当所述使用状态为空闲时，返回所述使用状态，以触发将所述任务队列中的下一任务发送到对应的仲裁队列的操作；否则，读取所述读状态任务使能标识，当所述读状态任务使能标识开启时，启动定时器，在预设定时时间后触发读状态任务，并将该读状态任务发送到对应的仲裁队列，当所述读状态任务使能标识关闭时，触发将所述任务队列中的下一任务发送到对应的仲裁队列的操作。
下面通过一个具体实施例对本发明技术方案进行详细的解释说明。
参见图8，本发明实施例中，当NAND颗粒对应的任务队列为非空时，根提取任务队列中当前待执行任务的任务头信息，判定头信息中的任务类型，并根据任务类型，将待执行任务压入对应的仲裁队列，等待NAND任务仲裁器将NAND接口仲裁给待执行任务，等待任务在NAND接口执行完毕后，判定刚执行完毕的任务是否为读状态任务，若是读状态任务，则根据所述读状态任务的执行结果确定对应的NAND颗粒的使用状态，当所述使用状态为繁忙时，启动定时器timer，在预设定时时间timer后自动触发读状态任务，并将该读状态任务发送到对应的非IO仲裁队列，当所述使用状态为空闲时，返回所述使用状态，并触发将所述任务队列中的下一任务发送到对应的仲裁队列的操作；若不是读状态任务，则读取所述读状态任务使能标识poll status enable，当所述读状态任务使能标识开启时，即当poll status enable为1时，启动定时器timer，在预设定时时间timer后触发读状态任务，并将该读状态任务发送到对应的非IO仲裁队列，当所述读状态任务使能标识关闭时，即当poll status enable为0时，触发将所述任务队列中的下一任务发送到对应的仲裁队列的操作。
在本发明的一个可选实施例中，所述任务头信息中还包含有接口独占许可标识。
相应的。在所述根据所述仲裁队列的优先级信息为所述仲裁队列中的待执行任务调度NAND接口之后，所述方法还包括：在执行完所述待执行任务之后，读取所述接口独占许可标识，当所述接口独占许可标识开启时，屏蔽当前的所述NAND颗粒之外的其他NAND颗粒对应的任务，否则解除对其他NAND颗粒对应的任务的屏蔽，和/或触发将所述任务队列中的下一任务发送到对应的仲裁队列的操作。
本发明实施例中，任务头信息中包含有接口独占许可标识continue flag，continue flag的设置是为了增加调度的灵活性，比如对于multi-plane操作时，可能需要一个颗粒的任务尽量一起完成，保持原子性。将continue flag置1，可以保证只要这个颗粒被调度到，这些任务就可以尽快完成，其他的颗粒被屏蔽掉，不参与仲裁。
下面通过一个具体实施例对本发明技术方案进行详细的解释说明。
参见图9，本发明实施例中，当NAND颗粒的仲裁队列非空时，首先判定非IO仲裁队列是否为非空，若非IO仲裁队列非空，则从非IO仲裁队列仲裁中取出任务发送到NAND接口控制器执行，等待任务在NAND接口执行完毕后，读取任务头信息中的接口独占许可标识continue flag，当所述接口独占许可标识开启时，即continue flag置1时，屏蔽当前的所述NAND颗粒之外的其他NAND颗粒对应的任务，否则，如果别的NAND颗粒被屏蔽，则解除对其他NAND颗粒对应的任务的屏蔽，并触发将任务队列中的下一任务发送到对应的仲裁队列的 操作，如果没有NAND颗粒被屏蔽，则直接触发将任务队列中的下一任务发送到对应的仲裁队列的操作。若非IO仲裁队列为空，则判定写IO仲裁队列和读IO仲裁队列中是否都存放有任务，若写IO仲裁队列和读IO仲裁队列中都存放有任务，则根据预先设置的任务执行策略从写IO任务对应的写IO仲裁队列或读IO任务对应的读IO仲裁队列中提取待执行任务，并为所述待执行任务调度NAND接口；否则，直接从非空的仲裁队列中提取待执行任务，并为所述待执行任务调度NAND接口。
在本发明的一个可选实施例中，所述任务头信息中还包含有任务标识ID。
在所述根据所述仲裁队列的优先级信息为所述仲裁队列中的待执行任务调度NAND接口之后，所述方法还包括：在执行完所述待执行任务之后，监测并返回任务执行结果，所述任务执行结果中携带有所述待执行任务的任务标识ID。
本发明实施例中，任务头信息中还包含有任务标识ID，即task no，任务标识ID是任务生成模块为任务分配的任务号，用于软件的管理。在执行完所述待执行任务之后，任务仲裁器监测并返回任务执行结果，会同时将任务标识ID返回。
综上所述，本发明实施例提供的NAND闪存设备的操作指令调度方法，将NAND读写操作以NAND变繁忙的时间点为分界线分解为多个任务，以任务为单位进行调度，由硬件设备任务管理模块根据任务生成模块配置的timer值自动发起read status任务。将不同的任务根据调度策略的需要划分为3种类型，其中非IO任务具有最高的优先级，而读写IO任务则根据软件配置他们占据NAND接口的权重进行调度。本发明实施例大大减少了软件的负载，高效地实现NAND闪存设备的操作指令的灵活调度。
可理解的是，本发明实施例对一个NAND接口上连接的NAND颗粒的数量进行具体限定，可根据实际应用需求进行设置。对于每个NAND颗粒，不限于只有一个timer，使用多个timer对本发明技术方案进行简单扩展，也属于本发明实施例技术方案的精神和范围。对于头信息中的continue flag，不限于只有一位，使用多位来代表不同的级别以实现对本发明的简单扩展，也属于本发明实施例技术方案的精神和范围。
对于方法实施例，为了简单描述，故将其都表述为一系列的动作组合，但是本领域技术人员应该知悉，本发明实施例并不受所描述的动作顺序的限制，因为依据本发明实施例，某些步骤可以采用其他顺序或者同时进行。其次，本领域技术人员也应该知悉，说明书中所描述的实施例均属于优选实施例，所涉及的动作并不一定是本发明实施例所必须的。
图10示意性示出了本发明一个实施例的NAND闪存设备的操作指令调度装置的结构框 图。参照图10，本发明实施例的NAND闪存设备的操作指令调度装置具体包括任务生成模块201、任务管理模块202以及任务仲裁器203，其中：所述的任务生成模块201，用于对NAND闪存设备的操作指令进行任务分解，并将得到的任务发送到对应的任务队列；所述的任务管理模块202，用于根据所述任务队列中当前任务的任务类型将所述当前任务发送到对应的仲裁队列；所述的任务仲裁器203，用于根据所述仲裁队列的优先级信息为所述仲裁队列中的待执行任务调度NAND接口。
在本发明的一个可选实施例中，所述任务生成模块201，具体用于将所述操作指令对应的NAND颗粒在执行所述操作指令过程中由空闲状态更新为繁忙状态的时间点作为分界点，对所述操作指令进行任务分解；
其中，所述NAND颗粒对应有唯一的任务队列，以存放任务分解后得到的任务。
在本发明的一个可选实施例中，所述任务生成模块201，还用于在对NAND闪存设备的操作指令进行任务分解之后，为每一任务配置任务头信息，所述任务头信息中包含有任务类型标识；
所述任务管理模块202，具体用于根据所述当前任务的任务头信息中包含的任务类型标识确定所述当前任务的任务类型，并根据所述任务类型将所述当前任务发送到对应的仲裁队列。
在本发明的一个可选实施例中，所述任务类型包括非IO任务、写IO任务和读IO任务，所述写IO任务和读IO任务的优先级相同，所述非IO任务的优先级高于所述写IO任务和读IO任务；
所述的任务仲裁器203，还用于根据所述仲裁队列中存放的任务优先级确定仲裁队列的优先级。
进一步地，所述的任务仲裁器203，包括第一判断单元和仲裁单元，所述第一判断单元，用于判定非IO任务对应的非IO仲裁队列是否为非空；所述仲裁单元，用于当第一判断单元的判定结果为非IO仲裁队列为非空时，从所述非IO仲裁队列中提取待执行任务，并为所述待执行任务调度NAND接口，当第一判断单元的判定结果为非IO仲裁队列为空时，根据预先设置的任务执行策略从写IO任务对应的写IO仲裁队列或读IO任务对应的读IO仲裁队列中提取待执行任务，并为所述待执行任务调度NAND接口。
本发明实施例中，所述任务仲裁器203还包括：第二判断单元，用于当所述仲裁单元根据预先设置的任务执行策略从写IO任务对应的写IO仲裁队列或读IO任务对应的读IO仲裁 队列中提取待执行任务之前，判定所述写IO仲裁队列和读IO仲裁队列中是否都存放有任务；
若是，则所述仲裁单元执行所述根据预先设置的任务执行策略从写IO任务对应的写IO仲裁队列或读IO任务对应的读IO仲裁队列中提取待执行任务的操作，否则，所述仲裁单元直接从非空的仲裁队列中提取待执行任务。
本发明实施例中，所述任务头信息中还包含有读状态任务使能标识。
相应的，所述任务管理模块202还包括第三判断单元和任务触发单元，其中：所述第三判断单元，用于在所述根据所述仲裁队列的优先级信息为所述仲裁队列中的待执行任务调度NAND接口之后，且在执行完所述待执行任务之后，判定所述待执行任务是否为读状态任务；所述任务触发单元，用于当第三判断单元的判定结果为所述待执行任务为读状态任务时，根据所述读状态任务的执行结果确定对应的NAND颗粒的使用状态，当所述使用状态为繁忙时，启动定时器，在预设定时时间后触发读状态任务，并将该读状态任务发送到对应的仲裁队列，当所述使用状态为空闲时，返回所述使用状态，以触发将所述任务队列中的下一任务发送到对应的仲裁队列的操作；
所述任务触发单元，还用于当第三判断单元的判定结果为所述待执行任务不是读状态任务时，读取所述读状态任务使能标识，当所述读状态任务使能标识开启时，启动定时器，在预设定时时间后触发读状态任务，并将该读状态任务发送到对应的仲裁队列，当所述读状态任务使能标识关闭时，触发将所述任务队列中的下一任务发送到对应的仲裁队列的操作。
本发明实施例中，所述任务头信息中还包含有接口独占许可标识。
相应的，所述任务仲裁器203还包括独占控制单元，所述独占控制单元，用于在根据所述仲裁队列的优先级信息为所述仲裁队列中的待执行任务调度NAND接口之后，且在执行完所述待执行任务之后，读取所述接口独占许可标识，当所述接口独占许可标识开启时，屏蔽当前的所述NAND颗粒之外的其他NAND颗粒对应的任务，否则解除对其他NAND颗粒对应的任务的屏蔽，和/或触发将所述任务队列中的下一任务发送到对应的仲裁队列的操作。
本发明实施例中，所述任务头信息中还包含有任务标识ID。
相应的，所述任务仲裁器203还包括执行结果监测单元，所述执行结果监测单元，用于在根据所述仲裁队列的优先级信息为所述仲裁队列中的待执行任务调度NAND接口之后，且在执行完所述待执行任务之后，监测并返回任务执行结果，所述任务执行结果中携带有所述待执行任务的任务标识ID。
与现有技术相比，本发明技术方案主要的优点如下：
本发明的NAND闪存设备的操作指令调度方法及装置，通过对NAND闪存设备的操作指令进行任务分解，将一条操作指令分解为多条任务，并将得到的任务发送到对应的任务队列，然后根据队列中当前任务的任务类型将任务发送到对应的仲裁队列，以供任务仲裁器根据仲裁队列的优先级为仲裁队列中的待执行任务调度NAND接口。本发明实施例以任务为单位进行调度，能够高效地实现NAND闪存设备的操作指令调度，提高NAND闪存设备的操作指令调度的灵活性，提升NAND闪存设备的总体性能。
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (10)

  1. 一种NAND闪存设备的操作指令调度方法，其特征在于，包括:
    对NAND闪存设备的操作指令进行任务分解，并将得到的任务发送到对应的任务队列；
    根据所述任务队列中当前任务的任务类型将所述当前任务发送到对应的仲裁队列；
    根据所述仲裁队列的优先级信息为所述仲裁队列中的待执行任务调度NAND接口。
  2. 根据权利要求1所述的方法，其特征在于，所述对NAND闪存设备的操作指令进行任务分解，包括：
    将所述操作指令对应的NAND颗粒在执行所述操作指令过程中由空闲状态更新为繁忙状态的时间点作为分界点，对所述操作指令进行任务分解；
    其中，所述NAND颗粒对应有唯一的任务队列，以存放任务分解后得到的任务。
  3. 根据权利要求1所述的方法，其特征在于，在所述对NAND闪存设备的操作指令进行任务分解之后，所述方法还包括：
    为每一任务配置任务头信息，所述任务头信息中包含有任务类型标识；
    所述根据所述任务队列中当前任务的任务类型将所述当前任务发送到对应的仲裁队列，包括：
    根据所述当前任务的任务头信息中包含的任务类型标识确定所述当前任务的任务类型，并根据所述任务类型将所述当前任务发送到对应的仲裁队列。
  4. 根据权利要求3所述的方法，其特征在于，所述任务类型包括非IO任务、写IO任务和读IO任务，所述写IO任务和读IO任务的优先级相同，所述非IO任务的优先级高于所述写IO任务和读IO任务；
    所述方法还包括：
    根据所述仲裁队列中存放的任务优先级确定仲裁队列的优先级。
  5. 根据权利要求4所述的方法，其特征在于，所述根据所述仲裁队列的优先级信息为所述仲裁队列中的待执行任务调度NAND接口，包括：
    判定非IO任务对应的非IO仲裁队列是否为非空；
    若是，则从所述非IO仲裁队列中提取待执行任务，并为所述待执行任务调度NAND接口；
    否则，根据预先设置的任务执行策略从写IO任务对应的写IO仲裁队列或读IO任务对应的读IO仲裁队列中提取待执行任务，并为所述待执行任务调度NAND接口。
  6. 根据权利要求3-5任一项所述的方法，其特征在于，所述任务头信息中还包含有读状态任务使能标识；
    在所述根据所述仲裁队列的优先级信息为所述仲裁队列中的待执行任务调度NAND接口之后，所述方法还包括：
    在执行完所述待执行任务之后，判定所述待执行任务是否为读状态任务；
    若是，则根据所述读状态任务的执行结果确定对应的NAND颗粒的使用状态，当所述使用状态为繁忙时，启动定时器，在预设定时时间后触发读状态任务，并将该读状态任务发送到对应的仲裁队列，当所述使用状态为空闲时，返回所述使用状态，以触发将所述任务队列中的下一任务发送到对应的仲裁队列的操作；
    否则，读取所述读状态任务使能标识，当所述读状态任务使能标识开启时，启动定时器，在预设定时时间后触发读状态任务，并将该读状态任务发送到对应的仲裁队列，当所述读状态任务使能标识关闭时，触发将所述任务队列中的下一任务发送到对应的仲裁队列的操作。
  7. 根据权利要求3-5任一项所述的方法，其特征在于，所述任务头信息中还包含有接口独占许可标识；
    在所述根据所述仲裁队列的优先级信息为所述仲裁队列中的待执行任务调度NAND接口之后，所述方法还包括：
    在执行完所述待执行任务之后，读取所述接口独占许可标识，当所述接口独占许可标识开启时，屏蔽当前的所述NAND颗粒之外的其他NAND颗粒对应的任务，否则解除对其他NAND颗粒对应的任务的屏蔽，和/或触发将所述任务队列中的下一任务发送到对应的仲裁队列的操作。
  8. 根据权利要求3-5任一项所述的方法，其特征在于，所述任务头信息中还包含有任务标识ID；
    在所述根据所述仲裁队列的优先级信息为所述仲裁队列中的待执行任务调度NAND接口之后，所述方法还包括：
    在执行完所述待执行任务之后，监测并返回任务执行结果，所述任务执行结果中携带有所述待执行任务的任务标识ID。
  9. 一种NAND闪存设备的操作指令调度装置，其特征在于，包括:
    任务生成模块，用于对NAND闪存设备的操作指令进行任务分解，并将得到的任务发送到对应的任务队列；
    任务管理模块，用于根据所述任务队列中当前任务的任务类型将所述当前任务发送到对应的仲裁队列；
    任务仲裁器，用于根据所述仲裁队列的优先级信息为所述仲裁队列中的待执行任务调度NAND接口。
  10. 根据权利要求9所述的装置，其特征在于，所述任务生成模块，还用于在对NAND闪存设备的操作指令进行任务分解之后，为每一任务配置任务头信息，所述任务头信息中包含有任务类型标识；
    所述任务管理模块，具体用于根据所述当前任务的任务头信息中包含的任务类型标识确定所述当前任务的任务类型，并根据所述任务类型将所述当前任务发送到对应的仲裁队列。
PCT/CN2017/114939 2016-12-08 2017-12-07 一种nand闪存设备的操作指令调度方法及装置 WO2018103685A1 (zh)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111008072A (zh) * 2019-12-25 2020-04-14 青梧桐有限责任公司 任务调度方法、装置、存储介质及电子设备
CN112732422A (zh) * 2020-12-29 2021-04-30 北京浪潮数据技术有限公司 一种Norflash异步擦写方法、装置、设备及介质
CN115080468A (zh) * 2022-05-12 2022-09-20 珠海全志科技股份有限公司 一种非阻塞的信息传输方法和装置
CN115878272A (zh) * 2021-09-22 2023-03-31 中科寒武纪科技股份有限公司 图任务调度方法、执行端设备、存储介质及程序产品

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106547492B (zh) * 2016-12-08 2018-03-20 北京得瑞领新科技有限公司 一种nand闪存设备的操作指令调度方法及装置
CN109697017B (zh) * 2017-10-20 2022-03-15 上海宝存信息科技有限公司 数据储存装置以及非挥发式存储器操作方法
CN107728953B (zh) * 2017-11-03 2021-03-02 记忆科技(深圳)有限公司 一种提升固态硬盘混合读写性能的方法
CN107704323A (zh) * 2017-11-07 2018-02-16 广州探迹科技有限公司 一种网络爬虫任务调度方法及装置
CN108172249B (zh) * 2017-12-22 2021-09-17 湖南国科微电子股份有限公司 一种NAND Flash访问操作方法、装置及系统
CN108829346B (zh) * 2018-05-28 2020-11-17 华中科技大学 一种适应闪存页差异的固态硬盘的用户写请求处理方法
CN109144420B (zh) * 2018-08-22 2021-07-13 深圳忆联信息系统有限公司 多颗粒自适应初始化方法、装置、计算机设备及存储介质
CN111858039B (zh) * 2020-07-06 2023-07-07 河南信大网御科技有限公司 基于分时式的拟态快速裁决方法、裁决器、架构及介质
US11556272B2 (en) * 2020-09-18 2023-01-17 Kioxia Corporation System and method for NAND multi-plane and multi-die status signaling
CN112506639A (zh) * 2020-12-31 2021-03-16 河南信大网御科技有限公司 执行体调度清洗方法、调度清洗装置及拟态OpenStack系统
CN112748883B (zh) * 2021-01-15 2023-01-10 苏州浪潮智能科技有限公司 一种io请求流水线处理设备、方法、系统及存储介质
CN112817542A (zh) * 2021-02-24 2021-05-18 成都佰维存储科技有限公司 Nand指令调度方法、装置、可读存储介质及电子设备
CN113157205B (zh) * 2021-02-26 2023-03-14 西安微电子技术研究所 一种nand阵列的控制方法、控制器、电子设备及存储介质
CN113055028B (zh) * 2021-03-18 2022-05-17 北京得瑞领新科技有限公司 Ldpc解码方法、解码器、解码装置及存储介质
US11972135B2 (en) * 2021-07-21 2024-04-30 Micron Technology, Inc. Status polling based on die-generated pulsed signal
CN114721978B (zh) * 2022-03-04 2023-08-25 成都储迅科技有限责任公司 一种加快Nand Flash控制命令执行速度的方法及系统
CN115033370B (zh) * 2022-08-09 2022-11-18 北京得瑞领新科技有限公司 存储设备中闪存任务调度方法、装置、存储介质及设备
CN116048809B (zh) * 2023-02-02 2023-12-22 广州万协通信息技术有限公司 多芯粒异构安全芯片的任务处理方法及安全芯片装置
CN117312199B (zh) * 2023-11-30 2024-03-08 杭州海康威视数字技术股份有限公司 多端口访问仲裁方法、装置、设备及存储介质

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102591823A (zh) * 2011-01-17 2012-07-18 上海华虹集成电路有限责任公司 一种具有指令队列功能的Nandflash控制器
US8341300B1 (en) * 2007-08-30 2012-12-25 Virident Systems, Inc. Systems for sustained read and write performance with non-volatile memory
CN103778013A (zh) * 2014-01-24 2014-05-07 中国科学院空间应用工程与技术中心 一种多通道Nand Flash控制器及其控制方法
CN103809917A (zh) * 2012-11-12 2014-05-21 擎泰科技股份有限公司 用于存储器的工作调度方法及其存储系统
CN106547492A (zh) * 2016-12-08 2017-03-29 北京得瑞领新科技有限公司 一种nand闪存设备的操作指令调度方法及装置

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102567120B (zh) * 2012-02-13 2014-04-23 北京星网锐捷网络技术有限公司 一种节点调度优先级确定方法及装置
CN102799391B (zh) * 2012-06-14 2015-05-27 记忆科技(深圳)有限公司 一种闪存控制器及其控制方法、闪存存储设备
CN103488691A (zh) * 2013-09-02 2014-01-01 用友软件股份有限公司 任务调度装置和任务调度方法
US9362000B2 (en) * 2014-09-05 2016-06-07 Kabushiki Kaisha Toshiba Memory system and management method thereof
CN105677455A (zh) * 2014-11-21 2016-06-15 深圳市中兴微电子技术有限公司 一种设备调度方法及任务管理器
US9575669B2 (en) * 2014-12-09 2017-02-21 Western Digital Technologies, Inc. Programmable solid state drive controller and method for scheduling commands utilizing a data structure
US10156994B2 (en) * 2015-02-27 2018-12-18 Western Digital Technologies, Inc. Methods and systems to reduce SSD IO latency
US10073714B2 (en) * 2015-03-11 2018-09-11 Western Digital Technologies, Inc. Task queues
KR20160118836A (ko) * 2015-04-03 2016-10-12 에스케이하이닉스 주식회사 호스트 커맨드 큐를 포함하는 메모리 컨트롤러 및 그것의 동작 방법
KR102370733B1 (ko) 2015-04-13 2022-03-08 에스케이하이닉스 주식회사 출력 커맨드들을 전송하는 컨트롤러 및 그것의 동작 방법
CN106067321B (zh) * 2015-04-21 2020-09-15 爱思开海力士有限公司 适于存储器编程暂停-恢复的控制器

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8341300B1 (en) * 2007-08-30 2012-12-25 Virident Systems, Inc. Systems for sustained read and write performance with non-volatile memory
CN102591823A (zh) * 2011-01-17 2012-07-18 上海华虹集成电路有限责任公司 一种具有指令队列功能的Nandflash控制器
CN103809917A (zh) * 2012-11-12 2014-05-21 擎泰科技股份有限公司 用于存储器的工作调度方法及其存储系统
CN103778013A (zh) * 2014-01-24 2014-05-07 中国科学院空间应用工程与技术中心 一种多通道Nand Flash控制器及其控制方法
CN106547492A (zh) * 2016-12-08 2017-03-29 北京得瑞领新科技有限公司 一种nand闪存设备的操作指令调度方法及装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3553646A4 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111008072A (zh) * 2019-12-25 2020-04-14 青梧桐有限责任公司 任务调度方法、装置、存储介质及电子设备
CN112732422A (zh) * 2020-12-29 2021-04-30 北京浪潮数据技术有限公司 一种Norflash异步擦写方法、装置、设备及介质
CN112732422B (zh) * 2020-12-29 2023-12-22 北京浪潮数据技术有限公司 一种Norflash异步擦写方法、装置、设备及介质
CN115878272A (zh) * 2021-09-22 2023-03-31 中科寒武纪科技股份有限公司 图任务调度方法、执行端设备、存储介质及程序产品
CN115080468A (zh) * 2022-05-12 2022-09-20 珠海全志科技股份有限公司 一种非阻塞的信息传输方法和装置

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