WO2018099118A1 - 同步整流时序控制器、无线充电全桥同步整流电路及系统 - Google Patents

同步整流时序控制器、无线充电全桥同步整流电路及系统 Download PDF

Info

Publication number
WO2018099118A1
WO2018099118A1 PCT/CN2017/095605 CN2017095605W WO2018099118A1 WO 2018099118 A1 WO2018099118 A1 WO 2018099118A1 CN 2017095605 W CN2017095605 W CN 2017095605W WO 2018099118 A1 WO2018099118 A1 WO 2018099118A1
Authority
WO
WIPO (PCT)
Prior art keywords
synchronous rectification
switch
gate
comparator
input
Prior art date
Application number
PCT/CN2017/095605
Other languages
English (en)
French (fr)
Inventor
袁巍
Original Assignee
无锡华润矽科微电子有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 无锡华润矽科微电子有限公司 filed Critical 无锡华润矽科微电子有限公司
Publication of WO2018099118A1 publication Critical patent/WO2018099118A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J50/00—Circuit arrangements or systems for wireless supply or distribution of electric power
    • H02J50/10—Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling
    • H02J50/12—Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling of the resonant type
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33576—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer
    • H02M3/33592—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer

Definitions

  • the present invention relates to the field of wireless charging, and in particular, to a synchronous rectification timing controller, a wireless charging full-bridge synchronous rectification circuit and a system.
  • FIG. 1 illustrates a prior art diode based wireless charging full bridge synchronous rectification system 100.
  • the wireless charging full bridge synchronous rectification system 100 includes a transmitting end Tx and a receiving end Rx.
  • the transmitting end Tx includes a Pulse Width Modulation (PWM) unit, a DC-AC power conversion unit, and a Primary Coil.
  • the receiving end Rx includes a secondary coil (Secondary Coil), capacitors C S and C d , a full bridge circuit composed of diodes D1 - D4 and a voltage stabilizing capacitor C, and the receiving end Rx may also be referred to as wireless charging.
  • Bridge synchronous rectification circuit is also be referred to as wireless charging.
  • the conduction voltage drop of the diodes D1-D4 is about 0.7V
  • the rectified output terminal Rect carries a large current of 1A
  • the rectification system has a large heat loss due to the conduction voltage drop, and the rectification efficiency is low.
  • FIG. 2 illustrates a wireless charging full bridge synchronous rectification system 200 based on an N-type LDMOS transistor. As shown in FIG. 2, which is different from FIG.
  • the full bridge circuit in the wireless charging full-bridge synchronous rectification system 200 is composed of four N-type LDMOS rectifier tubes N1, N2, N3 and N4 instead of It consists of four diodes, and it also includes a synchronous rectification timing controller to control the turn-on or turn-off of the four N-type LDMOS transistors N1, N2, N3, and N4 to achieve rectification.
  • the existing wireless charging full-bridge synchronous rectification circuit generally switches the rectifier tubes N1, N2, N3 and N4 when the AC signals AC1 and AC2 before rectification are zero, that is, as far as possible
  • the rectifiers N1, N2, N3 and N4 operate in a Discontinuous Conduction Mode (DCM) of the AC signal.
  • DCM Discontinuous Conduction Mode
  • a high-performance AC zero-crossing detection circuit is required, which puts high requirements on the offset control of the comparator in the AC zero-crossing detection circuit, and improves the cost of the wireless charging full-bridge synchronous rectifier circuit. And complexity.
  • the existing synchronous rectification circuit only performs zero-crossing detection on the AC AC signal before rectification.
  • the zero-cross detection output may have an erroneous waveform such as a glitch, and the digital signal processing adjustment station needs to be performed at this time.
  • the duty ratio of the output signal of the AC zero-crossing detection circuit is described, and the glitch occurring in the signal is filtered out; finally, the processed signal is sent to the synchronous rectification driving circuit.
  • the transmitting end Tx and the receiving end Rx can also be performed, the communication is transmitted by 2FSK (binary frequency shift keying), and the communication envelope data is superimposed on the AC alternating signal, for understanding
  • 2FSK binary frequency shift keying
  • the reference frequency required for FSK demodulation needs to be demodulated in advance.
  • a hardware circuit needs to be separately designed to demodulate the reference frequency required for FSK demodulation, which is also invisibly increased.
  • the layout area increases the hardware cost.
  • One of the objects of the present invention is to provide a synchronous rectification timing controller that can improve synchronous rectification efficiency and reliability.
  • Another object of the present invention is to provide a wireless charging full-bridge synchronous rectification circuit, which can improve synchronous rectification efficiency and reliability.
  • a third object of the present invention is to provide a wireless charging full-bridge synchronous rectification system that can improve synchronous rectification efficiency and reliability.
  • the present invention provides a synchronous rectification timing controller for a first rectification switch, a second rectification switch, a third rectification switch, and a fourth rectification switch in a full bridge circuit Turning on or off for timing control, comprising: a first comparator for comparing a first alternating current signal of the first alternating current input with a rectified signal of the rectified output, outputting a first alternating high sampling signal; and a second comparator The second alternating current signal and the rectified signal of the rectified output end are compared to output a second alternating current high sampling signal; and the third comparator is configured to compare the first alternating current signal of the first alternating current input with a predetermined low voltage threshold, Outputting a first AC low sampling signal; a fourth comparator for comparing the second AC signal of the second AC input with a predetermined low voltage threshold, outputting a second AC low sampling signal; and a logic combination circuit for using the first AC high Sampling signal
  • a wireless charging full-bridge synchronous rectification system includes: the wireless charging full-bridge synchronous rectification circuit described above; and a transmitting end including a pulse width modulation unit and a direct current An AC power conversion unit and a primary coil, the primary coil being capable of being wirelessly coupled to the secondary coil to form a transformer.
  • the present invention can improve the synchronous rectification by performing high and low level sampling on the AC signal before rectification, and sending the sampling data into the hardware circuit for timing processing to control the on or off of each rectification switch. Efficiency and reliability.
  • the reference frequency required for demodulating the communication envelope data can be obtained directly according to the frequency of each drive control signal.
  • Figure 1 illustrates an existing diode-based wireless charging full-bridge synchronous rectification system
  • FIG. 2 illustrates a wireless charging full bridge synchronous rectification system based on an N-type LDMOS tube
  • Figure 3 is a circuit diagram showing the synchronous rectification timing controller of the present invention in one embodiment
  • FIG. 4 is a timing diagram showing a portion of signals in the synchronous rectification timing controller of FIG. 3;
  • FIG. 5 shows a simulation waveform of the wireless charging full-bridge synchronous rectification circuit of the present invention in one example
  • FIG. 9 is simulation data of the verification example of FIG. 8.
  • the invention provides a synchronous rectification timing controller, a wireless charging full-bridge synchronous rectification circuit and a system, which can improve synchronous rectification efficiency and reliability.
  • the reference frequency required to demodulate the communication envelope data can be obtained at the same time.
  • FIG. 2 illustrates a wireless charging full bridge synchronous rectification system 200 based on an N-type LDMOS transistor.
  • the wireless charging full bridge synchronous rectification system 200 includes a transmitting end Tx and a receiving end Rx.
  • the transmitting end Tx includes a Pulse Width Modulation (PWM) unit, a DC-AC power conversion unit, and a Primary Coil.
  • the receiving end Rx includes a secondary coil (Secondary Coil), a first capacitor C d , and a second capacitor C s , and is composed of a first rectifying switch N1, a second rectifying switch N2, a third rectifying switch N3, and a fourth rectifying switch N4.
  • a full bridge circuit, a voltage stabilizing capacitor C1 and a synchronous rectification timing controller 220 are formed.
  • the receiving end Rx may also be referred to as a wireless charging full bridge synchronous rectification circuit.
  • the transmitting end Tx can use the primary coil to wirelessly transmit energy in the form of an electromagnetic field
  • the receiving end Rx can use the secondary coil to receive the energy of the electromagnetic field and convert it into alternating current, and the power transmission between the two is through electromagnetic induction technology. After that, it is rectified into a DC voltage by a full-bridge circuit, and is outputted through the rectified output terminal Rect to supply power to the load RL.
  • the drive control signals of the four rectifier switches are determined by the synchronous rectification timing controller 220.
  • the secondary coil has a first connection end and a second connection end, and the second connection end serves as a second AC input terminal AC2.
  • the first capacitor C d is connected between the first connection end and the second connection end of the secondary coil.
  • One end of the second capacitor C s is connected to the first connection end of the secondary coil, and the other end is used as the first AC input terminal AC1.
  • the first rectifier switch N1 is connected between the rectification output terminal Rect and the first AC input terminal AC1
  • the second rectifier switch N2 is connected between the rectification output terminal Rect and the second AC input terminal AC2
  • the third rectifier switch N3 is connected to the first rectifier switch N3.
  • the fourth rectifier switch N4 is connected between the AC input terminal AC1 and the ground terminal PGND, and is connected between the second AC input terminal AC2 and the ground terminal PGND.
  • the voltage stabilizing capacitor C1 is connected between the rectified output terminal Rect and the ground terminal PGND.
  • the synchronous rectification timing controller 220 uses the hardware to perform high and low sampling on the first alternating current signal of the first alternating current input terminal AC1 and the second alternating current signal of the second alternating current input terminal AC2 to obtain the first alternating current high sampling signal and the second alternating current high.
  • the sampling signal, the first AC low sampling signal and the second AC low sampling signal, and logically combining the first alternating current high sampling signal, the first alternating current low sampling signal, the second alternating current high sampling signal, and the second alternating current low sampling signal Generating a first driving control signal for controlling the first rectifying switch N1 to be turned on or off, a second driving control signal for controlling the second rectifying switch N2 to be turned on or off, and a third driving control for controlling the third rectifying switch N3 to be turned on or off. a signal, and a fourth drive control signal that controls the fourth rectifier switch N4 to be turned on or off.
  • the first driving control signal and the fourth driving control signal drive the first rectifying switch N1 and the fourth rectifying switch N4 to be turned on or off synchronously, and the second driving control signal and the third driving control signal drive the second rectification
  • the switch N2 and the third rectifier switch N3 are turned on or off synchronously, and the conduction periods of the first rectifier switch N1 and the fourth rectifier switch N4 do not overlap with the conduction periods of the second rectifier switch N2 and the third rectifier switch N3.
  • the first rectification switch N1, the second rectification switch N2, the third rectification switch N3, and the fourth rectification switch N4 are all N-type LDMOS tubes.
  • the drain of the first rectifier switch N1 is connected to the rectified output terminal Rect, and the source thereof is connected to the first AC input terminal AC1, and the first driving control signal controls the conduction of the first rectifying switch N1 through the gate of the first rectifying switch N1. Or deadline.
  • the drain of the third rectifier switch N3 is connected to the first AC input terminal AC1, the source thereof is connected to the ground terminal, and the third driving control signal controls the conduction or the third rectifier switch N3 to be turned on or off by the gate of the third rectifier switch N3. .
  • the drain of the second rectifier switch N2 is connected to the rectified output terminal Rect, the source thereof is connected to the second AC input terminal AC2, and the second driving control signal controls the conduction of the second rectifying switch N2 through the gate of the second rectifying switch N2. Or deadline.
  • the drain of the fourth rectifier switch N4 is connected to the second AC input terminal AC2, the source thereof is connected to the ground terminal, and the fourth drive control signal controls the conduction or the turn-off of the fourth rectifier switch N4 through the gate of the fourth rectifier switch N4. .
  • other types of MOS transistors can also be employed as the rectifier switch.
  • the full-bridge synchronous rectification circuit based on Qi standard adopts N-type LDMOS tube as the rectifier switch, and the conduction voltage drop of the LDMOS tube can be less than 0.1V.
  • the efficiency of the wireless charging full-bridge synchronous rectification circuit depends on the LDMOS tube N1- Timing control of the gate of N4.
  • FIG. 3 shows a circuit diagram of a synchronous rectification timing controller 220 in one embodiment of the present invention.
  • the synchronous rectification timing controller 220 includes a first comparator CP1, a second comparator CP2, a third comparator CP3, a fourth comparator CP4, a logic combination circuit 221, and a rectification drive circuit 222.
  • the first comparator CP1 compares the first alternating current signal of the first alternating current input terminal AC1 with the rectified signal of the rectified output end Rect, and outputs a first alternating current high sampling signal AC1_high.
  • the second comparator CP2 compares the second AC signal of the second AC input terminal AC2 with the rectified signal of the rectified output terminal Rect, and outputs a second AC high sampling signal AC2_high.
  • the third comparator CP3 compares the first alternating current signal of the first alternating current input terminal AC1 with a predetermined low voltage threshold value Vth, and outputs a first alternating current low sampling signal AC1_low.
  • the fourth comparator CP4 compares the second alternating current signal of the second alternating current input terminal AC2 with a predetermined low voltage threshold value Vth, and outputs a second alternating current low sampling signal AC2_low.
  • the predetermined low voltage threshold Vth ranges from 0.1 to 0.4 V, such as 0.1 V, 0.25 V, 0.3 V, 0.4 V, etc., which can be divided by resistance to the power supply voltage. The way is obtained, here is an example of 0.25V.
  • the logic combination circuit 221 performs a logical combination operation on the first AC high sampling signal AC1_high, the first AC low sampling signal AC1_low, the second AC high sampling signal AC2_high, and the second AC low sampling signal AC2_low to generate a control first driving control signal N1_d And a second drive control signal N2_d, a third drive control signal N3_d, and a fourth drive control signal N4_d.
  • the logic of the logic combination circuit 221 can ensure the first drive control signal N1_d and the fourth drive The control signal N4_d is the same, the second drive control signal N2_d and the third drive control signal N3_d are the same, and the first drive control signal N1_d and the second drive control signal N2_d are non-overlapping.
  • the logic combination circuit 221 includes a first NAND gate NA1, a second NAND gate NA2, a first NOR gate NO1, a second NOR gate NO2, a first AND gate AN1, and a second AND Door AN2.
  • the two input terminals of the first NAND gate NA1 are respectively connected to the output end of the first comparator CP1 and the output end of the fourth comparator CP4, and the output end of the first NAND gate NA1 and the first NOR gate NO1 One input is connected.
  • the two input terminals of the second NAND gate NA2 are respectively connected to the output end of the second comparator CP2 and the output end of the third comparator CP3, and the output end of the second NAND gate NA2 and one of the second NOR gate NO2
  • the inputs are connected.
  • the output end of the first NOR gate NO1 is connected to the other input end of the second NOR gate NO2, and the output end of the first NOR gate NO1 outputs a fourth drive control signal N4_d, and the output end of the second NOR gate NO2 is The other input of the first NOR gate NO1 is connected, and the output of the second NOR gate NO2 outputs a third drive control signal N3_d.
  • the three input terminals of the first AND gate AN1 are respectively connected to the output terminal of the first comparator CP1, the output terminal of the fourth comparator CP4, and the output terminal of the first NOR gate NO1, and the output of the first AND gate AN1 is output.
  • the first driving control signal N1_d, the three input terminals of the second AND gate AN2 are respectively connected to the output end of the second comparator CP2, the output end of the third comparator CP3 and the output end of the second NOR gate NO2, and second The output of the AND gate AN2 outputs a second drive control signal N2_d.
  • the synchronous rectification timing controller 220 further includes a rectification driving circuit 222.
  • the first driving control signal N1_d, the second driving control signal N2_d, the third driving control signal N3_d, and the fourth driving control signal N4_d are respectively driven by the rectifying driving circuit 222.
  • the synchronous rectification timing controller 220 can realize the automatic synchronization timing control of the rectification switches N1-N4 by using hardware, improve the synchronous rectification efficiency, and meet the Qi standard design requirements.
  • the synchronous rectification timing controller 220 of the present invention may further include: a first resistor R1 connected between the first AC input terminal AC1 and the first input end of the first comparator CP1; and connected to the first comparator CP1 a first adjustable current source S1 between the first input terminal and the ground terminal; a second resistor R2 connected between the rectified output terminal Rect and the second input terminal of the first comparator CP1; connected to the first comparator a second adjustable current source S2 between the second input end and the ground end of the CP1; a third resistor R3 connected between the second AC input terminal AC2 and the first input end of the second comparator CP2; a third adjustable current source S3 between the first input terminal and the ground terminal of the comparator CP2; a fourth resistor R4 connected between the rectified output terminal Rect and the second input terminal of the second comparator CP2; A fourth resistor R4 connected between the rectified output terminal Rect and the second input terminal of the second comparator CP2; A fourth resistor R
  • the rectified signal comparison points of the AC signals AC1 and AC2 and the rectified output terminal RECT can be adjusted, and the first rectifying switch N1 and the third rectifying switch N3 can be adjusted.
  • the dead zone is turned on to prevent the upper and lower rectifier switches from being turned on at the same time, and the rectification efficiency is improved.
  • the current value of the first adjustable current source S1 is between 0 and 10 uA
  • the current value of the second adjustable current source S2 is between 5-12.5 uA
  • the current value of the fourth adjustable current source S4 is between 5-12.5 uA
  • the resistance value of the first to fourth resistors is 2K.
  • the N-type LDMOS transistor is selected as the rectifier switch, and the rectified signal RECT is required to output 12V, the driving capability is 1.25A, the input AC signals AC1 and AC2 are 160KHz, the amplitude is 12.2V, the duty ratio is 50%, and a large current is considered.
  • the driving capability is simulated and verified based on the above synchronous rectification circuit, and the simulation data is as shown in FIG. 5.
  • the wireless charging Qi standard communication between the transmitting end Tx and the receiving end Rx is also possible, and the communication is transmitted by 2FSK (binary frequency shift keying), and the communication envelope data is superimposed on the alternating current.
  • the signal including the first AC signal AC1 and the second AC signal AC2
  • the reference frequency required for FSK demodulation needs to be demodulated in advance, and the hardware needs to be separately designed in the prior art.
  • the circuit demodulates the reference frequency required for FSK demodulation, which inevitably increases the layout area and increases the hardware cost.
  • the frequency of each of the drive control signals N1_d, N2_d, N3_d, and N4_d can be directly used as the reference frequency FSK_1 required for demodulating the communication envelope data, so that it is not necessary to provide an additional circuit.
  • the worst AC signal waveform acquired during FSK debugging is selected and simulated by the aforementioned synchronous rectification timing controller 220 to verify whether it is compatible with FSK frequency demodulation.
  • FIG. 6 shows AC signals AC1, AC2 for the first verification example for performing synchronous rectification timing controller 220 verification.
  • the obtained reference frequency FSK_1 can be mainly viewed, and one cycle is the duration between BASELINE and TIMEA, which is about 4.9 us, and its frequency is 1/4.9 us 205 KHz, which meets the design requirements.
  • the obtained reference frequency FSK_1 can be mainly viewed, and one cycle is the duration between BASELINE and TIMEA, which is about 6.24 us, and its frequency is 1/6.24 us ⁇ 160 KHz, which meets the design requirements.
  • the synchronous rectification timing controller designed by the invention performs high and low sampling processing on the AC signal before rectification by hardware, thereby reducing design difficulty, avoiding delay caused by software processing, and ensuring large driving current capability. Under the premise, it is compatible with the FSK frequency demodulation function, which avoids the increase of hardware cost and improves the synchronous rectification efficiency and reliability.
  • the words “coupled”, “connected”, “connected”, “connected”, “grounded”, etc., which are electrically connected, mean, unless otherwise stated, a direct or indirect electrical connection, indirect.
  • the electrical connection means that some devices can be connected in series, such as resistors or inductors.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Rectifiers (AREA)

Abstract

一种同步整流时序控制器（220）、无线充电全桥同步整流电路及系统（200）。同步整流时序控制器包括：第一比较器（CP1），用于比较第一交流信号和整流信号，输出第一交流高采样信号（AC1_high）；第二比较器（CP2），用于比较第二交流信号和整流信号，输出第二交流高采样信号（AC2_high）；第三比较器（CP3），用于比较第一交流信号和预定低电压阈值（Vth），输出第一交流低采样信号（AC1_low）；第四比较器（CP4），用于比较第二交流信号和预定低电压阈值，输出第二交流低采样信号（AC2_low）；逻辑组合电路221，用于对四个采样信号进行逻辑组合运算，产生控制对应整流开关的四个驱动控制信号（N1_d, N2_d, N3_d, N4_d）。该控制器对两个交流信号进行了高低采样，由硬件电路对采样数据进行时序处理，可以提高同步整流效率及可靠性。

Description

同步整流时序控制器、无线充电全桥同步整流电路及系统
相关申请的交叉引用
本申请主张2016年11月30日提交的申请号为201611078539.4的中国发明专利申请的优先权，其内容通过引用的方式并入本申请中。
技术领域
本发明涉及无线充电领域，特别涉及一种同步整流时序控制器、无线充电全桥同步整流电路及系统。
背景技术
图1示意出了现有的基于二极管的无线充电全桥同步整流系统100。所述无线充电全桥同步整流系统100包括发送端Tx和接收端Rx。所述发送端Tx包括脉宽调制(Pulse width Modulation,PWM)单元、直流-交流功率转换单元和初级线圈(Primary Coil)。所述接收端Rx包括次级线圈(Secondary Coil)、电容CS和Cd、由二极管D1-D4组成的全桥电路和稳压电容C，所述接收端Rx也可以被称为无线充电全桥同步整流电路。
然而，由于二极管D1-D4导通压降约为0.7V，在整流输出端Rect带载大电流1A时，整流系统由于导通压降产生的发热损耗较大，整流效率偏低。
采用NLDMOS(N-type Laterally Diffused Metal Oxide Semiconductor，N型LDMOS管)管全桥同步整流技术可以降低整流电路自身损耗，提高整机效率。目前，对整流效率要求高的电路应用中常用同步整流技术。图2示意出了一种基于N型LDMOS管的无线充电全桥同步整流系统200。如图2所示，其与图1不同的是，所述无线充电全桥同步整流系统200中的全桥电路由四个N型LDMOS整流管N1、N2、N3和N4组成，，而不是由四个二极管组成，另外其还包括同步整流时序控制器来控制四个N型LDMOS管N1、N2、N3和N4的导通或截止，从而实现整流。
现有无线充电全桥同步整流电路为了获取较高的系统效率，一般是在整流前的交流信号AC1和AC2为零时，将所述整流管N1、N2、N3和N4进行切换，即尽量将整流管N1、N2、N3和N4工作在AC交流信号的断续模式(Discontinuous Conduction Mode，简称DCM)。为了实现DCM的控制，需要高性能的AC过零检测电路，这就对AC过零检测电路中的比较器的偏移量控制提出较高的要求，提高了无线充电全桥同步整流电路的成本和复杂度。
另外，现有同步整流电路仅对整流前的AC交流信号做过零检测，当被采样的交流信号有干扰时，过零检测输出会出现毛刺等错误波形，此时需要通过数字信号处理调整所述AC过零检测电路的输出信号的占空比，并滤除信号中出现的毛刺；最终将处理后的信号送入同步整流驱动电路。
此外，由于AC交流信号在同步整流过程中会出现过冲现象(高于整流输出电平或低于交流地电平)，对于受到干扰的AC交流信号，仅通过AC过零检测做硬件采样，并依靠软件处理产生同步整流驱动控制信号，既增加了硬件采样设计难度，也增加了软件处理的复杂度，同时软件信号处理必然带来相对于硬件处理而言更长的时序延迟，进而影响同步整流效率。
另外，在无线充电Qi标准中，发送端Tx与接收端Rx之间还可以进行通讯，通讯是以2FSK(二进制频移键控)方式传输，通讯包络数据叠加于AC交流信号中，为了解调出所述通讯包络数据，需要事先解调出FSK解调所需的参考频率，现有技术中需要单独设计硬件电路来解调出FSK解调所需的参考频率，无形中也增大了版图面积，抬高了硬件成本。
因此，有必要提供一种新的解决方案来解决上述问题。
发明内容
本发明的目的之一在于提供一种同步整流时序控制器，其可以提高了同步整流效率及可靠性。
本发明的目的之二在于提供一种无线充电全桥同步整流电路，其可以提高了同步整流效率及可靠性。
本发明的目的之三在于提供一种无线充电全桥同步整流系统，其可以提高了同步整流效率及可靠性。
为实现上述目的，根据本发明的一个方面，本发明提供一种同步整流时序控制器，用于对全桥电路中的第一整流开关、第二整流开关、第三整流开关和第四整流开关的导通或关断进行时序控制，其包括：第一比较器，用于比较第一交流输入端的第一交流信号和整流输出端的整流信号，输出第一交流高采样信号；第二比较器，用于比较第二交流输入端的第二交流信号和整流输出端的整流信号，输出第二交流高采样信号；第三比较器，用于比较第一交流输入端的第一交流信号和预定低电压阈值，输出第一交流低采样信号；第四比较器，用于比较第二交流输入端的第二交流信号和预定低电压阈值，输出第二交流低采样信号；逻辑组合电路，用于对第一交流高采样信号、第一交流低采样信号、第二交流高采样信号、第二交 流低采样信号进行逻辑组合运算，产生控制第一整流开关导通或截止的第一驱动控制信号、控制第二整流开关导通或截止的第二驱动控制信号、控制第三整流开关导通或截止的第三驱动控制信号，以及控制第四整流开关导通或截止的第四驱动控制信号。
根据本发明的再一个方面，本发明提供一种无线充电全桥同步整流系统，其包括：上文所述的无线充电全桥同步整流电路；和，发送端，其包括脉宽调制单元、直流-交流功率转换单元和初级线圈，所述初级线圈能够与所述次级线圈无线耦合形成变压器。
与现有技术相比，本发明通过对整流前的交流信号进行高低电平采样，并将采样数据送入硬件电路进行时序处理，以控制各个整流开关的导通或截止，可以提高了同步整流效率及可靠性。此外，直接根据各个驱动控制信号的频率就可以得到解调所述通讯包络数据时所需的参考频率。
附图说明
结合参考附图及接下来的详细描述，本发明将更容易理解，其中同样的附图标记对应同样的结构部件，其中：
图1示意出了现有的基于二极管的无线充电全桥同步整流系统；
图2示意出了一种基于N型LDMOS管的无线充电全桥同步整流系统；
图3示出了本发明中的同步整流时序控制器在一个实施例中的电路图；
图4示出了图3中的同步整流时序控制器中的部分信号的时序图；
图5示出了本发明中的无线充电全桥同步整流电路在一个示例中的仿真波形；
图6示出了用于进行同步整流时序控制器验证的第一验证示例的交流信号AC1、AC2的波形，其中，所述交流信号AC1、AC2的频率为205KHz，10％占空比，整流信号的电压Vrect＝7V，无负载；
图7为图6的验证示例的仿真数据；
图8示出了用于进行同步整流时序控制器验证的第一验证示例的交流信号AC1、AC2的波形，其中，所述交流信号AC1、AC2的频率为160KHz，整流信号的电压Vrect＝10.2V，无负载；
图9为图8的验证示例的仿真数据。
具体实施方式
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图和具体实施方式对本发明作进一步详细的说明。
本发明提供一种同步整流时序控制器、无线充电全桥同步整流电路及系统，其可以提高了同步整流效率及可靠性。另外，还可以同时得到解调通讯包络数据时所需的参考频率。
图2示意出了一种基于N型LDMOS管的无线充电全桥同步整流系统200。所述无线充电全桥同步整流系统200包括发送端Tx和接收端Rx。
所述发送端Tx包括脉宽调制(Pulse width Modulation,PWM)单元、直流-交流功率转换单元和初级线圈(Primary Coil)。所述接收端Rx包括次级线圈(Secondary Coil)、第一电容Cd、第二电容Cs，由第一整流开关N1、第二整流开关N2、第三整流开关N3、第四整流开关N4组成的全桥电路、稳压电容C1和同步整流时序控制器220。所述接收端Rx也可以被称为无线充电全桥同步整流电路。所述发送端Tx可以利用初级线圈以电磁场的形式无线发送能量，而接收端Rx可以利用次级线圈接收电磁场的能量并将其转化为交流电，两者之间的电能传输是通过电磁感应技术，之后，通过全桥电路将其整流成直流电压，并通过整流输出端Rect输出，给负载RL供电。四个整流开关的驱动控制信号由所述同步整流时序控制器220决定。
所述次级线圈具有第一连接端和第二连接端，第二连接端作为第二交流输入端AC2。第一电容Cd连接于所述次级线圈的第一连接端和第二连接端之间。第二电容Cs的一端与所述次级线圈的第一连接端相连，另一端作为第一交流输入端AC1。第一整流开关N1连接于整流输出端Rect和第一交流输入端AC1之间，第二整流开关N2连接于整流输出端Rect和第二交流输入端AC2之间，第三整流开关N3连接于第一交流输入端AC1和接地端PGND之间，第四整流开关N4连接于第二交流输入端AC2和接地端PGND之间。所述稳压电容C1连接于整流输出端Rect和接地端PGND之间。
所述同步整流时序控制器220利用硬件对第一交流输入端AC1的第一交流信号和第二交流输入端AC2的第二交流信号分别进行高低采样得到第一交流高采样信号、第二交流高采样信号、第一交流低采样信号和第二交流低采样信号，并对第一交流高采样信号、第一交流低采样信号、第二交流高采样信号、第二交流低采样信号进行逻辑组合运算产生控制第一整流开关N1导通或截止的第一驱动控制信号、控制第二整流开关N2导通或截止的第二驱动控制信号、控制第三整流开关N3导通或截止的第三驱动控制信号，以及控制第四整流开关N4导通或截止的第四驱动控制信号。第一驱动控制信号和第四驱动控制信号驱动第一整流开关N1和第四整流开关N4同步导通或截止，第二驱动控制信号和第三驱动控制信号驱动第二整流 开关N2和第三整流开关N3同步导通或截止，第一整流开关N1和第四整流开关N4的导通时段与第二整流开关N2和第三整流开关N3的导通时段不交叠。
在一个实施例中，第一整流开关N1、第二整流开关N2、第三整流开关N3、第四整流开关N4均为N型LDMOS管。第一整流开关N1的漏极与整流输出端Rect相连，其源极与第一交流输入端AC1相连，第一驱动控制信号通过第一整流开关N1的栅极控制第一整流开关N1的导通或截止。第三整流开关N3的漏极与第一交流输入端AC1相连，其源极与接地端相连，第三驱动控制信号通过第三整流开关N3的栅极控制第三整流开关N3的导通或截止。第二整流开关N2的漏极与整流输出端Rect相连，其源极与第二交流输入端AC2相连，第二驱动控制信号通过第二整流开关N2的栅极控制第二整流开关N2的导通或截止。第四整流开关N4的漏极与第二交流输入端AC2相连，其源极与接地端相连，第四驱动控制信号通过第四整流开关N4的栅极控制第四整流开关N4的导通或截止。当然在其他实施例中，也可以采用其他类型的MOS晶体管作为整流开关。基于Qi标准的全桥同步整流电路采用N型LDMOS管做整流开关，LDMOS管的导通压降可以做到小于0.1V，此时无线充电全桥同步整流电路的效率就取决于LDMOS管N1-N4的栅极的时序控制。
图3示出了本发明中的同步整流时序控制器220在一个实施例中的电路图。所述同步整流时序控制器220包括第一比较器CP1、第二比较器CP2、第三比较器CP3、第四比较器CP4、逻辑组合电路221和整流驱动电路222。
第一比较器CP1比较第一交流输入端AC1的第一交流信号和整流输出端Rect的整流信号，输出第一交流高采样信号AC1_high。第二比较器CP2比较第二交流输入端AC2的第二交流信号和整流输出端Rect的整流信号，输出第二交流高采样信号AC2_high。第三比较器CP3比较第一交流输入端AC1的第一交流信号和预定低电压阈值Vth，输出第一交流低采样信号AC1_low。第四比较器CP4比较第二交流输入端AC2的第二交流信号和预定低电压阈值Vth，输出第二交流低采样信号AC2_low。在一个实施例中，所述预定低电压阈值Vth的取值范围为0.1-0.4V，比如可以是0.1V，0.25V，0.3V，0.4V等，其可以通过对电源电压进行电阻分压的方式得到，这里以0.25V为例进行介绍。
所述逻辑组合电路221对第一交流高采样信号AC1_high、第一交流低采样信号AC1_low、第二交流高采样信号AC2_high、第二交流低采样信号AC2_low进行逻辑组合运算产生控制第一驱动控制信号N1_d、第二驱动控制信号N2_d、第三驱动控制信号N3_d，以及第四驱动控制信号N4_d。所述逻辑组合电路221的逻辑可以确保第一驱动控制信号N1_d和第四驱动 控制信号N4_d是相同的，第二驱动控制信号N2_d和第三驱动控制信号N3_d是相同的，第一驱动控制信号N1_d和第二驱动控制信号N2_d是不交叠的。
在一个实施例中，所述逻辑组合电路221包括第一与非门NA1、第二与非门NA2、第一或非门NO1、第二或非门NO2、第一与门AN1和第二与门AN2。其中第一与非门NA1的两个输入端分别与第一比较器CP1的输出端和第四比较器CP4的输出端相连，第一与非门NA1的输出端与第一或非门NO1的一个输入端相连。第二与非门NA2的两个输入端分别与第二比较器CP2的输出端和第三比较器CP3的输出端相连，第二与非门NA2的输出端与第二或非门NO2的一个输入端相连。第一或非门NO1的输出端与第二或非门NO2的另一个输入端相连，第一或非门NO1的输出端输出第四驱动控制信号N4_d，第二或非门NO2的输出端与第一或非门NO1的另一个输入端相连，第二或非门NO2的输出端输出第三驱动控制信号N3_d。第一与门AN1的三个输入端分别与第一比较器CP1的输出端、第四比较器CP4的输出端和第一或非门NO1的输出端相连，第一与门AN1的输出端输出第一驱动控制信号N1_d，第二与门AN2的三个输入端分别与第二比较器CP2的输出端、第三比较器CP3的输出端和第二或非门NO2的输出端相连，第二与门AN2的输出端输出第二驱动控制信号N2_d。
所述同步整流时序控制器220还包括整流驱动电路222，第一驱动控制信号N1_d、第二驱动控制信号N2_d、第三驱动控制信号N3_d和第四驱动控制信号N4_d经过整流驱动电路222分别驱动第一整流开关N1、第二整流开关N2、第三整流开关N3、第四整流开关N4。
图4示出了图3中的同步整流时序控制器中的部分信号的时序图，其中其余的信号的时序原理也是类似的。这样，所述同步整流时序控制器220就可以利用硬件实现所述整流开关N1-N4的自动同步时序控制，提高同步整流效率，满足Qi标准设计要求。
由于比较器本身具有延迟，在一些特殊的情形下可能会导致整流开关出现短暂的上下整流开关同时导通。因此，本发明中的同步整流时序控制器220还可以包括：连接于第一交流输入端AC1和第一比较器CP1的第一输入端之间的第一电阻R1；连接于第一比较器CP1的第一输入端和接地端之间的第一可调整电流源S1；连接于整流输出端Rect和第一比较器CP1的第二输入端之间的第二电阻R2；连接于第一比较器CP1的第二输入端和接地端之间的第二可调整电流源S2；连接于第二交流输入端AC2和第二比较器CP2的第一输入端之间的第三电阻R3；连接于第二比较器CP2的第一输入端和接地端之间的第三可调整电流源S3；连接于整流输出端Rect和第二比较器CP2的第二输入端之间的第四电阻R4；连接于第二比较器CP2的第二输入端和接地端之间的第四可调整电流源S4。
通过调整各个可调整电流源S1-S4的电流值，可以调整交流信号AC1、AC2与整流输出端RECT的整流信号比较点，进而可以能够调整第一整流开关N1和第三整流开关N3之间的导通死区，避免上下整流开关同时导通，同时提高整流效率。在一个实例中，第一可调整电流源S1的电流值在0-10uA之间，第二可调整电流源S2的电流值在5-12.5uA之间，第三可调整电流源S3的电流值在0-10uA之间，第四可调整电流源S4的电流值在5-12.5uA之间，第一电阻至第四电阻的电阻值为2K。
在一个验证示例中，选择N型LDMOS管作为整流开关，要求整流信号RECT输出12V，驱动能力为1.25A，输入交流信号AC1和AC2为160KHz，幅度12.2V，占空比50％，考虑大电流驱动能力，基于上述同步整流电路进行仿真验证，仿真数据如下图5所示。从图5可以看出，前述设计的同步整流时序控制器220功能正常，同步整流电路的大电流输出驱动能力正常，N型LDMOS管导通压降12.2V-12.147V＝0.053V，符合设计预期，满足设计要求。
如背景技术中所述的，在无线充电Qi标准中，发送端Tx与接收端Rx之间还可以进行通讯，通讯是以2FSK(二进制频移键控)方式传输，通讯包络数据叠加于交流信号(包括第一交流信号AC1和第二交流信号AC2)中，为了解调出所述通讯包络数据，需要事先解调出FSK解调所需的参考频率，现有技术中需要单独设计硬件电路来解调出FSK解调所需的参考频率，无形中也增大了版图面积，抬高了硬件成本。而在本发明中，可以直接将各个驱动控制信号N1_d、N2_d、N3_d、N4_d的频率作为解调所述通讯包络数据时所需的参考频率FSK_1，这样就不需要在设置额外的电路了。
另外，在无线充电标准Qi中需要解调FSK所需的参考频率，那么就需要验证上述同步整流时序控制器220是否如预期般在硬件设计中兼容FSK频率解调，从而避免硬件成本增加，提高同步整流效率及可靠性。
由于基于Qi标准的FSK实装调试解调解码过程中，容易出现以下问题：
1.无负载时接收端RX的信号波动比较大，而有负载时接收端Rx信号的毛刺逐渐变小甚至消失。
2.相同情况下，205KHz调占空比时与160KHz调相位时，接收端Rx的信号波动较大，尤其是无负载160KHz调相位时，接收端Rx信号的杂波最多。
选取FSK调试中采集的最差的交流信号波形曲线，并通过前述同步整流时序控制器220进行仿真，验证其是否兼容FSK频率解调。
图6示出了用于进行同步整流时序控制器220验证的第一验证示例的交流信号AC1、AC2 的波形，其频率为205KHz，10％占空比，整流信号的电压Vrect＝7，无负载。
图6中标尺数据如表1所示。
表1
a b c d e V1 V2 V3 V4 V5 U1 U2 U3 U4
4.92us 680ns 880ns 960ns 960ns 7.2V 6.7V 6.1V 5.3V 3.9V 7.2V 1.6V 1.1V 0.8V
同步整流时序控制器220的仿真结果如图7。
从图7可以看出，主要可以查看得到的参考频率FSK_1，其一个周期是BASELINE和TIMEA之间的时长，为约4.9us，其频率为1/4.9us≈205KHz，符合设计要求。
图8示出了用于进行同步整流时序控制器220验证的第一验证示例的交流信号AC1、AC2的波形，其频率为160KHz调相位，整流信号的电压Vrect＝10.2V，无负载。
图8中标尺数据如表2所示。
表2
a b c d e f g h i j k l
420ns 900ns 1.38us 1.84us 2.1us 2.98us 3.43us 3.88us 4.38us 4.86us 5.26us 6.22us
U1 U2 U3 U4 U5 U6 U7          
0.96 1.76 5.36 7.48 9.24 10.36 11.12          
V1 V2 V3 V4 V5 V6 V7          
0.44 1.2 5.16 7.84 8.48 9.42 10.92          
同步整流时序控制器220的仿真结果如图9。
从图9可以看出，主要可以查看得到的参考频率FSK_1，其一个周期是BASELINE和TIMEA之间的时长，为约6.24us，其频率为1/6.24us≈160KHz，符合设计要求。
综上所述，本发明设计的同步整流时序控制器，通过硬件对整流前的交流信号做高低采样处理，降低了设计难度，避免了软件处理带来的延迟，同时在保证大驱动电流能力的前提下，兼容FSK频率解调功能，避免了硬件成本的增加，提高了同步整流效率及可靠性。
本发明中的“耦接”、“相连”、“相接”、“连接”、“接地”等表示电性连接的词，除了特别说明的外，都表示直接或间接的电性相连，间接的电性相连意味着中间可以串联一些器件，比如电阻或电感等。
上述说明已经充分揭露了本发明的具体实施方式。需要指出的是，熟悉该领域的技术人员对本发明的具体实施方式所做的任何改动均不脱离本发明的权利要求书的范围。相应地，本发明的权利要求的范围也并不仅仅局限于所述具体实施方式。

Claims (13)

  1. 一种同步整流时序控制器，用于对全桥电路中的第一整流开关、第二整流开关、第三整流开关和第四整流开关的导通或关断进行时序控制，其特征在于，所述的同步整流时序控制器包括：
    第一比较器，用于比较第一交流输入端的第一交流信号和整流输出端的整流信号，输出第一交流高采样信号；
    第二比较器，用于比较第二交流输入端的第二交流信号和整流输出端的整流信号，输出第二交流高采样信号；
    第三比较器，用于比较第一交流输入端的第一交流信号和预定低电压阈值，输出第一交流低采样信号；
    第四比较器，用于比较第二交流输入端的第二交流信号和预定低电压阈值，输出第二交流低采样信号；
    逻辑组合电路，用于对第一交流高采样信号、第一交流低采样信号、第二交流高采样信号、第二交流低采样信号进行逻辑组合运算，产生控制第一整流开关导通或截止的第一驱动控制信号、控制第二整流开关导通或截止的第二驱动控制信号、控制第三整流开关导通或截止的第三驱动控制信号，以及控制第四整流开关导通或截止的第四驱动控制信号。
  2. 根据权利要求1所述的同步整流时序控制器，其特征在于，第一驱动控制信号和第四驱动控制信号驱动第一整流开关和第四整流开关同步导通或截止，第二驱动控制信号和第三驱动控制信号驱动第二整流开关和第三整流开关同步导通或截止，第一整流开关和第四整流开关的导通时段与第二整流开关和第三整流开关的导通时段不交叠。
  3. 根据权利要求1所述的同步整流时序控制器，其特征在于，
    第一交流信号和第二交流信号中加载有通讯包络数据，基于各个驱动控制信号的频率得到解调所述通讯包络数据时所需的参考频率。
  4. 根据权利要求1所述的同步整流时序控制器，其特征在于，所述的同步整流时序控制器还包括：
    连接于第一交流输入端和第一比较器的第一输入端之间的第一电阻；
    连接于第一比较器的第一输入端和接地端之间的第一可调整电流源；
    连接于所述整流输出端和第一比较器的第二输入端之间的第二电阻；
    连接于第一比较器的第二输入端和接地端之间的第二可调整电流源；
    连接于第二交流输入端和第二比较器的第一输入端之间的第三电阻；
    连接于第二比较器的第一输入端和接地端之间的第三可调整电流源；
    连接于所述整流输出端和第二比较器的第二输入端之间的第四电阻；
    连接于第二比较器的第二输入端和接地端之间的第四可调整电流源。
  5. 根据权利要求4所述的同步整流时序控制器，其特征在于，通过调整各个可调整电流源的电流值，能够调整第一整流开关和第三整流开关之间的导通死区。
  6. 根据权利要求1所述的同步整流时序控制器，其特征在于，
    所述预定低电压阈值高于且接近地电平，其取值范围为0.1至0.4V。
  7. 根据权利要求6所述的同步整流时序控制器，其特征在于，所述预定低电压阈值为0.25V。
  8. 根据权利要求1所述的同步整流时序控制器，其特征在于，
    所述逻辑组合电路包括第一与非门、第二与非门、第一或非门、第二或非门、第一与门和第二与门，
    其中第一与非门的两个输入端分别与第一比较器的输出端和第四比较器的输出端相连，第一与非门的输出端与第一或非门的一个输入端相连，
    第二与非门的两个输入端分别与第二比较器的输出端和第三比较器的输出端相连，第二与非门的输出端与第二或非门的一个输入端相连，
    第一或非门的输出端与第二或非门的另一个输入端相连，第一或非门的输出端输出第四驱动控制信号，第二或非门的输出端与第一或非门的另一个输入端相连，第二或非门的输出端输出第三驱动控制信号，
    第一与门的三个输入端分别与第一比较器的输出端、第四比较器的输出端和第一或非门的输出端相连，第一与门的输出端输出第一驱动控制信号，
    第二与门的三个输入端分别与第二比较器的输出端、第三比较器的输出端和第二或非门的输出端相连，第二与门的输出端输出第二驱动控制信号。
  9. 根据权利要求1所述的同步整流时序控制器，其特征在于，所述的同步整流时序控制器还包括整流驱动电路，第一驱动控制信号、第二驱动控制信号、第三驱动控制信号和第四驱动控制信号通过所述整流驱动电路分别驱动第一整流开关、第二整流开关、第三整流开关、第四整流开关。
  10. 一种无线充电全桥同步整流电路，其特征在于，所述的无线充电全桥同步整流电路 包括：
    全桥电路，其包括第一整流开关、第二整流开关、第三整流开关和第四整流开关，第一整流开关连接于整流输出端和第一交流输入端之间，第二整流开关连接于整流输出端和第二交流输入端之间，第三整流开关连接于第一交流输入端和接地端之间，第四整流开关连接于第二交流输入端和接地端之间；
    稳压电容，其连接于整流输出端和接地端之间；
    如权利要求1-9任一所述同步整流时序控制器。
  11. 根据权利要求10所述的无线充电全桥同步整流电路，其特征在于，所述的无线充电全桥同步整流电路还包括有：
    次级线圈，其具有第一连接端和第二连接端，其第二连接端作为所述第二交流输入端；
    第一电容，连接于所述次级线圈的第一连接端和第二连接端之间；
    第二电容，其一端与次级线圈的第一连接端相连，其另一端作为所述第一交流输入端。
  12. 根据权利要求10所述的无线充电全桥同步整流电路，其特征在于，第一整流开关、第二整流开关、第三整流开关、第四整流开关均为N型LDMOS管，
    第一整流开关的漏极与所述整流输出端相连，其源极与第一交流输入端相连，第一驱动控制信号通过所述第一整流开关的栅极控制第一整流开关的导通或截止，
    第三整流开关的漏极与第一交流输入端相连，其源极与接地端相连，第三驱动控制信号通过所述第三整流开关的栅极控制第三整流开关的导通或截止，
    第二整流开关的漏极与所述整流输出端相连，其源极与第二交流输入端相连，第二驱动控制信号通过所述第二整流开关的栅极控制第二整流开关的导通或截止，
    第四整流开关的漏极与第二交流输入端相连，其源极与接地端相连，第四驱动控制信号通过所述第四整流开关的栅极控制第四整流开关的导通或截止。
  13. 一种无线充电全桥同步整流系统，其特征在于，所述的无线充电全桥同步整流系统包括：
    如权利要求11所述的无线充电全桥同步整流电路；和
    发送端，其包括脉宽调制单元、直流-交流功率转换单元和初级线圈；
    所述初级线圈能够与所述次级线圈无线耦合形成变压器。
PCT/CN2017/095605 2016-11-30 2017-08-02 同步整流时序控制器、无线充电全桥同步整流电路及系统 WO2018099118A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201611078539.4 2016-11-30
CN201611078539.4A CN106487235B (zh) 2016-11-30 2016-11-30 同步整流时序控制器、无线充电全桥同步整流电路及系统

Publications (1)

Publication Number Publication Date
WO2018099118A1 true WO2018099118A1 (zh) 2018-06-07

Family

ID=58275735

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/095605 WO2018099118A1 (zh) 2016-11-30 2017-08-02 同步整流时序控制器、无线充电全桥同步整流电路及系统

Country Status (2)

Country Link
CN (1) CN106487235B (zh)
WO (1) WO2018099118A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4283856A4 (en) * 2021-02-25 2024-03-13 Huawei Technologies Co., Ltd. RECTIFIER AND CONTROL METHOD AND DEVICE THEREOF

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106487235B (zh) * 2016-11-30 2017-11-10 无锡华润矽科微电子有限公司 同步整流时序控制器、无线充电全桥同步整流电路及系统
CN109802582B (zh) * 2017-11-17 2021-03-05 无锡华润矽科微电子有限公司 无线充电接收端的同步整流电路
CN108768556B (zh) * 2018-03-26 2021-08-31 成都市易冲半导体有限公司 一种用于无线充电发射端解调电路测试的方法
TWI694655B (zh) * 2019-03-11 2020-05-21 茂達電子股份有限公司 頻移鍵控訊號解調系統及方法
CN110299348A (zh) * 2019-07-02 2019-10-01 贵州大学 一种大功率同步整流器结构的三维集成方法
CN110445736B (zh) * 2019-08-09 2021-11-05 美芯晟科技（北京）有限公司 一种fsk解调器、相关设备和方法
CN111355393B (zh) * 2020-05-09 2020-08-25 成都市易冲半导体有限公司 一种无线充电接收端的高度自适应同步整流的控制方法
CN118264135A (zh) * 2024-04-24 2024-06-28 四川杰莱美科技有限公司 一种基于电路信号控制的整流电路及电子装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103546047A (zh) * 2013-10-25 2014-01-29 矽力杰半导体技术(杭州)有限公司 一种适用于电子变压器的同步整流电路及开关电源
CN103973142A (zh) * 2014-06-06 2014-08-06 余丽丽 无线电力传输芯片片内全同步桥式整流器架构以及电路
CN106487235A (zh) * 2016-11-30 2017-03-08 无锡华润矽科微电子有限公司 同步整流时序控制器、无线充电全桥同步整流电路及系统
CN206195614U (zh) * 2016-11-30 2017-05-24 无锡华润矽科微电子有限公司 同步整流时序控制器、无线充电全桥同步整流电路及系统

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5176810B2 (ja) * 2008-09-18 2013-04-03 セイコーエプソン株式会社 整流制御装置、全波整流回路、受電装置、無接点電力伝送システムおよび電子機器
JP5282502B2 (ja) * 2008-09-18 2013-09-04 セイコーエプソン株式会社 整流制御装置、全波整流回路、受電装置、電子機器および無接点電力伝送システム
CN105356564B (zh) * 2015-12-09 2019-04-09 深圳市英特源电子有限公司 无线能量接收系统
CN105471286B (zh) * 2015-12-10 2017-09-29 无锡华润矽科微电子有限公司 同步整流电路、无线充电系统以及同步整流方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103546047A (zh) * 2013-10-25 2014-01-29 矽力杰半导体技术(杭州)有限公司 一种适用于电子变压器的同步整流电路及开关电源
CN103973142A (zh) * 2014-06-06 2014-08-06 余丽丽 无线电力传输芯片片内全同步桥式整流器架构以及电路
CN106487235A (zh) * 2016-11-30 2017-03-08 无锡华润矽科微电子有限公司 同步整流时序控制器、无线充电全桥同步整流电路及系统
CN206195614U (zh) * 2016-11-30 2017-05-24 无锡华润矽科微电子有限公司 同步整流时序控制器、无线充电全桥同步整流电路及系统

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4283856A4 (en) * 2021-02-25 2024-03-13 Huawei Technologies Co., Ltd. RECTIFIER AND CONTROL METHOD AND DEVICE THEREOF

Also Published As

Publication number Publication date
CN106487235B (zh) 2017-11-10
CN106487235A (zh) 2017-03-08

Similar Documents

Publication Publication Date Title
WO2018099118A1 (zh) 同步整流时序控制器、无线充电全桥同步整流电路及系统
US7843708B2 (en) Synchronous rectifier type series resonant converter for operating in intermittence mode
US9685876B2 (en) Resonant converter with capacitive mode detection and associated detection method
US9812983B2 (en) Synchronous rectifier circuit
US9246394B2 (en) Synchronous rectification control circuit and power supply thereof
US10110143B2 (en) Synchronous rectifier circuit and control method thereof
US8218340B2 (en) Switching power supply apparatus and primary side control circuit
US10608542B2 (en) Power conversion device with operation in dual-leg resonant mode or single-leg resonant mode
CN111049385B (zh) 用于通信的系统以及用于检测的设备和方法
WO2017049900A1 (zh) Igbt短路检测保护电路及基于igbt的可控整流电路
US8547072B2 (en) Phase control apparatus
US20140268894A1 (en) Dc-dc converter
US20100302824A1 (en) Power source apparatus
CN209930162U (zh) 同步整流电路
CN105634260B (zh) 输出短路保护电路
US9380678B2 (en) Auxiliary power supply circuit of two wire dimmer
US20130271271A1 (en) Receiving control circuit for a wall control interface with phase modulation and detection for power management
US11522537B2 (en) Galvanic isolated gate driver based on a transformer used for both power transfer from primary to secondary coil and data transmission
WO2018136147A1 (en) Transformer based gate drive circuit
US10084451B2 (en) Level shifter circuit
CN105471286A (zh) 同步整流电路、无线充电系统以及同步整流方法
TW202345506A (zh) 開關電源和用在開關電源中的方法
TW202341607A (zh) 開關電源和用在開關電源中的方法
US10784794B2 (en) GaN FET gate driver for self-oscillating converters
US12047011B2 (en) Gate driver circuit for a synchronous rectifier of a wireless power receiver system

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17876504

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17876504

Country of ref document: EP

Kind code of ref document: A1