WO2018096973A1

WO2018096973A1 - Pulse frequency control circuit, microcontroller, dc-dc converter, and pulse frequency control method

Info

Publication number: WO2018096973A1
Application number: PCT/JP2017/040869
Authority: WO
Inventors: 勝幸今村; 剛明本
Original assignee: パナソニックＩｐマネジメント株式会社
Priority date: 2016-11-28
Filing date: 2017-11-14
Publication date: 2018-05-31
Also published as: JPWO2018096973A1; CN110024288A; US20190280598A1; CN110024288B; JP6826612B2; US10530252B2

Abstract

A pulse frequency control circuit (1) includes: a selection circuit (12) for acquiring and selecting a plurality of reference clocks having different phases with the same reference period; a setting register (13) for storing information specifying a set period a unit of which is a first period of time shorter than the reference period; and a control circuit (15) for controlling, on the basis of the information stored in the setting register (13), the selection circuit (12) to sequentially and repeatedly select, as rising determined edges, rising edges that rise at intervals of the set period from among rising edges of the plurality of reference clocks. The selection circuit (12) sequentially and repeatedly generates output pulses that rise at every timing of the selected rising determined edges, thereby outputting an output pulse train comprising the output pulses.

Description

Pulse frequency control circuit, microcomputer, DCDC converter, and pulse frequency control method

The present invention relates to a pulse frequency control circuit for controlling the frequency of an output pulse, a microcomputer including the pulse frequency control circuit, a DCDC converter including the pulse frequency control circuit, and a pulse frequency control method for controlling the frequency of an output pulse. About.

Conventionally, a DCDC converter having a switching element capable of repeatedly switching between a conductive state and a non-conductive state is known.

In general, such control of the output voltage of the DCDC converter is performed by controlling a control signal composed of a pulse train applied to the switching element for repeatedly switching between a conductive state and a non-conductive state (see Patent Document 1). ).

The control of the control signal composed of such a pulse train includes a pulse duty control for controlling the duty ratio of the pulse train and a pulse frequency control for controlling the frequency of the pulse train.

Conventionally, as a control circuit for performing the pulse frequency control, when a reference clock signal serving as a reference is input, a pulse train having a cycle set to an arbitrary integer multiple of the clock cycle of the reference clock signal is output. There is known a pulse frequency control circuit capable of performing the following.

JP 2013-236295 A

The conventional pulse frequency circuit cannot output a pulse train having a period in units shorter than the clock period of the reference clock signal.

Therefore, the present invention has been made in view of such problems, and a pulse frequency control circuit, a microcomputer, and a DCDC converter capable of outputting a pulse train having a period shorter than the clock period of a reference clock signal. And a pulse frequency control method.

A pulse frequency control circuit according to the present invention specifies a selection circuit that acquires and selects a plurality of reference clocks having the same reference period and different phases, and a set period in units of a first period shorter than the reference period Based on the setting register for storing information to be stored and the information stored in the setting register, a rising edge rising at an interval of the setting period is selected from the rising edges of the plurality of reference clocks with respect to the selection circuit. And a control circuit that sequentially and repeatedly selects the rising decision edge, and the selection circuit repeatedly generates output pulses that rise at every timing of the rising decision edge to be selected, thereby outputting an output pulse train composed of the output pulses. It is characterized by that.

A microcomputer according to the present invention includes the pulse frequency control circuit and a setting unit that sets a value in the setting register.

When the DCDC converter according to the present invention receives the microcomputer, a switching element that switches a DC input voltage in accordance with an output pulse train output from the selection circuit, and an input voltage that is switched by the switching element. An energy conversion circuit that generates an electromotive force due to a current variation caused by the voltage variation of the input voltage and outputs a voltage corresponding to the electromotive force; and a DC output by rectifying and smoothing the voltage output from the energy conversion circuit A rectifying / smoothing circuit that outputs a voltage, and the microcomputer further includes a comparison unit that compares the potential of the output voltage with a predetermined potential, and the setting unit is based on a result of comparison by the comparison unit. The setting is performed so that the potential of the output voltage approaches the predetermined potential.

A pulse frequency control method according to the present invention includes a selection circuit that acquires and selects a plurality of reference clocks having the same reference period and different phases, a pulse frequency control circuit that includes a setting register, and a control circuit. A control method, wherein the setting register stores information for specifying a setting period in units of a first period shorter than the reference period, and information stored in the setting step by the control circuit Based on the control step, the selection circuit sequentially and repeatedly selects the rising edge rising at the set cycle interval as the rising determination edge from the plurality of reference clocks. By successively generating output pulses that rise at every decision edge timing, Characterized in that it comprises an output step for outputting the output pulse train consisting of output pulses.

According to the pulse frequency control circuit, the microcomputer, the DCDC converter, and the pulse frequency control method, it is possible to output a pulse train having a cycle whose unit is a period shorter than the clock cycle of the reference clock signal.

FIG. 1 is a block diagram illustrating a configuration of a DCDC converter according to an embodiment. FIG. 2 is a block diagram showing a configuration of the pulse frequency control circuit according to the embodiment. FIG. 3 is a first timing diagram illustrating a specific example of an operation performed by the PWM phase adjustment circuit according to the embodiment in cooperation with another circuit. FIG. 4 is a second timing diagram illustrating a specific example of an operation performed by the PWM phase adjustment circuit according to the embodiment in cooperation with another circuit. FIG. 5 is a flowchart 1 of high-resolution pulse train output processing according to the embodiment. FIG. 6 is a flowchart 2 of high-resolution pulse train output processing according to the embodiment. FIG. 7 is a first timing diagram illustrating a specific example of an operation performed by the PWM phase adjustment circuit according to the modification in cooperation with another circuit. FIG. 8 is a second timing diagram illustrating a specific example of an operation performed by the PWM phase adjustment circuit according to the modification in cooperation with another circuit. FIG. 9 is a block diagram showing a configuration of a DCDC converter according to another modification. FIG. 10 is a block diagram showing a configuration of a DCDC converter according to another modification.

Specific examples of a pulse frequency control circuit, a microcomputer, a DCDC converter, and a pulse frequency control method according to one embodiment of the present invention are described below with reference to the drawings. Each of the embodiments described below shows a preferred specific example in the present invention. Accordingly, the numerical values, shapes, materials, components, arrangement positions and connection forms of components, steps, steps, and the like shown in the following embodiments are merely examples and are not intended to limit the present invention. Absent. Therefore, among the constituent elements in the following embodiments, constituent elements that are not described in the independent claims indicating the highest concept in the present invention are described as arbitrary constituent elements.

Each figure is a schematic diagram and is not necessarily shown strictly. Moreover, in each figure, the same code | symbol is attached | subjected to the substantially same structure, The overlapping description is abbreviate | omitted or simplified.

(Embodiment)
[1. Constitution]
FIG. 1 is a block diagram showing a configuration of a DCDC converter 3 according to the present embodiment.

As shown in the figure, the DCDC converter 3 includes a switching element 31, an energy conversion circuit 32, a rectifying / smoothing circuit 33, and a microcomputer 2.

As an example, the switching element 31 is realized by a gallium nitride FET (Field Effective Transistor), and switches a DC input voltage according to a control signal (an output pulse train described later) output from the microcomputer 2. Here, switching refers to repeatedly switching between a conductive state and a non-conductive state.

As an example, the energy conversion circuit 32 is realized by a transformer, and when an input voltage switched by the switching element 31 is input, an electromotive force is generated due to a current variation caused by the voltage variation of the input voltage, and the generated electromotive force is generated. The voltage according to is output.

As an example, the rectifying / smoothing circuit 33 is realized by one or more diodes and one or more capacitors, and rectifies and smoothes the voltage output from the energy conversion circuit 32 to output a DC output voltage.

The microcomputer 2 includes a comparison unit 21, a setting unit 22, and a pulse frequency control circuit 1.

The comparison unit 21 is realized by a comparator as an example, and compares the potential of the output voltage with a predetermined potential.

As an example, the setting unit 22 is realized by a processor (not shown) included in the microcomputer 2 executing a program stored in a memory (not shown) included in the microcomputer 2, and the pulse frequency control circuit 1. A value is set in a setting register (described later) included in. More specifically, the above setting is performed based on the result of comparison by the comparison unit 21 so that the potential of the output voltage approaches the predetermined potential.

FIG. 2 is a block diagram showing the configuration of the pulse frequency control circuit 1.

As shown in the figure, the pulse frequency control circuit 1 includes a reference clock generation circuit 11, a selection circuit 12, a setting register 13, a cumulative addition circuit 14, and a control circuit 15.

The reference clock generation circuit 11 generates a plurality of reference clocks acquired by a selection circuit 12 described later from a microcomputer clock (input reference clock) that the microcomputer 2 uses as a clock signal. More specifically, N reference clocks having the same period (reference period) as the input reference clock and having phases shifted from each other by 1 / N (N is an integer of 2 or more) are generated.

The reference clock generation circuit 11 is realized by a DLL (Delay Locked Loop) circuit as an example.

The selection circuit 12 acquires and selects a plurality of reference clocks having the same reference period and different phases. More specifically, N reference clocks generated by the reference clock generation circuit 11 are acquired and selected.

Further, the selection circuit 12 is controlled by a control circuit 15 (described later), thereby repeatedly selecting a rising determination edge (described later) from the rising edges of the plurality of reference clocks, and the timing of the rising determination edge to be selected. The generated output pulse train is output by sequentially generating output pulses that rise every time.

The selection circuit 12 is also controlled by the control circuit 15 to select a corresponding falling decision edge (described later) for each rising decision edge to be selected, and an output pulse that rises at the timing of one rising decision edge. However, the output pulse is generated so as to fall at the timing of one falling decision edge corresponding to the one rising decision edge.

The setting register 13 stores information for specifying a set period in units of a period (first period) shorter than the reference period. More specifically, a cycle setting register (first register) 131 that stores first information for specifying an integer value M (M is an integer of 1 or more) when the set cycle is divided by the reference cycle; , A high-resolution period setting register (second register) 132 for storing second information specifying the decimal value L of the quotient (L is a decimal number of 0 or more and less than 1), and an integer value P (P is 1 or more and less than M) And a duty setting register (third register) 133 for storing third information for specifying an integer).

These register values can be set at any time by the setting unit 22.

The cumulative addition circuit 14 accumulates L / 2 each time the output pulse output from the selection circuit 12 rises or falls based on the second information stored in the high resolution period setting register (second register) 132. In the case of addition and cumulative addition J (J is an integer of 0 or more) times, a cumulative addition value LL (J) is calculated.

Further, the cumulative addition circuit 14 subtracts 1 from LL (J) to obtain a new LL (J) when LL (J) becomes 1 or more by cumulative addition of L / 2. (2) Information stored in the cycle setting register (first register) 131 is rewritten from information specifying M to information specifying M + 1. (3) After this rewriting, the selection circuit 12 When the output pulse train output from the signal rises, the information stored in the cycle setting register (first register) 131 is rewritten from information specifying M + 1 to information specifying M. Further, the cumulative addition circuit 14 (4) stores information stored in the duty setting register (third register) 133 when LL (J) becomes 1 or more by cumulative addition of L / 2. The information specifying P is rewritten to the information specifying P + 1. (5) After this rewriting, when the output pulse train output from the selection circuit 12 rises, the duty setting register (third register) 133 stores it. The information to be rewritten is changed from information specifying P + 1 to information specifying P.

Based on the information stored in the setting register 13, the control circuit 15 determines a rising edge that rises at the interval of the set period from the rising edges of the plurality of reference clocks to the selection circuit 12. Are repeatedly selected. More specifically, (1) based on the first information stored in the period setting register (first register) 131, the normal pulse having a period of M times the reference period is sequentially generated, so that the normal A normal pulse train composed of pulses is generated, and (2) based on the second information stored in the high resolution period setting register (second register) 132, K is selected for the selection circuit 12 (K is an integer of 0 or more). In the second time, the rising edge of the reference clock that rises in a phase delayed by LL (2 × K) times the reference period from the first rising edge of the normal pulse is selected as the rising decision edge, and the K + 1th time A phase delayed by a period LL (2 × (K + 1)) times the reference period from the rising edge of the normal pulse that rises next to the first rising edge The rising decision edge is sequentially and repeatedly selected so that the rising edge of the reference clock rising at is selected as the rising decision edge.

Further, the control circuit 15 causes the selection circuit 12 to start the reference period LL (2) from the first rising edge of the normal pulse train based on the third information stored in the duty setting register (third register) 133. When the rising edge of the reference clock that rises with a phase delayed by a period of (× K) times is selected as the first rising edge, it is further P + LL (2 × K + 1) times the reference period from the first rising edge. The rising edge of the reference clock that rises with a phase delayed by the period is selected as the first falling decision edge corresponding to the first rising decision edge.

The control circuit 15 includes a PWM binary counter 151, a cycle control circuit 152, a PWM waveform generation circuit 153, and a PWM phase adjustment circuit 154.

The PWM binary counter 151 is a counter that increments the count value by 1 at the timing of the rising edge of the input microcomputer clock, and outputs the incremented count value at the timing of the rising edge of the next microcomputer clock.

The cycle control circuit 152 initializes the count value every time the count value of the PWM binary counter 151 matches the value of M−1, based on the first information stored in the cycle setting register 131 sequentially and repeatedly. . Here, to initialize the count value means to set the count value to the initial value 0.

The PWM waveform generation circuit 153 rises at the timing when the initialized value is output from the PWM binary counter 151 based on the third information stored in the duty setting register 133 sequentially, and (2) PWM binary A normal pulse that falls at the timing when a value that matches the value of P is output from the counter 151 is repeatedly generated and output sequentially.

Based on the second information stored in the high resolution period setting register 132, the PWM phase adjustment circuit 154 makes the first rise of the normal pulse to the selection circuit 12 for the Kth (K is an integer of 0 or more) times. The rising edge of the reference clock that rises with a phase delayed by LL (2 × K) times the reference period from the edge is selected as the rising decision edge, and rises next to the first rising edge at the (K + 1) th time. The rising decision edge is sequentially selected so that the rising edge of the reference clock rising in a phase delayed by LL (2 × (K + 1)) times the reference period from the rising edge of the normal pulse is selected as the rising decision edge. Let it be selected repeatedly.

Further, the PWM phase adjustment circuit 154 sequentially repeats the third information stored in the duty setting register 133 to the selection circuit 12 from the first rising edge of the normal pulse train to the LL (2 × K) When the rising edge of the reference clock that rises with a phase delayed by a double period is selected as the first rising decision edge, it is further P + LL (2 × K + 1) times the reference period from the first rising edge. The rising edge of the reference clock rising at a phase delayed by the period is selected as the first falling determination edge corresponding to the first rising determination edge.

Hereinafter, the operation performed by the PWM phase adjustment circuit 154 in cooperation with other circuits will be described with reference to the drawings and specific examples.

3 and 4 are timing charts showing a specific example of the operation performed by the PWM phase adjustment circuit 154 in cooperation with other circuits.

3 and 4, N is 5, M is 6, the first information specifying M is 5 indicating M−1, and the second information specifying L and L is 0.2. Yes, P is 3, the third information specifying P is 2 indicating P-1, and an example in which the period of the microcomputer clock is t is illustrated as a specific example.

3 and 4, the “reference point” indicates a time point when the PWM binary counter outputs 0 when the cumulative addition value LL calculated by the cumulative addition circuit 14 is zero.

FIG. 3 is a timing diagram including a period from the reference point to a point in time when 10 times the period of the microcomputer clock elapses. FIG. 4 shows a period 25 times the period of the microcomputer clock from the reference point. It is a timing diagram including a period up to the time when elapses.

As shown in FIG. 3, the reference clock generation circuit 11 has the same period as the microcomputer clock, and is five (that is, N) whose phases are shifted from each other by 0.2 t (that is, (1 / N) × t). The reference clock is output. That is, the reference clock generation circuit 11 includes the 0th reference clock having the same phase as the microcomputer clock, the first reference clock having a phase delayed by 0.2 t from the microcomputer clock, and the first reference clock having a phase delayed by 0.4 t from the microcomputer clock. 2 reference clocks, a third reference clock having a phase delayed by 0.6 t from the microcomputer clock, and a fourth reference clock having a phase delayed by 0.8 t from the microcomputer clock are output.

At the reference point, the PWM waveform generation circuit 153 starts outputting a normal pulse that rises at a timing when 0 is output from the PWM binary counter 151.

Then, the PWM phase adjustment circuit 154 causes the selection circuit 12 to rise to the 0th reference that rises with a phase (that is, the same phase) delayed by 0 t (that is, the value 0 × t of the cumulative addition value LL) from the timing of the rising edge of the normal pulse. The rising edge of the clock is selected as the 0th rising determination edge. Then, the selection circuit 12 starts generating the output pulse so that the rising edge timing of the output pulse to be generated becomes the reference point. Then, the cumulative addition circuit 14 cumulatively adds 0.2 (that is, L / 2) to the value 0 of the cumulative addition value LL, and sets the value of the cumulative addition value LL to 0.2.

Next, the PWM waveform generation circuit 153 generates a normal pulse so that the generated normal pulse falls at the timing when 3 (that is, P) is output from the PWM binary counter 151. For this reason, the duty of the normal pulse generated by the PWM waveform generation circuit 153 is 3t (that is, P × t).

On the other hand, the PWM phase adjustment circuit 154 causes the selection circuit 12 to rise to a first reference that rises with a phase delayed by 3.2 t (that is, (P value 3 + cumulative addition value LL value 0.2) × t) from the reference point. The rising edge of the clock is selected as the 0th falling decision edge. Then, the selection circuit 12 generates the output pulse so that the timing of the falling edge of the output pulse to be generated is the timing delayed by 3.2 t from the reference point. Therefore, the duty of the output pulse generated by the selection circuit 12 is 3.2t (that is, (P + L / 2) × t).

Then, the cumulative addition circuit 14 cumulatively adds 0.2 (that is, L / 2) to the cumulative addition value LL, and sets the cumulative addition value LL to 0.4.

Next, the PWM waveform generation circuit 153 starts outputting a new normal pulse that rises at a timing (first rising point in FIG. 3) when 0 is output from the PWM binary counter 151. For this reason, the period of the normal pulse output last time by the PWM waveform generation circuit 153 is 6t (that is, M × t).

Next, the PWM phase adjustment circuit 154 causes the selection circuit 12 to rise the second reference clock that rises with a phase delayed by 0.4 t from the first rise point (that is, the value 0.4 × t of the cumulative addition value LL). The edge is selected as the first rising edge. Then, the selection circuit 12 generates the output pulse so that the rising edge timing of the generated output pulse is delayed by 0.4 t from the first rising point. Therefore, the cycle of the output pulse generated by the selection circuit 12 is 6.4t.

Then, the cumulative addition circuit 14 cumulatively adds 0.2 (that is, L / 2) to the cumulative addition value LL, and sets the cumulative addition value LL to 0.6.

Next, the PWM phase adjustment circuit 154 rises to the selection circuit 12 with a phase delayed by 3.6 t (that is, (P value 3 + cumulative addition value LL value 0.6) × t) from the first rising point. The rising edge of the third reference clock is selected as the first falling decision edge. Then, the selection circuit 12 starts generating a new output pulse so that the timing of the falling edge of the output pulse to be generated is 3.6 t delayed from the first rising point. For this reason, the duty of the output pulse generated by the selection circuit 12 is 3.2 t.

Then, the cumulative addition circuit 14 cumulatively adds 0.2 (that is, L / 2) to the cumulative addition value LL, and sets the cumulative addition value LL to 0.8.

The subsequent operation will be described with reference to FIG.

After the cumulative addition circuit 14 sets the cumulative addition value to 0.8, the PWM waveform generation circuit 153 starts a new normal operation that rises at the timing when the PWM binary counter 151 outputs 0 (second rising point in FIG. 4). Start pulse output. For this reason, the period of the normal pulse output last time by the PWM waveform generation circuit 153 is 6t (that is, M × t).

Next, the PWM phase adjustment circuit 154 causes the selection circuit 12 to enter a fourth reference clock (see FIG. 4) that rises with a phase delayed by 0.8 t (that is, the value of the cumulative addition value LL of 0.8 × t) from the second rising point. 4) is selected as the second rising decision edge. Then, the selection circuit 12 starts generating the output pulse so that the rising edge timing of the output pulse to be generated is 0.8 t delayed from the second rising point. Therefore, the cycle of the output pulse generated by the selection circuit 12 is 6.4t.

Then, the cumulative addition circuit 14 cumulatively adds 0.2 (that is, L / 2) to the cumulative addition value LL, and sets the cumulative addition value LL to 1.

Here, since the cumulative addition value LL becomes 1 or more, the cumulative addition circuit 14 subtracts 1 from the cumulative addition value LL to set the new cumulative addition value LL to 0, and the value stored in the cycle setting register 131. Is changed from 5 (ie, M−1) to 6 (ie, M−1 + 1), and the value stored in the duty setting register 133 is changed from 2 (ie, P−1) to 3 (ie, P−). Rewrite to 1 + 1).

Next, the PWM waveform generation circuit 153 generates a normal pulse so that the generated normal pulse falls at the timing when 4 (that is, P + 1) is output from the PWM binary counter 151. Therefore, the duty of the normal pulse generated by the PWM waveform generation circuit 153 is 4t (that is, (P + 1) t).

On the other hand, the PWM phase adjustment circuit 154 rises to the selection circuit 12 with a phase delayed by 4t (that is, (P (that is, 3) + 1 + the value 0 of the cumulative addition value LL) × t) from the second rising point. The rising edge of the reference clock is selected as the second falling decision edge. Then, the selection circuit 12 generates the output pulse so that the timing of the falling edge of the output pulse to be generated is the timing delayed by 4t from the second rising point. For this reason, the duty of the output pulse generated by the selection circuit 12 is 3.2 t.

Then, the cumulative addition circuit 14 cumulatively adds 0.2 (that is, L / 2) to the cumulative addition value LL, and sets the cumulative addition value LL to 0.2.

Here, since the PWM binary counter 151 has M of 6, it continues counting until the count value becomes 6. Therefore, the PWM binary counter 151 outputs the count value 6 after outputting the count value 5, and then outputs the initial value 0.

Next, the PWM waveform generation circuit 153 starts outputting a normal pulse that rises at a timing (third rising point in FIG. 4) when 0 is output from the PWM binary counter 151. For this reason, the period of the normal pulse last output by the PWM waveform generation circuit 153 is 7t.

Next, the PWM phase adjustment circuit 154 causes the selection circuit 12 to start with a first reference clock (see FIG. 5) that rises with a phase delayed by 0.2 t (that is, the value 0.2 × t of the cumulative addition value LL) from the third rising point. 4) is selected as the third rising determination edge. Then, the selection circuit 12 starts generating the output pulse so that the rising edge timing of the output pulse to be generated is delayed by 0.2 t from the third rising point. Therefore, the cycle of the output pulse generated by the selection circuit 12 is 6.4t.

Then, the cumulative addition circuit 14 rewrites the value stored in the cycle setting register 131 from 6 (ie, M−1 + 1) to 5 (ie, M−1), and changes the value stored in the duty setting register 133 to Rewrite from 3 (ie, P-1 + 1) to 2 (ie, P-1).

Thereafter, the PWM phase adjustment circuit 154 repeatedly performs the same operation, and in cooperation with other circuits, the duty is 3.2t (that is, (P + L / 2) × t) from the selection circuit 12 and the cycle is The selection circuit 12 is controlled so that the output pulse of 6.4t (that is, (M + L) × t) is continuously output.

As described with reference to the above specific example, the pulse frequency control circuit 1 configured as described above is configured so that the period setting register is set by the setting unit 22 when the period of the microcomputer clock that the microcomputer 2 uses as the clock signal is t. 131 is set to M-1 (M is an integer equal to or greater than 1), L is set to the high resolution cycle setting register 132 (L is a decimal number from 0 to less than 1), and the duty setting register 133 is set to P-1 (P is When an integer greater than or equal to 1 and less than M is set, an output pulse having a duty of (P + L / 2) × t and a cycle of (M + L) × t is continuously output. Here, since L is a decimal number, the pulse period of the output pulse can be a period having a period shorter than the period of the microcomputer clock as a unit.

[2. Operation]
The pulse frequency control circuit 1 configured as described above performs high-resolution pulse train output processing as its characteristic operation.

This high-resolution pulse train output process is a process for outputting an output pulse train having a period in units shorter than the clock period of the input microcomputer clock.

Hereinafter, this high-resolution pulse train output process will be described with reference to the drawings.

5 and 6 are flowcharts of the high-resolution pulse train output process.

In the high-resolution pulse train output processing, the PWM binary counter 151 is initialized to 0, the cumulative addition value LL is initialized to 0, and the setting unit 22 causes the cycle setting register 131, the high-resolution cycle setting register 132, and the duty setting register 133 to be set. Is set by inputting a microcomputer clock to the pulse frequency control circuit 1.

Here, for the sake of explanation, when the period of the microcomputer clock is t and the number of reference clocks is N (N is an integer of 2 or more) and the high-resolution pulse train output process is started, the period setting register 131 stores the period. The value to be stored is M-1 (M is an integer equal to or greater than 1), the value stored in the high resolution cycle setting register 132 is L (L is a decimal number between 0 and less than 1), and the value stored in the duty setting register 133 is P −1 (P is an integer of 1 or more and less than M).

When the high-resolution pulse train output processing is started, the reference clock generation circuit 11 starts generating N reference clocks whose period is t and whose phases are shifted by 1 / N from each other. The PWM binary counter 151 Starts counting the number of rising edges of the microcomputer clock. Thereafter, as long as the microcomputer clock is input, the reference clock generation circuit 11 continues to generate the N reference clocks, and the PWM binary counter 151 is initialized at times to detect the rising edge of the microcomputer clock. Continue to count the number.

After the PWM binary counter 151 starts counting, when the count value matches M−1, the PWM binary counter 151 initializes the count value and outputs the initial value 0 (step S5).

Then, the PWM waveform generation circuit 153 starts generating a normal pulse that rises at an output timing of an initial value 0 (step S10).

Thereafter, when the time LL × t has elapsed since the normal pulse rises, the PWM phase adjustment circuit 154 causes the selection circuit 12 to reference the clock that rises with a phase delayed by LL × t after the normal pulse rises. Are selected as rising edge determination edges. Then, the selection circuit 12 starts generating an output pulse that rises at a timing delayed by LL × t after the normal pulse rises (step S15). Then, the cumulative addition circuit 14 cumulatively adds L / 2 to the cumulative addition value LL (step S20).

When L / 2 is cumulatively added, the cumulative addition circuit 14 determines whether or not the cumulative addition value LL is 1 or more (step S25).

In the process of step S25, when the cumulative addition value LL is not 1 or more (step S25: No), when the PWM binary counter 151 outputs the count value P-1 (step S30), the PWM waveform generation circuit 153 outputs the PWM binary value. The generated normal pulse falls at the timing when the counter 151 outputs the count value P-1 (step S35).

On the other hand, when the time of (P + LL) × t has elapsed since the normal pulse rises, the PWM phase adjustment circuit 154 delays the selection circuit 12 by (P + LL) × t after the normal pulse rises. The rising edge of the reference clock that rises at is selected as the falling edge determination edge. Then, the selection circuit 12 falls the output pulse to be generated at a timing delayed by (P + LL) × t after the normal pulse rises (step S40). Then, the cumulative addition circuit 14 cumulatively adds L / 2 to the cumulative addition value LL (step S45).

When L / 2 is cumulatively added, the cumulative addition circuit 14 determines whether or not the cumulative addition value LL is 1 or more (step S50).

In the process of step S50, when the cumulative addition value LL is not 1 or more (step S50: No), when the PWM binary counter 151 outputs the count value 0 (step S55), the pulse frequency control circuit 1 again performs step S10. Proceed to the process and continue the subsequent processes.

In the process of step S25, when the cumulative addition value LL is 1 or more (step S25: Yes), the cumulative addition circuit 14 subtracts 1 from the cumulative addition value LL to obtain a new cumulative addition value LL ( Simultaneously with step S100 (see FIG. 6), the value stored in the cycle setting register 131 is rewritten from M-1 to M, and the value stored in the duty setting register 133 is rewritten from P-1 to P (step S105).

Thereafter, when the PWM binary counter 151 outputs the count value P (step S110), the PWM waveform generation circuit 153 causes the generated normal pulse to fall at the timing when the count value P is output from the PWM binary counter 151 (step S115). ).

On the other hand, when the time of (P + 1 + LL) × t has elapsed since the normal pulse rises, the PWM phase adjustment circuit 154 delays the selection circuit 12 by (P + 1 + LL) × t after the normal pulse rises. The rising edge of the reference clock that rises at is selected as the falling edge determination edge. Then, the selection circuit 12 falls the generated output pulse at a timing delayed by (P + 1 + LL) × t after the normal pulse rises (step S120). Then, the cumulative addition circuit 14 cumulatively adds L / 2 to the cumulative addition value LL (step S125).

Thereafter, when the PWM binary counter 151 outputs a count value 0 (step S130), the PWM waveform generation circuit 153 starts generating a normal pulse that rises at the output timing of the initial value 0 (step S135).

Thereafter, when the time LL × t has elapsed since the normal pulse rises, the PWM phase adjustment circuit 154 causes the selection circuit 12 to reference the clock that rises with a phase delayed by LL × t after the normal pulse rises. Are selected as rising edge determination edges. Then, the selection circuit 12 starts generating an output pulse that rises at a timing delayed by LL × t after the normal pulse rises (step S140). Then, the cumulative addition circuit 14 rewrites the value stored in the cycle setting register 131 from M to M-1, and rewrites the value stored in the duty setting register 133 from P to P-1 (step S145).

When the process of step S145 is completed, the pulse frequency control circuit 1 proceeds to the process of step S20 (see FIG. 5) again and continues the subsequent processes.

In the processing of step S50, when the cumulative addition value LL is 1 or more (step S50: Yes), the cumulative addition circuit 14 subtracts 1 from the cumulative addition value LL to obtain a new cumulative addition value LL ( Simultaneously with step S150 (see FIG. 6), the value stored in cycle setting register 131 is rewritten from M-1 to M, and the value stored in duty setting register 133 is rewritten from P-1 to P (step S155).

When the process of step S155 ends, the pulse frequency control circuit 1 proceeds to the process of step S130 and continues the subsequent processes.

[3. Summary]
As described above, the pulse frequency control circuit 1 according to the present embodiment can output an output pulse train having a period whose unit is a period shorter than the period of the microcomputer clock. For this reason, by using this pulse frequency control circuit 1, the switching frequency control of the switching element 31 can be performed as compared with the case of using the conventional pulse frequency control circuit that outputs an output pulse train having a cycle that is an integral multiple of the cycle of the microcomputer clock. Can be realized with higher resolution.

Therefore, the DCDC converter 3 according to the present embodiment using the pulse frequency control circuit 1 can control the output voltage with higher accuracy than the conventional DCDC converter using the conventional pulse frequency control device.

(Modification)
In the embodiment, regarding the operation performed by the PWM phase adjustment circuit 154 in cooperation with other circuits, when M is 6 and P is 3 using FIGS. 3 and 4, that is, the duty ratio is The case of 50% has been described as a specific example.

On the other hand, here, a specific example in which the duty ratio does not become 50% will be described with reference to the drawings for the operation performed by the PWM phase adjustment circuit 154 in cooperation with other circuits.

7 and 8 are timing charts showing another specific example of the operation performed by the PWM phase adjustment circuit 154 in cooperation with other circuits.

7 and 8, N is 5, M is 6, the first information specifying M is 5 indicating M-1, and the second information specifying L and L is 0.2. Yes, P is 2, the third information specifying P is 1 indicating P-1, and an example in which the period of the microcomputer clock is t is illustrated as a specific example.

Next, the PWM waveform generation circuit 153 generates a normal pulse so that the generated normal pulse falls at the timing when 2 (that is, P) is output from the PWM binary counter 151. For this reason, the duty of the normal pulse generated by the PWM waveform generation circuit 153 is 2t (that is, P × t).

On the other hand, the PWM phase adjustment circuit 154 causes the selection circuit 12 to rise to a first reference that rises with a phase delayed by 2.2 t (ie, (P value 2 + cumulative addition value LL value 0.2) × t) from the reference point. The rising edge of the clock is selected as the 0th falling decision edge. Then, the selection circuit 12 generates the output pulse so that the timing of the falling edge of the output pulse to be generated is the timing delayed by 2.2 t from the reference point. Therefore, the duty of the output pulse generated by the selection circuit 12 is 2.2t (that is, (P + L / 2) × t).

Next, the PWM waveform generation circuit 153 starts outputting a new normal pulse that rises at a timing (first rising point in FIG. 7) when 0 is output from the PWM binary counter 151. For this reason, the period of the normal pulse output last time by the PWM waveform generation circuit 153 is 6t (that is, M × t).

Next, the PWM phase adjustment circuit 154 rises to the selection circuit 12 with a phase delayed by 2.6 t (ie, (P value 2 + cumulative addition value LL value 0.6) × t) from the first rising point. The rising edge of the third reference clock is selected as the first falling decision edge. Then, the selection circuit 12 starts generating a new output pulse so that the timing of the falling edge of the output pulse to be generated is 2.6 t delayed from the first rising point. For this reason, the duty of the output pulse generated by the selection circuit 12 is 2.2 t.

The subsequent operation will be described with reference to FIG.

After the cumulative addition circuit 14 sets the cumulative addition value to 0.8, the PWM waveform generation circuit 153 starts a new normal operation that rises at the timing when the PWM binary counter 151 outputs 0 (second rising point in FIG. 8). Start pulse output. For this reason, the period of the normal pulse output last time by the PWM waveform generation circuit 153 is 6t (that is, M × t).

Next, the PWM phase adjustment circuit 154 causes the selection circuit 12 to enter a fourth reference clock (see FIG. 4) that rises with a phase delayed by 0.8 t (that is, the value of the cumulative addition value LL of 0.8 × t) from the second rising point. 8) is selected as the second rising decision edge. Then, the selection circuit 12 starts generating the output pulse so that the rising edge timing of the output pulse to be generated is 0.8 t delayed from the second rising point. Therefore, the cycle of the output pulse generated by the selection circuit 12 is 6.4t.

Here, since the cumulative addition value LL becomes 1 or more, the cumulative addition circuit 14 subtracts 1 from the cumulative addition value LL to set the new cumulative addition value LL to 0, and the value stored in the cycle setting register 131. Is changed from 5 (ie, M−1) to 6 (ie, M−1 + 1), and the value stored in the duty setting register 133 is changed from 1 (ie, P−1) to 2 (ie, P−). Rewrite to 1 + 1).

Next, the PWM waveform generation circuit 153 generates a normal pulse so that the generated normal pulse falls at the timing when 3 (that is, P + 1) is output from the PWM binary counter 151. For this reason, the duty of the normal pulse generated by the PWM waveform generation circuit 153 is 3t (that is, (P + 1) t).

On the other hand, the PWM phase adjustment circuit 154 rises to the selection circuit 12 with a phase delayed by 3t from the second rising point (that is, (P (that is, 2) + 1 + the value 0 of the cumulative addition value LL) × t). The rising edge of the reference clock is selected as the second falling decision edge. Then, the selection circuit 12 generates the output pulse so that the timing of the falling edge of the output pulse to be generated is 3 t delayed from the second rising point. For this reason, the duty of the output pulse generated by the selection circuit 12 is 2.2 t.

Next, the PWM waveform generation circuit 153 starts outputting a normal pulse that rises at a timing (third rising point in FIG. 8) when 0 is output from the PWM binary counter 151. For this reason, the period of the normal pulse last output by the PWM waveform generation circuit 153 is 7t.

Next, the PWM phase adjustment circuit 154 causes the selection circuit 12 to start with a first reference clock (see FIG. 5) that rises with a phase delayed by 0.2 t (that is, the value 0.2 × t of the cumulative addition value LL) from the third rising point. 8) is selected as the third rising edge. Then, the selection circuit 12 starts generating the output pulse so that the rising edge timing of the output pulse to be generated is delayed by 0.2 t from the third rising point. Therefore, the cycle of the output pulse generated by the selection circuit 12 is 6.4t.

Then, the cumulative addition circuit 14 rewrites the value stored in the cycle setting register 131 from 6 (ie, M−1 + 1) to 5 (ie, M−1), and changes the value stored in the duty setting register 133 to Rewrite from 2 (ie, P-1 + 1) to 1 (ie, P-1).

Thereafter, the PWM phase adjustment circuit 154 repeatedly performs the same operation, and in cooperation with other circuits, the selection circuit 12 outputs a duty of 2.2t (that is, (P + L / 2) × t) and a cycle of The selection circuit 12 is controlled so that the output pulse of 6.4t (that is, (M + L) × t) is continuously output.

As described above with reference to another specific example, the pulse frequency control circuit 1 having the above configuration realizes output of an output pulse train having various duty ratios according to a combination of the M value and the P value. it can.

(Supplement)
As described above, the embodiments and the modification examples have been described as examples of the technology disclosed in the present application. However, the technology according to the present disclosure is not limited to these, and can be applied to embodiments in which changes, replacements, additions, omissions, and the like are appropriately performed.

(1) In the embodiment, the DCDC converter 3 having the configuration shown in FIG. 1 has been described as an example of the DCDC converter according to the present invention.

However, the DCDC converter according to the present invention is not necessarily limited to the DCDC converter 3 having the configuration shown in FIG.

Hereinafter, some examples of other configurations of the DCDC converter according to the present invention will be described.

FIG. 9 is a block diagram showing a configuration of a DCDC converter 3A which is another example of the DCDC converter according to the present invention.

As shown in the figure, the DCDC converter 3A includes a switching element 91, an energy conversion circuit 92, a rectifying / smoothing circuit 93, and the microcomputer 2.

The DCDC converter 3 (see FIG. 1) according to the first embodiment is an example in which the energy conversion circuit 32 includes a transformer, whereas the DCDC converter 3A includes an energy conversion circuit 92 that includes a transformer. This is an example of a so-called chopper type DCDC converter realized by including a coil.

FIG. 10 is a block diagram showing a configuration of a DCDC converter 3B which is still another example of the DCDC converter according to the present invention.

As shown in the figure, the DCDC converter 3B includes a first switching element 101A, a second switching element 101B, an energy conversion circuit 102, a rectifying / smoothing circuit 103, and a microcomputer 2A.

The DCDC converter 3 (see FIG. 1) according to the first embodiment is an example realized by including one switching element and a pulse frequency control circuit 1 that outputs one output pulse train. The DCDC converter 3B is modified in part from the pulse frequency control circuit 1 according to the first embodiment so as to output two switching elements that switch at different phases and two output pulse trains with different phases. In this example, the pulse frequency control circuit 1A is realized.

(2) In the embodiment, the pulse frequency control circuit 1 is described as being built in the microcomputer (microcomputer 2).

However, the pulse frequency control circuit according to the present invention is not necessarily limited to the configuration built in the microcomputer.

As an example, the pulse frequency control circuit 1 may be realized as a single semiconductor integrated circuit without being included in the microcomputer, or may be realized by being incorporated in an electronic component other than the microcomputer.

The present invention can be widely used in circuits that output pulses.

DESCRIPTION OF

SYMBOLS

1, 1A Pulse

frequency control circuit

2,

2A Microcomputer

3, 3A, 3B DCDC converter 11 Reference clock generation circuit 12 Selection circuit 13 Setting register 14 Cumulative addition circuit 15 Control circuit 21

Comparison part

22,

22A Setting part

31, 91, 101A,

101B Switching element

32, 92, 102

Energy conversion circuit

33, 93, 103 Rectification smoothing circuit 131 1st register 132 2nd register 133 3rd register 151 PWM binary counter 152 Period control circuit 153 PWM waveform generation circuit 154 PWM phase adjustment circuit

Claims

A selection circuit that acquires and selects a plurality of reference clocks having the same reference period and different phases, and
A setting register that stores information for specifying a setting period in units of a first period shorter than the reference period;
Based on information stored in the setting register, the selection circuit sequentially and repeatedly selects rising edges rising at the set cycle intervals as rising determination edges from among the rising edges of the plurality of reference clocks. A control circuit,
The selection circuit outputs an output pulse train composed of the output pulses by repeatedly generating output pulses that rise at every timing of a rising determination edge to be selected.
The control circuit generates a normal pulse of the normal pulse by generating a normal pulse having a period M (M is an integer of 1 or more) times the reference period,
The pulse frequency control circuit according to claim 1, wherein the value of M is changed to I (I is an integer of 1 or more) under a predetermined condition.
The plurality of reference clocks include N reference clocks whose phases are shifted by 1 / N (N is an integer of 2 or more) of the reference period,
The first period is 1 / N of the reference period,
M is an integer value of a quotient when the set period is divided by the reference period.
The setting register includes a first register that stores first information that specifies M, and a second register that stores second information that specifies the decimal value L of the quotient (L is a decimal number of 0 or more and less than 1). Including
The control circuit generates the normal pulse train by sequentially and repeatedly generating a normal pulse having a period M times the reference period based on the first information stored in the first register,
The pulse frequency control circuit further accumulates L / 2 each time the output pulse train output from the selection circuit rises or falls based on the second information stored in the second register, A cumulative addition circuit that calculates a cumulative addition value LL (J) when J (J is an integer of 0 or more) times of cumulative addition;
The control circuit, based on the second information stored in the second register, from the first rising edge of the normal pulse train to the selection circuit at the Kth (K is an integer of 0 or more) times, The normal pulse train that rises next to the first rising edge at the (K + 1) th time by causing the rising edge of the reference clock that rises with a phase delayed by LL (2 × K) times the reference period to be selected as the rising edge. 2. The control is performed by selecting, as the rising decision edge, a rising edge of a reference clock that rises with a phase delayed by a period LL (2 × (K + 1)) times the reference period from the rising edge of the reference period. Or the pulse frequency control circuit of 2.
When the LL (J) becomes 1 or more by cumulative addition of L / 2, the cumulative addition circuit subtracts 1 from the LL (J) to obtain a new LL (J). And (2) rewriting the information stored in the first register from information specifying M to information specifying M + 1, and (3) an output output from the selection circuit after the rewriting The pulse frequency control circuit according to claim 3, wherein when the pulse train first rises, the information stored in the first register is rewritten from information specifying M + 1 to information specifying M.
M is an integer greater than or equal to 2,
The setting register further includes a third register for storing third information for specifying an integer value P (P is an integer of 1 or more and less than M),
Based on the third information stored in the third register, the control circuit has a period LL (2 × K) times the reference period from the first rising edge of the normal pulse train with respect to the selection circuit. When the rising edge of the reference clock that rises with a phase delayed by only one is selected as the first rising edge, the phase is further delayed from the first rising edge by a period P + LL (2 × K + 1) times the reference period. Selecting the rising edge of the reference clock rising at 1 as the first falling decision edge corresponding to the first rising decision edge,
5. The output pulse generation according to claim 4, wherein the selection circuit generates the output pulse so that an output pulse generated at the timing of the first rising decision edge falls at the timing of the first falling decision edge. Pulse frequency control circuit.
The cumulative addition circuit further adds (1) information stored in the third register to P + 1 from information specifying P when LL (J) becomes 1 or more by cumulative addition of L / 2. (2) After the rewriting, when the output pulse train output from the selection circuit first rises, the information stored in the third register is changed from the information specifying P + 1. The pulse frequency control circuit according to claim 5, wherein P is rewritten into information for specifying P.
The pulse frequency control circuit according to any one of claims 1 to 6, further comprising a reference clock generation circuit that generates the plurality of reference clocks acquired by the selection circuit from an input reference clock having the reference period.
A pulse frequency control circuit according to any one of claims 1 to 7,
A microcomputer comprising: a setting unit that sets a value in the setting register.
A microcomputer according to claim 8;
A switching element that switches a DC input voltage according to an output pulse train output from the selection circuit;
When an input voltage switched by the switching element is input, an energy conversion circuit that generates an electromotive force due to current fluctuation caused by voltage fluctuation of the input voltage and outputs a voltage corresponding to the electromotive force;
A rectifying / smoothing circuit that outputs a DC output voltage by rectifying and smoothing the voltage output from the energy conversion circuit;
The microcomputer further includes a comparison unit that compares the potential of the output voltage with a predetermined potential.
The setting unit performs the setting so that the potential of the output voltage approaches the predetermined potential based on a result of comparison by the comparison unit. DCDC converter.
A pulse frequency control method performed by a pulse frequency control circuit including a selection circuit that acquires and selects a plurality of reference clocks having the same reference period and different phases, a setting register, and a control circuit,
A setting step in which the setting register stores information for specifying a setting period in units of a first period shorter than the reference period;
Based on the information stored in the setting step, the control circuit sequentially repeats the rising edge rising at the set cycle interval from the plurality of reference clocks as the rising determination edge with respect to the selection circuit. A pulse frequency control method comprising: a control step of selecting, and an output step of outputting an output pulse train composed of the output pulses by successively generating output pulses that rise every time the rising decision edge is selected by the selection circuit.