JP6672195B2 - Power supply - Google Patents

Description

  The present invention relates to a power supply device, and more particularly to a technique that is effective in controlling power supply by a power supply device that supplies power to an ECU (Electronic Control Unit) mounted on a vehicle.

  In recent years, the operating voltage of an in-vehicle ECU also tends to be low due to the low voltage of an LSI (Large Scale Integration) circuit. For example, the operating voltage of a microcomputer used for an on-vehicle ECU is about 5 V or 3.3 V, but is about 1 V or lower.

  Accordingly, a power supply device for supplying power to the ECU is required to have a lower voltage. As this type of power supply device, for example, a switching power supply device is widely used, and a power supply voltage supplied from a battery is reduced to generate a low voltage of about 1 V or less.

  In addition, a switching power supply device having a two-stage configuration in which two switching power supply circuits are connected in series is widely used, and the two switching power supply circuits sequentially reduce the power supply voltage of a battery and supply the battery to an ECU. A power supply is created.

  Here, the reason for having two switching circuits is as follows.

  When there is one switching power supply circuit, the switching duty ratio is determined by the input / output voltage ratio. For example, when the input voltage is about 40 V and the output voltage is about 1 V, the switching duty ratio is 2.5%.

  By increasing the switching frequency, a switching circuit that can apply a duty ratio of 2.5% can be made. However, when the load suddenly changes, the switching frequency is generally required to be 500 kHz or more depending on the specification of the power supply voltage fluctuation of the microcomputer in the ECU, and it is difficult to create a switching circuit to which a duty ratio of 2.5% can be applied.

  In addition, the output voltage of the first switching power supply circuit in the two-stage configuration is generally used as a power supply voltage of another load mounted on the ECU board, for example, an A / D (Analog / Digital) converter. Since the performance of the A / D converter depends on the performance of the power supply voltage, that is, the precision of the power supply voltage, the ripple requirement of the output voltage of the first switching power supply circuit is higher.

  For the above reasons, a power supply device in which two switching power supply circuits are connected in series is used.

  As this type of switching power supply circuit, for example, there is a switching power supply circuit having an appropriate number of cascade connection stages according to a voltage ratio between an input voltage and an output voltage (for example, see Patent Document 1).

JP-A-2011-211769

  In the case of a power supply device having a configuration in which the two switching power supply circuits described above are connected in series, the switching frequency of the next-stage switching power supply circuit is set high in order to suppress the output voltage ripple of the first-stage switching power supply circuit. Need arises.

  However, when the switching frequency of the second switching power supply circuit increases, there is a problem that as the switching frequency increases, switching loss due to the switching element and drive loss of a driver for driving the switching element increase. . As a result, the efficiency of the power supply device decreases.

  An object of the present invention is to provide a technique capable of generating a high-precision power supply voltage with low loss without increasing a switching frequency in a switching power supply circuit.

  The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows.

  That is, a typical power supply device includes a first switching power supply circuit, a second switching power supply circuit, a first control circuit, a second control circuit, and a delay generation unit.

  The first switching power supply circuit generates a first output voltage from an input voltage input from outside. The second switching power supply circuit generates a second output voltage from the first output voltage.

  The first control circuit controls a first output voltage generated by the first switching power supply circuit based on a first clock. The second control circuit controls a second output voltage generated by the second switching power supply circuit based on a second clock.

  The delay generator adjusts the frequency of the first clock and the frequency of the second clock to an integral multiple to reduce the delay between the first clock and the second clock to reduce the ripple of the first output voltage. Control.

  In addition, the first switching power supply circuit has a first switching unit, and the second switching power supply circuit has a second switching unit. The first switching unit switches an input voltage. The second switching unit switches the first output voltage.

  Then, the first control circuit generates a first control signal for controlling the first switching unit from the first clock, and the second control circuit controls the second switching unit from the second clock. A second control signal is generated. The delay generator controls the phases of the first control signal and the second control signal to control the delay of the first clock and the second clock.

  In addition, a typical power supply has an edge detector. The edge detector detects a signal rising edge or a signal falling edge of the first control signal and the second control signal.

  The delay generator controls the delay of the first clock and the second clock so that the rising edge or the falling edge of the first control signal and the second control signal are aligned.

  The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.

  (1) The loss in the power supply device can be reduced.

  (2) A highly accurate output voltage can be generated.

  (3) According to the above (1) and (2), a highly reliable power supply device can be realized.

FIG. 3 is an explanatory diagram illustrating an example of a configuration of the power supply device according to the first embodiment; FIG. 2 is an explanatory diagram illustrating an example of a phase relationship of a control signal generated by the control circuit in FIG. 1. 3 is a timing chart illustrating an example of each signal in a control unit included in the power supply device of FIG. 1. 6 is a timing chart illustrating another example of each signal in the control unit included in the power supply device of FIG. 1. FIG. 8 is an explanatory diagram illustrating an example of a configuration of a power supply device according to a second embodiment. 6 is a timing chart showing an example of each signal in the power supply device of FIG. 6 is a timing chart illustrating another example of each signal in the power supply device of FIG. 5. FIG. 13 is an explanatory diagram illustrating an example of a configuration of a power supply device according to a third embodiment. 9 is a timing chart illustrating an example of each signal in a control unit in the power supply device of FIG. FIG. 4 is an explanatory diagram illustrating an example of a configuration of a power supply device according to a comparative technique with respect to the embodiment; FIG. 11 is an explanatory diagram illustrating an example of an operation in the power supply device of FIG. 10. FIG. 11 is an explanatory diagram showing an example of a cause of a worst-case occurrence of output voltage ripple when a control signal generated by the control circuit in FIG. 10 has a phase difference. FIG. 13 is an explanatory diagram showing an example in which the ripple of the output voltage in the worst case shown in FIG. 12 is reduced.

 In all the drawings for describing the embodiments, the same members are denoted by the same reference numerals in principle, and the repeated description thereof will be omitted.

(Embodiment 1)
<Comparison technology for the embodiment>
In the following embodiments, in order to make the features of the present invention easy to understand, a description will be given in comparison with a comparative technique for the present embodiment. First, a comparison technique for the present embodiment will be described.

  A power supply device having a two-stage configuration in a comparative technique for the present embodiment will be described.

  FIG. 10 is an explanatory diagram illustrating an example of a configuration of a power supply device according to a comparative technique for the present embodiment.

  In this case, the power supply device has a configuration including a switching power supply circuit 30 and a switching power supply circuit 31, as shown in FIG. 10, and these switching power supply circuits 30, 31 are connected in series.

  The first switching power supply circuit 30 generates an output voltage Vo1 from the input voltage Batt. The input voltage Batt is a power supply voltage of a battery (not shown). The output voltage Vo1 is a voltage lower than the battery voltage Batt.

  The second switching power supply circuit 31 generates an output voltage Vo2 from the output voltage Vo1. The output voltage Vo2 is a voltage lower than the output voltage Vo1. Here, the output voltage Vo1 is a first output voltage, and the output voltage Vo2 is a second output voltage.

  The load 49 connected to the power supply device is a load using the output voltage Vo1 as an operation power supply, and is, for example, an analog circuit such as an A / D converter. Similarly, the load 50 connected to the power supply device is a load using the output voltage Vo2 as an operation power supply, and is, for example, a microcomputer.

  The switching power supply circuit 30 has a switching operation unit 1 and a control unit 3. The switching power supply circuit 30 inputs a feedback voltage from the output voltage Vo1 to the control unit 3, inputs a control signal Ctrl1 generated by the control unit 3 to the switching operation unit 1, and generates a desired output voltage value. The control signal Ctrl1 becomes a first control signal.

  The switching operation section 1 includes a switching element 7, a switching element 8, an inductor 9, a smoothing output capacitor 10, and a driver 11.

  When the switching element 7 is turned on and the switching element 8 as the first switching unit is turned off, the load 49 and the load 50 are driven while energy is stored in the inductor 9. On the other hand, when the switching element 7 is turned off and the switching element 8 is turned on, the energy stored in the inductor 9 is released, and the load 49 and the load 50 are driven.

  The smoothing output capacitor 10 is a capacitor, and suppresses a voltage ripple of the output voltage Vo1 of the switching power supply circuit 30. The driver 11 is a drive circuit that drives the switching element 7 and the switching element 8 by a control signal Ctrl1 output from the control unit 3 to perform a switching operation.

  The switching element 7 includes, for example, an N-channel MOS (Metal Oxide Semiconductor) transistor, and the switching element 8 includes a P-channel MOS transistor. The switching element 7 turns on when the signal output from the driver 11 is a high signal, and the switching element 8 turns on when the signal output from the driver 11 is a low signal.

  The control unit 3 includes a control circuit 12, a frequency divider 21, and a clock generation circuit 4. The clock generation circuit 4 generates a reference clock, and this reference clock becomes a reference clock of the control unit 3 of the switching power supply circuit 30.

  The frequency divider 21 is a circuit that generates a clock that determines the frequency of the on / off operation of the switching elements 7 and 8 of the switching power supply circuit 30 based on the reference clock from the clock generation circuit 4.

  The control circuit 12, which is the first control circuit, is a circuit that generates the control signal Ctrl1 based on the feedback voltage at the output voltage Vo1 and the clock output from the frequency divider 21. The frequency of the control signal Ctrl1 is determined by the frequency of the clock output from the frequency divider 21.

  The switching power supply circuit 31 includes the switching operation unit 2 and the control unit 29. The switching power supply circuit 31 generates a desired output voltage value by inputting the feedback voltage of the output voltage Vo2 to the control unit 29 and inputting the control signal Ctrl2 generated by the control unit 29 to the switching operation unit 2. The control signal Ctrl2 becomes the second control signal.

  The switching operation unit 2 includes a switching element 14, a switching element 15, an inductor 16, a smoothing output capacitor 17, and a driver 18. The switching elements 14 and 15 are composed of, for example, MOS transistors.

  When the switching element 14 is turned on and the switching element 15 which is the second switching is turned off, the load 50 is driven while storing energy in the inductor 16 which is the second inductor. On the other hand, when the switching element 14 is turned off and the switching element 15 is turned on, the energy stored in the inductor 16 is released, and the load 50 is driven.

  The smoothing output capacitor 17 is a capacitor similarly to the smoothing output capacitor 10, and suppresses a voltage ripple of the output voltage Vo2 of the switching power supply circuit 31.

  The driver 18 is a drive circuit that controls the switching operation of the switching elements 14 and 15 based on the control signal Ctrl2 of the control unit 29.

  The switching element 14 includes, for example, an N-channel MOS (Metal Oxide Semiconductor) transistor, and the switching element 15 includes a P-channel MOS transistor. The switching element 14 is turned on when the signal output from the driver 18 is a high signal, and the switching element 15 is turned on when the signal output from the driver 18 is a low signal.

  The control unit 29 has a control circuit 20, a frequency divider 22, and a clock generation circuit 23. The clock generation circuit 23 generates a reference clock. This reference clock serves as a reference clock for the control unit 29 of the switching power supply circuit 31.

  The frequency divider 22 generates a clock for determining the frequency of the on / off operation of the switching elements 14 and 15 of the switching power supply circuit 31 from the reference clock generated by the clock generation circuit 23.

  The control circuit 20, which is the second control circuit, generates the control signal Ctrl2 based on the feedback voltage at the output voltage Vo2 and the clock generated by the frequency divider 22. The frequency of the control signal Ctrl2 is determined by the frequency of the clock generated by the frequency divider 22.

  FIG. 11 is an explanatory diagram showing an example of an operation in the power supply device of FIG.

  FIG. 11 shows the signal timing of the control signal Ctrl1 output from the control circuit 12 in the upper part, and the signal timing of the control signal Ctrl2 output from the control circuit 20 in the lower part.

  FIGS. 12 and 13 show signal timings from the top to the bottom of the ripples of the control signal Ctrl1 output from the control circuit 12, the control signal Ctrl2 output from the control circuit 20, the currents Io and IL, and the output voltage Vo1. Are respectively shown. The current IL, which is an inductor current, is an input current of the smoothing output capacitor 10, and the current Io is an output current of the smoothing output capacitor 10.

  In the power supply device shown in FIG. 10, control signals Ctrl1 and Ctrl2 are generated by the control circuits 12 and 20, respectively. Therefore, the phase relationship between the control signal Ctrl1 and the control signal Ctrl2 is not controlled. In other words, it is not fixed.

  If there is a difference between the frequencies of the control signal Ctrl1 and the control signal Ctrl2, the phase relationship between the control signal Ctrl1 and the control signal Ctrl2 gradually changes. As a result, as shown in FIG. 11, a worst case occurs in which the ripple of the output voltage Vo1 of the switching power supply circuit 30 is maximized.

  FIG. 12 illustrates an example of the cause of the worst-case occurrence of ripple in the output voltage Vo1 of the switching power supply circuit 30 when there is a phase difference between the control signal Ctrl1 and the control signal Ctrl2 generated by the control circuit in FIG. FIG.

  The larger the difference between the input and output charge amounts of the smoothing output capacitor 10 and the larger the area indicated by hatching in FIG. 12, the larger the ripple of the output voltage Vo1. The difference between the input and output charge amounts of the smoothing output capacitor 10, that is, the area of the region indicated by hatching in FIG.

  The input current of the smoothing output capacitor 10, that is, the current IL is a current like a triangular wave generated from the on / off operation of the switching elements 7 and 8 by the control signal Ctrl1.

  The output current of the smoothing output capacitor 10, that is, the current Io, is a current like a rectangular wave generated from the ON / OFF operation of the switching element 14 and the switching element 15 by the control signal Ctrl2.

  As shown in FIG. 12, a period in which the difference between the current IL and the current Io is largest occurs due to the phase relationship between the control signal Ctrl1 and the control signal Ctrl2, and the difference between the input and output charge amounts (indicated by hatching). Since the area (area of the region) becomes maximum, a worst case occurs in which the ripple of the output voltage Vo1 becomes maximum.

  FIG. 13 is an explanatory diagram showing an example of reducing the ripple of the output voltage Vo1 in the worst case shown in FIG.

  In this case, by shortening the period in which the difference between the current IL and the current Io is the largest, it is possible to reduce the difference in the charge amount between the input and output of the smoothing output capacitor 10 (the area of the region indicated by hatching). it can. That is, the frequency of the control signal Ctrl2 is set to be higher than the frequency of the control signal Ctrl1.

  However, when the frequency of the control signal Ctrl2 increases, the switching loss of the switching elements 14 and 15 and the driving loss of the driver 18 increase. Therefore, in the present embodiment, a measure is taken against the problem existing in the above-described comparative technique.

  Hereinafter, embodiments will be described in detail.

<Configuration example of power supply unit>
FIG. 1 is an explanatory diagram illustrating an example of the configuration of the power supply device according to the first embodiment. In FIG. 1, the same components as those in FIG. 10 described above are denoted by the same reference numerals.

  The power supply device 32 illustrated in FIG. 1 includes a switching operation unit 1, a switching operation unit 2, and a control unit 5. The power supply device 32 inputs a feedback voltage from the output voltage Vo1 and the output voltage Vo2 to the control unit 5.

  Then, the control signal Ctrl1 and the control signal Ctrl2 generated by the control unit 5 are input to the switching operation units 1 and 2, respectively, to generate desired output voltage values, thereby supplying operating power to the loads 49 and 50. The switching operation unit 1 is a first switching power supply circuit, and the switching operation unit 2 is a second switching power supply circuit.

  The control unit 5 includes a control circuit 12, a control circuit 20, a frequency divider 24, a clock generation circuit 26, a voltage detection comparison unit 56, and a phase control unit 6.

  Here, the switching operation unit 1, the switching operation unit 2, the loads 49 and 50, the control circuit 12, and the control circuit 20 in FIG. 1 are the same as those in FIG.

  The clock generation circuit 26 generates a reference clock for the control unit 5. The frequency divider 24 generates a clock CLOCK1 and a clock CLOCK2_1 based on the reference clock generated by the clock generation circuit 26. The clock CLOCK1 becomes the first clock.

  The clock CLOCK1 is a clock that determines the frequency 1 / Ts1 of the ON / OFF operation of the switching elements 7 and 8 of the switching operation unit 1. The clock CLOCK2_1 is a clock that determines the frequency 1 / Ts2 of the on / off operation of the switching element 14 and the switching element 15 of the switching operation unit 2. The clocks CLOCK1 and CLOCK2_1 have an integer multiple of frequency.

  The voltage detection / comparison unit 56 includes an input voltage detector 53, an output voltage detector 54, and a voltage comparator 55. The voltage detection and comparison unit 56 generates a signal Slope1. This signal Slope1 is a signal that is input to the power supply device 32 and indicates the relationship between the magnitude of the rise and fall of the current IL flowing through the inductor 9 according to the relationship between the input voltage Batt and the output voltage Vo1. The input voltage Batt is output from a battery mounted on an automobile (not shown).

  The input voltage detector 53 detects a voltage level of the input voltage Batt. The output voltage detector 54 detects the voltage level of the output voltage Vo1. The input voltage detector 53 and the output voltage detector 54 constitute a voltage detector.

  The voltage comparator 55 compares the input voltage Batt detected by the input voltage detector 53 with the output voltage Vo1 detected by the output voltage detector 54 to generate a signal Slope.

  When the difference between the input voltage Batt and the output voltage Vo1 is larger than the output voltage Vo1, the slope of the rise of the current IL flowing through the inductor 9, which is the first inductor, is larger than the slope of the fall of the current IL, and the signal Slope1 becomes low. Become.

  When the difference between the input voltage Batt and the output voltage Vo1 is smaller than the output voltage Vo1, the rising slope of the current IL flowing through the inductor 9 is smaller than the falling slope of the current IL, and the signal Slope1 becomes high.

  The phase controller 6 serving as a delay generator has an edge detector 28 and a unit delay generator 27. The phase control unit 6 controls a phase relationship between the control signal Ctrl1 and the control signal Ctrl2.

  The edge detector 28 detects a phase difference between the control signal Ctrl1 and the control signal Ctrl2. The edge detector 28 detects high / low of the control signal Ctrl2 at the timing of the falling edge of the control signal Ctrl1. When the control signal Ctrl2 is high, it generates and outputs a pulse signal H_out, and when the control signal Ctrl2 is low, it generates and outputs a pulse signal L_out.

  The unit delay generator 27 converts the clock CLOCK2_1 from the frequency divider 24 with a desired delay time based on the pulse signals H_out and L_out detected by the edge detector 28 and the signal Slope1 output from the voltage detection comparator 56. A clock CLOCK2_2 serving as the delayed second clock is generated.

  When the signal Slope1 is low and the pulse signal output from the edge detector 28 is the pulse signal H_out, the clock CLOCK2_1 from the frequency divider 24 is delayed so as to be increased by one unit and output as the clock CLOCK2_2. I do. Here, one unit is the minimum time during which the switching element 7 can be turned on, that is, the minimum time of the switching time.

  On the other hand, when the signal Slope1 is low and the pulse signal output from the edge detector 28 is the pulse signal L_out, a clock obtained by delaying the delay time of the clock CLOCK2_1 by one unit is output as the clock CLOCK2_2. I do.

  If the signal Slope1 is high and the output of the edge detector 28 is the pulse signal H_out, a clock obtained by delaying the delay time of the clock signal CLOCK2_1 by one unit is output as the clock CLOCK2_2.

  When the signal Slope1 is high and the output of the edge detector 28 is the pulse signal L_out, a clock obtained by delaying the delay time of the clock CLOCK2_1 by one unit is output as the clock CLOCK2_2.

  The control unit 5 can reduce the ripple of the output voltage Vo1 without increasing the frequency of the control signal Ctrl2 by the following measures.

  (1) In order to fix the phase relationship between the control signal Ctrl1 and the control signal Ctrl2, a frequency divider 24 that generates the control signals Ctrl1 and Ctrl2 whose frequencies are integral multiples is provided. Here, a case where the frequencies of the control signals Ctrl1 and Ctrl2 are the same will be described as an example.

  (2) The phase controller 6 delays the control signal Ctrl2 so that the phase relationship between the control signal Ctrl1 and the control signal Ctrl2 becomes a desired phase relationship. The desired phase relationship between the control signal Ctrl1 and the control signal Ctrl2 is such that the difference between the current IL, which is the input / output current of the smoothing output capacitor 10, and the current Io is smaller than that in FIG. (The area of the region indicated by hatching in FIG. 12) becomes smaller.

<About the phase of the control signal>
FIG. 2 is an explanatory diagram illustrating an example of a phase relationship between control signals Ctrl1 and Ctrl2 generated by the control circuit in FIG.

  FIG. 2A shows a case where the gradient of the increase in the current IL is larger than the gradient of the decrease in the current IL. FIG. 2B shows that the gradient of the increase in the current IL is smaller than the gradient of the decrease in the current IL. This is a case where the value is smaller than the above.

  FIG. 2 shows signal timings of ripples of the control signal Ctrl1, the control signal Ctrl2, the currents IL and Io, and the output voltage Vo1 from above to below.

  During the period in which the current Io, which is the output current of the smoothing output capacitor 10, flows, the smaller the gradient of the change in the current IL, the smaller the difference between the input and output charge amounts, that is, the area of the region shown by hatching in FIG. For this reason, the timing of matching the phase between the control signal Ctrl1 and the control signal Ctrl2 differs depending on the slope of the rise and fall of the current IL.

  The slope of the rise and fall of the current IL is obtained from the following equation.

The slope of the rise of the current IL: (Batt-Vo1) / L1
Slope of decrease in current IL: -Vo1 / L1
If the rising slope of the current IL is larger than the falling slope of the current IL, as shown in FIG. 2 (a), when the falling edge of the control signal Ctrl1 and the rising edge of the control signal Ctrl2 are combined, The difference in the charge amount (the area of the area indicated by hatching and gray area) is reduced, and the ripple of the output voltage Vo1 can be reduced as compared with FIG. 12 described above.

  When the rising slope of the current IL is smaller than the falling slope of the current IL, if the falling edge of the control signal Ctrl1 and the falling edge of the control signal Ctrl2 are combined, as shown in FIG. , The difference between the input and output charge amounts (the area of the region indicated by hatching) is reduced, and similarly, the ripple of the output voltage Vo1 can be reduced.

<Operation example of power supply unit>
The operation of the power supply device 32 when the control unit 5 realizes the waveform shown in FIG. 4 will be described with reference to FIGS.

  FIG. 3 is a timing chart showing an example of each signal in the control unit 5 included in the power supply device 32 of FIG. FIG. 4 is a timing chart illustrating another example of each signal in the control unit 5 included in the power supply device 32 of FIG.

  FIG. 3 shows an example of signal timing when the falling edge of the control signal Ctrl1 and the falling edge of the control signal Ctrl2 shown in FIG. 2B are matched. FIG. 4 shows an example of signal timing when the falling edge of the control signal Ctrl1 and the rising edge of the control signal Ctrl2 shown in FIG. 2A are matched.

  3 and 4, the signal timings of the clock CLOCK1, the clock CLOCK2_1, the clock CLOCK2_2, the control signal Ctrl1, the control signal Ctrl2, the pulse signal L_out, the pulse signal H_out, the signal Slope1, and the input voltage Batt from the top to the bottom. Are respectively shown.

  First, an operation for matching the falling edge of the control signal Ctrl1 with the falling edge of the control signal Ctrl2 will be described with reference to FIG.

1st cycle (stable period)
The frequency divider 24 generates a clock CLOCK1 and a clock CLOCK2_1 whose frequencies are integer multiples from the reference clock from the clock generation circuit 26. Here, a case where the frequency of the control signal Ctrl1 and the frequency of the control signal Ctrl2 are the same (Ts1 = Ts2) will be described as an example.

  The control circuit 12 generates a control signal Ctrl1 based on the feedback voltage from the output voltage Vo1 and the clock CLOCK1. The delay setting time of the unit delay generator 27 is td. The unit delay generator 27 generates the clock CLOCK2_2 by delaying the clock CLOCK2_1 by a period of td.

  The control circuit 20 generates a control signal Ctrl2 based on the feedback voltage from the output voltage Vo2 and the clock CLOCK2_2. The edge detector 28 detects that the control signal Ctrl2 is high at the timing of the falling edge of the control signal Ctrl1, and outputs a pulse signal H_out.

  At this time, since the difference between the input voltage Batt and the output voltage Vo1 is larger than the output voltage Vo1, the rising slope of the current IL flowing through the inductor 9 is larger than the falling slope, and the signal Slope1 is low. As a result, the delay set in the unit delay generator 27 increases by one unit from td, and the delay time becomes td + x.

2nd to 5th cycle (follow-up period)
Second cycle: A change in the input voltage Batt increases the duty ratio of the control signal Ctrl1 generated from the control circuit 12. The unit delay generator 27 generates the clock CLOCK2_2 by delaying the clock CLOCK2_1 by a period of td + x. The edge detector 28 detects that the control signal Ctrl2 is low at the timing of the falling edge of the control signal Ctrl1, and outputs a pulse signal L_out.

  At this time, since the difference between the input voltage Batt and the output voltage Vo1 is smaller than the output voltage Vo1, the rising slope of the current IL flowing through the inductor 9 is smaller than the falling slope, and the signal Slope1 becomes high.

  As a result, the delay set in the unit delay generator 27 is increased by one unit from td + x, and becomes td + 2x.

  Third cycle: The unit delay generator 27 delays the clock CLOCK2_1 by a period of td + 2x, and generates the clock CLOCK2_2. The edge detector 28 detects that the control signal Ctrl2 is low at the timing of the falling edge of the control signal Ctrl1, and outputs a pulse signal L_out.

  At this time, since the difference between the input voltage Batt and the output voltage Vo1 is smaller than the output voltage Vo1, the rising slope of the current IL flowing through the inductor 9 is smaller than the falling slope, and the signal Slope1 remains high. As a result, the delay set in the unit delay generator 27 is increased by one unit from td + 2x, and becomes td + 3x.

  Fourth cycle: The same operation as in the third cycle is performed, and the delay set in the unit delay generator 27 is td + 4x.

  Fifth cycle: The unit delay generator 27 generates the clock CLOCK2_2 by delaying the clock CLOCK2_1 by the period of td + 4x. The edge detector 28 detects that the control signal Ctrl2 is high at the timing of the falling edge of the control signal Ctrl1, and outputs a pulse signal H_out.

  At this time, since the difference between the input voltage Batt and the output voltage Vo1 is smaller than the output voltage Vo1, the rising slope of the current IL flowing through the inductor 9 is smaller than the falling slope, and the signal Slope1 remains high.

  Thus, the delay set in the unit delay generator 27 is reduced by one unit from td + 4x to td + 3x.

After the 6th cycle (stable period)
As described above, the delay set in the unit delay generator 27 by the pulse signals H_out and L_out is repeatedly set to td + 3x and td + 4x for each cycle.

  Next, an operation when the falling edge of the control signal Ctrl1 and the rising edge of the control signal Ctrl2 are matched will be described with reference to FIG.

1st cycle (stable period)
The frequency divider 24 generates clocks CLOCK1 and CLOCK2_1 whose frequencies are integer multiples from the reference clock from the clock generation circuit 26, respectively. Here, a case where the frequency of the control signal Ctrl1 and the frequency of the control signal Ctrl2 are the same (Ts1 = Ts2) will be described as an example.

  The control circuit 12 generates a control signal Ctrl1 based on the feedback voltage from the output voltage Vo1 and the clock CLOCK1. The delay setting time of the unit delay generator 27 is td + 4x.

  The unit delay generator 27 delays the clock CLOCK2_1 by a period of td + 4x, and outputs it as the clock CLOCK2_2. The control circuit 20 generates a control signal Ctrl2 based on the feedback voltage from the output voltage Vo2 and the clock CLOCK2_2.

  The edge detector 28 detects that the control signal Ctrl2 is high at the timing of the falling edge of the control signal Ctrl1, and outputs a pulse signal H_out. At this time, since the difference between the input voltage Batt and the output voltage Vo1 is smaller than the output voltage Vo1, the rising slope of the current IL flowing through the inductor 9 is smaller than the falling slope, and the signal Slope1 is high.

  Thus, the delay set in the unit delay generator 27 is reduced by one unit from td + 4x to td + 3x.

2nd to 5th cycle (follow-up period)
Second cycle: The duty ratio of the control signal Ctrl1 generated from the control circuit 12 decreases due to the change in the input voltage Batt. The unit delay generator 27 delays the clock CLOCK2_1 by a period of td + 3x, and outputs the result as the clock CLOCK2_2.

  The edge detector 28 detects that the control signal Ctrl2 is low at the timing of the falling edge of the control signal Ctrl1, and outputs a pulse signal L_out. At this time, since the difference between the input voltage Batt and the output voltage Vo1 is larger than the output voltage Vo1, the rising slope of the current IL flowing through the inductor 9 is larger than the falling slope, and the signal Slope1 becomes low.

  Thus, the delay set in the unit delay generator 27 is reduced by one unit from td + 3x to td + 2x.

  Third cycle: The unit delay generator 27 delays the clock CLOCK2_1 by a period of td + 2x, and outputs it as the clock CLOCK2_2.

  The edge detector 28 detects that the control signal Ctrl2 is low at the falling edge timing of the control signal Ctrl1, and outputs a pulse signal L_out. At this time, since the difference between the input voltage Batt and the output voltage Vo1 is larger than the output voltage Vo1, the rising slope of the current IL flowing through the inductor 9 is larger than the falling slope, and the signal Slope1 remains low.

  Thus, the delay set in the unit delay generator 27 is reduced by one unit from td + 2x, and becomes td + x.

  Fourth cycle: The same operation as the above-described third cycle is performed, and the delay set in the unit delay generator 27 becomes td.

  Fifth cycle: The unit delay generator 27 generates the clock CLOCK2_2 by delaying the clock CLOCK2_1 by a period of td. The edge detector 28 detects that the control signal Ctrl2 is high at the timing of the falling edge of the control signal Ctrl1, and outputs a pulse signal H_out.

  At this time, since the difference between the input voltage Batt and the output voltage Vo1 is larger than the output voltage Vo1, the rising slope of the current IL flowing through the inductor 9 is larger than the falling slope, and the signal Slope1 remains low.

  Thus, the delay set in the unit delay generator 27 is increased by one unit from td to be td + x.

After the 6th cycle (stable period)
By the pulse signals H_out and L_out, the delay set in the unit delay generator 27 is repeatedly set between td + x and td for each cycle.

  As described above, the above operation makes it possible to make the falling edge of the control signal Ctrl1 substantially coincide with the rising edge or the falling edge of the control signal Ctrl2.

  As a result, the difference between the input and output charges of the smoothing output capacitor 10 can be reduced without increasing the frequency of the control signal Ctrl2, and the ripple of the output voltage Vo1 can be reduced.

  The load 49 using the output voltage Vo1 as an operation power supply is an analog circuit such as an A / D converter as described above. Therefore, the accuracy of the analog / digital conversion of the A / D converter can be improved by reducing the ripple of the output voltage Vo1.

  In addition, since a stable output voltage Vo2 can be generated without increasing the switching frequency in the switching operation unit 2, the loss of the power supply device 32 can be reduced.

  Thereby, a highly reliable and highly efficient power supply device 32 can be realized.

(Embodiment 2)
In the technique according to the first embodiment, as shown in FIG. 3 and the like, in order to follow a change in the duty ratio of the control signal Ctrl1, the time for adjusting the delay between the clock CLOCK2_1 and the clock CLOCK2_2 until the delay becomes appropriate. That would be. Thus, the ripple of the output voltage Vo1 increases during the following period.

  Therefore, in the second embodiment, a technique for reducing the ripple of the output voltage Vo1 during the follow-up period will be described.

<Configuration example of power supply unit>
FIG. 5 is an explanatory diagram illustrating an example of a configuration of the power supply device 41 according to the second embodiment.

  In FIG. 5, the same components as those in FIG. 1 are denoted by the same reference numerals. In FIG. 5, the switching operation unit 2, the clock generation circuit 26, the frequency divider 24, and the loads 49 and 50 constituting the power supply device 41 are the same as those in FIG.

  The power supply device 41 has a switching operation unit 1, a switching operation unit 2, and a control unit 19, as shown in FIG. The power supply device 41 inputs a feedback voltage from the output voltages Vo1 and Vo2 to the control unit 19. Then, the control signals Ctrl1 and Ctrl2 generated by the control unit 19 are input to the switching operation units 1 and 2, and the desired output voltages Vo1 and Vo2 are generated by the switching operation and supplied as the operating voltages of the loads 50 and 49. I do.

  The switching operation unit 1 includes a switching element 7, a switching element 8, an inductor 9, a smoothing output capacitor 10, a driver 11, and a current detector 57. The switching element 7, the switching element 8, the inductor 9, the smoothing output capacitor 10, and the driver 11 are the same as those in FIG. The current detector 57 changes the current IL flowing through the inductor 9 into a voltage value and outputs the voltage value.

  The control unit 19 includes a controller 33, a controller 34, a frequency divider 24, a current detection / comparison unit 60, and a clock generation circuit 26.

  The current detection comparator 60 includes a current detection ADC 58 and a current gradient comparator 59. The current detection / comparison section 60 generates a signal Slope2 indicating the relationship between the magnitude of the slope of the rise and fall of the current IL flowing through the inductor 9.

  The current detection ADC 58 converts the voltage value obtained by converting the current IL by the current detector 57 into a digital voltage value. The current slope comparator 59 outputs a signal Slope2 indicating the magnitude of the slope of the rise of the current IL flowing through the inductor 9 and the magnitude of the fall of the current IL from the current detection ADC 58 during one cycle in which the switching elements 7 and 8 are switched. Generated based on the output digital voltage value.

  If the slope of the rise of the current IL flowing through the inductor 9 is larger than the slope of the fall of the current IL, the signal Slope2 becomes low. If the slope of the rise of the current IL flowing through the inductor 9 is smaller than the slope of the fall of the current IL, the signal Slope2 becomes high.

  Further, since the current slope comparator 59 is a circuit that compares the rising and falling slopes of the current IL during one cycle, the result of the signal Slope2 is the result of comparing the rising and falling slopes of the current IL one cycle before. It is.

  The controller 33 has an AD converter 37, a PID controller 36, and a DPWM generator 35. The controller 33 converts a feedback voltage from the output voltage Vo1 into a digital feedback pressure value by the AD converter 37, and generates a digital control value Digital_in by the PID controller 36.

  The DPWM generator 35 generates the control signal Ctrl1 based on the clock CLOCK1 generated by the frequency divider 24 and the digital control value Digital_in generated by the PID controller 36. is there. The digital control value Digital_in indicates a high time of the control signal Ctrl1.

  The AD converter 37 is an analog-to-digital conversion circuit that converts a feedback voltage from the output voltage Vo1 into a digital feedback voltage value.

  The PID controller 36 performs a proportional-integral-differential operation using the digital feedback voltage value converted by the AD converter 37 so that the switching operation unit 1 can generate a desired output voltage. , A digital control value Digital_in is generated.

  The DPWM generator 35 is a so-called digital PWM (Pulse Width Modulation) circuit that uses the digital control value Digital_in from the PID controller 36 to generate a control signal Ctrl1 with the clock CLOCK1 output from the frequency divider 24.

  The controller 34 has an AD converter 40, a PID controller 39, a DPWM generator 38, and a variable delay unit 42. The controller 34 is a digital controller such as a microcomputer.

  Specifically, the feedback voltage from the output voltage Vo2 is converted into a digital feedback pressure value by the AD converter 40. Then, the PID controller 39 generates a digital control value Digital_in_2.

  Subsequently, in the variable delay unit 42, a clock CLOCK2_2 is generated based on the digital control value Digital_in_2, the digital control value Digital_in generated by the PID controller 36, and the clock CLOCK2_1 output from the frequency divider 24.

  The DPWM generator 38 generates a control signal Ctrl2 from the digital control value Digital_in_2 from the PID controller 39 and the clock CLOCK2_2. Further, the digital control value Digital_in_2 represents a high time of the control signal Ctrl2.

  The AD converter 40 is an analog-to-digital conversion circuit that converts a feedback voltage from the output voltage Vo2 into a digital feedback voltage value. The PID controller 39 performs a proportional-integral-differential (Proportional-Integral-Differential) operation using the digital feedback voltage value converted from the AD converter 40 so that the switching operation unit 2 can generate a desired output voltage. , A digital control value Digital_in_2 is generated.

  The DPWM generator 38 is a digital PWM (Pulse Width Modulation) circuit that generates a control signal Ctrl2 by a clock CLOCK2_2 using a digital control value Digital_in_2 generated by the PID controller 39.

  The variable delay unit 42 sets a delay time based on the digital control value Digital_in generated by the PID controller 36, the digital control value Digital_in_2 generated by the PID controller 39, and the signal Slope2 output from the current slope comparator 59, A clock CLOCK2_2 generated by delaying the clock CLOCK2_1 output from the frequency divider 24 by a set delay time is generated.

  When the signal Slope2 output from the current slope comparator 59 is high, the delay time is the difference between the high time of the control signal Ctrl1 and the high time of the control signal Ctrl2. When the signal Slope2 output from the current slope comparator 59 is low, the delay time is the high time of the control signal Ctrl1.

<Operation example of power supply unit>
FIG. 6 is a timing chart showing an example of each signal in the power supply device 41 of FIG. FIG. 7 is a timing chart showing another example of each signal in the power supply device 41 of FIG.

  FIG. 6 shows an example of signal timing when the power supply device 41 shown in FIG. 5 matches the falling edge of the control signal Ctrl1 and the falling edge of the control signal Ctrl2 shown in FIG. 2B. is there. FIG. 7 shows an example of signal timing when the power supply device 41 shown in FIG. 5 matches the falling edge of the control signal Ctrl1 and the rising edge of the control signal Ctrl2 shown in FIG. 2A. .

  6 and 7, in order from the top to the bottom, the clock CLOCK1, the clock CLOCK2_1, the clock CLOCK2_2, the digital control value Digital_in, the digital control value Digital_in_2, the control signal Ctrl1, the control signal Ctrl2, the signal Slope2, and the input voltage Batt Each signal timing is shown.

  First, the operation of the power supply device 41 when the falling edge of the control signal Ctrl1 and the falling edge of the control signal Ctrl2 shown in FIG. 2B are matched will be described with reference to FIG.

1st cycle (stable period)
First, the frequency divider 24 generates clocks CLOCK1 and CLOCK2_1 whose frequencies are integral multiples from the reference clock output from the clock generation circuit 26, respectively. Here, a case where the frequency of the control signal Ctrl1 and the frequency of the control signal Ctrl2 are substantially the same (Ts1 = Ts2) will be described as an example.

  The controller 33 generates a digital control value Digital_in representing the high time t1 of the control signal Ctrl1 from the feedback voltage from the output voltage Vo1 and the clock CLOCK1, and generates a control signal Ctrl1 having a pulse width of time t1.

  Since the difference between the input voltage Batt and the output voltage Vo1 one cycle before is larger than the output voltage Vo1, the slope of the rise of the current IL flowing through the inductor 9 is larger than the slope of the fall of the current IL, and the signal Slope2 becomes low.

  For this reason, the variable delay unit 42 sets the delay setting time to t1 by the digital control value Digital_in representing the time t1. The variable delay unit 42 generates the clock CLOCK2_2 by delaying the clock CLOCK2_1 by a period of t1.

  Since the control signal Ctrl2 is generated using the clock CLOCK2_2 as a reference clock, the falling edge of the control signal Ctrl1 coincides with the rising edge of the control signal Ctrl2.

Second cycle (follow-up period)
Due to the change in the input voltage Batt, the duty ratio of the control signal Ctrl1 generated by the controller 33 increases from t1 / Ts1 to t2 / Ts2. The controller 33 generates a digital control value Digital_in representing a time t2 from the feedback voltage from the output voltage Vo1 and the clock CLOCK1, and generates a control signal Ctrl1 having a pulse width of the time t2.

  Since the difference between the input voltage Batt in the second cycle and the output voltage Vo1 is larger than the output voltage Vo1, the signal Slope2 remains low. The variable delay unit 42 sets the delay set time to t2 by the digital control value Digital_in representing the time t2.

  The variable delay unit 42 delays the clock CLOCK2_1 by a period of t2 and generates the clock CLOCK2_2. Since the control signal Ctrl2 is generated using the clock CLOCK2_2 as a reference clock, the falling edge of the control signal Ctrl1 coincides with the rising edge of the control signal Ctrl2.

After the third cycle (stable period)
Since the difference between the input voltage Batt in the third cycle and the output voltage Vo1 is smaller than the output voltage Vo1, the signal Slope2 becomes high. The variable delay unit 42 sets the delay setting time to t2−t3 using the digital control value Digital_in representing the time t2 and the digital control value Digital_in_2 representing the time t3.

  The variable delay unit 42 generates the clock CLOCK2_2 by delaying the clock CLOCK2_1 by a period of t2 to t3. Since the control signal Ctrl2 is generated using the clock CLOCK2_2 as a reference clock, the falling edge of the control signal Ctrl1 coincides with the falling edge of the control signal Ctrl2.

  Next, the operation of the power supply device 41 when the falling edge of the control signal Ctrl1 and the rising edge of the control signal Ctrl2 shown in FIG. 2A are matched will be described with reference to FIG.

1st cycle (stable period)
First, the frequency divider 24 generates clocks CLOCK1 and CLOCK2_1 whose frequency is an integer multiple from the reference clock output from the clock generation circuit 26. Here, a case where the frequency of the control signal Ctrl1 and the frequency of the control signal Ctrl2 are substantially the same (Ts1 = Ts2) will be described as an example.

  The controller 33 generates a digital control value Digital_in representing a high time t2 of the control signal Ctrl1 from the feedback voltage from the output voltage Vo1 and the clock CLOCK1, and generates a control signal Ctrl1 having a pulse width of time t2.

  Since the difference between the input voltage Batt one cycle before and the output voltage Vo1 is smaller than the output voltage Vo1, the rising slope of the current IL flowing through the inductor 9 is smaller than the falling slope of the current IL, and the signal Slope2 becomes high.

  The variable delay unit 42 sets the delay set time to t2-t3 by using the digital control value Digital_in representing the time t2 and the digital control value Digital_in_2 representing the time t3.

  The variable delay unit 42 generates the clock CLOCK2_2 by delaying the clock CLOCK2_1 by a period of t2 to t3. Since the control signal Ctrl2 is generated using the clock CLOCK2_2 as a reference clock, the falling edge of the control signal Ctrl1 coincides with the falling edge of the control signal Ctrl2.

Second cycle (follow-up period)
Due to the change in the input voltage Batt, the duty ratio of the control signal Ctrl1 generated by the controller 33 decreases from t2 / Ts1 to t1 / Ts2. The controller 33 generates a digital control value Digital_in representing a time t2 from the feedback voltage from the output voltage Vo1 and the clock CLOCK1, and generates a control signal Ctrl1 having a pulse width of the time t1.

  Since the difference between the input voltage Batt in the second cycle and the output voltage Vo1 is larger than the output voltage Vo1, the signal Slope2 is low. The variable delay unit 42 sets the delay setting time to t1-t3 by using the digital control value Digital_in representing the time t2 and the digital control value Digital_in_2 representing the time t3.

  The variable delay unit 42 generates the clock CLOCK2_2 by delaying the clock CLOCK2_1 by a period of t2 to t3. Since the control signal Ctrl2 is generated using the clock CLOCK2_2 as a reference clock, the falling edge of the control signal Ctrl1 coincides with the falling edge of the control signal Ctrl2.

After the third cycle (stable period)
Since the difference between the input voltage Batt in the third cycle and the output voltage Vo1 is larger than the output voltage Vo1, the signal Slope2 is low. The variable delay unit 42 sets the delay set time to t1 by the digital control value Digital_in representing the time t1.

  The variable delay unit 42 generates the clock CLOCK2_2 by delaying the clock CLOCK2_1 by a period of t1. Since the control signal Ctrl2 is generated using the clock CLOCK2_2 as a reference clock, the falling edge of the control signal Ctrl1 coincides with the rising edge of the control signal Ctrl2.

  By the above-described operation, it is possible to realize that the falling edge of the control signal Ctrl1 and the rising edge or the falling edge of the control signal Ctrl2 always coincide.

  Thus, the difference between the input and output charge amounts of the smoothing output capacitor 10 (the area of the region shown by hatching in FIG. 2) can be reduced without increasing the frequency of the control signal Ctrl2. As a result, the ripple of the output voltage Vo1 can be reduced, and the loss of the power supply device 41 can be reduced.

  Further, in the power supply device 41 shown in FIG. 5, when the duty ratio of the control signal Ctrl1 changes, the follow-up time of the delay time of the control signal Ctrl2 can be reduced, so that the ripple of the output voltage Vo1 during the follow-up period is suppressed. can do.

  As a result, a more accurate output voltage Vo1 can be generated, and the reliability of the power supply device 41 can be improved.

(Embodiment 3)
In the first and second embodiments, the input voltage Batt and the output voltage Vo1 of the power supply devices 32 and 41 are grasped, and the falling edge of the control signal ctrl1 is set to the rising edge or the rising edge of the control signal ctrl2 as shown in FIG. It is necessary to set in advance to match either of the falling edges.

  This is not applicable when the input voltage Batt changes significantly and the relationship between the rise and fall of the input current IL of the smoothing output capacitor 10 changes. In other words, it cannot be applied when changing the falling edge of the control signal Ctrl1 to match the rising edge of the control signal Ctrl2 to the falling edge of the control signal Ctrl2.

  Therefore, in the third embodiment, instead of adjusting the delay between the control signals Ctrl1 and Ctrl2 by feedback control of the phase relationship between the control signal Ctrl1 and the control signal Ctrl2, the control signal is controlled by feedback control of the ripple of the output voltage Vo1. A technique for adjusting the delay of Ctrl1 and Ctrl2 will be described.

<Configuration example of power supply unit>
FIG. 8 is an explanatory diagram illustrating an example of the configuration of the power supply device 43 according to the third embodiment.

  In FIG. 8, the same reference numerals are given to the same components as those in FIGS. 1 and 5.

  8, the switching operation unit 1, the switching operation unit 2, the load 50, the load 49, the clock generation circuit 26, the frequency divider 24, the PID controller 36, the DPWM generator 35, the AD converter 40, the PID controller 39, and the DPWM The generator 38 and the unit delay generator 27 are the same as those in FIGS.

  The power supply device 43 has a switching operation unit 1, a switching operation unit 2, and a control unit 51. The power supply device 43 inputs a feedback voltage from the output voltages Vo1 and Vo2 to the control unit 51, inputs control signals Ctrl1 and Ctrl2 generated by the control unit 51 to the switching operation units 1 and 2, and outputs a desired output voltage value. Generate

  The control unit 51 includes a controller 25, a controller 44, a frequency divider 24, a clock generation circuit 26, and a delay adjustment circuit 47. The controller 44 has an AD converter 45, a PID controller 36, and a DPWM generator 35.

  The controller 44 is a digital controller such as a microcomputer, for example, and generates a control signal Ctrl1 to be input to the switching operation unit 1. Specifically, the feedback voltage from the output voltage Vo1 is converted into a digital feedback pressure value by the AD converter 45, and the PID controller 36 generates a digital control value.

  Then, the control signal Ctrl1 is generated from the DPWM generator 35 based on the clock CLOCK1 output from the frequency divider 24 and the digital control value generated by the PID controller 36.

  The AD converter 45 is an analog-to-digital conversion circuit that converts a feedback voltage from the output voltage Vo1 into a digital feedback voltage value. The digital feedback voltage converted by the AD converter 45 has two uses.

  One is input to the PID controller 36 as in the second embodiment. The other is to measure the magnitude of the ripple of the output voltage Vo1 every one cycle before the control signal Ctrl1. The difference between the AD converter 45 and the AD converter 37 in FIG. 5 of the second embodiment is the sampling frequency.

  The sampling frequency of the AD converter 37 is the same as the frequency of the control signal Ctrl1. In order to accurately measure the magnitude of the ripple of the output voltage Vo1 every one cycle before the control signal Ctrl1, the sampling frequency of the AD converter 45 is set to a frequency that is, for example, twice or more higher than the frequency of the control signal Ctrl1. There is a need.

  The delay adjustment circuit 47 includes a ripple comparator 52, a sample and hold circuit 48, a ripple comparator 46, and the unit delay generator 27. The delay adjustment circuit 47 adjusts the phase relationship between the control signal Ctrl1 and the control signal Ctrl2. The ripple comparator 52 and the sample hold circuit 48 constitute a detector.

  The ripple comparator 52 obtains a ripple value of the output voltage Vo1 during one cycle of the control signal Ctrl1, using the digital feedback voltage value of the output voltage Vo1 converted by the AD converter 45. The sample hold circuit 48 stores the ripple value of the output voltage Vo1 one cycle before the control signal Ctrl1.

  The ripple comparator 46 compares the ripple value of the output voltage Vo1 one cycle before and one cycle after the control signal Ctrl1, and outputs the comparison result as pulse signals H_out and L_out. When the ripple value of the output voltage Vo1 one cycle before the control signal Ctrl1 is larger than one cycle after, the pulse signal H_out is generated. When the ripple value of the output voltage Vo1 one cycle before the control signal Ctrl1 is smaller than one cycle after, the pulse signal L_out is generated.

  The unit delay generator 27 generates a clock CLOCK2_2 by delaying the clock CLOCK2_1 from the frequency divider 24 by a desired delay time based on the pulse signals H_out and L_out detected from the ripple comparator 46.

  When the ripple comparator 46 generates the pulse signal H_out, it outputs a clock (CLOCK2_2) obtained by delaying the clock CLOCK2_1 from the frequency divider 24 by increasing the delay time by one unit.

  On the other hand, when the ripple comparator 46 generates the pulse signal L_out, it outputs a clock CLOCK2_2 obtained by delaying the clock CLOCK2_1 from the frequency divider 24 by reducing the delay time by one unit.

  The controller 25 has an AD converter 40, a PID controller 39, and a DPWM generator 38. The controller 25 is a digital controller such as a microcomputer, for example, and generates a control signal Ctrl2.

  Specifically, a feedback voltage from the output voltage Vo2 is converted into a digital feedback pressure value by the AD converter 40, a digital control value is generated by the PID controller 39, and a clock output from the unit delay generator 27 is output. The DPWM generator 38 generates a control signal Ctrl2 based on CLOCK2_2 and the digital control value output from the PID controller 39.

<Operation example of power supply unit>
Next, an example of the operation of the power supply device 43 in FIG. 8 will be described with reference to FIG.

  FIG. 9 is a timing chart showing an example of each signal in the control unit 51 in the power supply device 43 of FIG.

  In FIG. 9, the signal timings of the ripple of the output voltage Vo1, the clock CLOCK1, the clock CLOCK2_1, the clock CLOCK2_2, the control signal Ctrl1, the control signal Ctrl2, the pulse signal L_out, and the pulse signal H_out are shown from the top to the bottom.

1st cycle (initial period)
First, the frequency divider 24 generates clocks CLOCK1 and CLOCK2_1 whose frequency is an integer multiple from the reference clock of the clock generation circuit 26. Here, a case where the frequencies of the control signals Ctrl1 and Ctrl2 are the same (Ts1 = Ts2) will be described as an example.

  The controller 44 generates a control signal Ctrl1 from the feedback voltage from the output voltage Vo1 and the clock CLOCK1. The initial delay setting time of the unit delay generator 27 is td. The unit delay generator 27 generates the clock CLOCK2_2 by delaying the clock CLOCK2_1 by a period of td.

  The controller 25 generates a control signal Ctrl2_2 from the feedback voltage from the output voltage Vo2 and the clock CLOCK2_2. The ripple comparator 46 detects that the ripple value of the output voltage Vo1 one cycle before the control signal Ctrl1 is greater than one cycle after, and outputs a pulse signal H_out. As a result, the delay set in the unit delay generator 27 becomes td + x obtained by adding one unit from the initial td.

Second or third cycle (follow-up period)
Second cycle: A change occurs in the output voltage Vo1 due to the input voltage Batt or the operating state of the loads 49 and 50, and the duty ratio of the control signal Ctrl1 generated from the controller 44 increases.

  The unit delay generator 27 generates the clock CLOCK2_2 by delaying the clock CLOCK2_1 by a period of td + x. The ripple comparator 46 detects that the ripple value of the output voltage (Vo1) one cycle before the control signal Ctrl1 is larger than one cycle after, and outputs a pulse signal H_out.

  Thus, the delay set in the unit delay generator 27 is increased by one unit from the initial td, and becomes td + 2x.

  Third cycle: The unit delay generator 27 delays the clock CLOCK2_1 by a period of td + 2x to generate the clock CLOCK2_2. The ripple comparator 46 detects that the ripple value of the output voltage Vo1 one cycle before the control signal Ctrl1 is smaller than one cycle after, and outputs a pulse signal L_out. Thus, the delay set in the unit delay generator 27 is reduced by one unit from td + 2x, and becomes td + x.

After the fourth cycle (stable period)
The delay set in the unit delay generator 27 by the pulse signal H_out or the pulse signal L_out is repeatedly set between td + 2x and td + x for each cycle.

  By the above operation, even when the input voltage Batt changes significantly, the ripple of the output voltage Vo1 can be further reduced without increasing the frequency of the control signal Ctrl2.

  Accordingly, it is possible to generate the output voltage Vo1 with high accuracy while further reducing the loss in the power supply device 43, and it is possible to further improve the reliability and power supply efficiency of the power supply device 43.

  As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say.

  Note that the present invention is not limited to the above-described embodiment, and includes various modifications. For example, the above-described embodiments have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described above.

  Further, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of one embodiment can be added to the configuration of another embodiment. . Further, for a part of the configuration of each embodiment, it is possible to add, delete, or replace another configuration.

  In addition, each of the above-described configurations, functions, processing units, processing means, and the like may be partially or entirely realized by hardware, for example, by designing an integrated circuit. In addition, the above-described configurations, functions, and the like may be realized by software by a processor interpreting and executing a program that realizes each function. Information such as a program, a table, and a file for realizing each function can be stored in a memory, a hard disk, a recording device such as an SSD (Solid State Drive), or a recording medium such as an IC card, an SD card, or a DVD.

  In addition, control lines and information lines are shown as necessary for the description, and do not necessarily indicate all control lines and information lines on a product. In fact, it can be considered that almost all components are connected to each other.

DESCRIPTION OF SYMBOLS 1 Switching operation part 2 Switching operation part 3 Control part 5 Control part 6 Phase control part 7 Switching element 8 Switching element 9 Inductor 10 Smoothing output capacitance 11 Driver 12 Control circuit 14 Switching element 15 Switching element 16 Inductor 17 Smoothing output capacitance 18 Driver 19 Control unit 20 Control circuit 24 Divider 25 Controller 26 Clock generation circuit 27 Unit delay generator 28 Edge detector 29 Control unit 32 Power supply device 33 Controller 34 Controller 35 DPWM generator 36 PID controller 37 AD conversion Device 38 DPWM generator 39 PID controller 40 A / D converter 41 Power supply device 42 Variable delay device 43 Power supply device 44 Controller 45 A / D converter 46 Ripple comparator 47 Delay adjustment circuit 48 Sample and hold circuit 51 Control unit 52 Ripple comparator 53 Input voltage Can 54 output voltage detector 55 voltage comparator 56 the voltage detecting comparator unit 57 current detector 59 current slope comparator 60 current detector comparator

Claims (5)

A first switching power supply circuit that generates a first output voltage from an input voltage input from outside;
A second switching power supply circuit that generates a second output voltage from the first output voltage;
A first control circuit that controls the first output voltage generated by the first switching power supply circuit based on a first clock;
A second control circuit that controls the second output voltage generated by the second switching power supply circuit based on a second clock;
The frequency of the first clock and the frequency of the second clock are adjusted to an integral multiple to reduce the delay between the first clock and the second clock to reduce the ripple of the first output voltage. Delay generation unit that controls the
Has,
The first switching power supply circuit has a first switching unit that switches the input voltage,
The second switching power supply circuit has a second switching unit that switches the first output voltage,
The first control circuit generates a first control signal for controlling the first switching unit from the first clock,
The second control circuit generates a second control signal for controlling the second switching unit from the second clock,
The delay generation unit controls a phase of the first control signal and a phase of the second control signal to control a delay of the first clock and the second clock,
Further, a current detector that detects a slope of an increase in the inductor current flowing through the inductor and a slope of a decrease in the inductor current,
By comparing the slope of the inductor current rise and the slope of the inductor current detected by the current detector, it is determined which of the slope of the inductor current rise and the slope of the inductor current fall is greater. A current slope comparator,
Has,
The inductor is provided in the first switching power supply circuit, and stores and discharges energy by switching of the first switching unit.
The delay generation unit may be configured to determine whether a signal rising edge or a signal falling edge of the first control signal and a signal rising edge or a signal falling edge of the second control signal based on a determination result of the current slope comparator. A power supply that controls to align with one of the edges. The power supply device according to claim 1 ,
The delay generation unit, when the current gradient comparator determines that the gradient of the increase in the inductor current is greater than the gradient of the decrease in the inductor current, the off operation of the first switching unit, and the second When it is determined that the on-operation of the switching unit is simultaneous and the slope of the rise of the inductor current is smaller than the slope of the decrease of the inductor current, the off-operation of the first switching unit and the second switching unit A power supply device that controls a signal rising edge or a signal falling edge of the first control signal and the second control signal so that the off operation is performed simultaneously. A first switching power supply circuit that generates a first output voltage from an input voltage input from outside;
A second switching power supply circuit that generates a second output voltage from the first output voltage;
A first control circuit that controls the first output voltage generated by the first switching power supply circuit based on a first clock;
A second control circuit that controls the second output voltage generated by the second switching power supply circuit based on a second clock;
The frequency of the first clock and the frequency of the second clock are adjusted to an integral multiple to reduce the delay between the first clock and the second clock to reduce the ripple of the first output voltage. Delay generation unit that controls the
Has,
The first switching power supply circuit has a first switching unit that switches the input voltage,
The second switching power supply circuit has a second switching unit that switches the first output voltage,
The first control circuit generates a first control signal for controlling the first switching unit from the first clock,
The second control circuit generates a second control signal for controlling the second switching unit from the second clock,
The delay generation unit controls a phase of the first control signal and a phase of the second control signal to control a delay of the first clock and the second clock,
Further, an edge detector for detecting a signal rising edge or a signal falling edge of the first control signal and the second control signal,
The delay generation unit controls a delay of the first clock and the second clock so that a signal rising edge or a signal falling edge of the first control signal and the second control signal are aligned, When the frequency of the first clock is equal to the frequency of the second clock, the first clock is controlled so that the off operation of the first switching unit and the off operation of the second switching unit are performed simultaneously. And a power supply device for controlling a delay of the second clock. A first switching power supply circuit that generates a first output voltage from an input voltage input from outside;
A second switching power supply circuit that generates a second output voltage from the first output voltage;
A first control circuit that controls the first output voltage generated by the first switching power supply circuit based on a first clock;
A second control circuit that controls the second output voltage generated by the second switching power supply circuit based on a second clock;
The frequency of the first clock and the frequency of the second clock are adjusted to an integral multiple to reduce the delay between the first clock and the second clock to reduce the ripple of the first output voltage. Delay generation unit that controls the
Has,
The first switching power supply circuit has a first switching unit that switches the input voltage,
The second switching power supply circuit has a second switching unit that switches the first output voltage,
The first control circuit generates a first control signal for controlling the first switching unit from the first clock,
The second control circuit generates a second control signal for controlling the second switching unit from the second clock,
The delay generation unit controls a phase of the first control signal and a phase of the second control signal to control a delay of the first clock and the second clock,
Further, an edge detector for detecting a signal rising edge or a signal falling edge of the first control signal and the second control signal,
The delay generation unit controls a delay of the first clock and the second clock so that a signal rising edge or a signal falling edge of the first control signal and the second control signal are aligned, When the frequency of the second clock is equal to or more than twice the frequency of the first clock, the second switching unit and the second switching unit are turned off at the same time. A power supply device for controlling delays of a first clock and the second clock. A first switching power supply circuit that generates a first output voltage from an input voltage input from outside;
A second switching power supply circuit that generates a second output voltage from the first output voltage;
A first control circuit that controls the first output voltage generated by the first switching power supply circuit based on a first clock;
A second control circuit that controls the second output voltage generated by the second switching power supply circuit based on a second clock;
The frequency of the first clock and the frequency of the second clock are adjusted to an integral multiple to reduce the delay between the first clock and the second clock to reduce the ripple of the first output voltage. Delay generation unit that controls the
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The first switching power supply circuit has a first switching unit that switches the input voltage,
The second switching power supply circuit has a second switching unit that switches the first output voltage,
The first control circuit generates a first control signal for controlling the first switching unit from the first clock,
The second control circuit generates a second control signal for controlling the second switching unit from the second clock,
The delay generation unit controls a phase of the first control signal and a phase of the second control signal to control a delay of the first clock and the second clock,
Further, an edge detector for detecting a signal rising edge or a signal falling edge of the first control signal and the second control signal,
The delay generation unit controls a delay of the first clock and the second clock so that a signal rising edge or a signal falling edge of the first control signal and the second control signal are aligned,
A voltage detection unit that detects a voltage level of the input voltage input to the first switching power supply circuit and a voltage level of the first output voltage generated by the first switching power supply circuit;
A voltage comparator that compares the input voltage detected by the voltage detection unit with the first output voltage and outputs a result of the comparison;
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The delay generation unit controls so that any one of a signal rising edge or a signal falling edge of the first control signal and any one of a signal rising edge or a signal falling edge of the second control signal is aligned. When the difference between the input voltage and the first output voltage is larger than the first output voltage based on the comparison result of the voltage comparator, the off operation of the first switching unit and the second switching And when the difference between the input voltage and the first output voltage is smaller than the first output voltage, the off operation of the first switching unit and the second switching unit A power supply device that controls the first control signal and the second control signal so that the off operation of the first control signal and the second control signal are performed simultaneously.

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