WO2018092326A1 - Display device - Google Patents
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- WO2018092326A1 WO2018092326A1 PCT/JP2017/011639 JP2017011639W WO2018092326A1 WO 2018092326 A1 WO2018092326 A1 WO 2018092326A1 JP 2017011639 W JP2017011639 W JP 2017011639W WO 2018092326 A1 WO2018092326 A1 WO 2018092326A1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1347—Arrangement of liquid crystal layers or cells in which the final condition of one light beam is achieved by the addition of the effects of two or more layers or cells
- G02F1/13471—Arrangement of liquid crystal layers or cells in which the final condition of one light beam is achieved by the addition of the effects of two or more layers or cells in which all the liquid crystal cells or layers remain transparent, e.g. FLC, ECB, DAP, HAN, TN, STN, SBE-LC cells
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134336—Matrix
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/302—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements characterised by the form or geometrical disposition of the individual elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/46—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character is selected from a number of characters arranged one behind the other
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/02—Composition of display devices
- G09G2300/023—Display panel composed of stacked panels
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0421—Structural details of the set of electrodes
- G09G2300/0426—Layout of electrodes and connections
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0439—Pixel structures
- G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/08—Details of timing specific for flat panels, other than clock recovery
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
- G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
Definitions
- the present invention relates to a display device.
- each of the above patent documents does not disclose a specific method for inclining the pixel arrangement direction in the operation of designing the pixel arrangement, and does not consider the work efficiency.
- the present invention has been made in view of the above circumstances, and an object of the present invention is to improve work efficiency when tilting the pixel array direction in a display device having a tilt angle in the pixel array direction.
- a display device includes a display panel in which a plurality of pixels are arranged in a matrix, and the plurality of pixels includes a plurality of first pixels and the plurality of first pixels. Including a plurality of second pixels arranged at a pitch different from the pixel arrangement pitch, wherein the number of the plurality of first pixels and the number of the plurality of second pixels are different from each other. .
- the first pixel group composed of the plurality of first pixels arranged adjacent to each other and the second pixel group composed of the plurality of second pixels arranged adjacent to each other are alternately arranged. May be arranged.
- the number of the plurality of first pixels included in the first pixel group may be different from the number of the plurality of second pixels included in the second pixel group.
- the plurality of pixels further include a plurality of third pixels and a plurality of fourth pixels, and the plurality of first pixels and the plurality of third pixels are in the second direction.
- the arrangement pitch of the first direction is different from each other, the arrangement pitch of the plurality of second pixels and the plurality of fourth pixels are equal to each other in the arrangement of the first direction.
- the plurality of third pixels and the plurality of fourth pixels may have different pitches in the first direction, and may have different pitches in the second direction.
- the number of the plurality of second pixels and the number of the plurality of third pixels are different from each other, the number of the plurality of third pixels, and the number of the plurality of fourth pixels. And may be different from each other.
- the display panel may include a substrate, and the first direction and the second direction may be inclined with respect to an edge of the substrate.
- a display device includes a first display panel and a second display panel that are arranged so as to overlap each other in plan view, and the first display panel includes a plurality of display panels. Pixels are arranged in a matrix in the first direction and the second direction, and a plurality of pixels are arranged in a matrix in the third direction and the fourth direction on the second display panel, and the first display
- the plurality of pixels arranged on the panel includes a plurality of first pixels and a plurality of second pixels, and the plurality of first pixels and the plurality of second pixels have an arrangement pitch in the first direction of each other.
- the plurality of pixels arranged in the second display panel are equal in the arrangement pitch in the third direction, and the arrangement pitch in the fourth direction is the same. Both are equal, the second display panel
- the arrangement pitch of the plurality of pixels arranged in the fourth direction is the arrangement pitch of the plurality of first pixels in the second direction and the arrangement pitch of the plurality of second pixels in the second direction. It is larger than one of them and smaller than the other.
- the second direction may be inclined by 28 degrees to 32 degrees with respect to the fourth direction.
- a display device includes a plurality of rectangular pixels each including a pair of sides extending in a first direction and a pair of sides extending in a second direction.
- a display panel arranged in a matrix in one direction and the second direction, wherein the plurality of pixels include a first pixel, a second pixel, and a third pixel; and a first end of the first pixel;
- the second end of the second pixel and the third end of the third pixel are apexes, the first end and the second end are connected, and the first end extends in the first direction.
- One display, the second end and the third end are connected, the second side extending in the second direction is connected, the first end and the third end, and the display panel
- a right triangle composed of a third side parallel to the edge side of the substrate constituting the substrate is formed, and the angle formed by the first side and the third side is ⁇ , t n ⁇ and cos ⁇ are rational respectively, characterized in that.
- the display panel includes a plurality of data lines and a plurality of gate lines, and the plurality of data lines or the plurality of gate lines are the angle ⁇ with respect to the edge of the substrate. It may be inclined.
- the display panel includes a plurality of gate lines extending in the first direction and a plurality of data lines extending in the second direction, and the length of the first side. May be an integer multiple of the array pitch of the plurality of data lines, and the length of the second side may be an integer multiple of the array pitch of the plurality of gate lines.
- a display device includes a first display panel and a second display panel that are arranged so as to overlap each other in a plan view, and the first display panel includes a first display panel and a first display panel.
- a plurality of rectangular pixels including a pair of sides extending in the direction and a pair of sides extending in the second direction are arranged in a matrix in the first direction and the second direction, and the plurality of pixels
- the pixel includes a first pixel, a second pixel, and a third pixel, and includes a first end of the first pixel, a second end of the second pixel, and a third end of the third pixel.
- the first end and the second end are connected, the first side extending in the first direction, the second end and the third end are connected, and the second When a right triangle composed of a second side extending in the direction and a third side connecting the first end and the third end is formed, the first side
- the side is parallel to the plurality of data lines or the plurality of gate lines formed on the second display panel, and tan ⁇ and cos ⁇ are rational numbers, where ⁇ is an angle formed by the first side and the third side. It is characterized by being.
- a display device includes a first display panel and a second display panel that overlap each other in plan view, and the first display panel extends in a first direction.
- a plurality of rectangular pixels each having a pair of sides and a pair of sides extending in the second direction are arranged in a matrix in the first direction and the second direction.
- the first end and the second end are connected to each other, the first side extending in the first direction, the second end and the third end are connected to each other, and the second end is extended to the second direction.
- the tan ⁇ is 3/4, 5/12, 8/15, 7/24, 20/21, 12/35, 9/40, 28/45, 11/60, 16 / Any one of 63 and 33/56 may be satisfied.
- the tan ⁇ may satisfy any one of 3/4, 5/12, 8/15, 7/24, and 20/21.
- the tan ⁇ may satisfy 8/15.
- the edge of the substrate constituting the first display panel may be inclined with respect to the edge of the substrate constituting the second display panel.
- the angle formed between the edge of the substrate constituting the first display panel and the edge of the substrate constituting the second display panel may be not less than 1 degree and not more than 3 degrees.
- the second display panel includes a plurality of rectangular pixels each including a pair of sides extending in the third direction and a pair of sides extending in the fourth direction.
- the plurality of pixels of the second display panel include a fourth pixel, a fifth pixel, and a sixth pixel, and are arranged in a matrix in three directions and the third direction, and a fourth end of the fourth pixel.
- the fifth end of the fifth pixel and the sixth end of the sixth pixel are connected to the fourth end and the fifth end, and extend in the third direction.
- the tan ⁇ is 3/4, 5/12, 8/15, 7/24, 20/21, 12/35, 9/40, 28/45, 11/60, 16 / Any one of 63 and 33/56 may be satisfied.
- the tan ⁇ and the tan ⁇ may each satisfy 7/24.
- the display device in a display device having an inclination angle in the pixel arrangement direction, it is possible to improve work efficiency when the pixel arrangement direction is inclined.
- FIG. 10 is a plan view showing another pixel arrangement (before rotation) for the first display panel. It is a top view which shows the pixel arrangement
- a liquid crystal display device is taken as an example, but the display device according to the present invention is not limited to a liquid crystal display device, and may be, for example, an organic EL display device.
- the liquid crystal display device includes a display panel for displaying an image, a drive circuit (source driver and gate driver) for driving the display panel, a timing controller for controlling the drive circuit, and an input video input from the outside.
- An image processing unit that performs image processing on the signal and outputs image data to the timing controller, and a backlight that irradiates the display panel with light from the back side.
- the number of display panels is not limited, and may be one or plural. When there are a plurality of display panels, the plurality of display panels are arranged so as to overlap each other in the front-rear direction when viewed from the observer side, and each displays an image.
- the liquid crystal display device 10 including two display panels will be described as an example.
- FIG. 1 is a plan view schematically showing a schematic configuration of a liquid crystal display device 10 according to the present embodiment. As shown in FIG. 1, the liquid crystal display device 10 is disposed at a position (front side) closer to the viewer than the first display panel 100 and a first display panel 100 disposed at a position farther from the viewer (rear side).
- the image processing unit 300 receives an input video signal Data transmitted from an external system (not shown), performs known image processing, and then outputs first image data DAT1 to the first timing controller 140.
- the second image data DAT2 is output to the second timing controller 240.
- the image processing unit 300 outputs a control signal (not shown in FIG. 1) such as a synchronization signal to the first timing controller 140 and the second timing controller 240.
- the first image data DAT1 is image data for displaying a monochrome image
- the second image data DAT2 is image data for displaying a color image.
- the first display panel 100 displays a black and white image corresponding to the input video signal Data in the first image display area 110
- the second display panel 200 displays a color image corresponding to the input video signal Data in the second image display area 210.
- the backlight (omitted in FIG. 1) is disposed on the back side of the first display panel 100.
- FIGS. 2 and 3 are plan views schematically showing a schematic configuration of the first display panel 100.
- FIG. As shown in FIGS. 2 and 3, in the first display panel 100, a plurality of pixels are arranged so as to be inclined with respect to the edge of the substrate, for example.
- two source driver ICs (SIC) constituting the first source driver 120 are arranged along one side (the lower side in FIG. 2) of the first image display area 110.
- Two gate driver ICs (GIC) constituting the gate driver 130 are arranged along one side (the right side in FIG. 2) of the first image display area 110.
- the gate lead line 31 is disposed on the side (upper side in FIG. 2) that faces the side on which the source driver IC (SIC) is disposed.
- each of the two source driver ICs (SICs) constituting the first source driver 120 is connected to each of two sides (upper side and lower side in FIG. 2) of the first image display region 110.
- the two gate driver ICs (GICs) constituting the first gate driver 130 are arranged along two sides of the first image display area 110 (the right side and the left side in FIG. 2).
- source leader lines 21 are arranged on two sides (upper side and lower side in FIG. 2) of the first image display region 110, and two sides (right side and left side in FIG. 2) of the first image display region 110.
- a gate lead-out line 31 is disposed at the end.
- FIG. 4 is a plan view schematically showing a schematic configuration of the first display panel 100
- FIG. 5 is a plan view schematically showing a schematic configuration of the second display panel 200
- FIG. 6 is a cross-sectional view of the first display panel 100 and the second display panel 200.
- FIG. 4 shows a configuration in which a plurality of pixels are arranged to be inclined with respect to the edge of the substrate, for example, as shown in FIGS. 4 and 5, for convenience of explanation, the pixel 114 of the first display panel 100 and the pixel 214 (sub-pixel) of the second display panel 200 are drawn in the same size, but this embodiment As will be described later (see FIG.
- the liquid crystal display device 10 includes an area of the pixel 114 of the first display panel 100 and a pixel 224 of the second display panel 200 (the red sub-pixel, the green sub-pixel, and the blue sub-pixel). Are included in each other.
- the first display panel 100 includes a thin film transistor substrate 101 (hereinafter referred to as a TFT substrate) disposed on the backlight 400 side, and a color filter disposed on the viewer side and facing the TFT substrate 101.
- a substrate 102 hereinafter referred to as a CF substrate
- a liquid crystal layer 103 disposed between the TFT substrate 101 and the CF substrate 102 are included.
- a polarizing plate 104 is disposed on the backlight 400 side of the first display panel 100, and a polarizing plate 105 is disposed on the viewer side.
- a plurality of gate lines 112 extending in the first direction and a plurality of data lines 111 extending in a second direction different from the first direction are formed on the TFT substrate 101.
- Thin film transistors 113 (hereinafter referred to as TFTs) are formed in the vicinity of the intersections of the plurality of data lines 111 and the plurality of gate lines 112.
- TFTs Thin film transistors 113
- a region surrounded by two adjacent data lines 111 and two adjacent gate lines 112 is defined as one pixel 114, and the pixels 114 are arranged in a matrix.
- the plurality of data lines 111 are arranged at equal intervals in the first direction, and the plurality of gate lines 112 are arranged at equal intervals in the second direction.
- a pixel electrode 115 is formed for each pixel 114, and one common electrode (not shown) common to the plurality of pixels 114 is formed.
- the drain electrode constituting the TFT 113 is electrically connected to the data line 111, the source electrode is electrically connected to the pixel electrode 115, and the gate electrode is electrically connected to the gate line 112.
- a black matrix 102b that blocks transmission of light is formed at a position corresponding to a boundary portion of each pixel 114.
- no colored portion is formed, and for example, an overcoat film is formed.
- the present invention is not limited to this.
- the stacked structure of each part included in the pixel 114 is not limited to the above structure.
- the first timing controller 140 based on the first image data DAT1 output from the image processing unit 300 and the first control signal CS1 (clock signal, vertical synchronization signal, horizontal synchronization signal, etc.), Various timing signals (data start pulse DSP1, data clock DCK1, gate start pulse GSP1, and gate clock GCK1) for controlling driving of the first source driver 120 and the first gate driver 130 are generated (see FIG. 4). .
- the first timing controller 140 outputs the first image data DA1, the data start pulse DSP1, and the data clock DCK1 to the first source driver 120, and outputs the gate start pulse GSP1 and the gate clock GCK1 to the first gate driver 130. Output.
- the first source driver 120 outputs a data signal (data voltage) corresponding to the first image data DA1 to the data line 111 based on the data start pulse DSP1 and the data clock DCK1.
- the first gate driver 130 outputs a gate signal (gate voltage) to the gate line 112 based on the gate start pulse GSP1 and the gate clock GCK1.
- the data voltage is supplied from the first source driver 120 to each data line 111, and the gate voltage is supplied from the first gate driver 130 to each gate line 112.
- a common voltage Vcom is supplied to the common electrode from a common driver (not shown).
- the gate voltage gate-on voltage
- the TFT 113 connected to the gate line 112 is turned on, and the data voltage is supplied to the pixel electrode 115 via the data line 111 connected to the TFT 113.
- An electric field is generated by the difference between the data voltage supplied to the pixel electrode 115 and the common voltage Vcom supplied to the common electrode.
- the liquid crystal is driven by this electric field to control the light transmittance of the backlight 400 to display an image. On the first display panel 100, a monochrome image is displayed.
- the second display panel 200 includes a TFT substrate 201 disposed on the backlight 400 side, a CF substrate 202 disposed on the viewer side and facing the TFT substrate 201, the TFT substrate 201, and the CF substrate And a liquid crystal layer 203 disposed between the substrates 202.
- a polarizing plate 204 is disposed on the backlight 400 side of the second display panel 200, and a polarizing plate 205 is disposed on the viewer side.
- An adhesive sheet 301 is disposed between the polarizing plate 105 of the first display panel 100 and the polarizing plate 204 of the second display panel 200.
- a plurality of gate lines 212 extending in the third direction and a plurality of data lines 211 extending in a fourth direction different from the third direction are formed.
- TFTs 213 are formed in the vicinity of the intersections of the plurality of data lines 211 and the plurality of gate lines 212.
- a region surrounded by two adjacent data lines 211 and two adjacent gate lines 212 is defined as one subpixel 214, and the subpixel 214 is a matrix.
- a plurality are arranged in a shape.
- the plurality of data lines 211 are arranged at equal intervals in the third direction, and the plurality of gate lines 212 are arranged at equal intervals in the fourth direction.
- a pixel electrode 215 is formed for each subpixel 214, and one common electrode (not shown) common to the plurality of subpixels 214 is formed.
- the drain electrode constituting the TFT 213 is electrically connected to the data line 211, the source electrode is electrically connected to the pixel electrode 215, and the gate electrode is electrically connected to the gate line 212.
- a plurality of colored portions 202 a are formed on the CF substrate 202 corresponding to the sub-pixels 214.
- Each colored portion 202a is surrounded by a black matrix 202b that blocks light transmission, and is formed in a rectangular shape, for example.
- the plurality of colored portions 202a are formed of a red (R color) material and transmit a red portion that transmits red light, and a green portion that is formed of a green (G color) material and transmits green light. And a blue portion that is formed of a blue (B color) material and transmits blue light.
- the red portion, the green portion, and the blue portion are repeatedly arranged in this order in the third direction, the colored portions of the same color are arranged in the fourth direction, and the black matrix 202b is formed at the boundary portion between the adjacent colored portions 202a.
- the plurality of sub-pixels 214 include a red sub-pixel 214R corresponding to the red portion, a green sub-pixel 214G corresponding to the green portion, and a blue sub-pixel 214B corresponding to the blue portion.
- one red sub-pixel 214R, one green sub-pixel 214G, and one blue sub-pixel 214B constitute one pixel 224.
- Each pixel 114 of the first display panel 100 and each pixel 224 of the second display panel 200 have the same area. For example, as shown in FIG. 7, the area of one pixel 114 (see FIG. 7B) of the first display panel 100, one red sub-pixel 214R of the second display panel 200, and one green The areas of one pixel 224 (see FIG. 7A) including the sub-pixel 214G and one blue sub-pixel 214B are equal to each other.
- the present invention is not limited to this.
- the stacked structure of each part included in the sub-pixel 214 is not limited to the above structure.
- the second timing controller 240 based on the second image data DAT2 output from the image processing unit 300 and the second control signal CS2 (clock signal, vertical synchronization signal, horizontal synchronization signal, etc.), Various timing signals (data start pulse DSP2, data clock DCK2, gate start pulse GSP2, and gate clock GCK2) for controlling the driving of the second source driver 220 and the second gate driver 230 are generated (see FIG. 5). .
- the second timing controller 240 outputs the second image data DA2, the data start pulse DSP2, and the data clock DCK2 to the second source driver 220, and outputs the gate start pulse GSP2 and the gate clock GCK2 to the second gate driver 230. Output.
- the second source driver 220 outputs a data voltage corresponding to the second image data DA2 to the data line 211 based on the data start pulse DSP2 and the data clock DCK2.
- the second gate driver 230 outputs a gate voltage to the gate line 212 based on the gate start pulse GSP2 and the gate clock GCK2.
- the data voltage is supplied from the second source driver 220 to each data line 211, and the gate voltage is supplied from the second gate driver 230 to each gate line 212.
- a common voltage Vcom is supplied to the common electrode from a common driver.
- the gate voltage gate-on voltage
- the TFT 213 connected to the gate line 212 is turned on, and the data voltage is supplied to the pixel electrode 215 via the data line 211 connected to the TFT 213.
- An electric field is generated by the difference between the data voltage supplied to the pixel electrode 215 and the common voltage Vcom supplied to the common electrode.
- the liquid crystal is driven by this electric field to control the light transmittance of the backlight 400 to display an image.
- a desired data voltage is supplied to the data lines 211 connected to the pixel electrodes 215 of the red sub-pixel 214R, the green sub-pixel 214G, and the blue sub-pixel 214B, thereby performing color image display. Is called.
- a liquid crystal display device configured by overlapping a plurality of display panels
- the design is restricted.
- CAD it is necessary to design a pixel arrangement in accordance with a so-called grid which is a rectangular pattern of dots or lines displayed in the entire drawing area and is the minimum unit of data processing.
- the grid is set at an interval of 0.05 ⁇ m, for example.
- the pixel arrangement needs to be designed so that the end of the pixel (intersection of the data line and the gate line) is placed on the grid. For this reason, when designing an array pattern of pixels having an inclination angle in the array direction, there is a possibility that the work time increases and the work efficiency decreases.
- FIG. 8 is a plan view for explaining the characteristic configuration of the liquid crystal display device 10.
- the pixel arrangement direction is inclined by an angle ⁇ with respect to the X axis.
- FIG. 8 shows a configuration example in which the arrangement direction (first direction) of the pixels 114 is inclined by an angle ⁇ with respect to the X axis in the first display panel 100.
- the X axis represents a horizontal axis
- the Y axis represents a vertical (vertical) axis.
- P1 the second end P2 of the second pixel 114q, and the third end P3 of the third pixel 114r are apexes, and the first end P1 and the second end P2 are connected to extend in the first direction.
- the first side 14a, the second end P2 and the third end P3 are connected, and the second side 14b extending in the second direction is connected to the first end P1 and the third end P3.
- the first side 14a and the third side 14c are formed. If the angle is ⁇ , tan ⁇ and cos ⁇ are rational numbers, respectively.
- the end side 101a of the TFT substrate 101 extends in the X-axis direction (horizontal direction).
- each ratio (L: M: N) Has the relationship shown in FIG. That is, in the right triangle, tan ⁇ is 3/4, 5/12, 8/15, 7/24, 20/21, 12/35, 9/40, 28/45, 11/60, 16/63, Any one of 33/56 is satisfied. Also, cos ⁇ is any of 4/5, 12/13, 15/17, 24/25, 21/29, 35/37, 40/41, 45/53, 60/61, 63/65, and 56/65. Satisfies one.
- the length L, the length M, and the length N are all rational numbers, and the length L is an integral multiple of the grid interval (here 0.05 um).
- the length M of the first side 14a is an integer multiple of the arrangement pitch of the plurality of data lines 111
- the length N of the second side 14b is an integer multiple of the arrangement pitch of the plurality of gate lines 112.
- the inclination angle with respect to the extending direction (X-axis direction) of the end side 101a is set in the range of about 10 degrees to about 44 degrees. Further, when designing the arrangement of the pixels 114, the working efficiency is higher when the first end P1, the second end P2, and the third end P3 are not far apart from each other. Therefore, among the conditions shown in FIG. 9, tan ⁇ satisfies any one of 3/4, 5/12, 8/15, 7/24, and 20/21, and cos ⁇ is 4/5, 12 / It is preferable to satisfy any one of 13, 15/17, 24/25, and 21/29.
- the end of the pixel 114 can be placed on the grid by a simple method, it is possible to improve the working efficiency when the arrangement direction of the pixel 114 is inclined.
- the pixels 114 of the first display panel 100 are inclined by the angle ⁇ with respect to the end side 101a (X-axis direction) of the TFT substrate 101.
- the plurality of gate lines 112 are inclined by an angle ⁇ with respect to the end side 101a (X-axis direction) of the TFT substrate 101.
- the liquid crystal display device 10 according to the present embodiment is not limited to the above configuration.
- the extending direction (third direction) of the gate line 212 coincides with the X-axis direction (horizontal direction), that is, the third side 14c (see FIG. 8).
- the pixel 114 of the first display panel 100 is inclined by an angle ⁇ with respect to the gate line 212 (X-axis direction) of the second display panel 200. Also good. Also in this case, as for the angle ⁇ , tan ⁇ and cos ⁇ satisfy the above condition (see FIG. 9).
- the inclination angle ⁇ of the pixel 114 in the first display panel 100 is preferably about 30 degrees (for example, 28 degrees to 32 degrees). Therefore, in the right triangle shown in FIG. 8, it is preferable that, for example, the inclination angle ⁇ is 28.07 degrees, tan ⁇ is 8/15, and cos ⁇ is 15/17. Also, the occurrence of moire affects the relative angular difference between the arrangement direction of the pixels 114 of the first display panel 100 and the arrangement direction of the pixels 224 of the second display panel.
- the relative angle difference is, for example, an angle formed by the arrangement direction (for example, the first direction) of the pixels 114 of the first display panel 100 and the arrangement direction (for example, the third direction) of the pixels 224 of the second display panel 200.
- it refers to an angle formed by the extending direction (for example, the first direction) of the gate line 112 of the first display panel 100 and the extending direction (for example, the third direction) of the gate line 212 of the second display panel 200.
- the first display panel 100 in addition to the configuration of the first display panel 100, a configuration in which the relative angle difference approaches 30 degrees may be provided.
- the second display panel 200 see FIG.
- the edge 101a of the TFT substrate 101 of the first display panel 100, the second side At least one of the first display panel 100 and the second display panel 200 may be rotated so that the angle ⁇ 2 formed by the edge 201a of the TFT substrate 201 of the display panel is 1 degree or more and 3 degrees or less.
- the angle ⁇ 2 may be set to 2 degrees by rotating the first display panel 100 left one degree and rotating the second display panel 200 right one degree.
- the pixels 224 of the second display panel 200 are arranged in the horizontal direction (X-axis direction) and the vertical direction (Y-axis direction), but are the same as the pixels 114 of the first display panel 100. Further, they may be arranged with an inclination angle.
- the tilt angle is set so that the pixel 114 of the first display panel 100 and the pixel 224 of the second display panel are rotated in different directions. For example, when the tilt angle is set so that the pixel 114 of the first display panel 100 is rotated left as shown in FIG. 8, the pixel 224 of the second display panel 200 is tilted so as to be rotated right. Set the angle.
- the pixels 114 of the first display panel 100 are inclined.
- a configuration for designing an arrangement pattern of pixels having an inclination angle in the arrangement direction by adjusting the arrangement pitch of the pixels will be described.
- the plurality of pixels 224 see FIG.
- the second display panel 200 are arranged at a pitch of 170.4 ⁇ m in each of the third direction and the fourth direction. Further, the grid interval is set to 0.05 ⁇ m.
- the third direction matches the X-axis direction (horizontal direction) and the fourth direction matches the Y-axis direction (vertical direction).
- the arrangement pitch of the plurality of pixels for the first display panel 100 in the X-axis direction and the Y-axis direction is an integral multiple of 0.85 ⁇ m, and the arrangement pitch of the pixels 224 of the second display panel 200 (170. 4 um).
- a plurality of pixels (pixel groups) having different arrangement pitches are arranged in combination.
- FIG. 13 is a plan view showing an example of the arrangement pattern of the pixels 114 before rotation.
- a plurality of pixels 114 (9 ⁇ 9 pixels when represented by “the number of pixels in the X-axis direction” ⁇ “the number of pixels in the Y-axis direction”) constituting the first pixel group 114a are X
- a plurality of pixels 114 (9 ⁇ 8 pixels) constituting the second pixel group 114b are arranged at a pitch of 170.0 ⁇ m in the X-axis direction, and are arranged at a pitch of 170.0 ⁇ m in the axial direction and the Y-axis direction.
- a plurality of pixels 114 (8 ⁇ 9 pixels) constituting the third pixel group 114c are arranged at a pitch of 170.85 um in the X-axis direction and 170 pixels in the Y-axis direction.
- a plurality of pixels 114 (8 ⁇ 8 pixels) constituting the fourth pixel group 114d are arranged at a pitch of 170.85 ⁇ m in the X-axis direction and at a pitch of 170.85 ⁇ m in the Y-axis direction. It is arranged.
- FIG. 14 shows the arrangement pitch of the plurality of pixels 114 at the boundary portion of each pixel group.
- the arrangement pitch in the X-axis direction of the plurality of pixels 114 is different from each other.
- the arrangement pitch in the Y-axis direction is equal to each other.
- the arrangement pitch of the plurality of pixels 114 in the Y-axis direction is different from each other, and the X-axis direction Are equal to each other.
- the arrangement pitches of the plurality of pixels 224 in the third direction (X-axis direction) are all the same, and the arrangement pitches in the fourth direction (Y-axis direction) are all. equal.
- the plurality of pixels 224 are arranged at a pitch of 170.4 ⁇ m in the third direction and the fourth direction.
- the arrangement pitch (170.4 ⁇ m) in the X-axis direction of the plurality of pixels 224 arranged on the second display panel 200 is the plurality of pixels 114 constituting the first pixel group 114a for the first display panel 100.
- the arrangement pitch (170.4 ⁇ m) in the Y-axis direction of the plurality of pixels 224 arranged on the second display panel 200 is the number of the plurality of pixels 114 constituting the first pixel group 114a for the first display panel 100. It is larger than the arrangement pitch (170.0 um) in the Y-axis direction and smaller than the arrangement pitch (170.85 um) in the Y-axis direction of the plurality of pixels 114 constituting the second pixel group 114b.
- a 17 ⁇ 17 pixel unit including the first pixel group 114a, the second pixel group 114b, the third pixel group 114c, and the fourth pixel group 114d is in the X-axis direction. And arranged in the Y-axis direction. That is, the first pixel group 114a and the third pixel group 114c are alternately arranged in the X-axis direction, and the second pixel group 114b and the fourth pixel group 114d are alternately arranged in the X-axis direction. Pixel groups 114a and second pixel groups 114b are alternately arranged in the Y-axis direction, and third pixel groups 114c and fourth pixel groups 114d are alternately arranged in the Y-axis direction.
- the number of pixels 114 included in each pixel group is different from each other.
- the first pixel group 114a includes 81 pixels 114
- the second pixel group 114b includes 72 pixels 114.
- pixel groups having the same number of pixels may be included as shown in the second pixel group 114b and the third pixel group 114c in FIG.
- the number of pixels in each pixel group is not limited to the above example.
- the first pixel group 114a is composed of 13 ⁇ 13 pixels
- the second pixel group 114b is composed of 13 ⁇ 4 pixels.
- the third pixel group 114c may be configured with 4 ⁇ 13 pixels
- the fourth pixel group 114d may be configured with 4 ⁇ 4 pixels.
- FIG. 16 shows a state in which a pixel unit (see FIG. 13) including the first pixel group 114a, the second pixel group 114b, the third pixel group 114c, and the fourth pixel group 114d is rotated by 28.07 degrees. .
- a pixel unit see FIG. 13
- tan ⁇ satisfies 8/15
- cos ⁇ satisfies 15/17
- length L, length M, and length N are all rational numbers
- length L is the grid interval ( Here, it is an integral multiple of 0.05 um).
- the end of the pixel 114 can be placed on the grid by a simple method, it is possible to improve work efficiency when the arrangement direction of the pixel 114 is inclined.
- the first display panel 100 having an inclination angle in the pixel arrangement direction can be easily manufactured. .
- the gate line 112 extends in the first direction
- the data line 111 extends in the second direction
- the gate line 212 is the third line.
- the gate line 112 extends in the second direction
- the data line 111 extends in the second direction
- the gate line 212 may extend in the fourth direction
- the data line 211 may extend in the third direction.
- the liquid crystal display device 10 is not limited to the above configuration.
- the relationship of the arrangement of the pixels of the first display panel 100 and the second display panel 200 is not limited to the configuration illustrated in FIG. 7, and may be the configuration illustrated in FIG. 17, for example.
- the area of the pixel 114 of the first display panel 100 and the area of the sub-pixel 214 of the second display panel 200 are equal to each other.
- the liquid crystal display device 10 has a configuration in which both the first display panel 100 and the second display panel 200 display color images, and one of them has an inclination angle in the pixel arrangement direction. Also good.
- the polarizing plate 105 of the first display panel 100 and the polarizing plate 204 of the second display panel 200 may be omitted.
- a gap may be formed between the first display panel 100 and the second display panel 200. According to the said structure, it can utilize as a three-dimensional (3D) image display apparatus.
- the liquid crystal display device 10 may be configured by a single display panel having an inclination angle in the pixel arrangement direction by the method described above.
- the display panel may have a configuration for displaying a color image or a configuration for displaying a monochrome image.
- the liquid crystal display device 10 has the polarizing plate 105 (see FIG. 6) of the first display panel 100 and the polarizing plate 204 (see FIG. 6) of the second display panel 200 in order to enhance the effect of suppressing the occurrence of moire. (See FIG. 6), a diffusion sheet may be disposed.
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Abstract
This display device has a display panel in which a plurality of pixels are arranged in a matrix. The plurality of pixels include a plurality of first pixels and a plurality of second pixels aligned at a pitch that differs from the alignment pitch of the plurality of first pixels, the number of the plurality of first pixels being different from the number of the plurality of second pixels.
Description
本発明は、表示装置に関する。
The present invention relates to a display device.
従来、液晶表示装置において、画素の配列方向を所定の軸(例えば、液晶表示装置を構成する基板の端辺に平行な軸)に対して傾斜(回転)させる技術が提案されている。例えば特許文献1には、画素の配列方向を所定角度だけ傾斜させることにより、所謂ディスクリネーションの発生を抑える技術が開示されている。また特許文献2には、複数の表示パネルを重ね合わせて、それぞれの表示パネルに表示される画像の輝度比を変化させることにより観察者に三次元画像(3D画像)を知覚させる液晶表示装置において、一方の表示パネルの画素の配列方向を所定角度だけ傾斜させることにより、所謂モアレの発生を抑える技術が開示されている。
Conventionally, in a liquid crystal display device, a technique for tilting (rotating) a pixel arrangement direction with respect to a predetermined axis (for example, an axis parallel to an edge of a substrate constituting the liquid crystal display device) has been proposed. For example, Patent Document 1 discloses a technique for suppressing the occurrence of so-called disclination by inclining the pixel arrangement direction by a predetermined angle. Patent Document 2 discloses a liquid crystal display device that allows a viewer to perceive a three-dimensional image (3D image) by overlapping a plurality of display panels and changing a luminance ratio of images displayed on the respective display panels. A technique is disclosed in which the occurrence of so-called moire is suppressed by inclining the arrangement direction of pixels of one display panel by a predetermined angle.
しかし、上記各特許文献には、画素の配列を設計する作業における、画素の配列方向を傾斜させる具体的な方法については開示されておらず、作業効率は考慮されていない。
However, each of the above patent documents does not disclose a specific method for inclining the pixel arrangement direction in the operation of designing the pixel arrangement, and does not consider the work efficiency.
本発明は、上記実情に鑑みてなされたものであり、その目的は、画素の配列方向に傾斜角度を有する表示装置において、画素の配列方向を傾斜させる際の作業効率を向上させることにある。
The present invention has been made in view of the above circumstances, and an object of the present invention is to improve work efficiency when tilting the pixel array direction in a display device having a tilt angle in the pixel array direction.
上記課題を解決するために、本発明に係る表示装置は、複数の画素がマトリクス状に配置された表示パネルを有し、前記複数の画素は、複数の第1画素と、前記複数の第1画素の配列ピッチとは異なるピッチで配列された複数の第2画素とを含み、前記複数の第1画素の数と、前記複数の第2画素の数とは、互いに異なる、ことを特徴とする。
In order to solve the above problems, a display device according to the present invention includes a display panel in which a plurality of pixels are arranged in a matrix, and the plurality of pixels includes a plurality of first pixels and the plurality of first pixels. Including a plurality of second pixels arranged at a pitch different from the pixel arrangement pitch, wherein the number of the plurality of first pixels and the number of the plurality of second pixels are different from each other. .
本発明に係る表示装置では、前記複数の画素は、第1方向及び第2方向にマトリクス状に配置されており、前記複数の第1画素及び前記複数の第2画素は、前記第1方向の配列ピッチは互いに等しく、前記第2方向の配列ピッチが互いに異なってもよい。
In the display device according to the present invention, the plurality of pixels are arranged in a matrix in the first direction and the second direction, and the plurality of first pixels and the plurality of second pixels are arranged in the first direction. The arrangement pitch may be equal to each other, and the arrangement pitch in the second direction may be different from each other.
本発明に係る表示装置では、隣り合って配列された複数の前記第1画素から成る第1画素グループと、隣り合って配列された複数の前記第2画素から成る第2画素グループとが、交互に配列されてもよい。
In the display device according to the present invention, the first pixel group composed of the plurality of first pixels arranged adjacent to each other and the second pixel group composed of the plurality of second pixels arranged adjacent to each other are alternately arranged. May be arranged.
本発明に係る表示装置では、前記第1画素グループに含まれる複数の前記第1画素の数と、前記第2画素グループに含まれる複数の前記第2画素の数とが、互いに異なってもよい。
In the display device according to the present invention, the number of the plurality of first pixels included in the first pixel group may be different from the number of the plurality of second pixels included in the second pixel group. .
本発明に係る表示装置では、前記複数の画素は、さらに、複数の第3画素と複数の第4画素とを含み、前記複数の第1画素及び前記複数の第3画素は、前記第2方向の配列ピッチは互いに等しく、前記第1方向の配列ピッチが互いに異なり、前記複数の第2画素及び前記複数の第4画素は、前記第2方向の配列ピッチは互いに等しく、前記第1方向の配列ピッチが互いに異なり、前記複数の第3画素及び前記複数の第4画素は、前記第1方向の配列ピッチは互いに等しく、前記第2方向の配列ピッチが互いに異なってもよい。
In the display device according to the present invention, the plurality of pixels further include a plurality of third pixels and a plurality of fourth pixels, and the plurality of first pixels and the plurality of third pixels are in the second direction. The arrangement pitch of the first direction is different from each other, the arrangement pitch of the plurality of second pixels and the plurality of fourth pixels are equal to each other in the arrangement of the first direction. The plurality of third pixels and the plurality of fourth pixels may have different pitches in the first direction, and may have different pitches in the second direction.
本発明に係る表示装置では、前記複数の第2画素の数と、前記複数の第3画素の数とが、互いに異なり、前記複数の第3画素の数と、前記複数の第4画素の数とが、互いに異なってもよい。
In the display device according to the present invention, the number of the plurality of second pixels and the number of the plurality of third pixels are different from each other, the number of the plurality of third pixels, and the number of the plurality of fourth pixels. And may be different from each other.
本発明に係る表示装置では、前記表示パネルは基板を含み、前記第1方向及び前記第2方向は、前記基板の端辺に対して傾斜してもよい。
In the display device according to the present invention, the display panel may include a substrate, and the first direction and the second direction may be inclined with respect to an edge of the substrate.
また上記課題を解決するために、本発明に係る表示装置は、平面視で互いに重畳して配置された第1表示パネル及び第2表示パネルを有し、前記第1表示パネルには、複数の画素が第1方向及び第2方向にマトリクス状に配置されており、前記第2表示パネルには、複数の画素が第3方向及び第4方向にマトリクス状に配置されており、前記第1表示パネルに配置された前記複数の画素は、複数の第1画素と複数の第2画素とを含み、前記複数の第1画素及び前記複数の第2画素は、前記第1方向の配列ピッチは互いに等しく、前記第2方向の配列ピッチが互いに異なり、前記第2表示パネルに配置された前記複数の画素は、前記第3方向の配列ピッチが何れも等しく、かつ、前記第4方向の配列ピッチが何れも等しく、前記第2表示パネルに配置された前記複数の画素の前記第4方向の配列ピッチは、前記複数の第1画素の前記第2方向の配列ピッチ、及び、前記複数の第2画素の前記第2方向の配列ピッチのうちの一方より大きく、かつ他方より小さい、ことを特徴とする。
In order to solve the above-described problem, a display device according to the present invention includes a first display panel and a second display panel that are arranged so as to overlap each other in plan view, and the first display panel includes a plurality of display panels. Pixels are arranged in a matrix in the first direction and the second direction, and a plurality of pixels are arranged in a matrix in the third direction and the fourth direction on the second display panel, and the first display The plurality of pixels arranged on the panel includes a plurality of first pixels and a plurality of second pixels, and the plurality of first pixels and the plurality of second pixels have an arrangement pitch in the first direction of each other. The plurality of pixels arranged in the second display panel are equal in the arrangement pitch in the third direction, and the arrangement pitch in the fourth direction is the same. Both are equal, the second display panel The arrangement pitch of the plurality of pixels arranged in the fourth direction is the arrangement pitch of the plurality of first pixels in the second direction and the arrangement pitch of the plurality of second pixels in the second direction. It is larger than one of them and smaller than the other.
本発明に係る表示装置では、前記第2方向は、前記第4方向に対して28度~32度傾斜してもよい。
In the display device according to the present invention, the second direction may be inclined by 28 degrees to 32 degrees with respect to the fourth direction.
上記課題を解決するために、本発明に係る表示装置は、第1方向に延在する一対の辺と第2方向に延在する一対の辺とからなる矩形状の複数の画素が、前記第1方向及び前記第2方向にマトリクス状に配置された表示パネルを有し、前記複数の画素は、第1画素、第2画素及び第3画素を含み、前記第1画素の第1端部と、前記第2画素の第2端部と、前記第3画素の第3端部とを頂点として、前記第1端部と前記第2端部とを結び、前記第1方向に延在する第1辺と、前記第2端部と前記第3端部とを結び、前記第2方向に延在する第2辺と、前記第1端部と前記第3端部とを結び、前記表示パネルを構成する基板の端辺に平行な第3辺と、からなる直角三角形を形成した場合に、前記第1辺と前記第3辺とがなす角度をθとすると、tanθ及びcosθがそれぞれ有理数である、ことを特徴とする。
In order to solve the above problems, a display device according to the present invention includes a plurality of rectangular pixels each including a pair of sides extending in a first direction and a pair of sides extending in a second direction. A display panel arranged in a matrix in one direction and the second direction, wherein the plurality of pixels include a first pixel, a second pixel, and a third pixel; and a first end of the first pixel; The second end of the second pixel and the third end of the third pixel are apexes, the first end and the second end are connected, and the first end extends in the first direction. One display, the second end and the third end are connected, the second side extending in the second direction is connected, the first end and the third end, and the display panel When a right triangle composed of a third side parallel to the edge side of the substrate constituting the substrate is formed, and the angle formed by the first side and the third side is θ, t nθ and cosθ are rational respectively, characterized in that.
本発明に係る表示装置では、前記表示パネルは、複数のデータ線及び複数のゲート線を含み、前記複数のデータ線又は前記複数のゲート線は、前記基板の端辺に対して前記角度θだけ傾斜してもよい。
In the display device according to the present invention, the display panel includes a plurality of data lines and a plurality of gate lines, and the plurality of data lines or the plurality of gate lines are the angle θ with respect to the edge of the substrate. It may be inclined.
本発明に係る表示装置では、前記表示パネルは、前記第1方向に延在する複数のゲート線と、前記第2方向に延在する複数のデータ線とを含み、前記第1辺の長さは前記複数のデータ線の配列ピッチの整数倍であり、前記第2辺の長さは前記複数のゲート線の配列ピッチの整数倍であってもよい。
In the display device according to the present invention, the display panel includes a plurality of gate lines extending in the first direction and a plurality of data lines extending in the second direction, and the length of the first side. May be an integer multiple of the array pitch of the plurality of data lines, and the length of the second side may be an integer multiple of the array pitch of the plurality of gate lines.
また上記課題を解決するために、本発明に係る表示装置は、平面視で互いに重畳して配置された第1表示パネル及び第2表示パネルを有し、前記第1表示パネルには、第1方向に延在する一対の辺と第2方向に延在する一対の辺とからなる矩形状の複数の画素が、前記第1方向及び前記第2方向にマトリクス状に配置されており、前記複数の画素は、第1画素、第2画素及び第3画素を含み、前記第1画素の第1端部と、前記第2画素の第2端部と、前記第3画素の第3端部とを頂点として、前記第1端部と前記第2端部とを結び、前記第1方向に延在する第1辺と、前記第2端部と前記第3端部とを結び、前記第2方向に延在する第2辺と、前記第1端部と前記第3端部とを結ぶ第3辺と、からなる直角三角形を形成した場合に、前記第3辺は、前記第2表示パネルに形成された複数のデータ線又は複数のゲート線に平行であり、前記第1辺と前記第3辺とがなす角度をθとすると、tanθ及びcosθがそれぞれ有理数である、ことを特徴とする。
In order to solve the above problems, a display device according to the present invention includes a first display panel and a second display panel that are arranged so as to overlap each other in a plan view, and the first display panel includes a first display panel and a first display panel. A plurality of rectangular pixels including a pair of sides extending in the direction and a pair of sides extending in the second direction are arranged in a matrix in the first direction and the second direction, and the plurality of pixels The pixel includes a first pixel, a second pixel, and a third pixel, and includes a first end of the first pixel, a second end of the second pixel, and a third end of the third pixel. , The first end and the second end are connected, the first side extending in the first direction, the second end and the third end are connected, and the second When a right triangle composed of a second side extending in the direction and a third side connecting the first end and the third end is formed, the first side The side is parallel to the plurality of data lines or the plurality of gate lines formed on the second display panel, and tan θ and cos θ are rational numbers, where θ is an angle formed by the first side and the third side. It is characterized by being.
また上記課題を解決するために、本発明に係る表示装置は、平面視で互いに重畳する第1表示パネル及び第2表示パネルを有し、前記第1表示パネルには、第1方向に延在する一対の辺と第2方向に延在する一対の辺とからなる矩形状の複数の画素が、前記第1方向及び前記第2方向にマトリクス状に配置されており、前記複数の画素は、第1画素、第2画素及び第3画素を含み、前記第1画素の第1端部と、前記第2画素の第2端部と、前記第3画素の第3端部とを頂点として、前記第1端部と前記第2端部とを結び、前記第1方向に延在する第1辺と、前記第2端部と前記第3端部とを結び、前記第2方向に延在する第2辺と、前記第1端部と前記第3端部とを結び、前記第1表示パネルを構成する基板の端辺に平行な第3辺と、からなる直角三角形を形成した場合に、前記第1辺と前記第3辺とがなす角度をθとすると、tanθ及びcosθがそれぞれ有理数である、ことを特徴とする。
In order to solve the above problems, a display device according to the present invention includes a first display panel and a second display panel that overlap each other in plan view, and the first display panel extends in a first direction. A plurality of rectangular pixels each having a pair of sides and a pair of sides extending in the second direction are arranged in a matrix in the first direction and the second direction. Including a first pixel, a second pixel, and a third pixel, with the first end of the first pixel, the second end of the second pixel, and the third end of the third pixel as vertices, The first end and the second end are connected to each other, the first side extending in the first direction, the second end and the third end are connected to each other, and the second end is extended to the second direction. A second side that connects the first end and the third end, and a third side parallel to the end of the substrate that constitutes the first display panel. That in the case of forming a right triangle, the angle of the first side and said third side forms a theta, a rational number tanθ and cosθ, respectively, be characterized.
本発明に係る表示装置では、前記tanθは、3/4、5/12、8/15、7/24、20/21、12/35、9/40、28/45、11/60、16/63、33/56の何れか1つを満たしてもよい。
In the display device according to the present invention, the tan θ is 3/4, 5/12, 8/15, 7/24, 20/21, 12/35, 9/40, 28/45, 11/60, 16 / Any one of 63 and 33/56 may be satisfied.
本発明に係る表示装置では、前記tanθは、3/4、5/12、8/15、7/24、20/21の何れか1つを満たしてもよい。
In the display device according to the present invention, the tan θ may satisfy any one of 3/4, 5/12, 8/15, 7/24, and 20/21.
本発明に係る表示装置では、前記tanθは、8/15を満たしてもよい。
In the display device according to the present invention, the tan θ may satisfy 8/15.
本発明に係る表示装置では、前記第1表示パネルを構成する基板の端辺は、前記第2表示パネルを構成する基板の端辺に対して傾斜してもよい。
In the display device according to the present invention, the edge of the substrate constituting the first display panel may be inclined with respect to the edge of the substrate constituting the second display panel.
本発明に係る表示装置では、前記第1表示パネルを構成する基板の端辺と、前記第2表示パネルを構成する基板の端辺とがなす角度は、1度以上3度以下でもよい。
In the display device according to the present invention, the angle formed between the edge of the substrate constituting the first display panel and the edge of the substrate constituting the second display panel may be not less than 1 degree and not more than 3 degrees.
本発明に係る表示装置では、平面視で、前記第1表示パネルに形成されたゲート線と前記第2表示パネルに形成されたゲート線とのなす角度が略30度でもよい。
In the display device according to the present invention, the angle formed by the gate line formed on the first display panel and the gate line formed on the second display panel may be approximately 30 degrees in plan view.
本発明に係る表示装置では、前記第2表示パネルには、第3方向に延在する一対の辺と第4方向に延在する一対の辺とからなる矩形状の複数の画素が、前記第3方向及び前記第3方向にマトリクス状に配置されており、前記第2表示パネルの前記複数の画素は、第4画素、第5画素及び第6画素を含み、前記第4画素の第4端部と、前記第5画素の第5端部と、前記第6画素の第6端部とを頂点として、前記第4端部と前記第5端部とを結び、前記第3方向に延在する第4辺と、前記第5端部と前記第6端部とを結び、前記第4方向に延在する第5辺と、前記第4端部と前記第6端部とを結び、前記第2表示パネルを構成する基板の端辺に平行な第6辺と、からなる直角三角形を形成した場合に、前記第4辺と前記第6辺とがなす角度をαとすると、tanα及びcosαがそれぞれ有理数でもよい。
In the display device according to the present invention, the second display panel includes a plurality of rectangular pixels each including a pair of sides extending in the third direction and a pair of sides extending in the fourth direction. The plurality of pixels of the second display panel include a fourth pixel, a fifth pixel, and a sixth pixel, and are arranged in a matrix in three directions and the third direction, and a fourth end of the fourth pixel. And the fifth end of the fifth pixel and the sixth end of the sixth pixel are connected to the fourth end and the fifth end, and extend in the third direction. Connecting the fourth side, the fifth end and the sixth end, connecting the fifth side extending in the fourth direction, the fourth end and the sixth end, When a right triangle composed of the sixth side parallel to the edge of the substrate constituting the second display panel is formed, the angle formed by the fourth side and the sixth side is α Then, tanα and cosα may be the rational numbers, respectively.
本発明に係る表示装置では、前記tanαは、3/4、5/12、8/15、7/24、20/21、12/35、9/40、28/45、11/60、16/63、33/56の何れか1つを満たしてもよい。
In the display device according to the present invention, the tan α is 3/4, 5/12, 8/15, 7/24, 20/21, 12/35, 9/40, 28/45, 11/60, 16 / Any one of 63 and 33/56 may be satisfied.
本発明に係る表示装置では、前記tanθ及び前記tanαはそれぞれ、7/24を満たしてもよい。
In the display device according to the present invention, the tan θ and the tan α may each satisfy 7/24.
本発明に係る表示装置によれば、画素の配列方向に傾斜角度を有する表示装置において、画素の配列方向を傾斜させる際の作業効率を向上させることができる。
According to the display device according to the present invention, in a display device having an inclination angle in the pixel arrangement direction, it is possible to improve work efficiency when the pixel arrangement direction is inclined.
本発明の実施形態について、図面を用いて以下に説明する。以下の実施形態では、液晶表示装置を例に挙げるが、本発明に係る表示装置は、液晶表示装置に限定されるものではなく、例えば有機EL表示装置等であってもよい。
Embodiments of the present invention will be described below with reference to the drawings. In the following embodiments, a liquid crystal display device is taken as an example, but the display device according to the present invention is not limited to a liquid crystal display device, and may be, for example, an organic EL display device.
本実施形態に係る液晶表示装置は、画像を表示する表示パネルと、表示パネルを駆動する駆動回路(ソースドライバ、ゲートドライバ)と、駆動回路を制御するタイミングコントローラと、外部から入力される入力映像信号に対して画像処理を行い、タイミングコントローラに画像データを出力する画像処理部と、表示パネルに背面側から光を照射するバックライトと、を含んでいる。表示パネルの数は限定されず、1枚であってもよいし、複数枚であってもよい。表示パネルが複数の場合は、複数の表示パネルが、観察者側から見て前後方向に互いに重ね合わされて配置されており、それぞれが画像を表示する。以下では、2枚の表示パネルを備える液晶表示装置10を例に挙げて説明する。
The liquid crystal display device according to the present embodiment includes a display panel for displaying an image, a drive circuit (source driver and gate driver) for driving the display panel, a timing controller for controlling the drive circuit, and an input video input from the outside. An image processing unit that performs image processing on the signal and outputs image data to the timing controller, and a backlight that irradiates the display panel with light from the back side. The number of display panels is not limited, and may be one or plural. When there are a plurality of display panels, the plurality of display panels are arranged so as to overlap each other in the front-rear direction when viewed from the observer side, and each displays an image. Hereinafter, the liquid crystal display device 10 including two display panels will be described as an example.
図1は、本実施形態に係る液晶表示装置10の概略構成を模式的に示す平面図である。図1に示すように、液晶表示装置10は、観察者から遠い位置(後側)に配置された第1表示パネル100と、第1表示パネル100より観察者に近い位置(前側)に配置された第2表示パネル200と、第1表示パネル100に設けられた第1ソースドライバ120及び第1ゲートドライバ130と、第1ソースドライバ120及び第1ゲートドライバ130を制御する第1タイミングコントローラ140と、第2表示パネル200に設けられた第2ソースドライバ220及び第2ゲートドライバ230と、第2ソースドライバ220及び第2ゲートドライバ230を制御する第2タイミングコントローラ240と、第1タイミングコントローラ140及び第2タイミングコントローラ240に画像データを出力する画像処理部300と、を含んでいる。画像処理部300は、外部のシステム(図示せず)から送信された入力映像信号Dataを受信し、周知の画像処理を実行した後、第1タイミングコントローラ140に第1画像データDAT1を出力し、第2タイミングコントローラ240に第2画像データDAT2を出力する。また画像処理部300は、第1タイミングコントローラ140及び第2タイミングコントローラ240に同期信号等の制御信号(図1では省略)を出力する。第1画像データDAT1は白黒画像表示用の画像データであり、第2画像データDAT2はカラー画像表示用の画像データである。第1表示パネル100は入力映像信号Dataに応じた白黒画像を第1画像表示領域110に表示し、第2表示パネル200は入力映像信号Dataに応じたカラー画像を第2画像表示領域210に表示する。バックライト(図1では省略)は、第1表示パネル100の背面側に配置されている。
FIG. 1 is a plan view schematically showing a schematic configuration of a liquid crystal display device 10 according to the present embodiment. As shown in FIG. 1, the liquid crystal display device 10 is disposed at a position (front side) closer to the viewer than the first display panel 100 and a first display panel 100 disposed at a position farther from the viewer (rear side). A second display panel 200, a first source driver 120 and a first gate driver 130 provided in the first display panel 100, a first timing controller 140 for controlling the first source driver 120 and the first gate driver 130, and , A second source driver 220 and a second gate driver 230 provided in the second display panel 200, a second timing controller 240 for controlling the second source driver 220 and the second gate driver 230, a first timing controller 140, and An image processing unit 300 that outputs image data to the second timing controller 240; Which comprise. The image processing unit 300 receives an input video signal Data transmitted from an external system (not shown), performs known image processing, and then outputs first image data DAT1 to the first timing controller 140. The second image data DAT2 is output to the second timing controller 240. The image processing unit 300 outputs a control signal (not shown in FIG. 1) such as a synchronization signal to the first timing controller 140 and the second timing controller 240. The first image data DAT1 is image data for displaying a monochrome image, and the second image data DAT2 is image data for displaying a color image. The first display panel 100 displays a black and white image corresponding to the input video signal Data in the first image display area 110, and the second display panel 200 displays a color image corresponding to the input video signal Data in the second image display area 210. To do. The backlight (omitted in FIG. 1) is disposed on the back side of the first display panel 100.
図2及び図3は第1表示パネル100の概略構成を模式的に示す平面図である。図2及び図3に示すように、第1表示パネル100では、複数の画素が、例えば基板の端辺に対して傾斜して配列されている。図2に示す例では、第1ソースドライバ120を構成する2個のソースドライバIC(SIC)が、第1画像表示領域110の一辺(図2では下辺)に沿って配置されており、第1ゲートドライバ130を構成する2個のゲートドライバIC(GIC)が、第1画像表示領域110の一辺(図2では右辺)に沿って配置されている。図2に示す構成では、ソースドライバIC(SIC)が配置される側の辺に対向する辺(図2では上辺)に、ゲート引出線31が配置されている。また、図3に示す例では、第1ソースドライバ120を構成する2個のソースドライバIC(SIC)のそれぞれが、第1画像表示領域110の二辺(図2では上辺及び下辺)のそれぞれに沿って配置されており、第1ゲートドライバ130を構成する2個のゲートドライバIC(GIC)のそれぞれが、第1画像表示領域110の二辺(図2では右辺及び左辺)のそれぞれに沿って配置されている。図3に示す構成では、第1画像表示領域110の二辺(図2では上辺及び下辺)にソース引出線21が配置され、第1画像表示領域110の二辺(図2では右辺及び左辺)にゲート引出線31が配置されている。
2 and 3 are plan views schematically showing a schematic configuration of the first display panel 100. FIG. As shown in FIGS. 2 and 3, in the first display panel 100, a plurality of pixels are arranged so as to be inclined with respect to the edge of the substrate, for example. In the example shown in FIG. 2, two source driver ICs (SIC) constituting the first source driver 120 are arranged along one side (the lower side in FIG. 2) of the first image display area 110. Two gate driver ICs (GIC) constituting the gate driver 130 are arranged along one side (the right side in FIG. 2) of the first image display area 110. In the configuration illustrated in FIG. 2, the gate lead line 31 is disposed on the side (upper side in FIG. 2) that faces the side on which the source driver IC (SIC) is disposed. In the example shown in FIG. 3, each of the two source driver ICs (SICs) constituting the first source driver 120 is connected to each of two sides (upper side and lower side in FIG. 2) of the first image display region 110. The two gate driver ICs (GICs) constituting the first gate driver 130 are arranged along two sides of the first image display area 110 (the right side and the left side in FIG. 2). Has been placed. In the configuration shown in FIG. 3, source leader lines 21 are arranged on two sides (upper side and lower side in FIG. 2) of the first image display region 110, and two sides (right side and left side in FIG. 2) of the first image display region 110. A gate lead-out line 31 is disposed at the end.
図4は第1表示パネル100の概略構成を模式的に示す平面図であり、図5は第2表示パネル200の概略構成を模式的に示す平面図である。図6は、第1表示パネル100及び第2表示パネル200の断面図である。図4では、図2及び図3に示すように、複数の画素が、例えば基板の端辺に対して傾斜して配列された構成を示している。尚、図4及び図5では、説明の便宜上、第1表示パネル100の画素114と、第2表示パネル200の画素214(サブ画素)とを、同じ大きさで描いているが、本実施形態に係る液晶表示装置10は、後述するように(図7参照)、第1表示パネル100の画素114の面積と、第2表示パネル200の画素224(赤色サブ画素と緑色サブ画素と青色サブ画素を含む)の面積とが、互いに等しくなっている。
4 is a plan view schematically showing a schematic configuration of the first display panel 100, and FIG. 5 is a plan view schematically showing a schematic configuration of the second display panel 200. As shown in FIG. FIG. 6 is a cross-sectional view of the first display panel 100 and the second display panel 200. FIG. 4 shows a configuration in which a plurality of pixels are arranged to be inclined with respect to the edge of the substrate, for example, as shown in FIGS. 4 and 5, for convenience of explanation, the pixel 114 of the first display panel 100 and the pixel 214 (sub-pixel) of the second display panel 200 are drawn in the same size, but this embodiment As will be described later (see FIG. 7), the liquid crystal display device 10 according to the present invention includes an area of the pixel 114 of the first display panel 100 and a pixel 224 of the second display panel 200 (the red sub-pixel, the green sub-pixel, and the blue sub-pixel). Are included in each other.
図4及び図6を用いて、第1表示パネル100の構成について説明する。図6に示すように、第1表示パネル100は、バックライト400側に配置された薄膜トランジスタ基板101(以下、TFT基板という。)と、観察者側に配置され、TFT基板101に対向するカラーフィルタ基板102(以下、CF基板という。)と、TFT基板101及びCF基板102の間に配置された液晶層103と、を含んでいる。第1表示パネル100のバックライト400側には偏光板104が配置されており、観察者側には偏光板105が配置されている。
The configuration of the first display panel 100 will be described with reference to FIGS. As shown in FIG. 6, the first display panel 100 includes a thin film transistor substrate 101 (hereinafter referred to as a TFT substrate) disposed on the backlight 400 side, and a color filter disposed on the viewer side and facing the TFT substrate 101. A substrate 102 (hereinafter referred to as a CF substrate) and a liquid crystal layer 103 disposed between the TFT substrate 101 and the CF substrate 102 are included. A polarizing plate 104 is disposed on the backlight 400 side of the first display panel 100, and a polarizing plate 105 is disposed on the viewer side.
TFT基板101には、図4に示すように、第1方向に延在する複数のゲート線112と、第1方向とは異なる第2方向に延在する複数のデータ線111とが形成され、複数のデータ線111と複数のゲート線112とのそれぞれの交差部近傍に薄膜トランジスタ113(以下、TFTという。)が形成されている。第1表示パネル100を平面的に見て、隣り合う2本のデータ線111と隣り合う2本のゲート線112とにより囲まれる領域が1つの画素114として規定され、該画素114がマトリクス状に複数配置されている。複数のデータ線111は、第1方向に等間隔で配置されており、複数のゲート線112は、第2方向に等間隔で配置されている。TFT基板101には、画素114ごとに画素電極115が形成されており、複数の画素114に共通する1つの共通電極(図示せず)が形成されている。TFT113を構成するドレイン電極はデータ線111に電気的に接続され、ソース電極は画素電極115に電気的に接続され、ゲート電極はゲート線112に電気的に接続されている。
As shown in FIG. 4, a plurality of gate lines 112 extending in the first direction and a plurality of data lines 111 extending in a second direction different from the first direction are formed on the TFT substrate 101. Thin film transistors 113 (hereinafter referred to as TFTs) are formed in the vicinity of the intersections of the plurality of data lines 111 and the plurality of gate lines 112. When the first display panel 100 is viewed in plan, a region surrounded by two adjacent data lines 111 and two adjacent gate lines 112 is defined as one pixel 114, and the pixels 114 are arranged in a matrix. Several are arranged. The plurality of data lines 111 are arranged at equal intervals in the first direction, and the plurality of gate lines 112 are arranged at equal intervals in the second direction. On the TFT substrate 101, a pixel electrode 115 is formed for each pixel 114, and one common electrode (not shown) common to the plurality of pixels 114 is formed. The drain electrode constituting the TFT 113 is electrically connected to the data line 111, the source electrode is electrically connected to the pixel electrode 115, and the gate electrode is electrically connected to the gate line 112.
図6に示すように、CF基板102には、各画素114の境界部分に対応する位置に、光の透過を遮断するブラックマトリクス102bが形成されている。ブラックマトリクス102bで囲まれた領域102aには、着色部は形成されておらず、例えばオーバーコート膜が形成されている。
As shown in FIG. 6, on the CF substrate 102, a black matrix 102b that blocks transmission of light is formed at a position corresponding to a boundary portion of each pixel 114. In the region 102a surrounded by the black matrix 102b, no colored portion is formed, and for example, an overcoat film is formed.
上記第1表示パネル100の例では、IPS方式の画素構造を挙げたが、これに限定されない。また、画素114を構成する各部の積層構造は、上記の構成に限定されない。
In the example of the first display panel 100, an IPS pixel structure is described, but the present invention is not limited to this. In addition, the stacked structure of each part included in the pixel 114 is not limited to the above structure.
第1タイミングコントローラ140は、画像処理部300から出力される第1画像データDAT1と第1制御信号CS1(クロック信号、垂直同期信号、水平同期信号等)とに基づいて、第1画像データDA1と、第1ソースドライバ120及び第1ゲートドライバ130の駆動を制御するための各種タイミング信号(データスタートパルスDSP1、データクロックDCK1、ゲートスタートパルスGSP1、ゲートクロックGCK1)とを生成する(図4参照)。第1タイミングコントローラ140は、第1画像データDA1と、データスタートパルスDSP1と、データクロックDCK1とを第1ソースドライバ120に出力し、ゲートスタートパルスGSP1とゲートクロックGCK1とを第1ゲートドライバ130に出力する。
The first timing controller 140, based on the first image data DAT1 output from the image processing unit 300 and the first control signal CS1 (clock signal, vertical synchronization signal, horizontal synchronization signal, etc.), Various timing signals (data start pulse DSP1, data clock DCK1, gate start pulse GSP1, and gate clock GCK1) for controlling driving of the first source driver 120 and the first gate driver 130 are generated (see FIG. 4). . The first timing controller 140 outputs the first image data DA1, the data start pulse DSP1, and the data clock DCK1 to the first source driver 120, and outputs the gate start pulse GSP1 and the gate clock GCK1 to the first gate driver 130. Output.
第1ソースドライバ120は、データスタートパルスDSP1及びデータクロックDCK1に基づいて、第1画像データDA1に応じたデータ信号(データ電圧)をデータ線111に出力する。第1ゲートドライバ130は、ゲートスタートパルスGSP1及びゲートクロックGCK1に基づいて、ゲート信号(ゲート電圧)をゲート線112に出力する。
The first source driver 120 outputs a data signal (data voltage) corresponding to the first image data DA1 to the data line 111 based on the data start pulse DSP1 and the data clock DCK1. The first gate driver 130 outputs a gate signal (gate voltage) to the gate line 112 based on the gate start pulse GSP1 and the gate clock GCK1.
各データ線111には、第1ソースドライバ120からデータ電圧が供給され、各ゲート線112には、第1ゲートドライバ130からゲート電圧が供給される。共通電極には、コモンドライバ(図示せず)から共通電圧Vcomが供給される。ゲート電圧(ゲートオン電圧)がゲート線112に供給されると、ゲート線112に接続されたTFT113がオンし、TFT113に接続されたデータ線111を介して、データ電圧が画素電極115に供給される。画素電極115に供給されたデータ電圧と、共通電極に供給された共通電圧Vcomとの差により電界が生じる。この電界により液晶を駆動してバックライト400の光の透過率を制御することによって画像表示を行う。第1表示パネル100では、白黒画像表示が行われる。
The data voltage is supplied from the first source driver 120 to each data line 111, and the gate voltage is supplied from the first gate driver 130 to each gate line 112. A common voltage Vcom is supplied to the common electrode from a common driver (not shown). When the gate voltage (gate-on voltage) is supplied to the gate line 112, the TFT 113 connected to the gate line 112 is turned on, and the data voltage is supplied to the pixel electrode 115 via the data line 111 connected to the TFT 113. . An electric field is generated by the difference between the data voltage supplied to the pixel electrode 115 and the common voltage Vcom supplied to the common electrode. The liquid crystal is driven by this electric field to control the light transmittance of the backlight 400 to display an image. On the first display panel 100, a monochrome image is displayed.
次に、図5及び図6を用いて、第2表示パネル200の構成について説明する。図6に示すように、第2表示パネル200は、バックライト400側に配置されたTFT基板201と、観察者側に配置され、TFT基板201に対向するCF基板202と、TFT基板201及びCF基板202の間に配置された液晶層203と、を含んでいる。第2表示パネル200のバックライト400側には偏光板204が配置されており、観察者側には偏光板205が配置されている。第1表示パネル100の偏光板105と、第2表示パネル200の偏光板204との間には、接着シート301が配置されている。
Next, the configuration of the second display panel 200 will be described with reference to FIGS. As shown in FIG. 6, the second display panel 200 includes a TFT substrate 201 disposed on the backlight 400 side, a CF substrate 202 disposed on the viewer side and facing the TFT substrate 201, the TFT substrate 201, and the CF substrate And a liquid crystal layer 203 disposed between the substrates 202. A polarizing plate 204 is disposed on the backlight 400 side of the second display panel 200, and a polarizing plate 205 is disposed on the viewer side. An adhesive sheet 301 is disposed between the polarizing plate 105 of the first display panel 100 and the polarizing plate 204 of the second display panel 200.
TFT基板201には、図5に示すように、第3方向に延在する複数のゲート線212と、第3方向とは異なる第4方向に延在する複数のデータ線211とが形成され、複数のデータ線211と複数のゲート線212とのそれぞれの交差部近傍にTFT213が形成されている。第2表示パネル200を平面的に見て、隣り合う2本のデータ線211と隣り合う2本のゲート線212とにより囲まれる領域が1つのサブ画素214として規定され、該サブ画素214がマトリクス状に複数配置されている。複数のデータ線211は、第3方向に等間隔で配置されており、複数のゲート線212は、第4方向に等間隔で配置されている。TFT基板201には、サブ画素214ごとに画素電極215が形成されており、複数のサブ画素214に共通する1つの共通電極(図示せず)が形成されている。TFT213を構成するドレイン電極はデータ線211に電気的に接続され、ソース電極は画素電極215に電気的に接続され、ゲート電極はゲート線212に電気的に接続されている。
On the TFT substrate 201, as shown in FIG. 5, a plurality of gate lines 212 extending in the third direction and a plurality of data lines 211 extending in a fourth direction different from the third direction are formed. TFTs 213 are formed in the vicinity of the intersections of the plurality of data lines 211 and the plurality of gate lines 212. When the second display panel 200 is viewed in plan, a region surrounded by two adjacent data lines 211 and two adjacent gate lines 212 is defined as one subpixel 214, and the subpixel 214 is a matrix. A plurality are arranged in a shape. The plurality of data lines 211 are arranged at equal intervals in the third direction, and the plurality of gate lines 212 are arranged at equal intervals in the fourth direction. On the TFT substrate 201, a pixel electrode 215 is formed for each subpixel 214, and one common electrode (not shown) common to the plurality of subpixels 214 is formed. The drain electrode constituting the TFT 213 is electrically connected to the data line 211, the source electrode is electrically connected to the pixel electrode 215, and the gate electrode is electrically connected to the gate line 212.
図6に示すように、CF基板202には、各サブ画素214に対応して複数の着色部202aが形成されている。各着色部202aは、光の透過を遮断するブラックマトリクス202bで囲まれており、例えば矩形状に形成されている。また、複数の着色部202aは、赤色(R色)の材料で形成され、赤色の光を透過する赤色部と、緑色(G色)の材料で形成され、緑色の光を透過する緑色部と、青色(B色)の材料で形成され、青色の光を透過する青色部と、を含んでいる。赤色部、緑色部、及び青色部は、第3方向にこの順に繰り返し配列され、同一色の着色部が第4方向に配列され、隣り合う着色部202aの境界部分にブラックマトリクス202bが形成されている。図5に示すように、複数のサブ画素214は、赤色部に対応する赤色サブ画素214Rと、緑色部に対応する緑色サブ画素214Gと、青色部に対応する青色サブ画素214Bと、を含んでいる。また、1個の赤色サブ画素214Rと1個の緑色サブ画素214Gと1個の青色サブ画素214Bとが、1個の画素224を構成している。
As shown in FIG. 6, a plurality of colored portions 202 a are formed on the CF substrate 202 corresponding to the sub-pixels 214. Each colored portion 202a is surrounded by a black matrix 202b that blocks light transmission, and is formed in a rectangular shape, for example. The plurality of colored portions 202a are formed of a red (R color) material and transmit a red portion that transmits red light, and a green portion that is formed of a green (G color) material and transmits green light. And a blue portion that is formed of a blue (B color) material and transmits blue light. The red portion, the green portion, and the blue portion are repeatedly arranged in this order in the third direction, the colored portions of the same color are arranged in the fourth direction, and the black matrix 202b is formed at the boundary portion between the adjacent colored portions 202a. Yes. As shown in FIG. 5, the plurality of sub-pixels 214 include a red sub-pixel 214R corresponding to the red portion, a green sub-pixel 214G corresponding to the green portion, and a blue sub-pixel 214B corresponding to the blue portion. Yes. Further, one red sub-pixel 214R, one green sub-pixel 214G, and one blue sub-pixel 214B constitute one pixel 224.
第1表示パネル100の各画素114と、第2表示パネル200の各画素224とは、互いに面積が等しくなっている。例えば、図7に示すように、第1表示パネル100の1個の画素114(図7(b)参照)の面積と、第2表示パネル200の1個の赤色サブ画素214R、1個の緑色サブ画素214G、及び1個の青色サブ画素214Bで構成される1個の画素224(図7(a)参照)の面積とが、互いに等しくなっている。
Each pixel 114 of the first display panel 100 and each pixel 224 of the second display panel 200 have the same area. For example, as shown in FIG. 7, the area of one pixel 114 (see FIG. 7B) of the first display panel 100, one red sub-pixel 214R of the second display panel 200, and one green The areas of one pixel 224 (see FIG. 7A) including the sub-pixel 214G and one blue sub-pixel 214B are equal to each other.
上記第2表示パネル200の例では、IPS方式の画素構造を挙げたが、これに限定されない。また、サブ画素214を構成する各部の積層構造は、上記の構成に限定されない。
In the example of the second display panel 200, an IPS pixel structure is described, but the present invention is not limited to this. In addition, the stacked structure of each part included in the sub-pixel 214 is not limited to the above structure.
第2タイミングコントローラ240は、画像処理部300から出力される第2画像データDAT2と第2制御信号CS2(クロック信号、垂直同期信号、水平同期信号等)とに基づいて、第2画像データDA2と、第2ソースドライバ220及び第2ゲートドライバ230の駆動を制御するための各種タイミング信号(データスタートパルスDSP2、データクロックDCK2、ゲートスタートパルスGSP2、ゲートクロックGCK2)とを生成する(図5参照)。第2タイミングコントローラ240は、第2画像データDA2と、データスタートパルスDSP2と、データクロックDCK2とを第2ソースドライバ220に出力し、ゲートスタートパルスGSP2とゲートクロックGCK2とを第2ゲートドライバ230に出力する。
The second timing controller 240, based on the second image data DAT2 output from the image processing unit 300 and the second control signal CS2 (clock signal, vertical synchronization signal, horizontal synchronization signal, etc.), Various timing signals (data start pulse DSP2, data clock DCK2, gate start pulse GSP2, and gate clock GCK2) for controlling the driving of the second source driver 220 and the second gate driver 230 are generated (see FIG. 5). . The second timing controller 240 outputs the second image data DA2, the data start pulse DSP2, and the data clock DCK2 to the second source driver 220, and outputs the gate start pulse GSP2 and the gate clock GCK2 to the second gate driver 230. Output.
第2ソースドライバ220は、データスタートパルスDSP2及びデータクロックDCK2に基づいて、第2画像データDA2に応じたデータ電圧をデータ線211に出力する。第2ゲートドライバ230は、ゲートスタートパルスGSP2及びゲートクロックGCK2に基づいて、ゲート電圧をゲート線212に出力する。
The second source driver 220 outputs a data voltage corresponding to the second image data DA2 to the data line 211 based on the data start pulse DSP2 and the data clock DCK2. The second gate driver 230 outputs a gate voltage to the gate line 212 based on the gate start pulse GSP2 and the gate clock GCK2.
各データ線211には、第2ソースドライバ220からデータ電圧が供給され、各ゲート線212には、第2ゲートドライバ230からゲート電圧が供給される。共通電極には、コモンドライバから共通電圧Vcomが供給される。ゲート電圧(ゲートオン電圧)がゲート線212に供給されると、ゲート線212に接続されたTFT213がオンし、TFT213に接続されたデータ線211を介して、データ電圧が画素電極215に供給される。画素電極215に供給されたデータ電圧と、共通電極に供給された共通電圧Vcomとの差により電界が生じる。この電界により液晶を駆動してバックライト400の光の透過率を制御することによって画像表示を行う。第2表示パネル200では、赤色サブ画素214R、緑色サブ画素214G、青色サブ画素214Bそれぞれの画素電極215に接続されたデータ線211に、所望のデータ電圧を供給することにより、カラー画像表示が行われる。
The data voltage is supplied from the second source driver 220 to each data line 211, and the gate voltage is supplied from the second gate driver 230 to each gate line 212. A common voltage Vcom is supplied to the common electrode from a common driver. When the gate voltage (gate-on voltage) is supplied to the gate line 212, the TFT 213 connected to the gate line 212 is turned on, and the data voltage is supplied to the pixel electrode 215 via the data line 211 connected to the TFT 213. . An electric field is generated by the difference between the data voltage supplied to the pixel electrode 215 and the common voltage Vcom supplied to the common electrode. The liquid crystal is driven by this electric field to control the light transmittance of the backlight 400 to display an image. In the second display panel 200, a desired data voltage is supplied to the data lines 211 connected to the pixel electrodes 215 of the red sub-pixel 214R, the green sub-pixel 214G, and the blue sub-pixel 214B, thereby performing color image display. Is called.
ここで、複数の表示パネルを重ね合わせて構成された液晶表示装置では、モアレの発生を抑えるために、一方の表示パネルの画素の配列方向を所定角度だけ傾斜させることが望ましい。但し、画素の配列方向に傾斜角度をつける場合、設計上の制約を受ける。例えば、CADにおいて、作図領域全体に表示されるドット又は線による矩形状のパターンであって、データ処理の最小単位である所謂グリッドに合わせて、画素の配列を設計する必要がある。グリッドは、例えば0.05um間隔に設定される。具体的には、画素の配列は、画素の端部(データ線とゲート線との交差部)がグリッドに載るように設計する必要がある。このため、配列方向に傾斜角度を有する画素の配列パターンを設計する場合、作業時間が多くなり作業効率が低下する可能性がある。
Here, in a liquid crystal display device configured by overlapping a plurality of display panels, in order to suppress the occurrence of moire, it is desirable to incline the pixel array direction of one display panel by a predetermined angle. However, when the inclination angle is set in the pixel arrangement direction, the design is restricted. For example, in CAD, it is necessary to design a pixel arrangement in accordance with a so-called grid which is a rectangular pattern of dots or lines displayed in the entire drawing area and is the minimum unit of data processing. The grid is set at an interval of 0.05 μm, for example. Specifically, the pixel arrangement needs to be designed so that the end of the pixel (intersection of the data line and the gate line) is placed on the grid. For this reason, when designing an array pattern of pixels having an inclination angle in the array direction, there is a possibility that the work time increases and the work efficiency decreases.
この点、本実施形態に係る液晶表示装置10は、画素の配列方向を傾斜させる際の作業効率を向上させることができる特徴的構成を有している。以下では、液晶表示装置10における上記特徴的構成について説明する。図8は、液晶表示装置10における上記特徴的構成を説明するための平面図である。液晶表示装置10では、第1表示パネル100及び第2表示パネル200の少なくとも何れか一方において、画素の配列方向がX軸に対して角度θだけ傾斜している。図8では、第1表示パネル100において、画素114の配列方向(第1方向)がX軸に対して角度θだけ傾斜している構成例を示している。尚、X軸は水平方向の軸を表し、Y軸は垂直(鉛直)方向の軸を表すものとする。
In this regard, the liquid crystal display device 10 according to the present embodiment has a characteristic configuration that can improve the working efficiency when tilting the pixel arrangement direction. Hereinafter, the characteristic configuration of the liquid crystal display device 10 will be described. FIG. 8 is a plan view for explaining the characteristic configuration of the liquid crystal display device 10. In the liquid crystal display device 10, in at least one of the first display panel 100 and the second display panel 200, the pixel arrangement direction is inclined by an angle θ with respect to the X axis. FIG. 8 shows a configuration example in which the arrangement direction (first direction) of the pixels 114 is inclined by an angle θ with respect to the X axis in the first display panel 100. The X axis represents a horizontal axis, and the Y axis represents a vertical (vertical) axis.
図8に示すように、第1表示パネル100では、任意の3つの画素、例えば第1画素114p、第2画素114q及び第3画素114rに着目した場合に、第1画素114pの第1端部P1と、第2画素114qの第2端部P2と、第3画素114rの第3端部P3とを頂点として、第1端部P1と第2端部P2とを結び、第1方向に延在する第1辺14aと、第2端部P2と第3端部P3とを結び、第2方向に延在する第2辺14bと、第1端部P1と第3端部P3とを結び、第1表示パネル100を構成する基板(TFT基板101)の端辺101aに平行な第3辺14cと、からなる直角三角形を形成した場合に、第1辺14aと第3辺14cとがなす角度をθとすると、tanθ及びcosθがそれぞれ有理数となっている。ここでは、TFT基板101の端辺101aは、X軸方向(水平方向)に延在している。
As shown in FIG. 8, in the first display panel 100, when attention is paid to arbitrary three pixels, for example, the first pixel 114p, the second pixel 114q, and the third pixel 114r, the first end portion of the first pixel 114p. P1, the second end P2 of the second pixel 114q, and the third end P3 of the third pixel 114r are apexes, and the first end P1 and the second end P2 are connected to extend in the first direction. The first side 14a, the second end P2 and the third end P3 are connected, and the second side 14b extending in the second direction is connected to the first end P1 and the third end P3. When a right triangle composed of the third side 14c parallel to the end side 101a of the substrate (TFT substrate 101) constituting the first display panel 100 is formed, the first side 14a and the third side 14c are formed. If the angle is θ, tan θ and cos θ are rational numbers, respectively. Here, the end side 101a of the TFT substrate 101 extends in the X-axis direction (horizontal direction).
より具体的には、第1辺14aの長さをM、第2辺14bの長さをN、第3辺14cの長さをLとしたときに、それぞれの比(L:M:N)が、図9に示す関係を有している。すなわち、上記直角三角形において、tanθが、3/4、5/12、8/15、7/24、20/21、12/35、9/40、28/45、11/60、16/63、33/56の何れか1つを満たしている。またcosθが、4/5、12/13、15/17、24/25、21/29、35/37、40/41、45/53、60/61、63/65、56/65の何れか1つを満たしている。また、長さL、長さM及び長さNは何れも有理数であり、長さLはグリッド間隔(ここでは0.05um)の整数倍となっている。尚、第1辺14aの長さMは複数のデータ線111の配列ピッチの整数倍であり、第2辺14bの長さNは複数のゲート線112の配列ピッチの整数倍である。
More specifically, when the length of the first side 14a is M, the length of the second side 14b is N, and the length of the third side 14c is L, each ratio (L: M: N) Has the relationship shown in FIG. That is, in the right triangle, tan θ is 3/4, 5/12, 8/15, 7/24, 20/21, 12/35, 9/40, 28/45, 11/60, 16/63, Any one of 33/56 is satisfied. Also, cos θ is any of 4/5, 12/13, 15/17, 24/25, 21/29, 35/37, 40/41, 45/53, 60/61, 63/65, and 56/65. Satisfies one. The length L, the length M, and the length N are all rational numbers, and the length L is an integral multiple of the grid interval (here 0.05 um). The length M of the first side 14a is an integer multiple of the arrangement pitch of the plurality of data lines 111, and the length N of the second side 14b is an integer multiple of the arrangement pitch of the plurality of gate lines 112.
上記条件を満たす画素114の配列では、端辺101aの延在方向(X軸方向)に対する傾斜角度が約10度から約44度の範囲に設定される。また画素114の配列を設計する際、第1端部P1と第2端部P2と第3端部P3とは互いに大きく離れていない方が作業効率は高くなる。このため、図9に示す条件のうち、tanθが、3/4、5/12、8/15、7/24、20/21の何れか1つを満たし、cosθが、4/5、12/13、15/17、24/25、21/29の何れか1つを満たしていることが好ましい。
In the arrangement of the pixels 114 satisfying the above conditions, the inclination angle with respect to the extending direction (X-axis direction) of the end side 101a is set in the range of about 10 degrees to about 44 degrees. Further, when designing the arrangement of the pixels 114, the working efficiency is higher when the first end P1, the second end P2, and the third end P3 are not far apart from each other. Therefore, among the conditions shown in FIG. 9, tan θ satisfies any one of 3/4, 5/12, 8/15, 7/24, and 20/21, and cos θ is 4/5, 12 / It is preferable to satisfy any one of 13, 15/17, 24/25, and 21/29.
上記特徴的構成によれば、簡易な方法により画素114の端部をグリッドに載せることができるため、画素114の配列方向を傾斜させる際の作業効率を向上させることができる。
According to the above characteristic configuration, since the end of the pixel 114 can be placed on the grid by a simple method, it is possible to improve the working efficiency when the arrangement direction of the pixel 114 is inclined.
上記構成では、第1表示パネル100の画素114が、TFT基板101の端辺101a(X軸方向)に対して角度θだけ傾斜している。また複数のゲート線112は、TFT基板101の端辺101a(X軸方向)に対して角度θだけ傾斜している。本実施形態に係る液晶表示装置10は上記構成に限定されない。例えば、図10に示すように第2表示パネル200において、ゲート線212の延在方向(第3方向)がX軸方向(水平方向)と一致する場合、すなわち第3辺14c(図8参照)が第2表示パネル200のゲート線212と平行である場合、第1表示パネル100の画素114は、第2表示パネル200のゲート線212(X軸方向)に対して角度θだけ傾斜していてもよい。この場合も角度θは、tanθ及びcosθが上記条件(図9参照)を満たしている。
In the above configuration, the pixels 114 of the first display panel 100 are inclined by the angle θ with respect to the end side 101a (X-axis direction) of the TFT substrate 101. The plurality of gate lines 112 are inclined by an angle θ with respect to the end side 101a (X-axis direction) of the TFT substrate 101. The liquid crystal display device 10 according to the present embodiment is not limited to the above configuration. For example, as shown in FIG. 10, in the second display panel 200, the extending direction (third direction) of the gate line 212 coincides with the X-axis direction (horizontal direction), that is, the third side 14c (see FIG. 8). Is parallel to the gate line 212 of the second display panel 200, the pixel 114 of the first display panel 100 is inclined by an angle θ with respect to the gate line 212 (X-axis direction) of the second display panel 200. Also good. Also in this case, as for the angle θ, tan θ and cos θ satisfy the above condition (see FIG. 9).
ここで、モアレの発生を抑える効果を高めるためには、第1表示パネル100における画素114の傾斜角度θが約30度(例えば28度~32度)であることが好ましい。このため、図8に示す直角三角形において、例えば傾斜角度θが28.07度となる、tanθが8/15、cosθが15/17を満たしていることが好ましい。また、モアレの発生は、第1表示パネル100の画素114の配列方向と、第2表示パネルの画素224の配列方向との相対的な角度差に影響する。この相対的な角度差は、例えば、第1表示パネル100の画素114の配列方向(例えば第1方向)と、第2表示パネル200の画素224の配列方向(例えば第3方向)とのなす角度や、第1表示パネル100のゲート線112の延在方向(例えば第1方向)と、第2表示パネル200のゲート線212の延在方向(例えば第3方向)とのなす角度をいう。
Here, in order to enhance the effect of suppressing the occurrence of moiré, the inclination angle θ of the pixel 114 in the first display panel 100 is preferably about 30 degrees (for example, 28 degrees to 32 degrees). Therefore, in the right triangle shown in FIG. 8, it is preferable that, for example, the inclination angle θ is 28.07 degrees, tan θ is 8/15, and cos θ is 15/17. Also, the occurrence of moire affects the relative angular difference between the arrangement direction of the pixels 114 of the first display panel 100 and the arrangement direction of the pixels 224 of the second display panel. The relative angle difference is, for example, an angle formed by the arrangement direction (for example, the first direction) of the pixels 114 of the first display panel 100 and the arrangement direction (for example, the third direction) of the pixels 224 of the second display panel 200. In addition, it refers to an angle formed by the extending direction (for example, the first direction) of the gate line 112 of the first display panel 100 and the extending direction (for example, the third direction) of the gate line 212 of the second display panel 200.
そこで、第1表示パネル100の上記構成に加えて、さらに上記相対的な角度差が30度に近づくような構成を備えてもよい。例えば、図11に示すように、上記相対的な角度差θ1が30度に近づくように、画素114の配列がtanθ=8/15及びcosθ=15/17に設計された第1表示パネル100(図8参照)と、画素224が第3方向及び第4方向に配列された第2表示パネル200(図10参照)とにおいて、第1表示パネル100のTFT基板101の端辺101aと、第2表示パネルのTFT基板201の端辺201aとがなす角度θ2が、1度以上3度以下となるように、第1表示パネル100及び第2表示パネル200の少なくとも何れか一方を回転させてもよい。例えば、上記第1表示パネル100を1度左回転させ、上記第2表示パネル200を1度右回転させることにより、角度θ2を2度に設定してもよい。これにより、上記相対的な角度差θ1は、30.07度(=28.07度+2度)となる。
Therefore, in addition to the configuration of the first display panel 100, a configuration in which the relative angle difference approaches 30 degrees may be provided. For example, as shown in FIG. 11, the first display panel 100 (in which the arrangement of the pixels 114 is designed to be tan θ = 8/15 and cos θ = 15/17 so that the relative angle difference θ1 approaches 30 degrees. 8) and the second display panel 200 (see FIG. 10) in which the pixels 224 are arranged in the third direction and the fourth direction, the edge 101a of the TFT substrate 101 of the first display panel 100, the second side At least one of the first display panel 100 and the second display panel 200 may be rotated so that the angle θ2 formed by the edge 201a of the TFT substrate 201 of the display panel is 1 degree or more and 3 degrees or less. . For example, the angle θ2 may be set to 2 degrees by rotating the first display panel 100 left one degree and rotating the second display panel 200 right one degree. Thus, the relative angle difference θ1 is 30.07 degrees (= 28.07 degrees + 2 degrees).
また、図10に示す構成では、第2表示パネル200の画素224は水平方向(X軸方向)及び垂直方向(Y軸方向)に配列されているが、第1表示パネル100の画素114と同様に、傾斜角度を有して配列されていてもよい。この場合、第1表示パネル100の画素114と第2表示パネルの画素224とは、互いに異なる方向に回転した状態となるように傾斜角度を設定する。例えば、第1表示パネル100の画素114が図8に示すように左回転した状態となるように傾斜角度を設定した場合、第2表示パネル200の画素224は右回転した状態となるように傾斜角度を設定する。この場合、上記相対的な角度差θ1が30度に近づくように、第1表示パネル100及び第2表示パネル200それぞれにおいて、tanθが何れも7/24を満たすように設定してもよい。これにより、上記相対的な角度差θ1は、32.53度(=16.26度+16.26度)となる。
In the configuration shown in FIG. 10, the pixels 224 of the second display panel 200 are arranged in the horizontal direction (X-axis direction) and the vertical direction (Y-axis direction), but are the same as the pixels 114 of the first display panel 100. Further, they may be arranged with an inclination angle. In this case, the tilt angle is set so that the pixel 114 of the first display panel 100 and the pixel 224 of the second display panel are rotated in different directions. For example, when the tilt angle is set so that the pixel 114 of the first display panel 100 is rotated left as shown in FIG. 8, the pixel 224 of the second display panel 200 is tilted so as to be rotated right. Set the angle. In this case, in each of the first display panel 100 and the second display panel 200, tan θ may be set to satisfy 7/24 so that the relative angle difference θ1 approaches 30 degrees. Accordingly, the relative angle difference θ1 is 32.53 degrees (= 16.26 degrees + 16.26 degrees).
ところで、第1表示パネル100に所定数の画素114を配置する場合や、第2表示パネル200の画素224の配列パターン(水平垂直配列)を利用して第1表示パネル100の画素114の傾斜配列パターンを設計する場合には、画素の配列ピッチの調整を行うことが好ましい。以下では、画素の配列ピッチを調整することにより、配列方向に傾斜角度を有する画素の配列パターンを設計する構成について説明する。ここでは、第1表示パネル100の画素114の傾斜角度θを28.07度(tanθ=8/15、cosθ=15/17)に設定する場合を例に挙げる。また、第2表示パネル200の複数の画素224(図10参照)を、第3方向及び第4方向それぞれに170.4umピッチで配列したと仮定する。また、グリッドの間隔は0.05umとする。尚、ここでは、第3方向はX軸方向(水平方向)に一致し、第4方向はY軸方向(垂直方向)に一致するものとする。
By the way, when the predetermined number of pixels 114 are arranged on the first display panel 100, or the arrangement pattern (horizontal and vertical arrangement) of the pixels 224 of the second display panel 200 is used, the pixels 114 of the first display panel 100 are inclined. When designing a pattern, it is preferable to adjust the arrangement pitch of the pixels. Hereinafter, a configuration for designing an arrangement pattern of pixels having an inclination angle in the arrangement direction by adjusting the arrangement pitch of the pixels will be described. Here, a case where the inclination angle θ of the pixel 114 of the first display panel 100 is set to 28.07 degrees (tan θ = 8/15, cos θ = 15/17) will be described as an example. Further, it is assumed that the plurality of pixels 224 (see FIG. 10) of the second display panel 200 are arranged at a pitch of 170.4 μm in each of the third direction and the fourth direction. Further, the grid interval is set to 0.05 μm. Here, it is assumed that the third direction matches the X-axis direction (horizontal direction) and the fourth direction matches the Y-axis direction (vertical direction).
第1表示パネル100の画素114の配列パターンの設計において、X軸方向(水平方向)及びY軸方向(垂直方向)に画素を配列した配列パターンを28.07度回転させた場合、回転後の画素のXY座標は、図12に示す変換式(1)により表される。回転後の画素の端部がグリッドに載るためには、画素のX軸方向及びY軸方向の配列ピッチが、0.85um(=17×0.05um)の整数倍であることが必要となる。そこで、第1表示パネル100用の複数の画素のX軸方向及びY軸方向の配列ピッチを、0.85umの整数倍であって、かつ第2表示パネル200の画素224の配列ピッチ(170.4um)の近似値に設定する。また配列ピッチが異なる複数の画素(画素グループ)を組み合わせて配列する。
In designing the arrangement pattern of the pixels 114 of the first display panel 100, when the arrangement pattern in which the pixels are arranged in the X-axis direction (horizontal direction) and the Y-axis direction (vertical direction) is rotated 28.07 degrees, The XY coordinates of the pixel are expressed by a conversion formula (1) shown in FIG. In order for the end portion of the pixel after rotation to be placed on the grid, it is necessary that the arrangement pitch of the pixels in the X-axis direction and the Y-axis direction is an integer multiple of 0.85 um (= 17 × 0.05 um). . Therefore, the arrangement pitch of the plurality of pixels for the first display panel 100 in the X-axis direction and the Y-axis direction is an integral multiple of 0.85 μm, and the arrangement pitch of the pixels 224 of the second display panel 200 (170. 4 um). A plurality of pixels (pixel groups) having different arrangement pitches are arranged in combination.
図13は、回転前の画素114の配列パターンの一例を示す平面図である。図13に示す例では、第1画素グループ114aを構成する複数の画素114(「X軸方向の画素数」×「Y軸方向の画素数」で表した場合、9×9画素)は、X軸方向及びY軸方向に170.0umピッチで配列されており、第2画素グループ114bを構成する複数の画素114(9×8画素)は、X軸方向に170.0umピッチで配列され、Y軸方向に170.85umピッチで配列されており、第3画素グループ114cを構成する複数の画素114(8×9画素)は、X軸方向に170.85umピッチで配列され、Y軸方向に170.0umピッチで配列されており、第4画素グループ114dを構成する複数の画素114(8×8画素)は、X軸方向に170.85umピッチで配列され、Y軸方向に170.85umピッチで配列されている。図14は、各画素グループの境界部分の複数の画素114の配列ピッチを示している。
FIG. 13 is a plan view showing an example of the arrangement pattern of the pixels 114 before rotation. In the example shown in FIG. 13, a plurality of pixels 114 (9 × 9 pixels when represented by “the number of pixels in the X-axis direction” × “the number of pixels in the Y-axis direction”) constituting the first pixel group 114a are X A plurality of pixels 114 (9 × 8 pixels) constituting the second pixel group 114b are arranged at a pitch of 170.0 μm in the X-axis direction, and are arranged at a pitch of 170.0 μm in the axial direction and the Y-axis direction. A plurality of pixels 114 (8 × 9 pixels) constituting the third pixel group 114c are arranged at a pitch of 170.85 um in the X-axis direction and 170 pixels in the Y-axis direction. A plurality of pixels 114 (8 × 8 pixels) constituting the fourth pixel group 114d are arranged at a pitch of 170.85 μm in the X-axis direction and at a pitch of 170.85 μm in the Y-axis direction. It is arranged. FIG. 14 shows the arrangement pitch of the plurality of pixels 114 at the boundary portion of each pixel group.
このように、X軸方向に隣り合って配置される2つの画素グループ(例えば、第1画素グループ114a及び第3画素グループ114c)では、複数の画素114のX軸方向の配列ピッチが互いに異なり、Y軸方向の配列ピッチが互いに等しい。またY軸方向に隣り合って配置される2つの画素グループ(例えば、第1画素グループ114a及び第2画素グループ114b)では、複数の画素114のY軸方向の配列ピッチが互いに異なり、X軸方向の配列ピッチが互いに等しい。
Thus, in two pixel groups (for example, the first pixel group 114a and the third pixel group 114c) that are arranged adjacent to each other in the X-axis direction, the arrangement pitch in the X-axis direction of the plurality of pixels 114 is different from each other. The arrangement pitch in the Y-axis direction is equal to each other. Further, in two pixel groups (for example, the first pixel group 114a and the second pixel group 114b) arranged adjacent to each other in the Y-axis direction, the arrangement pitch of the plurality of pixels 114 in the Y-axis direction is different from each other, and the X-axis direction Are equal to each other.
また第2表示パネル200(図10参照)では、複数の画素224の第3方向(X軸方向)の配列ピッチは何れも等しく、かつ、第4方向(Y軸方向)の配列ピッチは何れも等しい。例えば、複数の画素224は、第3方向及び第4方向に170.4umピッチで配列されている。このように、第2表示パネル200に配置された複数の画素224のX軸方向の配列ピッチ(170.4um)は、第1表示パネル100用の第1画素グループ114aを構成する複数の画素114のX軸方向の配列ピッチ(170.0um)より大きく、かつ、第3画素グループ114cを構成する複数の画素114のX軸方向の配列ピッチ(170.85um)より小さい。同様に、第2表示パネル200に配置された複数の画素224のY軸方向の配列ピッチ(170.4um)は、第1表示パネル100用の第1画素グループ114aを構成する複数の画素114のY軸方向の配列ピッチ(170.0um)より大きく、かつ、第2画素グループ114bを構成する複数の画素114のY軸方向の配列ピッチ(170.85um)より小さい。
In the second display panel 200 (see FIG. 10), the arrangement pitches of the plurality of pixels 224 in the third direction (X-axis direction) are all the same, and the arrangement pitches in the fourth direction (Y-axis direction) are all. equal. For example, the plurality of pixels 224 are arranged at a pitch of 170.4 μm in the third direction and the fourth direction. As described above, the arrangement pitch (170.4 μm) in the X-axis direction of the plurality of pixels 224 arranged on the second display panel 200 is the plurality of pixels 114 constituting the first pixel group 114a for the first display panel 100. Is larger than the arrangement pitch in the X-axis direction (170.0 μm) and smaller than the arrangement pitch in the X-axis direction of the plurality of pixels 114 constituting the third pixel group 114 c (170.85 μm). Similarly, the arrangement pitch (170.4 μm) in the Y-axis direction of the plurality of pixels 224 arranged on the second display panel 200 is the number of the plurality of pixels 114 constituting the first pixel group 114a for the first display panel 100. It is larger than the arrangement pitch (170.0 um) in the Y-axis direction and smaller than the arrangement pitch (170.85 um) in the Y-axis direction of the plurality of pixels 114 constituting the second pixel group 114b.
また第1表示パネル100用の画素114の配列パターンでは、第1画素グループ114a、第2画素グループ114b、第3画素グループ114c、及び第4画素グループ114dから成る17×17画素ユニットがX軸方向及びY軸方向に配列されている。すなわち、第1画素グループ114a及び第3画素グループ114cがX軸方向に交互に配列されており、第2画素グループ114b及び第4画素グループ114dがX軸方向に交互に配列されており、第1画素グループ114a及び第2画素グループ114bがY軸方向に交互に配列されており、第3画素グループ114c及び第4画素グループ114dがY軸方向に交互に配列されている。
In the arrangement pattern of the pixels 114 for the first display panel 100, a 17 × 17 pixel unit including the first pixel group 114a, the second pixel group 114b, the third pixel group 114c, and the fourth pixel group 114d is in the X-axis direction. And arranged in the Y-axis direction. That is, the first pixel group 114a and the third pixel group 114c are alternately arranged in the X-axis direction, and the second pixel group 114b and the fourth pixel group 114d are alternately arranged in the X-axis direction. Pixel groups 114a and second pixel groups 114b are alternately arranged in the Y-axis direction, and third pixel groups 114c and fourth pixel groups 114d are alternately arranged in the Y-axis direction.
また各画素グループに含まれる画素114の数は、互いに異なっている。例えば、第1画素グループ114aには81個の画素114が含まれ、第2画素グループ114bには72個の画素114が含まれている。尚、図13の第2画素グループ114b及び第3画素グループ114cに示すように、画素数が同じ画素グループが含まれていてもよい。
Also, the number of pixels 114 included in each pixel group is different from each other. For example, the first pixel group 114a includes 81 pixels 114, and the second pixel group 114b includes 72 pixels 114. Note that pixel groups having the same number of pixels may be included as shown in the second pixel group 114b and the third pixel group 114c in FIG.
また各画素グループの画素数は上記の例に限定されず、例えば図15に示すように、第1画素グループ114aが13×13画素で構成され、第2画素グループ114bが13×4画素で構成され、第3画素グループ114cが4×13画素で構成され、第4画素グループ114dが4×4画素で構成されてもよい。
Further, the number of pixels in each pixel group is not limited to the above example. For example, as shown in FIG. 15, the first pixel group 114a is composed of 13 × 13 pixels, and the second pixel group 114b is composed of 13 × 4 pixels. The third pixel group 114c may be configured with 4 × 13 pixels, and the fourth pixel group 114d may be configured with 4 × 4 pixels.
図16は、第1画素グループ114a、第2画素グループ114b、第3画素グループ114c、及び第4画素グループ114dから成る画素ユニット(図13参照)を28.07度回転させた状態を示している。図16に示す状態では、直角三角形において、tanθが8/15、cosθが15/17を満たし、長さL、長さM及び長さNが何れも有理数であり、長さLがグリッド間隔(ここでは0.05um)の整数倍となっている。
FIG. 16 shows a state in which a pixel unit (see FIG. 13) including the first pixel group 114a, the second pixel group 114b, the third pixel group 114c, and the fourth pixel group 114d is rotated by 28.07 degrees. . In the state shown in FIG. 16, in the right triangle, tan θ satisfies 8/15, cos θ satisfies 15/17, length L, length M, and length N are all rational numbers, and length L is the grid interval ( Here, it is an integral multiple of 0.05 um).
上記構成によれば、簡易な方法により画素114の端部をグリッドに載せることができるため、画素114の配列方向を傾斜させる際の作業効率を向上させることができる。また、水平方向(X軸方向)及び垂直方向(Y軸方向)に配列した複数の画素を利用して、画素の配列方向に傾斜角度を有する第1表示パネル100を容易に作製することができる。
According to the above configuration, since the end of the pixel 114 can be placed on the grid by a simple method, it is possible to improve work efficiency when the arrangement direction of the pixel 114 is inclined. In addition, by using a plurality of pixels arranged in the horizontal direction (X-axis direction) and the vertical direction (Y-axis direction), the first display panel 100 having an inclination angle in the pixel arrangement direction can be easily manufactured. .
以上の各構成では、第1表示パネル100において、ゲート線112が第1方向に延在し、データ線111が第2方向に延在し、第2表示パネル200において、ゲート線212が第3方向に延在し、データ線211が第4方向に延在しているが、これに限定されず、第1表示パネル100において、ゲート線112が第2方向に延在し、データ線111が第1方向に延在し、第2表示パネル200において、ゲート線212が第4方向に延在し、データ線211が第3方向に延在してもよい。
In each configuration described above, in the first display panel 100, the gate line 112 extends in the first direction, the data line 111 extends in the second direction, and in the second display panel 200, the gate line 212 is the third line. In the first display panel 100, the gate line 112 extends in the second direction, and the data line 111 extends in the second direction. In the second display panel 200, the gate line 212 may extend in the fourth direction, and the data line 211 may extend in the third direction.
本実施形態に係る液晶表示装置10は上記構成に限定されない。例えば、第1表示パネル100及び第2表示パネル200のそれぞれの画素の配置の関係は、図7に示す構成に限定されず、例えば図17に示す構成でもよい。図17に示す構成では、第1表示パネル100の画素114の面積と、第2表示パネル200のサブ画素214の面積とが、互いに等しくなっている。
The liquid crystal display device 10 according to the present embodiment is not limited to the above configuration. For example, the relationship of the arrangement of the pixels of the first display panel 100 and the second display panel 200 is not limited to the configuration illustrated in FIG. 7, and may be the configuration illustrated in FIG. 17, for example. In the configuration shown in FIG. 17, the area of the pixel 114 of the first display panel 100 and the area of the sub-pixel 214 of the second display panel 200 are equal to each other.
また、本実施形態に係る液晶表示装置10は、第1表示パネル100及び第2表示パネル200の両方がカラー画像を表示し、何れか一方が画素の配列方向に傾斜角度を有する構成であってもよい。この構成では、第1表示パネル100の偏光板105と、第2表示パネル200の偏光板204とが、省略されてもよい。また、第1表示パネル100と第2表示パネル200との間に間隙が形成されてもよい。上記構成によれば、3次元(3D)画像表示装置として利用することができる。
In addition, the liquid crystal display device 10 according to the present embodiment has a configuration in which both the first display panel 100 and the second display panel 200 display color images, and one of them has an inclination angle in the pixel arrangement direction. Also good. In this configuration, the polarizing plate 105 of the first display panel 100 and the polarizing plate 204 of the second display panel 200 may be omitted. In addition, a gap may be formed between the first display panel 100 and the second display panel 200. According to the said structure, it can utilize as a three-dimensional (3D) image display apparatus.
また、本実施形態に係る液晶表示装置10は、上述した方法により画素の配列方向に傾斜角度を有する1枚の表示パネルで構成されてもよい。この場合、上記表示パネルは、カラー画像を表示する構成を有してもよいし、白黒画像を表示する構成を有してもよい。
Further, the liquid crystal display device 10 according to the present embodiment may be configured by a single display panel having an inclination angle in the pixel arrangement direction by the method described above. In this case, the display panel may have a configuration for displaying a color image or a configuration for displaying a monochrome image.
また、本実施形態に係る液晶表示装置10は、モアレの発生を抑える効果を高めるために、第1表示パネル100の偏光板105(図6参照)と、第2表示パネル200の偏光板204(図6参照)との間に、拡散シートが配置されてもよい。
In addition, the liquid crystal display device 10 according to the present embodiment has the polarizing plate 105 (see FIG. 6) of the first display panel 100 and the polarizing plate 204 (see FIG. 6) of the second display panel 200 in order to enhance the effect of suppressing the occurrence of moire. (See FIG. 6), a diffusion sheet may be disposed.
以上、本発明の実施形態について説明したが、本発明は上記各実施形態に限定されるものではなく、本発明の趣旨を逸脱しない範囲内で上記各実施形態から当業者が適宜変更した形態も本発明の技術的範囲に含まれることは言うまでもない。
As mentioned above, although embodiment of this invention was described, this invention is not limited to said each embodiment, The form suitably changed by those skilled in the art from said each embodiment within the range which does not deviate from the meaning of this invention. Needless to say, it is included in the technical scope of the present invention.
Claims (26)
- 複数の画素がマトリクス状に配置された表示パネルを有し、
前記複数の画素は、複数の第1画素と、前記複数の第1画素の配列ピッチとは異なるピッチで配列された複数の第2画素とを含み、
前記複数の第1画素の数と、前記複数の第2画素の数とは、互いに異なる、
ことを特徴とする表示装置。 A display panel having a plurality of pixels arranged in a matrix;
The plurality of pixels include a plurality of first pixels and a plurality of second pixels arranged at a pitch different from the arrangement pitch of the plurality of first pixels,
The number of the plurality of first pixels and the number of the plurality of second pixels are different from each other.
A display device characterized by that. - 前記複数の画素は、第1方向及び第2方向にマトリクス状に配置されており、
前記複数の第1画素及び前記複数の第2画素は、前記第1方向の配列ピッチは互いに等しく、前記第2方向の配列ピッチが互いに異なる、
ことを特徴とする請求項1に記載の表示装置。 The plurality of pixels are arranged in a matrix in the first direction and the second direction,
The plurality of first pixels and the plurality of second pixels have the same arrangement pitch in the first direction and the different arrangement pitch in the second direction.
The display device according to claim 1. - 隣り合って配列された複数の前記第1画素から成る第1画素グループと、隣り合って配列された複数の前記第2画素から成る第2画素グループとが、交互に配列されている、
ことを特徴とする請求項1に記載の表示装置。 First pixel groups composed of a plurality of the first pixels arranged adjacent to each other and second pixel groups composed of the plurality of the second pixels arranged adjacent to each other are alternately arranged.
The display device according to claim 1. - 前記第1画素グループに含まれる複数の前記第1画素の数と、前記第2画素グループに含まれる複数の前記第2画素の数とが、互いに異なる、
ことを特徴とする請求項3に記載の表示装置。 A number of the plurality of first pixels included in the first pixel group is different from a number of the plurality of second pixels included in the second pixel group;
The display device according to claim 3. - 前記複数の画素は、さらに、複数の第3画素と複数の第4画素とを含み、
前記複数の第1画素及び前記複数の第3画素は、前記第2方向の配列ピッチは互いに等しく、前記第1方向の配列ピッチが互いに異なり、
前記複数の第2画素及び前記複数の第4画素は、前記第2方向の配列ピッチは互いに等しく、前記第1方向の配列ピッチが互いに異なり、
前記複数の第3画素及び前記複数の第4画素は、前記第1方向の配列ピッチは互いに等しく、前記第2方向の配列ピッチが互いに異なる、
ことを特徴とする請求項2に記載の表示装置。 The plurality of pixels further includes a plurality of third pixels and a plurality of fourth pixels,
The plurality of first pixels and the plurality of third pixels have the same arrangement pitch in the second direction, the arrangement pitch in the first direction is different from each other,
The plurality of second pixels and the plurality of fourth pixels have the same arrangement pitch in the second direction, the arrangement pitch in the first direction is different from each other,
The plurality of third pixels and the plurality of fourth pixels have the same arrangement pitch in the first direction, and the arrangement pitch in the second direction is different from each other.
The display device according to claim 2. - 前記複数の第2画素の数と、前記複数の第3画素の数とが、互いに異なり、
前記複数の第3画素の数と、前記複数の第4画素の数とが、互いに異なる、
ことを特徴とする請求項5に記載の表示装置。 The number of the plurality of second pixels and the number of the plurality of third pixels are different from each other,
The number of the plurality of third pixels and the number of the plurality of fourth pixels are different from each other;
The display device according to claim 5. - 前記表示パネルは基板を含み、
前記第1方向及び前記第2方向は、前記基板の端辺に対して傾斜している、
ことを特徴とする請求項1から6の何れか1項に記載の表示装置。 The display panel includes a substrate,
The first direction and the second direction are inclined with respect to an edge of the substrate;
The display device according to claim 1, wherein the display device is a display device. - 平面視で互いに重畳して配置された第1表示パネル及び第2表示パネルを有し、
前記第1表示パネルには、複数の画素が第1方向及び第2方向にマトリクス状に配置されており、
前記第2表示パネルには、複数の画素が第3方向及び第4方向にマトリクス状に配置されており、
前記第1表示パネルに配置された前記複数の画素は、複数の第1画素と複数の第2画素とを含み、
前記複数の第1画素及び前記複数の第2画素は、前記第1方向の配列ピッチは互いに等しく、前記第2方向の配列ピッチが互いに異なり、
前記第2表示パネルに配置された前記複数の画素は、前記第3方向の配列ピッチが何れも等しく、かつ、前記第4方向の配列ピッチが何れも等しく、
前記第2表示パネルに配置された前記複数の画素の前記第4方向の配列ピッチは、前記複数の第1画素の前記第2方向の配列ピッチ、及び、前記複数の第2画素の前記第2方向の配列ピッチのうちの一方より大きく、かつ他方より小さい、
ことを特徴とする表示装置。 Having a first display panel and a second display panel arranged to overlap each other in plan view;
In the first display panel, a plurality of pixels are arranged in a matrix in the first direction and the second direction,
In the second display panel, a plurality of pixels are arranged in a matrix in the third direction and the fourth direction,
The plurality of pixels arranged on the first display panel includes a plurality of first pixels and a plurality of second pixels,
The plurality of first pixels and the plurality of second pixels have the same arrangement pitch in the first direction, and the arrangement pitch in the second direction is different from each other.
The plurality of pixels arranged in the second display panel have the same arrangement pitch in the third direction and the same arrangement pitch in the fourth direction.
The arrangement pitch of the plurality of pixels arranged in the second display panel in the fourth direction is the arrangement pitch of the plurality of first pixels in the second direction, and the second of the plurality of second pixels. Greater than one of the directional array pitches and less than the other,
A display device characterized by that. - 前記第2方向は、前記第4方向に対して28度~32度傾斜している、
ことを特徴とする請求項8に記載の表示装置。 The second direction is inclined at 28 to 32 degrees with respect to the fourth direction.
The display device according to claim 8. - 第1方向に延在する一対の辺と第2方向に延在する一対の辺とからなる矩形状の複数の画素が、前記第1方向及び前記第2方向にマトリクス状に配置された表示パネルを有し、
前記複数の画素は、第1画素、第2画素及び第3画素を含み、
前記第1画素の第1端部と、前記第2画素の第2端部と、前記第3画素の第3端部とを頂点として、
前記第1端部と前記第2端部とを結び、前記第1方向に延在する第1辺と、前記第2端部と前記第3端部とを結び、前記第2方向に延在する第2辺と、前記第1端部と前記第3端部とを結び、前記表示パネルを構成する基板の端辺に平行な第3辺と、からなる直角三角形を形成した場合に、
前記第1辺と前記第3辺とがなす角度をθとすると、tanθ及びcosθがそれぞれ有理数である、
ことを特徴とする表示装置。 A display panel in which a plurality of rectangular pixels including a pair of sides extending in the first direction and a pair of sides extending in the second direction are arranged in a matrix in the first direction and the second direction. Have
The plurality of pixels includes a first pixel, a second pixel, and a third pixel,
With the first end of the first pixel, the second end of the second pixel, and the third end of the third pixel as vertices,
The first end and the second end are connected to each other, the first side extending in the first direction, the second end and the third end are connected to each other, and the second end is extended to the second direction. When forming a right triangle composed of a second side, a third side that connects the first end and the third end and is parallel to the end of the substrate constituting the display panel,
If the angle formed by the first side and the third side is θ, tan θ and cos θ are rational numbers, respectively.
A display device characterized by that. - 前記tanθは、3/4、5/12、8/15、7/24、20/21、12/35、9/40、28/45、11/60、16/63、33/56の何れか1つを満たす、
ことを特徴とする請求項10に記載の表示装置。 The tan θ is any of 3/4, 5/12, 8/15, 7/24, 20/21, 12/35, 9/40, 28/45, 11/60, 16/63, and 33/56. Satisfy one,
The display device according to claim 10. - 前記tanθは、3/4、5/12、8/15、7/24、20/21の何れか1つを満たす、
ことを特徴とする請求項10に記載の表示装置。 The tan θ satisfies any one of 3/4, 5/12, 8/15, 7/24, and 20/21.
The display device according to claim 10. - 前記表示パネルは、複数のデータ線及び複数のゲート線を含み、
前記複数のデータ線又は前記複数のゲート線は、前記基板の端辺に対して前記角度θだけ傾斜している、
ことを特徴とする請求項10に記載の表示装置。 The display panel includes a plurality of data lines and a plurality of gate lines,
The plurality of data lines or the plurality of gate lines are inclined by the angle θ with respect to an edge of the substrate.
The display device according to claim 10. - 前記表示パネルは、前記第1方向に延在する複数のゲート線と、前記第2方向に延在する複数のデータ線とを含み、
前記第1辺の長さは前記複数のデータ線の配列ピッチの整数倍であり、前記第2辺の長さは前記複数のゲート線の配列ピッチの整数倍である、
ことを特徴とする請求項10に記載の表示装置。 The display panel includes a plurality of gate lines extending in the first direction and a plurality of data lines extending in the second direction,
The length of the first side is an integer multiple of the arrangement pitch of the plurality of data lines, and the length of the second side is an integer multiple of the arrangement pitch of the plurality of gate lines.
The display device according to claim 10. - 平面視で互いに重畳して配置された第1表示パネル及び第2表示パネルを有し、
前記第1表示パネルには、第1方向に延在する一対の辺と第2方向に延在する一対の辺とからなる矩形状の複数の画素が、前記第1方向及び前記第2方向にマトリクス状に配置されており、
前記複数の画素は、第1画素、第2画素及び第3画素を含み、
前記第1画素の第1端部と、前記第2画素の第2端部と、前記第3画素の第3端部とを頂点として、
前記第1端部と前記第2端部とを結び、前記第1方向に延在する第1辺と、前記第2端部と前記第3端部とを結び、前記第2方向に延在する第2辺と、前記第1端部と前記第3端部とを結ぶ第3辺と、からなる直角三角形を形成した場合に、
前記第3辺は、前記第2表示パネルに形成された複数のデータ線又は複数のゲート線に平行であり、
前記第1辺と前記第3辺とがなす角度をθとすると、tanθ及びcosθがそれぞれ有理数である、
ことを特徴とする表示装置。 Having a first display panel and a second display panel arranged to overlap each other in plan view;
In the first display panel, a plurality of rectangular pixels including a pair of sides extending in the first direction and a pair of sides extending in the second direction are arranged in the first direction and the second direction. Arranged in a matrix,
The plurality of pixels includes a first pixel, a second pixel, and a third pixel,
With the first end of the first pixel, the second end of the second pixel, and the third end of the third pixel as vertices,
The first end and the second end are connected to each other, the first side extending in the first direction, the second end and the third end are connected to each other, and the second end is extended to the second direction. When forming a right triangle consisting of the second side and the third side connecting the first end and the third end,
The third side is parallel to a plurality of data lines or a plurality of gate lines formed on the second display panel,
If the angle formed by the first side and the third side is θ, tan θ and cos θ are rational numbers, respectively.
A display device characterized by that. - 前記tanθは、3/4、5/12、8/15、7/24、20/21、12/35、9/40、28/45、11/60、16/63、33/56の何れか1つを満たす、
ことを特徴とする請求項15に記載の表示装置。 The tan θ is any of 3/4, 5/12, 8/15, 7/24, 20/21, 12/35, 9/40, 28/45, 11/60, 16/63, and 33/56. Satisfy one,
The display device according to claim 15. - 前記tanθは、8/15を満たす、
ことを特徴とする請求項15に記載の表示装置。 The tan θ satisfies 8/15.
The display device according to claim 15. - 平面視で互いに重畳する第1表示パネル及び第2表示パネルを有し、
前記第1表示パネルには、第1方向に延在する一対の辺と第2方向に延在する一対の辺とからなる矩形状の複数の画素が、前記第1方向及び前記第2方向にマトリクス状に配置されており、
前記複数の画素は、第1画素、第2画素及び第3画素を含み、
前記第1画素の第1端部と、前記第2画素の第2端部と、前記第3画素の第3端部とを頂点として、
前記第1端部と前記第2端部とを結び、前記第1方向に延在する第1辺と、前記第2端部と前記第3端部とを結び、前記第2方向に延在する第2辺と、前記第1端部と前記第3端部とを結び、前記第1表示パネルを構成する基板の端辺に平行な第3辺と、からなる直角三角形を形成した場合に、
前記第1辺と前記第3辺とがなす角度をθとすると、tanθ及びcosθがそれぞれ有理数である、
ことを特徴とする表示装置。 A first display panel and a second display panel that overlap each other in plan view;
In the first display panel, a plurality of rectangular pixels including a pair of sides extending in the first direction and a pair of sides extending in the second direction are arranged in the first direction and the second direction. Arranged in a matrix,
The plurality of pixels includes a first pixel, a second pixel, and a third pixel,
With the first end of the first pixel, the second end of the second pixel, and the third end of the third pixel as vertices,
The first end and the second end are connected to each other, the first side extending in the first direction, the second end and the third end are connected to each other, and the second end is extended to the second direction. Forming a right triangle comprising a second side that connects the first end and the third end and a third side parallel to the end of the substrate constituting the first display panel. ,
If the angle formed by the first side and the third side is θ, tan θ and cos θ are rational numbers, respectively.
A display device characterized by that. - 前記tanθは、3/4、5/12、8/15、7/24、20/21、12/35、9/40、28/45、11/60、16/63、33/56の何れか1つを満たす、
ことを特徴とする請求項18に記載の表示装置。 The tan θ is any of 3/4, 5/12, 8/15, 7/24, 20/21, 12/35, 9/40, 28/45, 11/60, 16/63, and 33/56. Satisfy one,
The display device according to claim 18. - 前記tanθは、8/15を満たす、
ことを特徴とする請求項18に記載の表示装置。 The tan θ satisfies 8/15.
The display device according to claim 18. - 前記第1表示パネルを構成する基板の端辺は、前記第2表示パネルを構成する基板の端辺に対して傾斜している、
ことを特徴とする請求項18に記載の表示装置。 An edge of a substrate constituting the first display panel is inclined with respect to an edge of the substrate constituting the second display panel;
The display device according to claim 18. - 前記第1表示パネルを構成する基板の端辺と、前記第2表示パネルを構成する基板の端辺とがなす角度は、1度以上3度以下である、
ことを特徴とする請求項18に記載の表示装置。 The angle formed by the edge of the substrate constituting the first display panel and the edge of the substrate constituting the second display panel is 1 degree or more and 3 degrees or less.
The display device according to claim 18. - 平面視で、前記第1表示パネルに形成されたゲート線と前記第2表示パネルに形成されたゲート線とのなす角度が略30度である、
ことを特徴とする請求項18に記載の表示装置。 In plan view, an angle formed between the gate line formed on the first display panel and the gate line formed on the second display panel is approximately 30 degrees.
The display device according to claim 18. - 前記第2表示パネルには、第3方向に延在する一対の辺と第4方向に延在する一対の辺とからなる矩形状の複数の画素が、前記第3方向及び前記第3方向にマトリクス状に配置されており、
前記第2表示パネルの前記複数の画素は、第4画素、第5画素及び第6画素を含み、
前記第4画素の第4端部と、前記第5画素の第5端部と、前記第6画素の第6端部とを頂点として、
前記第4端部と前記第5端部とを結び、前記第3方向に延在する第4辺と、前記第5端部と前記第6端部とを結び、前記第4方向に延在する第5辺と、前記第4端部と前記第6端部とを結び、前記第2表示パネルを構成する基板の端辺に平行な第6辺と、からなる直角三角形を形成した場合に、
前記第4辺と前記第6辺とがなす角度をαとすると、tanα及びcosαがそれぞれ有理数である、
ことを特徴とする請求項18に記載の表示装置。 In the second display panel, a plurality of rectangular pixels including a pair of sides extending in the third direction and a pair of sides extending in the fourth direction are arranged in the third direction and the third direction. Arranged in a matrix,
The plurality of pixels of the second display panel includes a fourth pixel, a fifth pixel, and a sixth pixel,
With the fourth end of the fourth pixel, the fifth end of the fifth pixel, and the sixth end of the sixth pixel as vertices,
The fourth end and the fifth end are connected to each other, the fourth side extending in the third direction, the fifth end and the sixth end are connected to each other, and the fourth end extends in the fourth direction. Forming a right triangle comprising a fifth side, a fourth side connecting the fourth end and the sixth end, and a sixth side parallel to the end of the substrate constituting the second display panel. ,
If the angle formed by the fourth side and the sixth side is α, tan α and cos α are rational numbers, respectively.
The display device according to claim 18. - 前記tanαは、3/4、5/12、8/15、7/24、20/21、12/35、9/40、28/45、11/60、16/63、33/56の何れか1つを満たす、
ことを特徴とする請求項24に記載の表示装置。 The tan α is any of 3/4, 5/12, 8/15, 7/24, 20/21, 12/35, 9/40, 28/45, 11/60, 16/63, and 33/56. Satisfy one,
25. The display device according to claim 24. - 前記tanθ及び前記tanαはそれぞれ、7/24を満たす、
ことを特徴とする請求項24に記載の表示装置。 The tan θ and the tan α satisfy 7/24, respectively.
25. The display device according to claim 24.
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