JP2018087895A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve color reproducibility of a single color image in a liquid crystal display device composed of a plurality of display panels overlapping with each other.SOLUTION: A liquid crystal display device comprises a first display panel and a second display panel arranged so as to overlap with each other. The first display panel includes: a plurality of first source lines extending in a first direction; a plurality of first gate lines extending in a second direction; a plurality of first thin film transistors; a plurality of first pixel electrodes; and a plurality of first pixels. The second display panel includes: a plurality of second source lines extending in the first direction; a plurality of second gate lines extending in the second direction; a plurality of second thin film transistors; a plurality of third thin film transistors; a plurality of second pixel electrodes; a plurality of third pixel electrodes; a plurality of second pixels; and a plurality of third pixels. The second display panel further includes a first area in which the second source lines are not arranged in a pla view among the second pixel electrodes and the third pixel electrodes arranged so as to be adjacent to one another in the second direction.SELECTED DRAWING: Figure 20

Description

  The present invention relates to a liquid crystal display device.

  Conventionally, as a technique for improving the contrast of a liquid crystal display device, a technique has been proposed in which two display panels are overlapped and an image is displayed on each display panel based on an input video signal (for example, Patent Document 1). reference). Specifically, for example, a color image is displayed on the front (observer side) display panel among the two display panels arranged at the front and back, and a monochrome image is displayed on the rear (backlight side) display panel. Thus, the contrast is improved. Further, in the liquid crystal display device, in order to reduce the cost by reducing the number of source drivers, the arrangement of the pixels is set with respect to the three pixels (red pixel, green pixel, blue pixel) of the color image display panel. The monochrome image display panel is configured to have one pixel.

WO2007 / 040127

  By the way, in a normal liquid crystal display device composed of a single color image display panel, when a monochromatic image is displayed, color reproducibility deteriorates due to leakage light from a pixel different from the pixel that transmits the original color. The problem is known. For example, when a red single color image is displayed, part of the light leaks from the green and blue pixels in the off state due to scattering, etc., and this leaked light is mixed with red light. Decreases. In particular, when a low-brightness monochromatic image is displayed, the influence of the leakage light is increased, so that the color reproducibility is deteriorated. This problem also applies to the liquid crystal display device disclosed in Patent Document 1. That is, in the liquid crystal display device, even when displaying a monochromatic image, the red light, the green pixel, and the blue pixel of the color image display panel are uniformly irradiated with the backlight light transmitted through the monochrome image display panel. Similar to the liquid crystal display device, color reproducibility may be deteriorated due to light leakage.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to improve the color reproducibility of a single-color image in a liquid crystal display device configured by overlapping a plurality of display panels.

  In order to solve the above-described problems, a liquid crystal display device according to the present invention is a liquid crystal display device in which a plurality of display panels are arranged to overlap each other, and an image is displayed on each of the display panels. The first display panel includes a plurality of first source lines that extend in the first direction and a second direction that intersects the first direction. A plurality of first gate lines; a plurality of first thin film transistors; a plurality of first pixel electrodes electrically connected to each of the first thin film transistors; and a plurality of first gate electrodes defining drive regions of the first pixel electrodes. The second display panel includes a plurality of second source lines extending in the first direction, a plurality of second gate lines extending in the second direction, and a plurality of second lines. Thin film transistor and a plurality of third thin films A transistor, a plurality of second pixel electrodes electrically connected to the second thin film transistors, a plurality of third pixel electrodes electrically connected to the third thin film transistors, and a plurality of second pixel electrodes A plurality of second pixels defining a drive region; and a plurality of third pixels defining a drive region of each third pixel electrode, wherein the second display panel further includes the second pixel in plan view. A first region in which the second source line is not disposed is included between the second pixel electrode and the third pixel electrode disposed adjacent to each other in the direction.

  In the liquid crystal display device according to the present invention, the second display panel further includes the second display panel between the second pixel electrode and the third pixel electrode arranged adjacent to each other in the second direction in plan view. A second region in which two source lines are arranged may be included.

  In the liquid crystal display device according to the present invention, in the second display panel, the first region and the second region may be alternately and repeatedly arranged in the second direction.

  In the liquid crystal display device according to the present invention, one first pixel is included in one region surrounded by the two adjacent first source lines and the two adjacent first gate lines. One region surrounded by two adjacent second source lines and two adjacent second gate lines includes one second pixel and one third pixel. May be.

  In the liquid crystal display device according to the present invention, the second pixel may be superimposed on one first pixel or a plurality of the first pixels corresponding to the same color in plan view.

  In the liquid crystal display device according to the present invention, the plurality of first pixels include a red pixel corresponding to red, a green pixel corresponding to green, and a blue pixel corresponding to blue, and an area of the second pixel. And the area of the third pixel may be different from each other.

  In the liquid crystal display device according to the present invention, the first pixel and the second pixel overlap each other in plan view, and the area of the first pixel and the area of the second pixel are equal to each other. The area of the pixel may be equal to twice the area of the first pixel.

  In the liquid crystal display device according to the present invention, the plurality of first pixels include a red pixel corresponding to red, a green pixel corresponding to green, and a blue pixel corresponding to blue, and the second display panel includes And a plurality of fourth thin film transistors, a plurality of fourth pixel electrodes electrically connected to each of the fourth thin film transistors, and a plurality of fourth pixels defining a drive region of each of the fourth pixel electrodes, In the one second region, one second pixel, one third pixel, and one fourth pixel are arranged side by side, and in plan view, the second pixel becomes the red pixel. The third pixel may be superimposed on the green pixel, and the fourth pixel may be superimposed on the blue pixel.

  In the liquid crystal display device according to the present invention, the plurality of first pixels include a red pixel corresponding to red, a green pixel corresponding to green, a blue pixel corresponding to blue, and a white pixel corresponding to white. The second display panel further includes a plurality of fourth thin film transistors, a plurality of fifth thin film transistors, a plurality of fourth pixel electrodes electrically connected to the fourth thin film transistors, and the fifth thin film transistors. A plurality of fifth pixel electrodes that are electrically connected to each other, a plurality of fourth pixels that define a drive region of each of the fourth pixel electrodes, and a plurality of fifth pixels that define a drive region of each of the fifth pixel electrodes. One second pixel, one third pixel, one fourth pixel, and one fifth pixel arranged side by side in one second region, In view, the second pixel is the red color Superimposed on element, the third pixel is superposed on the green pixel, the fourth pixel are superimposed on the blue pixel, the fifth pixel may be superimposed on the white pixel.

  In the liquid crystal display device according to the present invention, the plurality of first pixels include a red pixel corresponding to red, a green pixel corresponding to green, and a blue pixel corresponding to blue. Two pixels may be superimposed on the red pixel, and the third pixel may be superimposed on the green pixel and the blue pixel.

  In the liquid crystal display device according to the present invention, the first display panel displays a color image, the second display panel displays a monochrome image, and the second display panel is farther from the viewer than the first display panel. The first black matrix extends in the first direction and the second direction so as to overlap the plurality of first source lines and the plurality of first gate lines in a plan view, The second black matrix may extend in the second direction so as to overlap the plurality of second gate lines in a plan view, and may be formed in a stripe shape.

  In the liquid crystal display device according to the present invention, the first display panel displays a color image, the second display panel displays a monochrome image, and the first display panel is farther from the viewer than the second display panel. The first black matrix extends in the second direction so as to overlap the plurality of first gate lines in a plan view, and is formed in a stripe shape. The second black matrix is , And extending in the first direction and the second direction so as to overlap the plurality of second source lines and the plurality of second gate lines in a plan view, and may be formed in a lattice shape.

  In the liquid crystal display device according to the present invention, the first black matrix extends in the first direction and the second direction so as to overlap the plurality of first source lines and the plurality of first gate lines in plan view. The second black matrix is formed in a lattice shape, and the second black matrix overlaps the plurality of second source lines and the plurality of second gate lines in a plan view. The length of the second direction of the portion extending in the first direction of the second black matrix extends in the first direction of the first black matrix. The length of the portion of the second black matrix that is shorter than the length of the second direction and that extends in the second direction of the second black matrix is the second direction of the first black matrix. Part of the portion extending to It may be shorter than the length of the direction.

  In the liquid crystal display device according to the present invention, the first display panel further includes a first black matrix, the second display panel further includes a second black matrix, and the second of the first black matrix. The length in the first direction of the portion extending in the direction may be different from the length in the first direction of the portion extending in the second direction of the second black matrix.

  In order to solve the above-described problem, a liquid crystal display device according to the present invention is a liquid crystal display device in which a plurality of display panels are arranged to overlap each other and display an image on each of the display panels. The first display panel includes a plurality of first source lines extending in a first direction and a second direction intersecting the first direction. A plurality of first gate lines, a plurality of first thin film transistors, a plurality of first pixel electrodes electrically connected to each of the first thin film transistors, and a plurality of driving regions for the first pixel electrodes. The second display panel includes a plurality of second source lines extending in the first direction, a plurality of second gate lines extending in the second direction, and a plurality of second pixels. Two thin film transistors and a plurality of second A thin film transistor; a plurality of second pixel electrodes electrically connected to each of the second thin film transistors; a plurality of third pixel electrodes electrically connected to each of the third thin film transistors; A plurality of second pixels defining a drive region and a plurality of third pixels defining a drive region of each third pixel electrode; and two adjacent first source lines and two adjacent pixels One region surrounded by the first gate line includes one first pixel, and includes two adjacent second source lines and two adjacent second gate lines. One surrounded region includes one of the second pixels and one of the third pixels.

  According to the liquid crystal display device according to the present invention, it is possible to improve the color reproducibility of a monochromatic image in a liquid crystal display device configured by overlapping a plurality of display panels.

It is a perspective view which shows schematic structure of the liquid crystal display device which concerns on this embodiment. It is a figure which shows typically schematic structure of the said liquid crystal display device. 3 is a plan view illustrating a schematic configuration of a front display panel according to Embodiment 1. FIG. 3 is a plan view illustrating a schematic configuration of a rear display panel according to Embodiment 1. FIG. It is 5-5 'sectional drawing of FIG.3 and FIG.4. FIG. 3 is a plan view illustrating a relationship between a pixel on the front display panel and a pixel on the rear display panel according to the first embodiment. It is a top view which shows the specific structure of the pixel corresponding to FIG. It is sectional drawing in the 8-8 'cut line of FIG. It is sectional drawing in the 9-9 'cutting line of FIG. 3 is a schematic diagram illustrating an example of image display (black image) in the liquid crystal display device according to Embodiment 1. FIG. 2 is a diagram illustrating a configuration of drivers of a front display panel and a rear display panel according to Embodiment 1. FIG. 10 is a plan view illustrating a schematic configuration of a front display panel according to Embodiment 2. FIG. 10 is a plan view illustrating a schematic configuration of a rear display panel according to Embodiment 2. FIG. FIG. 10 is a plan view illustrating a relationship between a pixel on a front display panel and a pixel on a rear display panel according to Embodiment 2. FIG. 15 is a plan view showing a specific configuration of pixels of the front display panel shown in FIG. FIG. 15 is a plan view showing a specific configuration of pixels of the rear display panel shown in FIG. It is sectional drawing in the 17-17 'cut line of FIG.15 and FIG.16. It is sectional drawing in the 18-18 'cut line of FIG.15 and FIG.16. 6 is a plan view showing a schematic configuration of a front display panel according to Embodiment 3. FIG. 10 is a plan view illustrating a schematic configuration of a rear display panel according to Embodiment 3. FIG. FIG. 10 is a plan view showing a relationship between a pixel on a front display panel and a pixel on a rear display panel according to Embodiment 3. It is a top view which shows the specific structure of the pixel corresponding to FIG. It is sectional drawing in the 23-23 'cut line of FIG. It is sectional drawing in the 24-24 'cut line of FIG. FIG. 10 is a diagram illustrating a configuration of drivers of a front display panel and a rear display panel according to a third embodiment. 10 is a plan view illustrating a schematic configuration of a front display panel according to Embodiment 4. FIG. 10 is a plan view showing a schematic configuration of a rear display panel according to Embodiment 4. FIG. It is 28-28 'sectional drawing of FIG.26 and FIG.27. FIG. 10 is a plan view illustrating a relationship between a pixel on a front display panel and a pixel on a rear display panel according to Embodiment 4. FIG. 30 is a plan view illustrating a specific configuration of a pixel corresponding to FIG. 29. It is sectional drawing in the 31-31 'cutting line of FIG. FIG. 32 is a cross-sectional view taken along the line 32-32 ′ of FIG. 30. FIG. 10 is a diagram illustrating a configuration of drivers of a front display panel and a rear display panel according to a fourth embodiment. FIG. 10 is a plan view illustrating a specific configuration of a pixel of a front display panel and a pixel of a rear display panel according to Embodiment 5. It is sectional drawing in the 35-35 'cutting line of FIG. 10 is a plan view showing a schematic configuration of a front display panel according to Embodiment 6. FIG. 10 is a plan view showing a schematic configuration of a rear display panel according to Embodiment 6. FIG. FIG. 10 is a plan view illustrating a relationship between a pixel on a front display panel and a pixel on a rear display panel according to Embodiment 6. FIG. 39 is a plan view showing a specific configuration of a pixel of the front display panel shown in FIG. FIG. 39 is a plan view showing a specific configuration of a pixel of the rear display panel shown in FIG. It is sectional drawing in the 41-41 'cutting line of FIG.39 and FIG.40. FIG. 10 is a diagram illustrating a configuration of drivers of a front display panel and a rear display panel according to a sixth embodiment. 10 is a plan view showing a schematic configuration of a rear display panel according to Embodiment 7. FIG. FIG. 10 is a plan view illustrating a relationship between a pixel on a front display panel and a pixel on a rear display panel according to Embodiment 7. FIG. 45 is a plan view illustrating a specific configuration of a pixel corresponding to FIG. 44. It is sectional drawing in the 46-46 'cutting line of FIG. FIG. 10 is a diagram illustrating a configuration of drivers of a front display panel and a rear display panel according to a seventh embodiment. FIG. 10 is a plan view illustrating a schematic configuration of a rear display panel according to an eighth embodiment. FIG. 10 is a plan view illustrating a relationship between a pixel on a front display panel and a pixel on a rear display panel according to Embodiment 8. FIG. 50 is a plan view showing a specific configuration of a pixel of the rear display panel shown in FIG. 49 (b). FIG. 10 is a diagram illustrating a configuration of drivers of a front display panel and a rear display panel according to an eighth embodiment. 10 is a plan view showing a schematic configuration of a front display panel according to Embodiment 9. FIG. 10 is a plan view showing a schematic configuration of a rear display panel according to Embodiment 9. FIG. FIG. 10 is a plan view showing a relationship between a pixel on a front display panel and a pixel on a rear display panel according to Embodiment 9. FIG. 10 is a diagram illustrating a configuration of drivers of a front display panel and a rear display panel according to a ninth embodiment. 22 is a plan view illustrating a schematic configuration of a front display panel according to Embodiment 10. FIG. 22 is a plan view showing a schematic configuration of a rear display panel according to Embodiment 10. FIG. FIG. 32 is a plan view illustrating a relationship between a pixel on the front display panel and a pixel on the rear display panel according to the tenth embodiment. 14 is a plan view illustrating a schematic configuration of a front display panel according to Embodiment 11. FIG. 14 is a plan view illustrating a schematic configuration of a rear display panel according to Embodiment 11. FIG. FIG. 22 is a plan view showing a relationship between a pixel on the front display panel and a pixel on the rear display panel according to the eleventh embodiment. FIG. 30 is a plan view illustrating a specific configuration of a pixel on a front display panel and a pixel on a rear display panel according to Embodiment 12. FIG. 63 is a cross-sectional view taken along line 62-62 ′ of FIG. 62. It is a top view which shows schematic structure of the back side display panel which concerns on other embodiment. It is a figure which shows typically the relationship between a black matrix and an opening part in two panels arrange | positioned mutually superimposed. It is a figure which shows typically the relationship between a black matrix and an opening part in two panels arrange | positioned mutually superimposed.

  Embodiments of the present invention will be described below with reference to the drawings. A liquid crystal display device according to each embodiment described below includes a plurality of display panels that display images, a plurality of drive circuits (a plurality of source drivers and a plurality of gate drivers) that drive the respective display panels, and respective drives. A plurality of timing controllers that control the circuit, an image processing unit that performs image processing on input video signals input from the outside, and outputs image data to each timing controller, and a plurality of display panels that emit light from the back side And a backlight for irradiating. The number of display panels is not limited and may be two or more. The plurality of display panels are arranged so as to overlap each other in the front-rear direction as viewed from the observer side, and each displays an image. Hereinafter, a liquid crystal display device LCD having two display panels will be described as an example.

  FIG. 1 is a perspective view showing a schematic configuration of a liquid crystal display device LCD according to the present embodiment. As shown in FIG. 1, the liquid crystal display device LCD includes a display panel LCP1 arranged at a position (front side) close to the observer, and a display panel LCP2 arranged at a position (rear side) farther from the observer than the display panel LCP1. An adhesive layer SEFIL that bonds the display panel LCP1 and the display panel LCP2, a backlight BL disposed on the back side of the display panel LCP2, and a front chassis FS that covers the display panel LCP1 and the display panel LCP2 from the display surface side. Contains.

  FIG. 2 is a diagram schematically showing a schematic configuration of the liquid crystal display device LCD according to the present embodiment. As shown in FIG. 2, the display panel LCP1 includes a first source driver SD1 and a first gate driver GD1, and the display panel LCP2 includes a second source driver SD2 and a second gate driver GD2. The liquid crystal display device LCD includes a first timing controller TCON1 that controls the first source driver SD1 and the first gate driver GD1, a second timing controller TCON2 that controls the second source driver SD2 and the second gate driver GD2, and a second timing controller TCON2. And an image processing unit IPU that outputs image data to the first timing controller TCON1 and the second timing controller TCON2. For example, the display panel LCP1 displays a color image corresponding to the input video signal in the first image display area DISP1, and the display panel LCP2 displays a monochrome image corresponding to the input video signal in the second image display area DISP2. The image processing unit IPU receives an input video signal Data transmitted from an external system (not shown), performs well-known image processing, and then outputs first image data DAT1 to the first timing controller TCON1, The second image data DAT2 is output to the second timing controller TCON2. The image processing unit IPU outputs a control signal (not shown in FIG. 2) such as a synchronization signal to the first timing controller TCON1 and the second timing controller TCON2. The first image data DAT1 is, for example, image data for displaying a color image, and the second image data DAT2 is, for example, image data for displaying a monochrome image. Note that the liquid crystal display device LCD may be configured such that the display panel LCP1 displays a monochrome image in the first image display area DISP1, and the display panel LCP2 displays a color image in the second image display area DISP2.

[Embodiment 1]
FIG. 3 is a plan view showing a schematic configuration of the display panel LCP1 according to the first embodiment, and FIG. 4 is a plan view showing a schematic configuration of the display panel LCP2 according to the first embodiment. FIG. 5 is a cross-sectional view taken along line 5-5 ′ of FIGS.

  A schematic configuration of the display panel LCP1 will be described with reference to FIGS. As shown in FIG. 5, the display panel LCP1 includes a thin film transistor substrate TFTB1 disposed on the backlight BL side, a counter substrate CF1 disposed on the viewer side and facing the thin film transistor substrate TFTB1, and the thin film transistor substrate TFTB1 and the counter substrate CF1. And a liquid crystal layer LC1 disposed between them. A polarizing plate POL2 is disposed on the backlight BL side of the display panel LCP1, and a polarizing plate POL1 is disposed on the viewer side.

  As shown in FIG. 3, the thin film transistor substrate TFTB1 extends in a second direction (for example, the row direction) that intersects the first direction and a plurality of source lines SL1 that extend in the first direction (for example, the column direction). A plurality of gate lines GL1 are formed, and a thin film transistor TFT1 is formed in the vicinity of each intersection of the plurality of source lines SL1 and the plurality of gate lines GL1. In the display panel LCP1, the minimum display unit (dot), that is, the drive region (dot display region) of the pixel electrode PX1 electrically connected to the thin film transistor TFT1 is defined as one pixel PIX1, and the pixel PIX1 is a matrix. A plurality are arranged in the shape (row direction and column direction). The plurality of source lines SL1 are arranged at equal intervals in the row direction, and the plurality of gate lines GL1 are arranged at equal intervals in the column direction. On the thin film transistor substrate TFTB1 (see FIG. 5), a pixel electrode PX1 is formed for each pixel PIX1, and one common electrode CT (see FIG. 8) common to the plurality of pixels PIX1 is formed. The source electrode constituting the thin film transistor TFT1 is electrically connected to the source line SL1, the drain electrode DD (see FIG. 7A) is electrically connected to the pixel electrode PX1 through a contact hole, and the gate electrode is a gate line. It is electrically connected to GL1.

  As shown in FIG. 5, the counter substrate CF1 is formed with a light transmitting portion that transmits light and a black matrix BM1 (light shielding portion) that blocks light transmission. In the light transmission portion, a plurality of color filters FIL (colored layers) are formed corresponding to each pixel PIX1. The light transmission part is surrounded by the black matrix BM1, and is formed in a rectangular shape, for example. As will be described in detail later, the plurality of color filters FIL are formed of a red (R color) material, and are formed of a red color filter FILR (red layer) that transmits red light and a green (G color) material. , A green color filter FILG (green layer) that transmits green light, and a blue color filter FILB (blue layer) that is formed of a blue (B color) material and transmits blue light. The red color filter FILR, the green color filter FILG, and the blue color filter FILB are repeatedly arranged in this order in the row direction, and the color filters FIL of the same color are arranged in the column direction, and are adjacent to each other in the row direction and the column direction. A black matrix BM1 is formed at the boundary portion of. As shown in FIG. 3, the plurality of pixels PIX1 corresponding to each color filter FIL includes a red pixel PIXR corresponding to the red color filter FILR, a green pixel PIXG corresponding to the green color filter FILG, and a blue color filter FILB. And a blue pixel PIXB corresponding to. In the display panel LCP1, red pixels PIXR, green pixels PIXG, and blue pixels PIXB are repeatedly arranged in this order in the row direction, and pixels PIX1 of the same color are arranged in the column direction.

  The first timing controller TCON1 has a known configuration. For example, the first timing controller TCON1 uses the first image data DA1 based on the first image data DAT1 output from the image processing unit IPU and the first control signal CS1 (clock signal, vertical synchronization signal, horizontal synchronization signal, etc.). And various timing signals (data start pulse DSP1, data clock DCK1, gate start pulse GSP1, gate clock GCK1) for controlling the driving of the first source driver SD1 and the first gate driver GD1 (see FIG. 3). ). The first timing controller TCON1 outputs the first image data DA1, the data start pulse DSP1, and the data clock DCK1 to the first source driver SD1, and the gate start pulse GSP1 and the gate clock GCK1 to the first gate driver GD1. Output.

  The first source driver SD1 outputs a data signal (data voltage) corresponding to the first image data DA1 to the source line SL1 based on the data start pulse DSP1 and the data clock DCK1. The first gate driver GD1 outputs a gate signal (gate voltage) to the gate line GL1 based on the gate start pulse GSP1 and the gate clock GCK1.

  A data voltage is supplied from the first source driver SD1 to each source line SL1, and a gate voltage is supplied from the first gate driver GD1 to each gate line GL1. A common voltage Vcom is supplied to the common electrode CT from a common driver (not shown). When the gate voltage (gate-on voltage) is supplied to the gate line GL1, the thin film transistor TFT1 connected to the gate line GL1 is turned on, and the data voltage is supplied to the pixel electrode PX1 via the source line SL connected to the thin film transistor TFT1. Is done. An electric field is generated by the difference between the data voltage supplied to the pixel electrode PX1 and the common voltage Vcom supplied to the common electrode CT. The liquid crystal is driven by this electric field to control the light transmittance of the backlight BL, thereby displaying an image. In the display panel LCP1, color image display is performed by supplying a desired data voltage to the source line SL1 connected to the pixel electrodes PX1 of the red pixel PIXR, the green pixel PIXG, and the blue pixel PIXB.

  Next, the configuration of the display panel LCP2 will be described with reference to FIGS. As shown in FIG. 5, the display panel LCP2 includes a thin film transistor substrate TFTB2 disposed on the backlight BL side, a counter substrate CF2 disposed on the observer side and facing the thin film transistor substrate TFTB2, and the thin film transistor substrate TFTB2 and the counter substrate CF2. And a liquid crystal layer LC2 disposed between the two. A polarizing plate POL4 is disposed on the backlight BL side of the display panel LCP2, and a polarizing plate POL3 is disposed on the viewer side. An adhesive layer SEFIL is arranged between the polarizing plate POL2 of the display panel LCP1 and the polarizing plate POL3 of the display panel LCP2.

  As shown in FIG. 4, a plurality of source lines SL2 extending in the column direction and a plurality of gate lines GL2 extending in the row direction are formed on the thin film transistor substrate TFTB2, and a plurality of source lines SL2 and a plurality of source lines SL2 are formed. A thin film transistor TFT2 is formed in the vicinity of each intersection with the gate line GL2. The plurality of source lines SL2 include a plurality of source lines SL2a and a plurality of source lines SL2b. The plurality of source lines SL2a are arranged at equal intervals in the row direction, and the plurality of source lines SL2b are arranged at equal intervals in the row direction. The source line SL2a and the source line SL2b are alternately arranged in the row direction. In the display panel LCP2, the minimum display unit (dot), that is, the drive region (dot display region) of the pixel electrode PX2 electrically connected to the thin film transistor TFT2 is defined as one pixel PIX2. In the example shown in FIG. 4, when the display panel LCP2 is viewed in a plan view, two pixels PIX2 are arranged in a region (pixel region) surrounded by adjacent source lines SL2a and SL2b and two adjacent gate lines GL2. (PIX2a, PIX2b) are arranged side by side in the row direction. The plurality of pixels PIX2 are arranged in a matrix (row direction and column direction). Between the source line SL2a and the source line SL2b arranged away from the source line SL2a, a pixel region is formed and two pixels PIX2 (PIX2a, PIX2b) are arranged. On the other hand, no pixel region is formed between the source line SL2a and the source line SL2b disposed in the vicinity of the source line SL2a. That is, of the two source lines SL2b adjacent to the source line SL2a, two pixel lines are formed between the source line SL2b and the source line SL2a which are arranged apart from the source line SL2a. Pixels PIX2 (PIX2a, PIX2b) (pixel electrode PX2) are arranged. Further, of the two source lines SL2b adjacent to the source line SL2a, no pixel region is formed between the source line SL2b and the source line SL2a that are disposed in the vicinity of the source line SL2a. The plurality of gate lines GL2 are arranged at equal intervals in the column direction. On the thin film transistor substrate TFTB2 (see FIG. 5), a pixel electrode PX2 is formed for each pixel PIX2, and one common electrode CT (see FIG. 8) common to the plurality of pixels PIX2 is formed. The source electrode constituting the thin film transistor TFT2 is electrically connected to the source line SL2, the drain electrode DD (see FIG. 7B) is electrically connected to the pixel electrode PX2 through the contact hole, and the gate electrode is the gate line. It is electrically connected to GL2.

  On the counter substrate CF2 (see FIG. 5), a light transmitting portion that transmits light and a black matrix BM1 (light shielding portion) (see FIG. 9) that blocks light transmission are formed. In the light transmitting portion, the color filter FIL (colored layer) is not formed, and for example, an overcoat film OC is formed.

  The second timing controller TCON2 has a known configuration. For example, the second timing controller TCON2 uses the second image data DA2 based on the second image data DAT2 output from the image processing unit IPU and the second control signal CS2 (clock signal, vertical synchronization signal, horizontal synchronization signal, etc.). And various timing signals (data start pulse DSP2, data clock DCK2, gate start pulse GSP2, gate clock GCK2) for controlling driving of the second source driver SD2 and the second gate driver GD2 (see FIG. 4). ). The second timing controller TCON2 outputs the second image data DA2, the data start pulse DSP2, and the data clock DCK2 to the second source driver SD2, and outputs the gate start pulse GSP2 and the gate clock GCK2 to the second gate driver GD2. Output.

  The second source driver SD2 outputs a data voltage corresponding to the second image data DA2 to the source line SL2 based on the data start pulse DSP2 and the data clock DCK2. The second gate driver GD2 outputs a gate voltage to the gate line GL2 based on the gate start pulse GSP2 and the gate clock GCK2.

  A data voltage is supplied from the second source driver SD2 to each source line SL2, and a gate voltage is supplied from the second gate driver GD2 to each gate line GL2. A common voltage Vcom is supplied to the common electrode CT from a common driver. When the gate voltage (gate-on voltage) is supplied to the gate line GL, the thin film transistor TFT2 connected to the gate line GL2 is turned on, and the data voltage is supplied to the pixel electrode PX2 via the source line SL2 connected to the thin film transistor TFT2. Is done. An electric field is generated by the difference between the data voltage supplied to the pixel electrode PX2 and the common voltage Vcom supplied to the common electrode CT. The liquid crystal is driven by this electric field to control the light transmittance of the backlight BL, thereby displaying an image. In the display panel LCP2, monochrome image display is performed by supplying a desired data voltage to the source line SL2 connected to the pixel electrode PX2 of each pixel PIX2.

  In the liquid crystal display device LCD, the number of pixels PIX1 per unit area of the display panel LCP1 is equal to the number of pixels PIX2 per unit area of the display panel LCP2, and the display panel LCP1 and the display panel LCP2 are identical to each other. Has resolution. The pixel PIX1 of the display panel LCP1 and the pixel PIX2 of the display panel LCP2 are arranged so as to overlap each other in plan view.

  FIG. 6 is a plan view showing the relationship between the pixel group DOT1 of the display panel LCP1 and the pixel group DOT2 of the display panel LCP2 that overlap each other in plan view, and FIG. 7 is a pixel group DOT1, DOT2 corresponding to FIG. It is a top view which shows the specific structure of these pixels PIX1, PIX2. The pixel group DOT1 includes two pixels PIX1 (one green pixel PIXG and one blue pixel PIXB in the example illustrated in FIG. 6) of the display panel LCP1, and the pixel group DOT2 includes one pixel of the display panel LCP2. Pixel PIX2a and one pixel PIX2b. FIG. 6 shows the common lines CL1 and CL2 connected to the common electrode CT (see FIG. 8) and the liquid crystal capacitor CLC. FIG. 7 shows the semiconductor layer SI (channel) and the drain electrode DD constituting the thin film transistors TFT1 and TFT2. Slits may be formed in the pixel electrodes PX1 and PX2.

  As shown in FIG. 6A, in each pixel PIX1, the source line SL1 is connected to the source electrode of the thin film transistor TFT1, the gate line GL1 is connected to the gate electrode of the thin film transistor TFT1, and the pixel electrode PX1 (FIG. 7 (a)) is connected to the drain electrode DD (see FIG. 7 (a)) of the thin film transistor TFT1. On the other hand, as shown in FIG. 6B, in the pixel PIX2a, the source line SL2a is connected to the source electrode of the thin film transistor TFT2a, the gate line GL2 is connected to the gate electrode of the thin film transistor TFT2a, and the pixel electrode PX2a ( 7B) is connected to the drain electrode DDa (see FIG. 7B) of the thin film transistor TFT2a. In the pixel PIX2b, the source line SL2b is connected to the source electrode of the thin film transistor TFT2b, the gate line GL2 is connected to the gate electrode of the thin film transistor TFT2b, and the pixel electrode is connected to the drain electrode DDb (see FIG. 7) of the thin film transistor TFT2b. It is connected.

  As shown in FIG. 7, the black matrix BM1 of the display panel LCP1 extends in the row direction and the column direction so as to overlap both the gate line GL1 and the source line SL1 in a plan view, and is formed in a lattice shape. Yes. That is, the black matrix BM1 of the display panel LCP1 includes a plurality of row stripe portions BM1a that overlap each of the plurality of gate lines GL1 of the display panel LCP1 in plan view, and a plurality of source lines SL1 of the display panel LCP1 in plan view. A plurality of column stripe portions BM1b overlapping each other are included. The row stripe portion BM1a is longer than the length of the gate line GL1 in the column direction, and the column stripe portion BM1b is longer than the length of the source line SL1 in the row direction. On the other hand, the black matrix BM2 of the display panel LCP2 extends in the row direction so as to overlap the gate line GL2, and is formed in a stripe shape. That is, the black matrix BM2 of the display panel LCP2 includes a plurality of row stripe portions BM2a that overlap each of the plurality of gate lines GL2 of the display panel LCP2 in plan view. The black matrix BM2 does not include a portion extending in the column direction so as to cover the entire source line SL2 in plan view. The row stripe portion BM2a is longer than the length of the gate line GL2 in the column direction. Further, as shown in FIG. 7, the length L2 in the column direction of the row stripe portion BM2a of the black matrix BM2 is shorter than the length L1 in the column direction of the row stripe portion BM1a of the black matrix BM1.

  8 is a cross-sectional view taken along the line 8-8 ′ of FIG. 7, and FIG. 9 is a cross-sectional view taken along the line 9-9 ′ of FIG. A cross-sectional structure of the pixels PIX1 and PIX2 will be described with reference to FIGS.

  In the thin film transistor substrate TFTB1 (see FIG. 5) constituting the pixel PIX1 of the display panel LCP1, the gate line GL1 (see FIG. 9) is formed on the transparent substrate SUB2 (glass substrate), and the gate is covered so as to cover the gate line GL1. An insulating film GSN is formed. A source line SL1 (see FIG. 8) is formed on the gate insulating film GSN, a protective film PAS and an organic film OPAS are formed so as to cover the source line SL1, and a common electrode CT is formed on the organic film OPAS. The protective film UPAS is formed so as to cover the common electrode CT. A pixel electrode PX1 is formed on the protective film UPAS, and an alignment film (not shown) is formed so as to cover the pixel electrode PX1. The pixel electrode PX1 is electrically connected to the drain electrode DD (see FIG. 9) through a contact hole. The source lines SL1 are arranged at equal intervals in the row direction, and the gate lines GL1 are arranged at equal intervals in the column direction. In the counter substrate CF1 (see FIG. 5), a grid-like black matrix BM1 and color filters FIL (red color filter FILR, green color filter FILG, and blue color filter FILB) are formed on the transparent substrate SUB1 (glass substrate). Has been. The surface of the color filter FIL is covered with an overcoat film OC, and an alignment film (not shown) is formed on the overcoat film OC. Each color filter FIL is arranged so that the boundary portion between adjacent color filters FIL overlaps the source line SL1 in plan view.

  In the thin film transistor substrate TFTB2 (see FIG. 5) constituting the pixel PIX2 of the display panel LCP2, the gate line GL2 (see FIG. 9) is formed on the transparent substrate SUB4, and the gate insulating film GSN is formed so as to cover the gate line GL2. Is formed. Source lines SL2a and SL2b (see FIG. 8) are formed on the gate insulating film GSN, and a protective film PAS and an organic film OPAS are formed so as to cover the source lines SL2a and SL2b, and are common on the organic film OPAS. An electrode CT is formed, and a protective film UPAS is formed so as to cover the common electrode CT. A pixel electrode PX2 is formed on the protective film UPAS, and an alignment film (not shown) is formed so as to cover the pixel electrode PX2. The pixel electrode PX2 is electrically connected to the drain electrode DD (see FIG. 9) through a contact hole. In FIG. 8, the left source line SL2b and the right source line SL2a are arranged close to each other in the row direction, and the gate lines GL are arranged at equal intervals in the column direction. In the counter substrate CF2 (see FIG. 5), a striped black matrix BM2 (see FIG. 9) is formed on the transparent substrate SUB3, and the openings (light transmission portions) of the black matrix BM2 and the black matrix BM2 are formed. The overcoat film OC is covered, and an alignment film (not shown) is formed on the overcoat film OC.

  Thus, in the display panel LCP2, the source line SL2a electrically connected to the pixel electrode PX2a (see FIG. 7) in the plan view is arranged on the left side of the pixel electrode PX2a, and the pixel electrode PX2b (FIG. 7) is arranged on the right side of the pixel electrode PX2b. Further, the source line SL2 is not disposed between the right side of the pixel electrode PX2a and the left side of the pixel electrode PX2b.

  In the liquid crystal display device LCD according to the first embodiment, each pixel PIX1 of the display panel LCP1 and each pixel PIX2 of the display panel LCP2 are arranged so as to overlap each other. In the above configuration, for example, when a red single color image is displayed as shown in FIG. 10A, the display panel LCP1 turns on the red pixel PIXR and turns off the green pixel PIXG and the blue pixel PIXB. In the display panel LCP2, the pixel PIX2 superimposed on the red pixel PIXR is turned on, and the pixel PIX2 superimposed on the green pixel PIXG and the blue pixel PIXB is turned off. In this state, when backlight light including RGB components (white) is irradiated, the original display light (red) is emitted from the red pixel PIXR as shown in FIG. In the green pixel PIXG, the leakage light (white) of the display panel LCP2 is incident on the display panel LCP1, the red component R and the blue component B of the leakage light are shielded by the green color filter FILG, and the green component G is polarized. Light is shielded by the plate POL1. In the blue pixel PIXB, the leakage light (white) of the display panel LCP2 is incident on the display panel LCP1, and the red component R and the green component G of the leakage light are shielded by the blue color filter FILB, and the blue component B is polarized. Light is shielded by the plate POL1.

  Thus, since the red pixel PIXR of the display panel LCP1 and the pixel PIX2 of the display panel LCP2 that overlaps the red pixel PIXR are arranged in a one-to-one relationship, the red pixel PIXR and the pixel PIX2 that overlap each other are arranged. On / off can be controlled independently of other pixels. Therefore, even if light leakage occurs in the display panel LCP2, each color component (for example, the green component G and the blue component B) of the leakage light can be shielded by the color filter FIL and the polarizing plate POL1 of the display panel LCP1. Thereby, since light leakage can be reduced as compared with the conventional configuration, the color reproducibility of the red image can be improved. In the above configuration, since each pixel PIX1 of the display panel LCP1 and each pixel PIX2 of the display panel LCP2 are arranged in a one-to-one relationship, on / off of the pixels PIX1 and PIX2 that overlap each other is independent. Can be controlled. Therefore, similarly to the red image, the color reproducibility of the green and blue monochrome images can be improved.

  Here, as a method of independently controlling on / off of each pixel PIX1, PIX2 as described above, the configuration of the source line SL2, black matrix BM2, and pixel PIX2 of the display panel LCP2 is the same as that of the display panel LCP1. It is conceivable to have a configuration. That is, in the display panel LCP2, it is conceivable that the source lines SL2 are arranged one by one on the boundary between adjacent pixels PIX2 in plan view, and the black matrix BM2 is formed in a matrix so as to surround each pixel PIX2. .

  However, with this configuration (hereinafter referred to as a comparative example), local luminance unevenness or moire may easily occur. For example, luminance unevenness and moire are easily visually recognized when the display panels LCP1 and LCP2 are bonded to each other when the display panels LCP1 and LCP2 are bonded to each other. 65 and 66 are diagrams schematically showing the relationship between the black matrix and the openings in the two panels A and B arranged so as to overlap each other. For example, in the configuration example 1 (see FIG. 65) corresponding to the comparative example described above, when a positional deviation occurs between the panel A and the panel B, the position of the black matrix of each of the panel A and the panel B in each pixel is By deviating from each other in the left-right direction, the up-down direction, or the rotation direction, the aperture ratio of the pixels becomes non-uniform in the display surface, and uneven brightness is easily recognized. In addition, when the display screen is viewed from an oblique direction, the upper and lower black matrices can be seen widely, which makes it easier to visually recognize the brightness and darkness of the periodic luminance, that is, moire. On the other hand, in the configuration example 2 (see FIG. 65), when the positional deviation occurs between the panel A and the panel B, the positions of the black matrices of the panel A and the panel B are shifted from each other particularly in the red pixel and the blue pixel. Therefore, luminance unevenness is visually recognized when displaying red and blue single-color images, but in the panel B, a black matrix is formed at the boundary between the green pixel and the red pixel and at the portion overlapping the boundary between the green pixel and the blue pixel. Therefore, the luminance unevenness or moire is reduced for the green pixel.

  On the other hand, in the configuration example 4 (see FIG. 66) corresponding to the liquid crystal display device LCD according to the first embodiment, the black matrix BM2 of the display panel LCP2 (corresponding to the panel B in FIG. 66) extends in the row direction. Are formed in a stripe shape, and a portion extending in the column direction is omitted. Further, the length in the column direction of the black matrix BM2 (row stripe portion BM2a) extending in the row direction (L2 shown in FIG. 7B) is the length in the column direction of the row stripe portion BM1a of the black matrix BM1 ( It is shorter than L1) shown in FIG. For this reason, even when the display panel LCP1 and the display panel LCP2 are misaligned, the influence of the misalignment of the black matrices BM1 and BM2 is small, so that luminance unevenness and moire are less likely to occur. In addition, in the configuration example 1 in FIG. 65, the aperture ratio of each pixel decreases, but in the first embodiment (configuration example 4 in FIG. 66), the decrease in the aperture ratio of the pixel can also be suppressed. In the present embodiment, the black matrix BM2 may include a column stripe portion whose length in the row direction is shorter than the column stripe portion BM1b of the black matrix BM1. Even in this configuration, as in the configuration example 3 shown in FIG. 65, luminance unevenness and moire are less likely to occur.

  FIG. 11 is a diagram illustrating a configuration of drivers of the display panel LCP1 and the display panel LCP2. Six TCP (Tape Carrier Packages) each having a source driver IC (SIC) mounted thereon are connected to the display panel LCP1, and each TCP is connected to the source printed circuit board SKIB. In addition, four gate driver ICs (GIC) are mounted on the display panel LCP1. Similarly, six TCPs each mounted with a source driver IC (SIC) are connected to the display panel LCP2, and each TCP is connected to the source printed circuit board SKIB. Further, four gate driver ICs (GICs) are mounted on the display panel LCP2.

[Embodiment 2]
Embodiment 2 of the present invention will be described below with reference to the drawings. For convenience of explanation, the same reference numerals are given to the constituent elements shown in the first embodiment and the description thereof will be omitted. In addition, the terms defined in the first embodiment are used in accordance with the definitions in the present embodiment unless otherwise specified. The same applies to each embodiment described later.

  FIG. 12 is a plan view showing a schematic configuration of the display panel LCP1 according to the second embodiment, and FIG. 13 is a plan view showing a schematic configuration of the display panel LCP2 according to the second embodiment. The configuration of the display panel LCP1 according to the second embodiment is the same as the configuration of the display panel LCP1 according to the first embodiment.

  In the display panel LCP2 according to the second embodiment, as illustrated in FIG. 13, the plurality of gate lines GL2 includes a plurality of gate lines GL2a and a plurality of gate lines GL2b. The gate lines GL2b are arranged at equal intervals in the column direction. The gate lines GL2a and the gate lines GL2b are alternately arranged in the column direction. Two pixels PIX2 (PIX2a, PIX2b) are arranged in a region (pixel region) surrounded by the adjacent gate lines GL2a, GL2b and the two adjacent source lines SL2 when the display panel LCP2 is viewed in plan. They are arranged side by side. The plurality of pixels PIX2 are arranged in a matrix (row direction and column direction). A pixel region is formed between the gate line GL2a and the gate line GL2b disposed away from the gate line GL2a, and two pixels PIX2 (PIX2a and PIX2b) are disposed. On the other hand, no pixel region is formed between the gate line GL2a and the gate line GL2b disposed in the vicinity of the gate line GL2a. That is, of the two gate lines GL2b adjacent to the gate line GL2a, a pixel region is formed between the gate line GL2a and the gate line GL2a, which are spaced apart from the gate line GL2a. Pixels PIX2 (PIX2a, PIX2b) (pixel electrode PX2) are arranged. Further, of the two gate lines GL2b adjacent to the gate line GL2a, no pixel region is formed between the gate line GL2b and the gate line GL2a, which are disposed in proximity to the gate line GL2a. The plurality of source lines SL2 are arranged at equal intervals in the row direction.

  FIG. 14 is a plan view showing the relationship between the pixel group DOT1 of the display panel LCP1 and the pixel group DOT2 of the display panel LCP2 that overlap each other in plan view, and FIG. 15 is a pixel group corresponding to FIG. It is a top view which shows the specific structure of pixel PIX1 of DOT1. FIG. 16 is a plan view showing a specific configuration of the pixel PIX2 of the pixel group DOT2 corresponding to FIG. The pixel group DOT1 includes two red pixels PIXR, two green pixels PIXG, and two blue pixels PIXB of the display panel LCP1, and the pixel group DOT2 includes three pixels PIX2a and three pixels of the display panel LCP2. It consists of a pixel PIX2b.

  As shown in FIG. 14B, in the pixel PIX2a, the source line SL2 is connected to the source electrode of the thin film transistor TFT2a, the gate line GL2a is connected to the gate electrode of the thin film transistor TFT2a, and the pixel electrode PX2a (FIG. 16). Is connected to the drain electrode DDa (see FIG. 16) of the thin film transistor TFT2a. In the pixel PIX2b, the source line SL2 is connected to the source electrode of the thin film transistor TFT2b, the gate line GL2b is connected to the gate electrode of the thin film transistor TFT2b, and the pixel electrode PX2b (see FIG. 16) is the drain electrode DDb of the thin film transistor TFT2b. (See FIG. 16).

  As shown in FIG. 16, the black matrix BM2 of the display panel LCP2 extends in the row direction so as to overlap the gate line GL2, and is formed in a stripe shape. That is, the black matrix BM2 of the display panel LCP2 includes a plurality of row stripe portions BM2a overlapping the gate lines GL2 of the display panel LCP2 in plan view. The black matrix BM2 does not include a portion extending in the column direction so as to cover the entire source line SL2 in plan view. As shown in FIG. 16, the length L2 in the column direction of the row stripe portion BM2a of the black matrix BM2 is the sum of the length in the column direction of the gate line GL2a and the length in the column direction of the gate line GL2b ( (Length in the column direction of two gate lines GL2). The length L2 in the column direction of the row stripe portion BM2a of the black matrix BM2 is longer than the length L1 in the column direction of the row stripe portion BM1a of the black matrix BM1.

  17 is a cross-sectional view taken along the line 17-17 ′ of FIGS. 15 and 16, and FIG. 18 is a cross-sectional view taken along the line 18-18 ′ of FIGS. A cross-sectional structure of the pixels PIX1 and PIX2 will be described with reference to FIGS.

  As shown in FIG. 17, the source lines SL1 and SL2 are arranged at equal intervals in the row direction, and the source lines SL1 and SL2 are arranged so as to overlap each other in plan view. As shown in FIG. 18, gate lines GL2a and GL2b are formed on the transparent substrate SUB4. The gate lines GL2a and GL2b are arranged close to each other, and the pair of gate lines GL2a and GL2b are arranged so as to overlap with one row stripe portion BM2a of the black matrix BM2 in plan view. In the display panel LCP2, the common wiring CL is formed on the common electrode CT. The common line CL extends in the row direction in a plan view and is disposed so as to overlap the black matrix BM1. Note that the column-direction length L1 (see FIG. 15) of the row stripe portion BM1a of the black matrix BM1 is longer than the column-direction length L4 (see FIG. 16) of the common wiring CL.

  Thus, in the display panel LCP2, the gate line GL2a electrically connected to the pixel electrode PX2a (see FIG. 16) in the plan view is disposed below the pixel electrode PX2a, and the pixel electrode PX2b ( A gate line GL2b that is electrically connected to the pixel electrode PX2b is disposed on the pixel electrode PX2b. Further, the gate line GL2 is not disposed between the upper side of the pixel electrode PX2a and the lower side of the pixel electrode PX2b.

  According to the configuration of the second embodiment, similarly to the configuration of the first embodiment, each pixel PIX1 of the display panel LCP1 and each pixel PIX2 of the display panel LCP2 are arranged in a one-to-one relationship. , PIX2 can be controlled independently. For this reason, since light leakage can be reduced as compared with the conventional configuration, the color reproducibility of the monochrome image of each color can be improved. In addition, it is possible to suppress the occurrence of uneven brightness and a decrease in the aperture ratio of the pixel.

  The configuration of the drivers of the display panel LCP1 and the display panel LCP2 is the same as that shown in FIG.

[Embodiment 3]
FIG. 19 is a plan view showing a schematic configuration of the display panel LCP1 according to the third embodiment, and FIG. 20 is a plan view showing a schematic configuration of the display panel LCP2 according to the third embodiment. The configuration of the display panel LCP1 according to the third embodiment is the same as the configuration of the display panel LCP1 according to the first embodiment.

  The display panel LCP2 according to the third embodiment generally has a pixel PIX2b having a size different from that of the display panel LCP2 according to the first embodiment, and the other configurations are the same.

  FIG. 21 is a plan view showing the relationship between the pixel group DOT1 of the display panel LCP1 and the pixel group DOT2 of the display panel LCP2 that overlap each other in plan view, and FIG. 22 is a pixel group DOT1, DOT2 corresponding to FIG. It is a top view which shows the specific structure of these pixels PIX1, PIX2. The pixel group DOT1 includes one red pixel PIXR, one green pixel PIXG, and one blue pixel PIXB of the display panel LCP1, and the pixel group DOT2 includes one pixel PIX2a and one pixel PIX2a of the display panel LCP2. It consists of a pixel PIX2b.

  The display panel LCP2 according to the third embodiment is configured such that the number of pixels PIX2 per unit area is smaller than the number of pixels PIX1 per unit area of the display panel LCP1. Specifically, as shown in FIG. 21 and FIG. 22, one pixel PIX1 (one red pixel PIXR) of the display panel LCP1 and one pixel PIX2a of the display panel LCP2 are mutually in plan view. Two pixels PIX1 (one green pixel PIXG and one blue pixel PIXB) of the display panel LCP1 and one pixel PIX2b of the display panel LCP2 are overlapped with each other in plan view. Has been. When the area (size) of each pixel PIX1 of the display panel LCP1 is equal to each other, the area of the pixel PIX2a of the display panel LCP2 is equal to the area of one pixel PIX1 of the display panel LCP1, and the area of the pixel PIX2b of the display panel LCP2 Is twice the area of one pixel PIX1 of the display panel LCP1. The area of one pixel PIX2b is equal to the total area of the area of one green pixel PIXG and the area of one blue pixel PIXB.

  As shown in FIG. 21B, in the pixel PIX2a, the source line SL2a is connected to the source electrode of the thin film transistor TFT2a, the gate line GL2 is connected to the gate electrode of the thin film transistor TFT2a, and the pixel electrode PX2a (FIG. 22). (See (b)) is connected to the drain electrode DDa (see FIG. 22B) of the thin film transistor TFT2a. In the pixel PIX2b, the source line SL2b is connected to the source electrode of the thin film transistor TFT2b, the gate line GL2 is connected to the gate electrode of the thin film transistor TFT2b, and the pixel electrode PX2b (see FIG. 22B) is connected to the thin film transistor TFT2b. The drain electrode DDb (see FIG. 22B) is connected. Further, as shown in FIG. 22, the length L2 in the column direction of the row stripe portion BM2a of the black matrix BM2 is shorter than the length L1 in the column direction of the row stripe portion BM1a of the black matrix BM1. In the row stripe portion BM2a, the length L3 in the column direction of the region (center portion) between the thin film transistors TFT2a and TFT2b is shorter than the length L2 in the column direction of the portion covering the thin film transistors TFT2a and TFT2b.

  23 is a cross-sectional view taken along the line 23-23 ′ of FIG. 22, and FIG. 24 is a cross-sectional view taken along the line 24-24 ′ of FIG. A cross-sectional structure of the pixels PIX1 and PIX2 will be described with reference to FIGS.

  As shown in FIG. 23, source lines SL2a and SL2b are formed on the gate insulating film GSN of the transparent substrate SUB4. The source lines SL2a and SL2b are arranged close to each other, and a part of the pair of source lines SL2a and SL2b is one column stripe portion BM2b of the black matrix BM1 in plan view (see FIG. 22A). It arrange | positions so that it may overlap.

  According to the configuration of the third embodiment, since the red pixel PIXR of the display panel LCP1 and the pixel PIX2a of the display panel LCP2 are arranged in a one-to-one relationship, on / off of the red pixel PIXR and the pixel PIX2a that overlap each other. Can be controlled independently of other pixels. For this reason, when displaying a red monochromatic image, the light leakage of the green component G and the blue component B can be suppressed. Therefore, the color reproducibility of the red image can be improved as compared with the conventional configuration. Further, similarly to the first embodiment, it is possible to suppress the occurrence of luminance unevenness and the decrease in the aperture ratio of the pixel.

  FIG. 25 is a diagram illustrating a configuration of drivers of the display panel LCP1 and the display panel LCP2. The display panel LCP1 is connected to six TCPs, each of which is mounted with a source driver IC (SIC), and each TCP is connected to the source printed circuit board SKIB. On the other hand, the display panel LCP2 is connected with four TCPs each mounted with a source driver IC (SIC), and each TCP is connected to the source printed circuit board SKIB. Thus, since the number of source driver ICs of the display panel LCP2 can be reduced as compared with the display panel LCP1, the cost of the liquid crystal display device LCD can be reduced.

  The display panel LCP1 according to the third embodiment may include white pixels. In this case, one pixel PIX2b of the display panel LCP2 may be superimposed on one green pixel PIXG, one blue pixel PIXB, and one white pixel in plan view.

[Embodiment 4]
FIG. 26 is a plan view showing a schematic configuration of the display panel LCP1 according to the fourth embodiment, and FIG. 27 is a plan view showing a schematic configuration of the display panel LCP2 according to the fourth embodiment. Schematically, the configuration of the display panel LCP1 according to the fourth embodiment is the same as the configuration of the display panel LCP2 according to the third embodiment (see FIG. 20), and the configuration of the display panel LCP2 according to the fourth embodiment is similar to that of the embodiment. The configuration is the same as that of the display panel LCP1 according to the third embodiment (see FIG. 19). That is, in the liquid crystal display device LCD according to the fourth embodiment, the display panel LCP1 displays a monochrome image, and the display panel LCP2 displays a color image.

  In the display panel LCP1 according to the fourth embodiment, as illustrated in FIG. 26, the plurality of source lines SL1 includes a plurality of source lines SL1a and a plurality of source lines SL1b in plan view. The plurality of source lines SL1a are arranged at equal intervals in the row direction, and the plurality of source lines SL1b are arranged at equal intervals in the row direction. The source line SL1a and the source line SL1b are alternately arranged in the row direction. Two pixels PIX1 (PIX1a, PIX1b) are arranged in a region (pixel region) surrounded by adjacent source lines SL1a, SL1b and two adjacent gate lines GL1 when the display panel LCP1 is viewed in plan view. They are arranged side by side. The plurality of pixels PIX1 are arranged in a matrix (row direction and column direction). Between the source line SL1a and the source line SL1b arranged away from the source line SL1a, a pixel region is formed and two pixels PIX1 (PIX1a, PIX1b) are arranged. On the other hand, a pixel region is not formed between the source line SL1a and the source line SL1b arranged close to the source line SL1a. The plurality of gate lines GL1 are arranged at equal intervals in the column direction.

  As shown in FIG. 28, the counter substrate CF1 of the display panel LCP1 is formed with a light transmission part that transmits light and a black matrix BM1 that blocks light transmission. In the light transmission portion, the color filter FIL is not formed, and for example, an overcoat film OC is formed. The counter substrate CF2 of the display panel LCP2 is formed with a light transmission portion and a black matrix BM2, and the light transmission portion is formed with a plurality of color filters FIL corresponding to each pixel PIX1. .

  29 is a plan view showing the relationship between the pixel group DOT1 of the display panel LCP1 and the pixel group DOT2 of the display panel LCP2 that overlap each other in plan view, and FIG. 30 is a pixel group DOT1, DOT2 corresponding to FIG. It is a top view which shows the specific structure of these pixels PIX1, PIX2. The pixel group DOT1 includes one pixel PIX1a and one pixel PIX1b of the display panel LCP1, and the pixel group DOT2 includes one red pixel PIXR, one green pixel PIXG, and one blue pixel of the display panel LCP2. It consists of pixels PIXB.

  The display panel LCP1 according to the fourth embodiment is configured such that the number of pixels PIX1 per unit area is smaller than the number of pixels PIX2 per unit area of the display panel LCP2. Specifically, as shown in FIG. 29 and FIG. 30, one pixel PIX1a of the display panel LCP1 and one pixel PIX2 (one red pixel PIXR) of the display panel LCP2 are mutually in plan view. Overlapping, one pixel PIX1b of the display panel LCP1 and two pixels PIX2 (one green pixel PIXG and one blue pixel PIXB) of the display panel LCP2 are configured to overlap each other in plan view Has been. When the area (size) of each pixel PIX2 of the display panel LCP2 is equal to each other, the area of the pixel PIX1a of the display panel LCP1 is equal to the area of one pixel PIX2 of the display panel LCP2, and the area of the pixel PIX1b of the display panel LCP1. Is twice the area of one pixel PIX2 of the display panel LCP2. The area of one pixel PIX1b is equal to the total area of the area of one green pixel PIXG and the area of one blue pixel PIXB.

  As shown in FIG. 29A, in the pixel PIX1a, the source line SL1a is connected to the source electrode of the thin film transistor TFT1a, the gate line GL1 is connected to the gate electrode of the thin film transistor TFT1a, and the pixel electrode PX1a (FIG. 30). (See (a)) is connected to the drain electrode DDa (see FIG. 30A) of the thin film transistor TFT1a. In the pixel PIX1b, the source line SL1b is connected to the source electrode of the thin film transistor TFT1b, the gate line GL1 is connected to the gate electrode of the thin film transistor TFT1b, and the pixel electrode PX1b (see FIG. 30A) is connected to the thin film transistor TFT1b. It is connected to the drain electrode DDb (see FIG. 30A). Further, the black matrix BM1 of the display panel LCP1 has a plurality of row stripe portions BM1a that overlap each of the plurality of gate lines GL1 of the display panel LCP1 in plan view, and the source lines SL1 and SL2 of the display panel LCP1 in plan view. A plurality of overlapping column stripe portions BM1b are included. As shown in FIG. 30, the length L1 in the column direction of the row stripe portion BM1a of the black matrix BM1 is longer than the length L2 in the column direction of the row stripe portion BM2a of the black matrix BM2. The length W1 in the row direction of the column stripe portion BM1b of the black matrix BM1 is longer than the length W2 in the row direction of the column stripe portion BM2b of the black matrix BM2.

  31 is a cross-sectional view taken along the line 31-31 ′ of FIG. 30, and FIG. 32 is a cross-sectional view taken along the line 32-32 ′ of FIG. A cross-sectional structure of the pixels PIX1 and PIX2 will be described with reference to FIGS.

  As shown in FIG. 31, source lines SL1a and SL1b are formed on the gate insulating film GSN of the transparent substrate SUB2. The source lines SL1a and SL1b are arranged close to each other, and the pair of source lines SL1a and SL1b overlap with one column stripe portion BM1b (see FIG. 30A) of the black matrix BM1 in plan view. Are arranged as follows.

  According to the configuration of the fourth embodiment, similar to the configuration of the third embodiment, the pixels PIX1a of the display panel LCP1 and the red pixels PIXR of the display panel LCP2 are arranged in a one-to-one relationship. On / off of the PIX1a and the red pixel PIXR can be controlled independently of other pixels. For this reason, when displaying a red monochromatic image, the light leakage of the green component G and the blue component B can be suppressed. Therefore, the color reproducibility of the red image can be improved as compared with the conventional configuration.

  In the liquid crystal display device LCD according to the fourth embodiment, the length L2 (see FIG. 30) of the row stripe portion BM2a of the black matrix BM2 of the display panel LCP2 is equal to the column direction of the row stripe portion BM1a of the black matrix BM1. Is shorter than the length L1 (see FIG. 30). Further, the length W2 (see FIG. 30) in the row direction of the column stripe portion BM2b of the black matrix BM2 is shorter than the length W1 (see FIG. 30) in the row direction of the column stripe portion BM1b of the black matrix BM1. The display panel LCP1 according to the fourth embodiment corresponds to the panel B of the configuration example 5 in FIG. 66, and the display panel LCP2 according to the fourth embodiment corresponds to the panel A of the configuration example 5 in FIG. According to the above configuration, as shown in Configuration Example 5, even when the display panel LCP1 and the display panel LCP2 are misaligned, the influence of the misalignment of the black matrices BM1 and BM2 is small. It becomes difficult to occur. Therefore, it is possible to suppress the occurrence of moire and a decrease in the aperture ratio of the pixel.

  FIG. 33 is a diagram illustrating a configuration of drivers of the display panel LCP1 and the display panel LCP2. Four TCPs each mounted with a source driver IC (SIC) are connected to the display panel LCP1, and each TCP is connected to the source printed circuit board SKIB. In contrast, the display panel LCP2 is connected to six TCPs each having a source driver IC (SIC) mounted thereon, and each TCP is connected to the source printed circuit board SKIB. As described above, since the number of source driver ICs of the display panel LCP1 can be reduced as compared with the display panel LCP2, the cost of the liquid crystal display device LCD can be reduced.

[Embodiment 5]
The configuration of the display panel LCP1 according to the fifth embodiment is the same as the configuration of the display panel LCP1 according to the fourth embodiment. The configuration of the display panel LCP2 according to the fifth embodiment is different from the configuration of the display panel LCP2 according to the fourth embodiment in the configuration of the black matrix BM2, and the other configurations are the same.

  FIG. 34 shows a specific configuration of the pixel PIX1 of the pixel group DOT1 of the display panel LCP1 and the pixel PIX2 of the pixel group DOT2 of the display panel LCP2 that overlap each other in plan view in the liquid crystal display device LCD according to the fifth embodiment. FIG. 35 is a cross-sectional view taken along the line 35-35 ′ of FIG. The cross-sectional configuration taken along the line 32-32 ′ of FIG. 34 is the same as the cross-sectional configuration shown in FIG.

  As shown in FIG. 34, the black matrix BM2 of the display panel LCP2 according to Embodiment 5 extends in the row direction so as to overlap the gate line GL2, and is formed in a stripe shape. That is, the black matrix BM2 of the display panel LCP2 includes a plurality of row stripe portions BM2a overlapping each of the plurality of gate lines GL2 of the display panel LCP2 in plan view, and extends in the column direction so as to cover the entire source line SL2. Does not include the part to be. The length L2 in the column direction of the row stripe portion BM2a of the black matrix BM2 is shorter than the length L1 in the column direction of the row stripe portion BM1a of the black matrix BM1.

  According to the configuration of the fifth embodiment, the same effect as that of the fourth embodiment can be obtained. In the configuration of the fifth embodiment, since the black matrix BM2 of the display panel LCP2 is not formed in the column direction, as in the configuration example 4 of FIG. 66, the occurrence of luminance unevenness and moire, and the aperture ratio of the pixel The decrease can be suppressed.

[Embodiment 6]
FIG. 36 is a plan view showing a schematic configuration of the display panel LCP1 according to the sixth embodiment, and FIG. 37 is a plan view showing a schematic configuration of the display panel LCP2 according to the sixth embodiment. The configuration of the display panel LCP1 according to the sixth embodiment is the same as the configuration of the display panel LCP1 according to the first embodiment.

  In the display panel LCP2 according to the sixth embodiment, as illustrated in FIG. 37, the plurality of source lines SL2 includes a plurality of source lines SL2a and a plurality of source lines SL2b as viewed in a plan view. The plurality of source lines SL2a are arranged at equal intervals in the row direction, and the plurality of source lines SL2b are arranged at equal intervals in the row direction. The source line SL2a and the source line SL2b are alternately arranged in the row direction. Two pixels PIX2 (PIX2a, PIX2b) are arranged in a region (pixel region) surrounded by adjacent source lines SL2a, SL2b and two adjacent gate lines GL2 when the display panel LCP2 is viewed in plan view. They are arranged side by side. The plurality of pixels PIX2 are arranged in a matrix (row direction and column direction). Between the source line SL2a and the source line SL2b arranged away from the source line SL2a, a pixel region is formed and two pixels PIX2 (PIX2a, PIX2b) are arranged. On the other hand, no pixel region is formed between the source line SL2a and the source line SL2b disposed in the vicinity of the source line SL2a. The plurality of gate lines GL2 are arranged at equal intervals in the column direction. The number of gate lines GL2 of the display panel LCP2 is half of the number of gate lines GL1 of the display panel LCP1.

  FIG. 38 is a plan view showing the relationship between the pixel group DOT1 of the display panel LCP1 and the pixel group DOT2 of the display panel LCP2 that overlap each other in plan view. FIG. 39 is a plan view showing a specific configuration of the pixel PIX1 of the pixel group DOT1 corresponding to FIG. 38A, and FIG. 40 shows a specific configuration of the pixel PIX2 of the pixel group DOT2 corresponding to FIG. It is a top view which shows a typical structure. The pixel group DOT1 includes two red pixels PIXR, two green pixels PIXG, and two blue pixels PIXB of the display panel LCP1, and the pixel group DOT2 includes one pixel PIX2a and one pixel of the display panel LCP2. It consists of a pixel PIX2b.

  The display panel LCP2 according to the sixth embodiment is configured such that the number of pixels PIX2 per unit area is smaller than the number of pixels PIX1 per unit area of the display panel LCP1. Specifically, as shown in FIGS. 38 and 39, two pixels PIX1 (two red pixels PIXR) of the display panel LCP1 and one pixel PIX2a of the display panel LCP2 are mutually viewed in plan view. The four pixels PIX1 (two green pixels PIXG and two blue pixels PIXB) of the display panel LCP1 and the one pixel PIX2b of the display panel LCP2 overlap each other in plan view. Has been. When the area (size) of each pixel PIX1 of the display panel LCP1 is equal to each other, the area of the pixel PIX2a of the display panel LCP2 is equal to twice the area of one pixel PIX1 of the display panel LCP1, and the pixels of the display panel LCP2 The area of PIX2b is equal to four times the area of one pixel PIX1 of the display panel LCP2.

  As shown in FIGS. 39 and 40, the length L2 in the column direction of the row stripe portion BM2a of the black matrix BM2 is shorter than the length L1 in the column direction of the row stripe portion BM1a of the black matrix BM1. In the row stripe portion BM2a, the length L3 in the column direction of the region (center portion) between the thin film transistors TFT2a and TFT2b is shorter than the length L2 in the column direction of the portion covering the thin film transistors TFT2a and TFT2b.

  41 is a cross-sectional view taken along the line 41-41 ′ of FIGS. 39 and 40. FIG. The cross-sectional configuration taken along the line 23-23 ′ in FIGS. 39 and 40 is the same as the cross-sectional configuration shown in FIG. As shown in FIG. 41, the gate line GL2 is arranged so as to overlap with the gate line GL1 in a plan view, and the common wiring CL extends in the row direction and is arranged so as to overlap with the black matrix BM1. .

  According to the configuration of the sixth embodiment, the two red pixels PIXR of the display panel LCP1 and the one pixel PIX2a of the display panel LCP2 are arranged in a one-to-one relationship. The on / off state of the pixel PIX2a can be controlled independently of other pixels. For this reason, when displaying a red monochromatic image, the light leakage of the green component G and the blue component B can be suppressed. Therefore, the color reproducibility of the red image can be improved as compared with the conventional configuration. In addition, since the number of row stripe portions BM2a of the black matrix BM2 is small as compared with the configuration of the third embodiment, it is possible to further suppress occurrence of luminance unevenness and moire and a decrease in pixel aperture ratio.

  FIG. 42 is a diagram illustrating a configuration of drivers of the display panel LCP1 and the display panel LCP2. The display panel LCP1 is connected to six TCPs, each of which is mounted with a source driver IC (SIC), and each TCP is connected to the source printed circuit board SKIB. On the other hand, the display panel LCP2 is connected with four TCPs each mounted with a source driver IC (SIC), and each TCP is connected to the source printed circuit board SKIB. In addition, four gate driver ICs (GIC) are mounted on the display panel LCP1, whereas two gate driver ICs (GIC) are mounted on the display panel LCP2. Thus, since the number of source driver ICs and gate driver ICs of the display panel LCP2 can be reduced as compared with the display panel LCP1, the cost of the liquid crystal display device LCD can be reduced.

[Embodiment 7]
FIG. 43 is a plan view showing a schematic configuration of the display panel LCP2 according to the seventh embodiment. The configuration of the display panel LCP1 according to the seventh embodiment is the same as the configuration of the display panel LCP1 according to the third embodiment (see FIG. 19).

  In the display panel LCP2 according to the seventh embodiment, as illustrated in FIG. 43, the plurality of gate lines GL2 includes a plurality of gate lines GL2a and a plurality of gate lines GL2b. The plurality of gate lines GL2a are arranged at equal intervals in the column direction, and the plurality of gate lines GL2b are arranged at equal intervals in the column direction. The gate lines GL2a and the gate lines GL2b are alternately arranged in the column direction. When the display panel LCP2 is viewed in plan view, two pixels PIX2 (PIX2a, PIX2b) are present in a region (pixel region) surrounded by the adjacent gate lines GL2a, GL2b and the two adjacent source lines SL2. They are arranged side by side in the row direction. The plurality of pixels PIX2 are arranged in a matrix (row direction and column direction). A pixel region is formed between the gate line GL2a and the gate line GL2b disposed away from the gate line GL2a, and two pixels PIX2 (PIX2a and PIX2b) are disposed. On the other hand, no pixel region is formed between the gate line GL2a and the gate line GL2b disposed in the vicinity of the gate line GL2a. Further, the number of gate lines GL2 of the display panel LCP2 is twice the number of gate lines GL1 of the display panel LCP1. Further, the gate line GL1 of the display panel LCP1 and the gate line GL2 of the display panel LCP2 are arranged so as to overlap each other in plan view. Note that the gate line GL1 of the display panel LCP1 may overlap with the gate line GL2a of the display panel LCP2, or may overlap with the gate line GL2b of the display panel LCP2, or may be overlapped with the gate lines GL2a and GL2b. You may superimpose on the area | region between. The plurality of source lines SL2 are arranged at equal intervals in the row direction.

  44 is a plan view showing the relationship between the pixel group DOT1 of the display panel LCP1 and the pixel group DOT2 of the display panel LCP2 that overlap each other in plan view, and FIG. 45 is a group of pixels DOT1, DOT2 corresponding to FIG. It is a top view which shows the specific structure of these pixels PIX1, PIX2. The pixel group DOT1 includes one red pixel PIXR, one green pixel PIXG, and one blue pixel PIXB of the display panel LCP1, and the pixel group DOT2 includes one pixel PIX2a and one pixel PIX2a of the display panel LCP2. It consists of a pixel PIX2b.

  In plan view, the pixel PIX2a of the display panel LCP2 is superimposed on the red pixel PIXR of the display panel LCP1, and the pixel PIX2b of the display panel LCP2 is superimposed on the green pixel PIXG and the blue pixel PIXB of the display panel LCP1.

  As shown in FIG. 44B, in the pixel PIX2a, the source line SL2 (here, the source line SL2s) is connected to the source electrode of the thin film transistor TFT2a, and the gate line GL2a is connected to the gate electrode of the thin film transistor TFT2a. The pixel electrode PX2a (see FIG. 45B) is connected to the drain electrode DDa (see FIG. 45B) of the thin film transistor TFT2a. In the pixel PIX2b, the extending portion SD (see FIG. 45B) of the source line SL2s is connected to the source electrode of the thin film transistor TFT2b, the gate line GL2b is connected to the gate electrode of the thin film transistor TFT2b, and the pixel electrode PX2b (See FIG. 45B) is connected to the drain electrode DDb (see FIG. 45B) of the thin film transistor TFT2b.

  As shown in FIG. 45, the black matrix BM2 of the display panel LCP2 extends in the row direction so as to overlap the gate line GL2, and is formed in a stripe shape. That is, the black matrix BM2 of the display panel LCP2 includes a plurality of row stripe portions BM2a overlapping the gate lines GL2 of the display panel LCP2 in plan view. The black matrix BM2 does not include a portion extending in the column direction so as to cover the entire source line SL2 in plan view. As shown in FIG. 45, the length L2 in the column direction of the row stripe portion BM2a of the black matrix BM2 is the total length of the length in the column direction of the gate line GL2a and the length in the column direction of the gate line GL2b ( (Length in the column direction of two gate lines GL2). The length L2 in the column direction of the row stripe portion BM2a of the black matrix BM2 is longer than the length L1 in the column direction of the row stripe portion BM1a of the black matrix BM1.

  46 is a cross-sectional view taken along the line 46-46 ′ of FIG. As shown in FIG. 46, the source lines SL1 and SL2 are arranged at equal intervals in the row direction. Further, in plan view, the source line SL2 is disposed at a boundary portion between the blue pixel PIXB and the red pixel PIXR.

  As described above, in the display panel LCP2, the gate line GL2a electrically connected to the pixel electrode PX2a (see FIG. 45B) in a plan view is disposed below the pixel electrode PX2a. A gate line GL2b electrically connected to the electrode PX2b (see FIG. 45B) is disposed above the pixel electrode PX2b. The pixel electrodes PX2a and PX2b are electrically connected to the same source line SL2 (source line SL2s in FIG. 45B). In the above configuration, the display panel LCP2 is driven (double speed driving) at a frame frequency (for example, 120 Hz) that is twice the frame frequency (for example, 60 Hz) in the display panel LCP1.

  According to the configuration of the seventh embodiment, similar to the configuration of the third embodiment, the red pixel PIXR of the display panel LCP1 and the pixel PIX2a of the display panel LCP2 are arranged in a one-to-one relationship, so On / off of the pixel PIXR and the pixel PIX2a can be controlled independently of other pixels. For this reason, when displaying a red monochromatic image, the light leakage of the green component G and the blue component B can be suppressed. Therefore, the color reproducibility of the red image can be improved as compared with the conventional configuration. In addition, it is possible to suppress the occurrence of luminance unevenness and moire and a decrease in the aperture ratio of the pixel.

  FIG. 47 is a diagram illustrating a configuration of drivers of the display panel LCP1 and the display panel LCP2. The display panel LCP1 is connected to six TCPs, each of which is mounted with a source driver IC (SIC), and each TCP is connected to the source printed circuit board SKIB. In contrast, the display panel LCP2 is connected to two TCPs each mounted with a source driver IC (SIC), and each TCP is connected to the source printed circuit board SKIB. In addition, four gate driver ICs (GIC) are mounted on the display panel LCP1, whereas eight gate driver ICs (GIC) are mounted on the display panel LCP2.

[Embodiment 8]
FIG. 48 is a plan view showing a schematic configuration of the display panel LCP2 according to the eighth embodiment. The configuration of the display panel LCP1 according to the eighth embodiment is the same as the configuration of the display panel LCP1 according to the sixth embodiment (see FIG. 36).

  In the display panel LCP2 according to the eighth embodiment, as shown in FIG. 48, the plurality of gate lines GL2 includes a plurality of gate lines GL2a and a plurality of gate lines GL2b. The plurality of gate lines GL2a are arranged at equal intervals in the column direction, and the plurality of gate lines GL2b are arranged at equal intervals in the column direction. The gate lines GL2a and the gate lines GL2b are alternately arranged in the column direction. When the display panel LCP2 is viewed in plan view, two pixels PIX2 (PIX2a, PIX2b) are present in a region (pixel region) surrounded by the adjacent gate lines GL2a, GL2b and the two adjacent source lines SL2. They are arranged side by side in the row direction. The plurality of pixels PIX2 are arranged in a matrix (row direction and column direction). A pixel region is formed between the gate line GL2a and the gate line GL2b disposed away from the gate line GL2a, and two pixels PIX2 (PIX2a and PIX2b) are disposed. On the other hand, no pixel region is formed between the gate line GL2a and the gate line GL2b disposed in the vicinity of the gate line GL2a. The plurality of source lines SL2 are arranged at equal intervals in the row direction.

  49 is a plan view showing the relationship between the pixel group DOT1 of the display panel LCP1 and the pixel group DOT2 of the display panel LCP2 that overlap each other in plan view, and FIG. 50 is a pixel group corresponding to FIG. It is a top view which shows the specific structure of the pixel PIX2 of DOT2. Note that the specific configuration of the pixel PIX1 of the pixel group DOT1 corresponding to FIG. 49A is the same as the configuration shown in FIG. The pixel group DOT1 includes two red pixels PIXR, two green pixels PIXG, and two blue pixels PIXB of the display panel LCP1, and the pixel group DOT2 includes one pixel PIX2a and one pixel of the display panel LCP2. It consists of a pixel PIX2b.

  In plan view, the pixel PIX2a of the display panel LCP2 overlaps with two pixels PIX1 (two red pixels PIXR) of the display panel LCP1, and the pixel PIX2b of the display panel LCP2 includes four pixels PIX1 of the display panel LCP1. It is superimposed on (two green pixels PIXG and two blue pixels PIXB).

  As shown in FIG. 49B, in the pixel PIX2a, the source line SL2 (here, the source line SL2s) is connected to the source electrode of the thin film transistor TFT2a, and the gate line GL2a is connected to the gate electrode of the thin film transistor TFT2a. The pixel electrode PX2a (see FIG. 50) is connected to the drain electrode DDa (see FIG. 50) of the thin film transistor TFT2a. In the pixel PIX2b, the extended portion SD (see FIG. 50) of the source line SL2s is connected to the source electrode of the thin film transistor TFT2b, the gate line GL2b is connected to the gate electrode of the thin film transistor TFT2b, and the pixel electrode PX2b (FIG. 50). Is connected to the drain electrode DDb (see FIG. 50) of the thin film transistor TFT2b.

  As shown in FIG. 50, the black matrix BM2 of the display panel LCP2 extends in the row direction so as to overlap the gate line GL2, and is formed in a stripe shape. That is, the black matrix BM2 of the display panel LCP2 includes a plurality of row stripe portions BM2a overlapping the gate lines GL2 of the display panel LCP2 in plan view. The black matrix BM2 does not include a portion extending in the column direction so as to cover the entire source line SL2 in plan view. As shown in FIG. 50, the length L2 in the column direction of the row stripe portion BM2a of the black matrix BM2 is the sum of the length in the column direction of the gate line GL2a and the length in the column direction of the gate line GL2b ( (Length in the column direction of two gate lines GL2). The length L2 in the column direction of the row stripe portion BM2a of the black matrix BM2 is longer than the length L1 in the column direction of the row stripe portion BM1a of the black matrix BM1 (see FIG. 39).

  The cross-sectional configuration taken along the line 46-46 ′ of FIG. 50 is the same as the configuration shown in FIG.

  Thus, in the display panel LCP2, the gate line GL2a electrically connected to the pixel electrode PX2a (see FIG. 50) in the plan view is disposed below the pixel electrode PX2a, and the pixel electrode PX2b ( A gate line GL2b electrically connected to the pixel electrode PX2b is disposed on the pixel electrode PX2b. The pixel electrodes PX2a and PX2b are electrically connected to the same source line SL2 (source line SL2s in FIG. 50). In the above configuration, the display panel LCP2 is driven (double speed driving) at a frame frequency (for example, 120 Hz) that is twice the frame frequency (for example, 60 Hz) in the display panel LCP1. Further, the display panel LCP2 sets the selection time (writing time) of each gate line GL2 to twice (2H) the selection time (one horizontal period) of each gate line GL1 in the display panel LCP1.

  According to the configuration of the eighth embodiment, similarly to the configuration of the sixth embodiment, the two red pixels PIXR of the display panel LCP1 and the one pixel PIX2a of the display panel LCP2 are arranged in a one-to-one relationship. Therefore, on / off of the red pixel PIXR and the pixel PIX2a that overlap each other can be controlled independently of other pixels. For this reason, when displaying a red monochromatic image, the light leakage of the green component G and the blue component B can be suppressed. Therefore, the color reproducibility of the red image can be improved as compared with the conventional configuration. Further, similarly to the configuration of the sixth embodiment, it is possible to suppress the occurrence of luminance unevenness and moire and the decrease in the aperture ratio of the pixel.

  FIG. 51 is a diagram illustrating a configuration of drivers of the display panel LCP1 and the display panel LCP2. The display panel LCP1 is connected to six TCPs, each of which is mounted with a source driver IC (SIC), and each TCP is connected to the source printed circuit board SKIB. In contrast, the display panel LCP2 is connected to two TCPs each mounted with a source driver IC (SIC), and each TCP is connected to the source printed circuit board SKIB. Thus, since the number of source driver ICs of the display panel LCP2 can be reduced as compared with the display panel LCP1, the cost of the liquid crystal display device LCD can be reduced.

[Embodiment 9]
52 is a plan view showing a schematic configuration of the display panel LCP1 according to the ninth embodiment, and FIG. 53 is a plan view showing a schematic configuration of the display panel LCP2 according to the ninth embodiment. The configuration of the display panel LCP1 according to the ninth embodiment is the same as the configuration of the display panel LCP1 according to the first embodiment.

  In the display panel LCP2 according to the ninth embodiment, as shown in FIG. 53, the plurality of gate lines GL2 includes a plurality of gate lines GL2a and a plurality of gate lines GL2b. The plurality of gate lines GL2a are arranged at equal intervals in the column direction, and the plurality of gate lines GL2b are arranged at equal intervals in the column direction. The gate lines GL2a and the gate lines GL2b are alternately arranged in the column direction. The plurality of source lines SL2 include a plurality of source lines SL2a, a plurality of source lines SL2b, and a plurality of source lines SL2c. The source lines SL2a, SL2b, and SL2c are repeatedly arranged in this order in the row direction. In addition, when the display panel LCP2 is viewed in plan view, three pixels PIX2 (PIX2a, PIX2b, PIX2b, PIX2a, PIX2b, PIX2c) are arranged side by side in the row direction. Similarly, when viewing the display panel LCP2 in plan view, three pixels PIX2 (PIX2a, PIX2b) are arranged in a region (pixel region) surrounded by the adjacent gate lines GL2a, GL2b and the adjacent source lines SL2b, SL2C. , PIX2c) are arranged side by side in the row direction. The plurality of pixels PIX2 are arranged in a matrix (row direction and column direction). A pixel region is formed between the gate line GL2a and the gate line GL2b arranged away from the gate line GL2a, and three pixels PIX2 (PIX2a, PIX2b, PIX2c) are arranged. On the other hand, no pixel region is formed between the gate line GL2a and the gate line GL2b disposed in the vicinity of the gate line GL2a. Further, a pixel region is formed between the source line SL2a and the source line SL2b that is spaced apart from the source line SL2a, and three pixels PIX2 (PIX2a, PIX2b, PIX2c) are arranged. In addition, a pixel region is formed between the source line SL2b and the source line SL2c arranged away from the source line SL2b, and three pixels PIX2 (PIX2a, PIX2b, PIX2c) are arranged. . On the other hand, a pixel region is not formed between the source line SL2a and the source line SL2c arranged close to the source line SL2a. Further, the number of gate lines GL2 of the display panel LCP2 is twice the number of gate lines GL1 of the display panel LCP1. Further, the gate line GL1 of the display panel LCP1 and the gate line GL2 of the display panel LCP2 are arranged so as to overlap each other in plan view. Note that the gate line GL1 of the display panel LCP1 may overlap with the gate line GL2a of the display panel LCP2, or may overlap with the gate line GL2b of the display panel LCP2, or may be overlapped with the gate lines GL2a and GL2b. You may superimpose on the area | region between.

  FIG. 54 is a plan view showing the relationship between the pixel group DOT1 of the display panel LCP1 and the pixel group DOT2 of the display panel LCP2 that overlap each other in plan view. The pixel group DOT1 includes two red pixels PIXR, two green pixels PIXG, and two blue pixels PIXB of the display panel LCP1, and the pixel group DOT2 includes two pixels PIX2a and two pixels of the display panel LCP2. It consists of a pixel PIX2b and two pixels PIX2c. In the following, for convenience of explanation, as shown in FIG. 54, the left three pixels PIX2 arranged between the source lines SL2a and SL2b in the pixel group DOT2 are respectively referred to as a pixel PIX2aL, a pixel PIX2bL, and a pixel PIX2cL. The right three pixels PIX2 disposed between the source lines SL2b and SL2c are referred to as a pixel PIX2aR, a pixel PIX2bR, and a pixel PIX2cR, respectively.

  In plan view, the pixel PIX2a (pixels PIX2aL, PIX2aR) of the display panel LCP2 overlaps the red pixel PIXR of the display panel LCP1, and the pixel PIX2b (pixels PIX2bL, PIX2bR) of the display panel LCP2 is a green pixel PIXG of the display panel LCP1. The pixel PIX2c (pixels PIX2cL, PIX2cR) of the display panel LCP2 is superimposed on the blue pixel PIXB of the display panel LCP1.

  As shown in FIG. 54B, in the pixel PIX2aL, the source line SL2a is connected to the source electrode of the thin film transistor TFT2aL, the gate line GL2a is connected to the gate electrode of the thin film transistor TFT2aL, and the pixel electrode PX2aL is connected to the thin film transistor TFT2aL. Connected to the drain electrode. In the pixel PIX2bL, the source line SL2a is connected to the source electrode of the thin film transistor TFT2bL, the gate line GL2b is connected to the gate electrode of the thin film transistor TFT2bL, and the pixel electrode PX2bL is connected to the drain electrode of the thin film transistor TFT2bL. In the pixel PIX2cL, the source line SL2b is connected to the source electrode of the thin film transistor TFT2cL, the gate line GL2b is connected to the gate electrode of the thin film transistor TFT2cL, and the pixel electrode PX2cL is connected to the drain electrode of the thin film transistor TFT2cL.

  In the pixel PIX2aR, the source line SL2b is connected to the source electrode of the thin film transistor TFT2aR, the gate line GL2a is connected to the gate electrode of the thin film transistor TFT2aR, and the pixel electrode PX2aR is connected to the drain electrode of the thin film transistor TFT2aR. In the pixel PIX2bR, the source line SL2c is connected to the source electrode of the thin film transistor TFT2bR, the gate line GL2b is connected to the gate electrode of the thin film transistor TFT2bR, and the pixel electrode PX2bR is connected to the drain electrode of the thin film transistor TFT2bR. In the pixel PIX2cR, the source line SL2c is connected to the source electrode of the thin film transistor TFT2cR, the gate line GL2a is connected to the gate electrode of the thin film transistor TFT2cR, and the pixel electrode PX2cR is connected to the drain electrode of the thin film transistor TFT2cR. In the display panel LCP2, a plurality of pixel groups DOT2 are arranged in a matrix (row direction and column direction).

  Similar to the configuration of the seventh embodiment (see FIG. 45B), the black matrix BM2 of the display panel LCP2 extends in the row direction so as to overlap the gate line GL2, and is formed in a stripe shape. In the above configuration, the display panel LCP2 is driven (double speed driving) at a frame frequency (for example, 120 Hz) that is twice the frame frequency (for example, 60 Hz) in the display panel LCP1.

  According to the configuration of the ninth embodiment, similar to the configuration of the first embodiment, each pixel PIX1 of the display panel LCP1 and each pixel PIX2 of the display panel LCP2 are arranged in a one-to-one relationship, and thus overlap each other. On / off of each pixel PIX1, PIX2 can be controlled independently. For this reason, since light leakage can be reduced as compared with the conventional configuration, the color reproducibility of the monochrome image of each color can be improved. In addition, it is possible to suppress the occurrence of luminance unevenness and moire and a decrease in the aperture ratio of the pixel.

  FIG. 55 is a diagram showing a configuration of drivers of the display panel LCP1 and the display panel LCP2. The display panel LCP1 is connected to six TCPs, each of which is mounted with a source driver IC (SIC), and each TCP is connected to the source printed circuit board SKIB. In contrast, the display panel LCP2 is connected with three TCPs each mounted with a source driver IC (SIC), and each TCP is connected to the source printed circuit board SKIB. In addition, four gate driver ICs (GIC) are mounted on the display panel LCP1, whereas eight gate driver ICs (GIC) are mounted on the display panel LCP2.

[Embodiment 10]
56 is a plan view showing a schematic configuration of the display panel LCP1 according to the tenth embodiment, and FIG. 57 is a plan view showing a schematic configuration of the display panel LCP2 according to the tenth embodiment. In the liquid crystal display device LCD according to the tenth embodiment, schematically, the display panel LCP1 includes a white pixel PIXW between the blue pixel PIXB and the red pixel PIXR in the display panel LCP1 according to the ninth embodiment (see FIG. 52). The display panel CLP2 has a configuration in which a pixel PIX2d that overlaps the white pixel PIXW is added to the display panel LCP2 (see FIG. 53) according to the ninth embodiment.

  In the display panel LCP2 according to the tenth embodiment, the plurality of source lines SL2 includes a plurality of source lines SL2a and a plurality of source lines SL2b. The plurality of source lines SL2a are arranged at equal intervals in the row direction, and the plurality of source lines SL2b are arranged at equal intervals in the row direction. The source lines SL2a and SL2b are alternately arranged in the row direction. When the display panel LCP2 is viewed in plan view, four pixels PIX2 (PIX2a, PIX2b, PIX2c, PIX2c, PIX2a, PIX2c, PIX2d) are arranged side by side in the row direction. The plurality of pixels PIX2 are arranged in a matrix (row direction and column direction). A pixel region is formed between the gate line GL2a and the gate line GL2b arranged away from the gate line GL2a, and four pixels PIX2 (PIX2a, PIX2b, PIX2c, PIX2d) are arranged. . On the other hand, no pixel region is formed between the gate line GL2a and the gate line GL2b disposed in the vicinity of the gate line GL2a. Further, a pixel region is formed between the source line SL2a and the source line SL2b that is spaced apart from the source line SL2a, and four pixels PIX2 (PIX2a, PIX2b, PIX2c, and PIX2d) are disposed. ing. On the other hand, no pixel region is formed between the source line SL2a and the source line SL2b disposed in the vicinity of the source line SL2a.

  FIG. 58 is a plan view showing the relationship between the pixel group DOT1 of the display panel LCP1 and the pixel group DOT2 of the display panel LCP2 that overlap each other in plan view. The pixel group DOT1 includes one red pixel PIXR, one green pixel PIXG, one blue pixel PIXB, and one white pixel PIXW of the display panel LCP1, and the pixel group DOT2 is one of the display panel LCP2. Each pixel PIX2a, one pixel PIX2b, one pixel PIX2c, and one pixel PIX2d.

  In plan view, the pixel PIX2a of the display panel LCP2 is superimposed on the red pixel PIXR of the display panel LCP1, the pixel PIX2b of the display panel LCP2 is superimposed on the green pixel PIXG of the display panel LCP1, and the pixel PIX2c of the display panel LCP2 is The pixel PIX2d of the display panel LCP1 is superimposed on the white pixel PIXW of the display panel LCP1.

  As shown in FIG. 58B, in the pixel PIX2a, the source line SL2a is connected to the source electrode of the thin film transistor TFT2a, the gate line GL2a is connected to the gate electrode of the thin film transistor TFT2a, and the pixel electrode PX2a is connected to the thin film transistor TFT2a. Connected to the drain electrode. In the pixel PIX2b, the source line SL2a is connected to the source electrode of the thin film transistor TFT2b, the gate line GL2b is connected to the gate electrode of the thin film transistor TFT2b, and the pixel electrode PX2b is connected to the drain electrode of the thin film transistor TFT2b. In the pixel PIX2c, the source line SL2b is connected to the source electrode of the thin film transistor TFT2c, the gate line GL2b is connected to the gate electrode of the thin film transistor TFT2c, and the pixel electrode PX2c is connected to the drain electrode of the thin film transistor TFT2c. In the pixel PIX2d, the source line SL2b is connected to the source electrode of the thin film transistor TFT2d, the gate line GL2a is connected to the gate electrode of the thin film transistor TFT2d, and the pixel electrode PX2d is connected to the drain electrode of the thin film transistor TFT2d.

  Similar to the configuration of the seventh embodiment (see FIG. 45B), the black matrix BM2 of the display panel LCP2 extends in the row direction so as to overlap the gate line GL2, and is formed in a stripe shape. In the above configuration, the display panel LCP2 is driven (double speed driving) at a frame frequency (for example, 120 Hz) that is twice the frame frequency (for example, 60 Hz) in the display panel LCP1.

  According to the configuration of the tenth embodiment, similar to the configuration of the first embodiment, each pixel PIX1 of the display panel LCP1 and each pixel PIX2 of the display panel LCP2 are arranged in a one-to-one relationship, and thus overlap each other. On / off of each pixel PIX1, PIX2 can be controlled independently. For this reason, since light leakage can be reduced as compared with the conventional configuration, the color reproducibility of the monochrome image of each color can be improved. In addition, it is possible to suppress the occurrence of luminance unevenness and moire and a decrease in the aperture ratio of the pixel.

  The configuration of the drivers of the display panel LCP1 and the display panel LCP2 is the same as that shown in FIG.

[Embodiment 11]
59 is a plan view showing a schematic configuration of the display panel LCP1 according to the eleventh embodiment. FIG. 60 is a plan view showing a schematic configuration of the display panel LCP2 according to the eleventh embodiment.

  As shown in FIG. 59, the display panel LCP1 according to the eleventh embodiment includes a plurality of red pixels PIXR, a plurality of green pixels PIXG, a plurality of blue pixels PIXB, and a plurality of white pixels PIXW. For example, in the nth row, red pixels PIXR and green pixels PIXG are alternately arranged in the row direction, and in the (n + 1) th row, blue pixels PIXB and white pixels PIXW are arranged in the row direction. Are arranged alternately. In the mth column, red pixels PIXR and blue pixels PIXB are alternately arranged in the column direction, and in the (m + 1) th column, green pixels PIXG and white pixels PIXW are arranged in the column direction. They are arranged alternately.

  As illustrated in FIG. 60, the display panel LCP2 according to the eleventh embodiment includes a plurality of pixels PIX2a, a plurality of pixels PIX2b, a plurality of pixels PIX2c, and a plurality of pixels PIX2d. For example, in the nth row, pixels PIX2a and PIX2b are alternately arranged in the row direction, and in the (n + 1) th row, pixels PIX2c and pixels PIX2d are arranged alternately in the row direction. Is arranged in. In the m-th column, pixels PIX2a and PIX2c are alternately arranged in the column direction, and in the (m + 1) -th column, pixels PIX2b and PIX2d are alternately arranged in the column direction. Has been placed.

  In the display panel LCP2 according to the eleventh embodiment, the plurality of gate lines GL2 include a plurality of gate lines GL2a and a plurality of gate lines GL2b. The plurality of gate lines GL2a are arranged at equal intervals in the column direction, and the plurality of gate lines GL2b are arranged at equal intervals in the column direction. The gate lines GL2a and the gate lines GL2b are alternately arranged in the column direction. The plurality of source lines SL2 include a plurality of source lines SL2a and a plurality of source lines SL2b. The plurality of source lines SL2a are arranged at equal intervals in the row direction, and the plurality of source lines SL2b are arranged at equal intervals in the row direction. The source lines SL2a and SL2b are alternately arranged in the row direction. When the display panel LCP2 is viewed in plan view, four pixels PIX2 (PIX2a, PIX2b, PIX2c, PIX2c, PIX2a, PIX2c, PIX2d) are arranged in a matrix. A pixel region is formed between the gate line GL2a and the gate line GL2b arranged away from the gate line GL2a, and four pixels PIX2 (PIX2a, PIX2b, PIX2c, PIX2d) are arranged. . On the other hand, no pixel region is formed between the gate line GL2a and the gate line GL2b disposed in the vicinity of the gate line GL2a. Further, a pixel region is formed between the source line SL2a and the source line SL2b that is spaced apart from the source line SL2a, and four pixels PIX2 (PIX2a, PIX2b, PIX2c, and PIX2d) are disposed. ing. On the other hand, no pixel region is formed between the source line SL2a and the source line SL2b disposed in the vicinity of the source line SL2a.

  FIG. 61 is a plan view showing the relationship between the pixel group DOT1 of the display panel LCP1 and the pixel group DOT2 of the display panel LCP2 that overlap each other in plan view. The pixel group DOT1 includes one red pixel PIXR, one green pixel PIXG, one blue pixel PIXB, and one white pixel PIXW of the display panel LCP1, and the pixel group DOT2 is one of the display panel LCP2. Each pixel PIX2a, one pixel PIX2b, one pixel PIX2c, and one pixel PIX2d.

  In plan view, the pixel PIX2a of the display panel LCP2 is superimposed on the red pixel PIXR of the display panel LCP1, the pixel PIX2b of the display panel LCP2 is superimposed on the green pixel PIXG of the display panel LCP1, and the pixel PIX2c of the display panel LCP2 is The pixel PIX2d of the display panel LCP1 is superimposed on the white pixel PIXW of the display panel LCP1.

  As shown in FIG. 61B, in the pixel PIX2a, the source line SL2a is connected to the source electrode of the thin film transistor TFT2a, the gate line GL2a is connected to the gate electrode of the thin film transistor TFT2a, and the pixel electrode PX2a is connected to the thin film transistor TFT2a. Connected to the drain electrode. In the pixel PIX2b, the source line SL2b is connected to the source electrode of the thin film transistor TFT2b, the gate line GL2a is connected to the gate electrode of the thin film transistor TFT2b, and the pixel electrode PX2b is connected to the drain electrode of the thin film transistor TFT2b. In the pixel PIX2c, the source line SL2a is connected to the source electrode of the thin film transistor TFT2c, the gate line GL2b is connected to the gate electrode of the thin film transistor TFT2c, and the pixel electrode PX2c is connected to the drain electrode of the thin film transistor TFT2c. In the pixel PIX2d, the source line SL2b is connected to the source electrode of the thin film transistor TFT2d, the gate line GL2b is connected to the gate electrode of the thin film transistor TFT2d, and the pixel electrode PX2d is connected to the drain electrode of the thin film transistor TFT2d.

  Similar to the configuration of Embodiment 8 (see FIG. 50), the black matrix BM2 of the display panel LCP2 extends in the row direction so as to overlap the gate line GL2, and is formed in a stripe shape.

  According to the configuration of the eleventh embodiment, similar to the configuration of the first embodiment, each pixel PIX1 of the display panel LCP1 and each pixel PIX2 of the display panel LCP2 are arranged in a one-to-one relationship, and thus overlap each other. On / off of each pixel PIX1, PIX2 can be controlled independently. For this reason, since light leakage can be reduced as compared with the conventional configuration, the color reproducibility of the monochrome image of each color can be improved. In addition, it is possible to suppress the occurrence of luminance unevenness and moire and a decrease in the aperture ratio of the pixel.

  The configuration of the drivers of the display panel LCP1 and the display panel LCP2 is the same as that shown in FIG.

[Embodiment 12]
The configuration of the display panel LCP1 according to the twelfth embodiment is the same as the configuration of the display panel LCP1 according to the third embodiment (see FIG. 19). The configuration of the display panel LCP2 according to the twelfth embodiment is different from the configuration of the display panel LCP2 according to the third embodiment (see FIG. 20) in the material of the liquid crystal LCB, and the other configurations are the same.

  FIG. 62 shows a specific configuration of the pixel PIX1 of the pixel group DOT1 of the display panel LCP1 and the pixel PIX2 of the pixel group DOT2 of the display panel LCP2 that overlap each other in plan view in the liquid crystal display device LCD according to the twelfth embodiment. FIG. 63 is a cross-sectional view taken along the line 63-63 ′ of FIG.

  In the display panel LCP1 according to the twelfth embodiment, the liquid crystal LCB is composed of a liquid crystal having a positive dielectric anisotropy (positive liquid crystal), and in the display panel LCP2, the liquid crystal LCB has a negative dielectric anisotropy. Liquid crystal (negative liquid crystal). As shown in FIGS. 62 and 63, the pixel electrode PX1 of the display panel LCP1 is formed with slits extending substantially in the column direction, and the pixel electrode PX2 (PX2a, PX2b) of the display panel LCP2 is formed. A slit extending in the substantially row direction is formed. That is, the pixel electrode PX1 and the pixel electrode PX2 are formed so as to be substantially orthogonal to each other in plan view.

  The liquid crystal display device LCD of the present invention is not limited to the configuration of each of the above embodiments. For example, the striped black matrix BM may be formed in an island pattern at a position overlapping the thin film transistor TFT in plan view. Further, yellow pixels may be arranged instead of the white pixels PIXW.

  For example, in the third embodiment, in the display panel LCP2, the source line SL2a electrically connected to the pixel electrode PX2a (see FIG. 22) in plan view is disposed on the left side of the pixel electrode PX2a. A source line SL2b electrically connected to the electrode PX2b (see FIG. 22) is disposed on the right side of the pixel electrode PX2b. The liquid crystal display device LCD of the present invention is not limited to the above configuration, and for example, the source line SL2a electrically connected to the pixel electrode PX2a may be arranged so as to overlap the pixel electrode PX2a in plan view. The source line SL2b electrically connected to the pixel electrode PX2b may be disposed so as to overlap the pixel electrode PX2b in plan view. Further, as shown in FIG. 64, the source line SL2 electrically connected to both the pixel electrodes PX2a and PX2b may be arranged so as to overlap the pixel electrode PX2a (or the pixel electrode PX2b) in plan view. Good. Considering these configurations, the display panel LCP2 preferably includes a first region P1 (see FIG. 20) in which the source line SL2 is not disposed between the pixel electrode PX2a and the pixel electrode PX2b. The display panel LCP2 may include a second region P2 (see FIG. 20) in which the source line SL2 is disposed between the pixel electrode PX2a and the pixel electrode PX2b. Furthermore, as shown in FIG. 20, the first region P1 and the second region P2 may be alternately and repeatedly arranged in the row direction.

  As mentioned above, although embodiment of this invention was described, this invention is not limited to said each embodiment, The form suitably changed by those skilled in the art from said each embodiment within the range which does not deviate from the meaning of this invention. Needless to say, it is included in the technical scope of the present invention.

  LCD liquid crystal display device, LCP1 display panel, SD1 first source driver, GD1 first gate driver, TCON1 first timing controller, LCP2 display panel, SD2 second source driver, SIC source driver IC, GIC gate driver IC, GD2 second Gate driver, TCON2 second timing controller, IPU image processing unit, SL source line, GL1, GL2 gate line, POL1-POL4 polarizing plate, BM1, BM2 black matrix, BM1a (extending in the row direction of black matrix BM1) , BM1b (extending in the column direction of the black matrix BM1), BM2a (extending in the row direction of the black matrix BM2), BM2b (extending in the column direction of the black matrix BM2) ) Portion, FIL color filter, PIX1, PIX2 pixel, PIXR red pixel, PIXG green pixel, PIXB blue pixel, PIXW white pixel, DOT1, DOT2 pixel group, PX1, PX2 pixel electrode, P1 first region, P2 second region.

Claims (15)

A plurality of display panels are arranged to overlap each other, and are liquid crystal display devices that display images on the respective display panels,
Including a first display panel and a second display panel arranged to overlap each other;
The first display panel includes a plurality of first source lines extending in a first direction, a plurality of first gate lines extending in a second direction intersecting the first direction, a plurality of first thin film transistors, A plurality of first pixel electrodes electrically connected to each first thin film transistor, and a plurality of first pixels defining a drive region of each first pixel electrode,
The second display panel includes a plurality of second source lines extending in the first direction, a plurality of second gate lines extending in the second direction, a plurality of second thin film transistors, and a plurality of third transistors. A thin film transistor; a plurality of second pixel electrodes electrically connected to each of the second thin film transistors; a plurality of third pixel electrodes electrically connected to each of the third thin film transistors; A plurality of second pixels defining a drive region; and a plurality of third pixels defining a drive region of each third pixel electrode;
The second display panel further includes a second display panel in which the second source line is not arranged between the second pixel electrode and the third pixel electrode arranged adjacent to each other in the second direction in plan view. Including one region,
A liquid crystal display device characterized by the above. The second display panel further has a second source line disposed between the second pixel electrode and the third pixel electrode disposed adjacent to each other in the second direction in plan view. Including regions,
The liquid crystal display device according to claim 1. In the second display panel, the first region and the second region are alternately and repeatedly arranged in the second direction.
The liquid crystal display device according to claim 2. One region surrounded by two adjacent first source lines and two adjacent first gate lines includes one first pixel,
One region surrounded by two adjacent second source lines and two adjacent second gate lines includes one second pixel and one third pixel. Yes,
The liquid crystal display device according to claim 1. In plan view, the second pixel is superimposed on one first pixel or a plurality of the first pixels corresponding to the same color,
The liquid crystal display device according to claim 1. The plurality of first pixels includes a red pixel corresponding to red, a green pixel corresponding to green, and a blue pixel corresponding to blue.
The area of the second pixel and the area of the third pixel are different from each other.
The liquid crystal display device according to claim 1. The first pixel and the second pixel overlap each other in plan view,
The area of the first pixel and the area of the second pixel are equal to each other,
The area of the third pixel is equal to twice the area of the first pixel;
The liquid crystal display device according to claim 1. The plurality of first pixels includes a red pixel corresponding to red, a green pixel corresponding to green, and a blue pixel corresponding to blue.
The second display panel further includes a plurality of fourth thin film transistors, a plurality of fourth pixel electrodes electrically connected to the fourth thin film transistors, and a plurality of drive regions for the fourth pixel electrodes. Including a fourth pixel,
One second pixel, one third pixel, and one fourth pixel are arranged side by side in one second region,
In plan view, the second pixel is superimposed on the red pixel, the third pixel is superimposed on the green pixel, and the fourth pixel is superimposed on the blue pixel.
The liquid crystal display device according to claim 1. The plurality of first pixels include a red pixel corresponding to red, a green pixel corresponding to green, a blue pixel corresponding to blue, and a white pixel corresponding to white.
The second display panel further includes a plurality of fourth thin film transistors, a plurality of fifth thin film transistors, a plurality of fourth pixel electrodes electrically connected to each of the fourth thin film transistors, and an electrical connection to each of the fifth thin film transistors. A plurality of fifth pixel electrodes connected to each other, a plurality of fourth pixels defining a drive region of each fourth pixel electrode, and a plurality of fifth pixels defining a drive region of each fifth pixel electrode; Including
In the one second region, one second pixel, one third pixel, one fourth pixel, and one fifth pixel are arranged side by side,
In plan view, the second pixel overlaps the red pixel, the third pixel overlaps the green pixel, the fourth pixel overlaps the blue pixel, and the fifth pixel overlaps the white pixel. doing,
The liquid crystal display device according to claim 1. The plurality of first pixels includes a red pixel corresponding to red, a green pixel corresponding to green, and a blue pixel corresponding to blue.
In plan view, the second pixel is superimposed on the red pixel, and the third pixel is superimposed on the green pixel and the blue pixel.
The liquid crystal display device according to claim 1. The first display panel displays a color image, the second display panel displays a black and white image;
The second display panel is disposed at a position farther from the observer than the first display panel,
The first black matrix extends in the first direction and the second direction so as to overlap the plurality of first source lines and the plurality of first gate lines in a plan view, and is formed in a lattice shape. And
The second black matrix extends in the second direction so as to overlap the plurality of second gate lines in plan view, and is formed in a stripe shape.
The liquid crystal display device according to claim 1. The first display panel displays a color image, the second display panel displays a black and white image;
The first display panel is disposed at a position farther from the observer than the second display panel,
The first black matrix extends in the second direction so as to overlap the plurality of first gate lines in plan view, and is formed in a stripe shape.
The second black matrix extends in the first direction and the second direction so as to overlap the plurality of second source lines and the plurality of second gate lines in a plan view, and is formed in a lattice shape. Yes,
The liquid crystal display device according to claim 1. The first black matrix extends in the first direction and the second direction so as to overlap the plurality of first source lines and the plurality of first gate lines in a plan view, and is formed in a lattice shape. And
The second black matrix extends in the first direction and the second direction so as to overlap the plurality of second source lines and the plurality of second gate lines in a plan view, and is formed in a lattice shape. And
The length in the second direction of the portion extending in the first direction of the second black matrix is shorter than the length in the second direction of the portion extending in the first direction of the first black matrix, And,
The length in the first direction of the portion extending in the second direction of the second black matrix is shorter than the length in the first direction of the portion extending in the second direction of the first black matrix.
The liquid crystal display device according to claim 1. The first display panel further includes a first black matrix,
The second display panel further includes a second black matrix,
The length in the first direction of the portion extending in the second direction of the first black matrix and the length in the first direction of the portion extending in the second direction of the second black matrix are Different,
The liquid crystal display device according to claim 1. A plurality of display panels are arranged to overlap each other, and are liquid crystal display devices that display images on the respective display panels,
Including a first display panel and a second display panel arranged to overlap each other;
The first display panel includes a plurality of first source lines extending in a first direction, a plurality of first gate lines extending in a second direction intersecting the first direction, a plurality of first thin film transistors, A plurality of first pixel electrodes electrically connected to each first thin film transistor, and a plurality of first pixels defining a drive region of each first pixel electrode,
The second display panel includes a plurality of second source lines extending in the first direction, a plurality of second gate lines extending in the second direction, a plurality of second thin film transistors, and a plurality of third transistors. A thin film transistor; a plurality of second pixel electrodes electrically connected to each of the second thin film transistors; a plurality of third pixel electrodes electrically connected to each of the third thin film transistors; A plurality of second pixels defining a drive region; and a plurality of third pixels defining a drive region of each third pixel electrode;
One region surrounded by two adjacent first source lines and two adjacent first gate lines includes one first pixel,
One region surrounded by two adjacent second source lines and two adjacent second gate lines includes one second pixel and one third pixel. Yes,
A liquid crystal display device characterized by the above.

Images