WO2018085972A1 - Circuit de détection de condensateur et son procédé de commande - Google Patents

Circuit de détection de condensateur et son procédé de commande Download PDF

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Publication number
WO2018085972A1
WO2018085972A1 PCT/CN2016/105002 CN2016105002W WO2018085972A1 WO 2018085972 A1 WO2018085972 A1 WO 2018085972A1 CN 2016105002 W CN2016105002 W CN 2016105002W WO 2018085972 A1 WO2018085972 A1 WO 2018085972A1
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WO
WIPO (PCT)
Prior art keywords
capacitor
reference voltage
capacitance
comparator
amplifier
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Application number
PCT/CN2016/105002
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English (en)
Chinese (zh)
Inventor
汪正锋
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深圳市汇顶科技股份有限公司
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Priority to PCT/CN2016/105002 priority Critical patent/WO2018085972A1/fr
Priority to CN201680001494.2A priority patent/CN106796259B/zh
Publication of WO2018085972A1 publication Critical patent/WO2018085972A1/fr

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
    • G01R27/2605—Measuring capacitance
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01D—MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
    • G01D5/00—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable
    • G01D5/12—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means
    • G01D5/14—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage
    • G01D5/24—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying capacitance

Definitions

  • Embodiments of the present invention relate to the field of electronic technologies, and in particular, to a capacitance detecting circuit and a control method thereof.
  • capacitive sensors are commonly used as input devices and are widely used in a variety of electronic systems to provide information about the input (such as position, motion, force, duration, etc.) to the electronic system.
  • the user generates a capacitive effect by sensing (eg, approaching, contacting, pressing, sliding, etc.) one or more sensing regions of the capacitive sensor, and by measuring the capacitive effect, the user's operation can be determined.
  • the capacitance detection circuit is the core of the capacitive sensor, and its circuit design directly affects the overall cost and power consumption of the capacitive sensor.
  • Figure 1 shows the existing capacitance detection circuit diagram, including the capacitor C x to be detected, the integrator F x and the analog-to-digital converter ADC.
  • the first end of the capacitor C x to be detected is connected to the analog-to-digital converter ADC through an integrator F x
  • the second end of the capacitor C x to be detected is grounded to GND 0 .
  • the integrator F x converts the capacitive effect into a voltage amount, and then samples and quantizes it into a digital quantity through an analog-to-digital converter ADC, thereby performing capacitance detection.
  • the inventors have found that the prior art has the following problems: the existing capacitance detecting circuit is relatively complicated, and the analog to digital converter ADC is used, resulting in a very large area and power consumption of the capacitance detecting circuit. It is very disadvantageous for capacitive sensors.
  • An object of embodiments of the present invention is to provide a capacitance detecting circuit and a controller thereof
  • the method simplifies the circuit structure and directly converts the capacitance value into a digital quantity, which greatly reduces the area and power consumption of the capacitance detecting circuit.
  • an embodiment of the present invention provides a capacitance detecting circuit, including: a switched capacitor amplifier, a comparator, and a timing control unit; the switched capacitor amplifier includes an N capacitor branch connected to a capacitor to be detected Variable capacitance array; wherein N is a natural number and N>1; a first input of the comparator is coupled to an output of the switched capacitor amplifier, and a second input of the comparator is coupled to a first reference a voltage; an input of the timing control unit is coupled to an output of the comparator, an output of the timing control unit is coupled to a capacitance adjustment terminal of the variable capacitor array; wherein, in N clock cycles, The timing control unit sequentially disables N capacitor branches in the variable capacitor array, and the output of the comparator sequentially outputs N digital quantities for characterizing the capacitance to be detected.
  • the embodiment of the present invention further provides a method for controlling a capacitance detecting circuit, which is applied to the above-mentioned capacitance detecting circuit, and the control method includes: controlling the switched capacitor amplifier to enter the first non in the i+1th clock cycle An overlap phase; in the non-overlap phase, discharging the switched capacitor amplifier, and when i+1 ⁇ 2, if the comparator outputs the ith number in the ith clock cycle The quantity is 0, enabling the Nith capacitor branch in the variable capacitor array; controlling the switched capacitor amplifier to enter a reset phase; in the reset phase, charging the switched capacitor amplifier; controlling the The switched capacitor amplifier enters a second non-overlapping phase; in the second non-overlapping phase, the N-(i+1)th capacitive branch in the variable capacitor array is disabled; and the switched capacitor is controlled
  • an embodiment of the present invention provides a capacitance detecting circuit including a switched capacitor amplifier, a comparator, and a timing control unit.
  • the switched capacitor amplifier includes a variable capacitor array with N capacitive branches (N is a natural number and N > 1). Timing control in N clock cycles
  • the unit sequentially disables the N capacitor branches in the variable capacitor array, and the output ends of the comparator sequentially output N digital quantities for characterizing the capacitor to be detected; that is, the analog-to-digital converter ADC is omitted in the embodiment of the present invention, and
  • the capacitance value of the capacitor to be detected is directly converted into a digital quantity by successive approximation, which simplifies the circuit structure and greatly reduces the area and power consumption of the capacitance detecting circuit.
  • the first reference voltage is greater than the third reference voltage and smaller than the second reference voltage
  • the first input end and the second input end of the comparator are a non-inverting input end and an inverting input end, respectively.
  • a connection mode of the switched capacitor amplifier and the comparator is provided.
  • the first reference voltage is greater than the second reference voltage and smaller than the third reference voltage
  • the first input end and the second input end of the comparator are respectively an inverting input end and a non-inverting input end.
  • another connection mode of the switched capacitor amplifier and the comparator is provided.
  • the first reference voltage is half of a sum of the second reference voltage and the third reference voltage.
  • a value manner of the first reference voltage is provided, so that the circuit reduces the calculation amount and saves power consumption.
  • the timing control unit is a timing control circuit; or the timing control unit is a control chip. In this embodiment, two implementations of the timing control unit are provided.
  • FIG. 1 is a schematic diagram of a capacitance detecting circuit in the background art
  • FIG. 2 is a schematic diagram of a capacitance detecting circuit of the first embodiment
  • FIG. 3 is a schematic diagram of a variable capacitor array in the first embodiment
  • FIG. 4 is a schematic diagram showing timing control of a capacitance detecting circuit in a third embodiment
  • FIG. 5 is a schematic diagram of the capacitance detecting circuit in the first non-overlapping phase in the third embodiment
  • FIG. 6 is a schematic diagram of the capacitance detecting circuit of the third embodiment in a reset phase
  • FIG. 7 is a schematic diagram of the capacitance detecting circuit of the third embodiment in a second non-overlapping phase
  • Fig. 8 is a schematic view showing the capacitance detecting circuit of the third embodiment in an amplification stage.
  • a first embodiment of the invention relates to a capacitance detecting circuit.
  • the capacitance detecting circuit includes a switched capacitor amplifier, a comparator C omp, and a timing control unit H.
  • the first input of the comparator C omp is connected to the output of the switched capacitor amplifier, and the second input of the comparator C omp is connected to the first reference voltage V cm .
  • the switched capacitor amplifier is connected to the capacitor to be detected is C x, which has N comprising a variable capacitance array capacitor branch C c, the operational amplifier O p, feedback capacitor C f, and the first to fifth switches S 0 ⁇ S 4 ; wherein N is a natural number and N>1.
  • the first end of the capacitor C x to be detected is connected to the second reference voltage V refp through the first switch S 0 , and the second end of the capacitor C x to be detected is grounded to GND 0 .
  • the first end of the variable capacitor array C c is connected to the third reference voltage V refn through the second switch S 1 , and is connected to the first end and the fourth switch S 3 of the capacitor C x to be detected through the third switch S 2 ;
  • the second end of the variable capacitance array C c is connected to the third reference voltage V refn .
  • Inverting input terminal of the operational amplifier O p is connected through a fourth switch S 3 to be detected the capacitance C x of the first terminal and the third switch S 2, the operational amplifier O p-inverting input terminal is connected to a first reference voltage V cm .
  • a feedback capacitor C f S 4 and the fifth switch are connected across the inverting input terminal and the output terminal of the operational amplifier O p.
  • the variable capacitor array C c in this embodiment includes N capacitor branches, and each capacitor branch includes a capacitor C i and a branch switch S c,i .
  • each capacitor branch includes a capacitor C i and a branch switch S c,i .
  • branch switch S c,i is turned on, indicating that the capacitor C i is connected to the variable capacitor array C c ; the switch S c,i is disconnected, indicating that the capacitor C i is removed from the variable capacitor array C c .
  • the present embodiment does not impose any limitation on the capacitance of each capacitor branch, and can be set by a person skilled in the art according to actual needs.
  • the timing control unit H is configured to generate a control signal of the variable capacitance array C c and the first to fifth switches (S 0 to 4 ).
  • the input of the timing control unit H is connected to the output D of the comparator C omp , and the output of the timing control unit H is connected to the capacitance regulating terminal of the variable capacitor array C c .
  • the timing control unit H includes first to fourth control terminals.
  • the first control end is connected to the first switch S 0 and the second switch S 1 ; the second control end is connected to the third switch S 2 and the fourth switch S 3 ; the third control end is connected to the fifth switch S 4 ;
  • the control terminal ie, the output of the timing control unit H is connected to the capacitance regulating terminal of the variable capacitance array C c .
  • the timing control unit H can be understood as a timing control unit comprising a successive approximation register (SAR); the successive approximation register is used to generate a control signal of the variable capacitance array C c from the output signal of the comparator C omp .
  • SAR successive approximation register
  • the timing control unit H is a timing control circuit; that is, a control signal is generated by hardware.
  • the timing control unit H is a control chip; that is, the timing control signal is generated by software; however, the specific implementation manner of the timing control unit H is not limited in this embodiment, and may be specifically designed according to actual conditions.
  • the first reference voltage V cm is between the second reference voltage V refp and the third reference voltage V refn .
  • the first reference voltage V cm is greater than the third reference voltage V refn and smaller than the second reference voltage V refp .
  • the first input end and the second input end of the comparator C omp are the positive phase input end and the opposite end respectively. Phase input.
  • the first reference voltage V cm can be set to be half of the sum of the second reference voltage V refp and the third reference voltage V refn ; thereby reducing the calculation amount of the circuit and saving power consumption;
  • the set value of the test voltage V cm is not limited as long as it satisfies between the second reference voltage V refp and the third reference voltage V refn .
  • the one-time detecting process for the capacitance detecting circuit substantially includes N clock cycles; in N clock cycles, the timing control unit H sequentially disables the N capacitor branches in the variable capacitor array C c
  • the output terminal D of the comparator C omp sequentially outputs N digital quantities d N-1 ⁇ 0 for characterizing the capacitance C x to be detected. That is, the capacitance value of the capacitor Cx to be detected is directly converted into N digital quantities by successive approximation.
  • the converted N digital quantities also change; therefore, By continuously detecting multiple times and comparing the changes of N digital quantities, the change of the capacitance to be detected can be detected in real time.
  • Embodiments of the present invention provide a capacitance detecting circuit including a switched capacitor amplifier, a comparator, and a timing control unit with respect to the prior art.
  • the switched capacitor amplifier includes a variable capacitor array with N capacitive branches (N is a natural number and N > 1).
  • the timing control unit disables the N capacitor branches in the variable capacitor array in descending order of capacitance values, and the output terminals of the comparator sequentially output N capacitors for characterizing the capacitor to be detected.
  • the digital quantity that is, the existing analog-to-digital converter ADC is omitted in the embodiment of the present invention, and the circuit value is simplified by directly converting the capacitance value of the capacitor to be detected into a digital quantity by a binary search algorithm or the like, thereby simplifying the circuit structure.
  • the area of the capacitance detecting circuit and the power consumption are greatly reduced.
  • a second embodiment of the present invention relates to a capacitance detecting circuit.
  • the second embodiment is substantially the same as the first embodiment.
  • the main difference is that in the first embodiment, the first reference voltage is greater than the third reference voltage and smaller than the second reference voltage, and the first input end of the comparator
  • the two input terminals are a positive phase input terminal and an inverting input terminal, respectively.
  • the first reference voltage is greater than the second reference voltage and less than the third reference voltage, and the first input end and the second input end of the comparator They are the inverting input and the positive input.
  • Embodiments of the present invention provide another way of connecting a switched capacitor amplifier to a comparator with respect to the first embodiment.
  • a third embodiment of the present invention relates to a method of controlling a capacitance detecting circuit, which is applied to a capacitance detecting circuit in the first embodiment or the second embodiment.
  • the control method of this embodiment can be understood as performing continuous multiple detections on the capacitance to be detected.
  • the one-time detection process of the detection capacitor essentially includes N clock cycles. In each clock cycle, the comparator outputs a digital quantity; that is, the N digital quantities sequentially output by the comparator are used to characterize the capacitance to be detected.
  • the primary circuit detecting process includes N clock cycles.
  • the first control terminal of the timing control unit H generates a clock signal ⁇ 1 to control the first switch S0 and the second switch S1
  • the second control terminal generates a clock signal ⁇ 2 to control the third switch S2 and the fourth switch S3
  • the third control terminal generates a signal ⁇ 3 to control the fifth switch S4
  • the fourth control terminal generates a signal ⁇ c,0 to control the branch switch Sc,0.
  • ⁇ 1 and ⁇ 2 are two-phase non-overlapping clocks
  • clk is the system clock
  • T1 is the first conversion (T1 to N indicate the first to Nth conversions); when the rising edge of the start signal comes, the detection process starts.
  • the timing control unit has similar control signals to the switched capacitor amplifier output; as follows:
  • the switched-capacitor amplifier is controlled to enter the first non-overlapping phase.
  • the switched capacitor amplifier discharges, and when i+1 ⁇ 2, if the ith digital quantity output by the comparator in the ith clock cycle is 0, the variable capacitor is enabled.
  • the Ni-th capacitor branch in the array if the ith digital quantity output by the comparator in the ith clock cycle is 0, the variable capacitor is enabled.
  • the switched-capacitor amplifier is controlled to enter the reset phase. During the reset phase, the switched capacitor amplifier is charged.
  • the switched-capacitor amplifier is controlled to enter a second non-overlapping phase.
  • the N-th (i+1)th capacitor branch in the variable capacitor array is disabled.
  • the switched-capacitor amplifier is controlled to enter the amplification phase.
  • the comparator outputs the i+1th digital quantity.
  • the switched capacitor amplifier is controlled to enter the first non-overlapping phase A 1 .
  • the feedback capacitor C f is discharged.
  • the switched capacitor amplifier is controlled to enter the reset phase B.
  • the switches S 0 ⁇ 1 are closed; the capacitance C x to be measured is charged, and the variable capacitance array C c is discharged.
  • the amount of charge in the variable capacitor array C c is zero before entering the reset phase B, there is no charge flow between the ends of the variable capacitor array C c after entering the reset phase B (not After experiencing the actual discharge process); if the voltage at one end of the variable capacitor array C c is greater than the voltage at the other end before entering the reset phase B, the voltage in the variable capacitor array C c is higher after entering the reset phase B One end of the capacitor discharges to the lower voltage end until the amount of charge in the variable capacitor array C c is zero. At this time, the voltage across the variable capacitor array C c is V refn ; that is, at the end of the reset phase B, The amount of charge in the variable capacitance array C c is zero.
  • the switched capacitor amplifier is controlled to enter the second non-overlapping phase A 2 .
  • the switched capacitor amplifier is controlled to enter the amplification phase C.
  • V out ⁇ V cm
  • the process of the first cycle is repeated N times.
  • the capacitance detection is completed; that is, the capacitors C N-2 , C N-3 , . . . , C 0 are sequentially removed from the variable capacitor.
  • the capacitance value of the capacitor C x to be detected can be expressed as:
  • the embodiment of the present invention applies the capacitance detecting circuit provided by the embodiment of the present invention to detect the change of the capacitance in real time, and performs corresponding control on the stage of the switched capacitor amplifier in each clock cycle. (including a first non-overlapping phase, a reset phase, a second non-overlapping phase, and an amplifying phase), so that the comparator sequentially outputs N digital quantities to correspond to the capacitance to be detected. Capacitance value.
  • the present embodiment is an embodiment of the method corresponding to the first and second embodiments, and the present embodiment can be implemented in cooperation with the first and second embodiments.
  • the related technical details mentioned in the first and second embodiments are still effective in the present embodiment, and are not described herein again in order to reduce repetition. Accordingly, the related technical details mentioned in the present embodiment can also be applied to the first and second embodiments.
  • a program instructing related hardware may be completed by a program instructing related hardware, and the program is stored in a storage medium, and includes a plurality of instructions for making a device (which may be a single chip microcomputer). , a chip, etc. or a processor performs all or part of the steps of the methods described in various embodiments of the present application.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like. .

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

L'invention concerne un circuit de détection de condensateur et son procédé de commande, qui se rapportent au domaine technique de l'électronique. Le circuit de détection de condensateur comprend : un amplificateur de condensateur de commutation, un comparateur (Comp), et une unité de commande séquentielle (H). L'amplificateur de condensateur de commutation comprend un réseau de condensateurs variables (Cc) qui est connecté à un condensateur à détecter et qui a N branches de condensateur, N étant un nombre entier et N étant supérieur à 1. Une première extrémité d'entrée du comparateur (Comp) est connectée à une extrémité de sortie de l'amplificateur de condensateur de commutation, et une seconde extrémité d'entrée du comparateur (Comp) est connectée à une première tension de référence (Vcm). Une extrémité d'entrée de l'unité de commande séquentielle (H) est connectée à une extrémité de sortie (D)_du comparateur (Comp), et une extrémité de sortie de l'unité de commande séquentielle (H) est connectée à une extrémité de réglage de condensateur du réseau de condensateurs variables (Cc). Au moyen du circuit de détection de condensateur, la structure d'un circuit est simplifiée, et une valeur de capacité est directement convertie en une valeur numérique, ce qui réduit considérablement la zone et la consommation d'énergie du circuit de détection de condensateur.
PCT/CN2016/105002 2016-11-08 2016-11-08 Circuit de détection de condensateur et son procédé de commande WO2018085972A1 (fr)

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Application Number Priority Date Filing Date Title
PCT/CN2016/105002 WO2018085972A1 (fr) 2016-11-08 2016-11-08 Circuit de détection de condensateur et son procédé de commande
CN201680001494.2A CN106796259B (zh) 2016-11-08 2016-11-08 电容检测电路及其控制方法

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PCT/CN2016/105002 WO2018085972A1 (fr) 2016-11-08 2016-11-08 Circuit de détection de condensateur et son procédé de commande

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US20220200588A1 (en) * 2020-12-17 2022-06-23 Realtek Semiconductor Corporation Current steering comparator and capacitor control method
CN117572090A (zh) * 2024-01-16 2024-02-20 北京全路通信信号研究设计院集团有限公司 电容传感器的信号检测电路、检测方法和检测设备

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WO2018085972A1 (fr) * 2016-11-08 2018-05-17 深圳市汇顶科技股份有限公司 Circuit de détection de condensateur et son procédé de commande
WO2019047214A1 (fr) 2017-09-11 2019-03-14 深圳市汇顶科技股份有限公司 Circuit de détection de capacité, procédé de détection de capacité, dispositif de détection tactile et dispositif terminal
CN109496273B (zh) * 2018-01-24 2021-05-11 深圳市汇顶科技股份有限公司 电容检测电路、触摸检测装置和终端设备
WO2019241968A1 (fr) * 2018-06-21 2019-12-26 深圳市汇顶科技股份有限公司 Procédé d'élimination de base de bouton, circuit de détection de bouton capacitif et terminal intelligent
CN108599739A (zh) * 2018-07-19 2018-09-28 重庆湃芯入微科技有限公司 一种基于非交叠时钟电荷转移技术的积分电路
CN111257673A (zh) * 2020-02-17 2020-06-09 广东博智林机器人有限公司 一种电容故障检测电路、检测方法和伺服驱动电路
WO2022047673A1 (fr) * 2020-09-02 2022-03-10 深圳市汇顶科技股份有限公司 Circuit de réseau de condensateurs, circuit de charge et de décharge, et circuit oscillant rc
CN113031081B (zh) * 2021-03-10 2024-06-04 维沃移动通信有限公司 接近传感检测电路、电容校准方法、装置及电子设备
CN113411085B (zh) * 2021-06-29 2023-11-10 成都信息工程大学 一种逐次逼近型电容检测电路
CN113472351A (zh) * 2021-07-13 2021-10-01 上海料聚微电子有限公司 一种精准测量片上电容比例的电路和方法

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JP4990198B2 (ja) * 2008-03-14 2012-08-01 日立オートモティブシステムズ株式会社 センサ出力装置
CN105954596A (zh) * 2016-04-21 2016-09-21 上海华力微电子有限公司 一种用于小电容失配检测及绝对值测量的电路及方法
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Publication number Priority date Publication date Assignee Title
US20220200588A1 (en) * 2020-12-17 2022-06-23 Realtek Semiconductor Corporation Current steering comparator and capacitor control method
US11482994B2 (en) * 2020-12-17 2022-10-25 Realtek Semiconductor Corporation Current steering comparator and capacitor control method
CN117572090A (zh) * 2024-01-16 2024-02-20 北京全路通信信号研究设计院集团有限公司 电容传感器的信号检测电路、检测方法和检测设备
CN117572090B (zh) * 2024-01-16 2024-03-19 北京全路通信信号研究设计院集团有限公司 电容传感器的信号检测电路、检测方法和检测设备

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