WO2018083870A1 - Current protection circuit - Google Patents

Current protection circuit Download PDF

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Publication number
WO2018083870A1
WO2018083870A1 PCT/JP2017/030927 JP2017030927W WO2018083870A1 WO 2018083870 A1 WO2018083870 A1 WO 2018083870A1 JP 2017030927 W JP2017030927 W JP 2017030927W WO 2018083870 A1 WO2018083870 A1 WO 2018083870A1
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Prior art keywords
transistor
output
current
voltage
terminal
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PCT/JP2017/030927
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French (fr)
Japanese (ja)
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日比　康博
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株式会社デンソー
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Publication of WO2018083870A1 publication Critical patent/WO2018083870A1/en

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit

Definitions

  • This disclosure relates to a current protection circuit that protects a circuit from a backflow that flows from an output terminal to an input terminal.
  • some series regulator type power supply circuits include a current protection circuit for protecting the circuit from a backflow flowing from the output terminal to the input terminal.
  • a backflow protection circuit is a configuration in which a backflow protection transistor is provided in series with the main transistor (see, for example, Patent Document 1).
  • the potential relationship between the input and output terminals is detected by a comparator, and when the potential relationship between the input and output terminals is reversed based on the output of the comparator, the reverse current protection transistor is turned off to prevent back flow. Is realized.
  • An object of the present disclosure is to provide a current protection circuit that can protect a circuit from backflow while suppressing an increase in circuit area.
  • the current protection circuit includes a MOS transistor, a current detection unit, an off drive unit, and a back gate control unit.
  • the MOS transistor is connected in series between an input terminal for inputting an input voltage and an output terminal for outputting an output voltage lower than the input voltage.
  • the MOS transistor connected to such a location is an N-channel type, its drain is connected to the input terminal side and its source is connected to the output terminal side.
  • the source is connected to the input terminal side, and the drain is connected to the output terminal side.
  • the current detection unit detects a current flowing between the input terminal and the output terminal, and outputs a detection signal indicating the direction of the detected current.
  • the off drive unit drives the MOS transistor off.
  • the back gate control unit applies a voltage on the drain side of the MOS transistor to the back gate of the MOS transistor at least during a period in which the detection signal indicating the first direction is output from the current detection unit.
  • the off drive unit drives the MOS transistor off when a detection signal representing the first direction is output from the current detection unit. As a result, backflow through the path through the channel of the MOS transistor is prevented.
  • the back gate control unit applies the voltage on the drain side of the MOS transistor to the back gate of the MOS transistor.
  • the MOS transistor is an N-channel type
  • a body diode having the anode on the drain side, that is, the input terminal side is formed between the drain and source of the MOS transistor.
  • the MOS transistor is a P-channel type
  • a body diode having an anode on the source side, that is, the input terminal side is formed between the source and drain of the MOS transistor. For this reason, backflow through the path through the body diode of the MOS transistor is also prevented.
  • the backflow that flows from the output terminal to the input terminal is controlled by controlling the driving of one MOS transistor provided in series in the path from the input terminal to the output terminal and controlling the back gate. Is prevented. Therefore, according to the said structure, the outstanding effect that a circuit can be protected from a backflow is obtained, suppressing the increase in a circuit area.
  • FIG. 1 is a diagram schematically showing the configuration of the power supply circuit according to the first embodiment.
  • FIG. 2 is a diagram schematically showing the configuration of the power supply circuit according to the second embodiment.
  • FIG. 3 is a diagram schematically showing the configuration of the power supply circuit according to the third embodiment.
  • FIG. 4 is a diagram schematically showing the configuration of the power supply circuit according to the fourth embodiment.
  • the power supply circuit 1 shown in FIG. 1 is used in, for example, an electronic control device (hereinafter also referred to as ECU) mounted on a vehicle.
  • the power supply circuit 1 is a series regulator type power supply circuit that steps down the input voltage AVDD given through the power supply input terminal Pi and outputs it as an output voltage VOUT having a desired voltage value from the power supply output terminal Po.
  • the input voltage AVDD is a battery voltage output from an in-vehicle battery (not shown) or a DC voltage output from another power supply circuit that receives the battery voltage.
  • the steady value of the input voltage AVDD is 12V, for example, and the target value of the output voltage VOUT is 5V, for example. That is, in a steady state, the input voltage AVDD and the output voltage VOUT have a relationship of “AVDD> VOUT”. Therefore, in a steady state, in the power supply circuit 1, a current flows in the forward direction from the power input terminal Pi to the power output terminal Po.
  • the power output terminal Po is led out of the ECU through, for example, wiring, and there is a possibility that the wiring or the like may be short-circuited with a high voltage portion existing outside.
  • the input voltage AVDD and the output voltage VOUT have a relationship of “AVDD ⁇ VOUT”. Therefore, at the time of abnormality, in the power supply circuit 1, a current may flow in the reverse direction from the power supply output terminal Po to the power supply output terminal Pi.
  • the power supply circuit 1 of the present embodiment includes a protection function for protecting the circuit from such a reverse current (hereinafter also referred to as a reverse flow).
  • the power supply circuit 1 includes transistors T1 and T2, a pre-driver 2, a shunt resistor Rs, a comparator CP1, inversion buffers 3 and 4, a voltage detection circuit 5, an error amplifier 6, a back gate control unit 7, and the like.
  • the transistor T1 is an N-channel power MOS transistor.
  • the drain of the transistor T1 is connected to the power input terminal Pi via the shunt resistor Rs.
  • the source of the transistor T1 is connected to the power output terminal Po. That is, the transistor T1 is interposed in series between the power input terminal Pi and the power output terminal Po, and corresponds to a main transistor.
  • a gate drive signal Sg output from the pre-driver 2 is given to the gate of the transistor T1.
  • the power input terminal Pi corresponds to an input terminal
  • the power output terminal Po corresponds to an output terminal.
  • the output signal of the comparator CP1 is supplied to the inverting buffers 3 and 4 as the detection signal Sc of the current flowing between the power input terminal Pi and the power output terminal Po.
  • the detection signal Sc has a level corresponding to the magnitude relationship between the terminal voltages of the shunt resistor Rs. Specifically, the detection signal Sc is at a high level (for example, 5 V) when one terminal voltage of the shunt resistor Rs is larger than the other terminal voltage, and the other terminal voltage of the shunt resistor Rs is one terminal voltage. If it is larger than the low level, it becomes a low level (for example, 0 V).
  • the current that flows between the power input terminal Pi and the power output terminal Po is detected by the shunt resistor Rs and the comparator CP1, and the detection signal Sc that represents the direction of the detected current is output.
  • a detection unit 8 is configured.
  • the direction of the current flowing from the power output terminal Po to the power output terminal Pi is defined as the first direction
  • the direction of the current that is, the direction of the forward current (forward current) is defined as the second direction. Therefore, the low level detection signal Sc corresponds to a detection signal representing the first direction (reverse direction), and the high level detection signal Sc corresponds to a detection signal representing the second direction (forward direction).
  • the voltage detection circuit 5 is composed of a series circuit of resistors R1 and R2.
  • the series circuit is connected between the source of the transistor T1, that is, the power supply output terminal Po, and the ground terminal Pg to which the reference potential GND (0 V) of the circuit is applied.
  • the voltage at the common connection point of the resistors R1 and R2, that is, the detection voltage Vd obtained by dividing the output voltage VOUT by the resistors R1 and R2 is applied to the inverting input terminal of the error amplifier 6.
  • the reference voltage Vr corresponding to the target value of the output voltage VOUT is given to the non-inverting input terminal of the error amplifier 6.
  • the error amplifier 6 outputs an error signal Sd corresponding to the difference between the reference voltage Vr and the detection voltage Vd.
  • the error signal Sd is given to the pre-driver 2.
  • a transistor T2 is connected between the control terminal P1 of the pre-driver 2 and the ground terminal Pg.
  • the transistor T2 is an N channel type MOS transistor.
  • the output signal of the inverting buffer 3 is given to the gate of the transistor T2. Therefore, the transistor T2 is turned on when the detection signal Sc is at a low level, and is turned off when the detection signal Sc is at a high level.
  • the control terminal P1 is pulled up inside the pre-driver 2. Therefore, the voltage level of the control terminal P1 becomes high level when the detection signal Sc becomes high level and the transistor T2 is turned off, and becomes low level when the detection signal Sc becomes low level and the transistor T2 is turned on.
  • the pre-driver 2 outputs a gate drive signal Sg corresponding to the error signal Sd when the voltage level of the control terminal P1 is high. Thereby, the drive of the transistor T1 is feedback controlled so that the output voltage VOUT matches the target value. Further, when the voltage level of the control terminal P1 is low level, the pre-driver 2 outputs the gate drive signal Sg of 0V, for example, to drive the transistor T1 off.
  • the pre-driver 2, the inverting buffer 3, and the transistor T2 constitute an off drive unit 9.
  • the back gate control unit 7 controls the voltage applied to the back gate of the transistor T1 in accordance with the detection signal Sc output from the current detection unit 8. Specifically, the back gate control unit 7 connects the back gate of the transistor T1 to the source side, that is, the power supply output terminal Po during a period in which the high level detection signal Sc is output. As a result, when a current flows in a direction flowing from the power input terminal Pi to the power output terminal Po, that is, in a steady state, the source side voltage, that is, the output voltage VOUT is applied to the back gate of the transistor T1.
  • the back gate control unit 7 connects the back gate of the transistor T1 to the drain side, that is, the power supply input terminal Pi during the period when the low level detection signal Sc is output.
  • the drain side voltage that is, the input voltage AVDD is applied to the back gate of the transistor T1.
  • the back gate control unit 7 includes transistors T3 to T6 and a current source 10.
  • the transistor T3 is an N-channel MOS transistor, and its source is connected to the ground terminal Pg.
  • the drain of the transistor T3 is connected to the power input terminal Pi via the current source 10.
  • the output signal of the inverting buffer 4 is given to the gate of the transistor T3.
  • the transistor T4 is a P-channel MOS transistor, and its source is connected to the power input terminal Pi.
  • the gate of the transistor T4 is connected to the drain of the transistor T3.
  • the drain of the transistor T4 is connected to the node N1.
  • Node N1 is connected to the back gate of transistor T1.
  • the transistors T5 and T6 are both N-channel MOS transistors, and their sources are connected to the node N1.
  • the drains of the transistors T5 and T6 are connected to the power output terminal Po.
  • the gate of the transistor T5 is connected to the power input terminal Pi.
  • the transistor T6 is driven on and off by the pre-driver 2. Specifically, the pre-driver 2 turns on the transistor T6 when the voltage level of the control terminal P1 is high. The pre-driver 2 drives off the transistor T6 when the voltage level of the control terminal P1 is low.
  • the transistor T4 when the high-level detection signal Sc is output from the current detection unit 8, the transistor T4 is turned off, thereby turning off the transistor T4. At this time, the transistor T6 is turned on by the pre-driver 2. Accordingly, the transistor T5 is also turned on. By such an operation, the node N1 is connected to the power supply output terminal Po, and the output voltage VOUT is applied to the back gate of the transistor T1.
  • the transistor T4 is turned on to turn on the transistor T4.
  • the transistor T6 is driven off by the pre-driver 2. Accordingly, the transistor T5 is turned off.
  • the node N1 is connected to the power supply input terminal Pi, and the input voltage AVDD is applied to the back gate of the transistor T1.
  • the transistor T1, the back gate control unit 7, the current detection unit 8, and the off drive unit 9 protect the circuit such as the power supply circuit 1 from the backflow that flows from the power supply output terminal Po to the power supply input terminal Pi.
  • a current protection circuit 11 that realizes the function is configured.
  • the current detection unit 8 when a backflow that flows from the power supply output terminal Po to the power supply input terminal Pi occurs, the current detection unit 8 outputs a low-level detection signal Sc.
  • the pre-driver 2 constituting the off-drive unit 9 forcibly drives the transistor T ⁇ b> 1 regardless of the error signal Sd output from the error amplifier 6. To do. Thereby, the backflow by the path
  • the back gate control unit 7 supplies the input voltage AVDD that is the voltage on the drain side of the transistor T1 to the back gate of the transistor T1.
  • AVDD the input voltage
  • a body diode having the drain side, that is, the power input terminal Pi side as an anode, is formed between the drain and source of the transistor T1. For this reason, backflow through the path through the body diode of the transistor T1 is also prevented.
  • the drive of one transistor T1 provided in series in the path from the power input terminal Pi to the power output terminal Po is controlled and the back gate is controlled to thereby control the power output terminal Po. Is prevented from flowing back to the power input terminal Pi. Therefore, according to the present embodiment, it is possible to obtain an excellent effect that the circuit can be protected from backflow while suppressing an increase in the circuit area of the power supply circuit 1.
  • the reverse flow does not flow because the transistor T1 is driven off by the pre-driver 2 at the time of abnormality. Then, since the detection signal Sc output from the current detection unit 8 turns to a high level, the transistor T1 is turned on by the pre-driver 2 so that a reverse flow can flow again. When the reverse flow again flows, the detection signal Sc output from the current detection unit 8 turns to a low level, so that the transistor T1 is driven off by the pre-driver 2.
  • an abnormal state that is, when a backflow can flow from the power supply output terminal Po to the power supply input terminal Pi
  • the transistor T1 is repeatedly turned on and off in this manner, so that the power supply circuit 1 is protected from the backflow. It has become.
  • the back gate control unit 7 may apply the voltage on the drain side of the transistor T1 to the back gate at least during the period when the low level detection signal Sc is output from the current detection unit 8.
  • the back gate controller 7 may always apply the drain side voltage of the transistor T1 to the back gate. Even with such a configuration, the effect of preventing the above-described backflow can be obtained.
  • a body diode whose drain side is the anode is always formed between the drain and source of the transistor T1. Therefore, in a steady state, a current (forward current) flows through the path through the body diode of the transistor T1, and the loss increases accordingly.
  • the back gate control unit 7 connects the back gate of the transistor T1 to the source side, that is, the power supply output terminal Po during the period when the high level detection signal Sc is output from the current detection unit 8.
  • the back gate control unit 7 connects the back gate of the transistor T1 to the source side, that is, the power supply output terminal Po during the period when the high level detection signal Sc is output from the current detection unit 8.
  • a body diode having the anode on the source side is formed between the drain and source of the transistor T1. Therefore, in a steady state, forward current does not flow through a path through the body diode of the transistor T1, so that an increase in loss can be prevented.
  • the power supply circuit 21 of the present embodiment is different from the power supply circuit 1 of the first embodiment in that a comparator CP21 and a D-type flip-flop 22 are added.
  • the output voltage VOUT is applied to the inverting input terminal of the comparator CP21, and the input voltage AVDD is applied to the non-inverting input terminal.
  • the output signal Sa of the comparator CP21 is at a high level when the input voltage AVDD is higher than the output voltage VOUT, and is at a low level when the output voltage VOUT is higher than the input voltage AVDD.
  • the comparator CP21 corresponds to a voltage detection unit that detects the input voltage AVDD and the output voltage VOUT.
  • the output signal Sa of the comparator CP21 is given to the clock terminal of the flip-flop 22.
  • a high level (for example, + 5V) signal is applied to the input terminal D of the flip-flop 22.
  • a detection signal Sc output from the current detection unit 8 is given to the reset terminal R bar of the flip-flop 22. In FIG. 2, the reset terminal R bar is indicated by “-” on the R.
  • the output signal Sf output from the output terminal Q of the flip-flop 22 is given to the inverting buffers 3 and 4.
  • the flip-flop 22 when the detection signal Sc output from the current detection unit 8 becomes low level, the flip-flop 22 outputs a low level output signal Sf. The output state continues until the output signal Sa of the comparator CP21 applied to the clock terminal changes from the low level to the high level.
  • the voltage level of the control terminal P1 of the pre-driver 2 is high when the output signal Sf is high, and is low when the output signal Sf is low. Therefore, when the output signal Sf is at the high level, the pre-driver 2 drives the transistor T1 by outputting the gate drive signal Sg corresponding to the error signal Sd. Further, when the output signal Sf is at a low level, the pre-driver 2 forcibly turns off the transistor T1 regardless of the error signal Sd.
  • the back gate controller 7 controls the voltage applied to the back gate of the transistor T1 according to the output signal Sf of the flip-flop 22. Specifically, the back gate control unit 7 connects the back gate of the transistor T1 to the power supply output terminal Po during a period in which the high level output signal Sf is output, so that the output voltage VOUT is applied to the back gate of the transistor T1. give. Further, the back gate control unit 7 applies the input voltage AVDD to the back gate of the transistor T1 by connecting the back gate of the transistor T1 to the power supply input terminal Pi during the period when the low level output signal Sf is output.
  • the pre-driver 2, the inverting buffer 3, the transistor T2, and the flip-flop 22 constitute an off drive unit 23.
  • the off drive unit 23 continues the off drive of the transistor T1 if the output signal Sa of the comparator CP21 does not change from the low level to the high level after the low level detection signal Sc is output, and the output signal Sa changes from the low level to the high level.
  • the off-drive of the transistor T1 is released.
  • the transistor T1, the back gate control unit 7, the current detection unit 8, and the off drive unit 23 constitute a current protection circuit 24.
  • the output signal Sa may change from the low level to the high level. Therefore, the off-drive of the transistor T1 by the pre-driver 2 is also continued.
  • the state in which the reverse flow can flow that is, when the input voltage AVDD becomes larger than the output voltage VOUT, the output signal Sa changes from the low level to the high level, and thus the pre-driver 2 releases the off drive of the transistor T1 Is done.
  • the off driving unit 23 continues the off driving of the transistor T1 unless the output signal Sa of the comparator CP21 changes from the low level to the high level after the low level detection signal Sc is output.
  • the transistor T1 is turned off. Therefore, when the transistor T1 is turned off in a state in which a reverse flow can flow, that is, in a state of “AVDD ⁇ VOUT”, the transistor T1 is continuously turned off unless the state in which the reverse flow can flow is eliminated. Therefore, in this embodiment, when the circuit is protected from the backflow, the transistor T1 is not repeatedly turned on and off, so that the fluctuation of the output voltage VOUT can be suppressed.
  • the power supply circuit 31 of the present embodiment is different from the power supply circuit 1 of the first embodiment in that a transistor T31 is provided instead of the transistor T1, and that the back gate control unit 7 The difference is that the gate control unit 32 is provided and the inversion buffer 4 is omitted.
  • the transistor T31 is a P-channel type power MOS transistor.
  • the source of the transistor T31 is connected to the power input terminal Pi via the shunt resistor Rs.
  • the drain of the transistor T31 is connected to the power output terminal Po. That is, the transistor T31 is interposed in series between the power input terminal Pi and the power output terminal Po, and corresponds to a main transistor.
  • a gate drive signal Sg output from the pre-driver 2 is given to the gate of the transistor T31.
  • the back gate control unit 32 controls the voltage applied to the back gate of the transistor T31 according to the detection signal Sc output from the current detection unit 8. Specifically, the back gate control unit 32 connects the back gate of the transistor T31 to the source side, that is, the power input terminal Pi during a period in which the high level detection signal Sc is output. As a result, when a current flows in a direction flowing from the power input terminal Pi to the power output terminal Po, that is, in a steady state, the source side voltage, that is, the input voltage AVDD is applied to the back gate of the transistor T31.
  • the back gate control unit 32 connects the back gate of the transistor T31 to the drain side, that is, the power supply output terminal Po during the period when the low level detection signal Sc is output.
  • the drain side voltage that is, the output voltage VOUT is applied to the back gate of the transistor T31.
  • the back gate control unit 32 includes transistors T33 to T36 and a current source 33.
  • the transistor T33 is a P-channel MOS transistor, and its source is connected to the power input terminal Pi.
  • the drain of the transistor T33 is connected to the ground terminal Pg through the current source 33.
  • a detection signal Sc is supplied to the gate of the transistor T33.
  • the transistor T34 is an N-channel MOS transistor, and its source is connected to the power output terminal Po.
  • the gate of the transistor T34 is connected to the drain of the transistor T33.
  • the drain of the transistor T34 is connected to the node N31.
  • the node N31 is connected to the back gate of the transistor T31.
  • the transistors T35 and T36 are both P-channel MOS transistors, and their sources are connected to the node N31.
  • the drains of the transistors T35 and T36 are connected to the power input terminal Pi.
  • the gate of the transistor T35 is connected to the power supply output terminal Po.
  • the transistor T36 is driven on and off by the pre-driver 2. Specifically, the pre-driver 2 turns on the transistor T36 when the voltage level of the control terminal P1 is high. Further, the pre-driver 2 drives the transistor T36 off when the voltage level of the control terminal P1 is low.
  • the transistor T33 when the high-level detection signal Sc is output from the current detection unit 8, the transistor T33 is turned off, thereby turning off the transistor T34. At this time, the transistor T36 is turned on by the pre-driver 2. Accordingly, the transistor T35 is also turned on. By such an operation, the node N31 is connected to the power supply input terminal Pi, and the input voltage AVDD is applied to the back gate of the transistor T31.
  • the transistor T33 is turned on to turn on the transistor T34.
  • the transistor T36 is driven off by the pre-driver 2. Accordingly, the transistor T35 is turned off.
  • the node N31 is connected to the power supply output terminal Po, and the output voltage VOUT is given to the back gate of the transistor T31.
  • the transistor T31, the back gate control unit 32, the current detection unit 8, and the off drive unit 9 protect the circuit such as the power supply circuit 31 from the backflow that flows from the power supply output terminal Po to the power supply input terminal Pi.
  • a current protection circuit 34 for realizing the function is configured.
  • the same operation and effect as the first embodiment can be obtained. That is, in the power supply circuit 31 configured as described above, when a backflow that flows from the power supply output terminal Po to the power supply input terminal Pi occurs as in the power supply circuit 1 of the first embodiment, the current detection unit 8 generates the low level detection signal Sc. Output. When the low-level detection signal Sc is output from the current detection unit 8, the pre-driver 2 that configures the off-drive unit 9 forcibly drives the transistor T31 off regardless of the error signal Sd output from the error amplifier 6. To do. Thereby, the backflow by the path
  • the back gate control unit 32 supplies the output voltage VOUT, which is the voltage on the drain side of the transistor T31, to the back gate of the transistor T31.
  • VOUT the voltage on the drain side of the transistor T31
  • the drive of one transistor T31 provided in series in the path from the power input terminal Pi to the power output terminal Po is controlled, and the back gate is controlled to control the power output terminal Po. Is prevented from flowing back to the power input terminal Pi. Therefore, also in the present embodiment, as in the first embodiment, an excellent effect that the circuit can be protected from the backflow while suppressing an increase in the circuit area of the power supply circuit 31 is obtained.
  • the power supply circuit 41 of this embodiment is different from the power supply circuit 1 of the first embodiment in that a current detection unit 42 is provided instead of the current detection unit 8.
  • the current detection unit 42 includes a transistor T41 and a current source 43 in addition to the configuration included in the current detection unit 8.
  • the drain of the transistor T1 is directly connected to the power input terminal Pi.
  • the transistor T41 is an N-channel MOS transistor, and its drain is connected to the power input terminal Pi via the shunt resistor Rs.
  • the source and gate of the transistor T41 are commonly connected, and the commonly connected source and gate are connected to the gate of the transistor T1 and to the ground terminal Pg via the current source 43.
  • the back gate of the transistor T41 is connected to the ground terminal Pg.
  • the transistor T1 and the transistor T41 constitute a current mirror circuit. Therefore, a current (hereinafter referred to as a detection current) corresponding to the current flowing through the transistor T1 flows through the transistor T41.
  • the detection current is determined by the size ratio of the transistor T1 and the transistor T41. Therefore, the transistor T41 corresponds to a current detection transistor that supplies a detection current corresponding to the current flowing through the transistor T1. That is, the current detection unit 42 of the present embodiment detects the current flowing through the transistor T1 based on the detection current flowing through the transistor T41.
  • the transistor T1, the back gate control unit 7, the current detection unit 42, and the off drive unit 9 protect the circuit such as the power supply circuit 41 from the backflow that flows from the power supply output terminal Po to the power supply input terminal Pi.
  • a current protection circuit 44 that realizes the function is configured.
  • the shunt resistor Rs is not interposed in the power supply path from the power input terminal Pi to the power output terminal Po. Therefore, according to the present embodiment, it is possible to further reduce the resistance of the power supply path, and as a result, it is possible to further reduce power loss and improve the accuracy of voltage control. The effect is obtained.
  • the specific configuration of the back gate control units 7 and 32 is not limited to the configuration shown in FIGS. 1 and 3 and the like, and can be appropriately changed as long as a desired operation can be realized.
  • the present disclosure is not limited to a power supply circuit included in an electronic control device mounted on a vehicle, and is a circuit having an input terminal for inputting an input voltage and an output terminal for outputting an output voltage lower than the input voltage.
  • the present invention can be applied to all circuits in which a backflow may flow from the output terminal to the input terminal.

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Abstract

A current protection circuit (11, 24, 34, 44), provided with an MOS transistor (T1, T31), a current detector (8, 42), an off driving unit (9, 23), and a back gate control unit (7, 32). The MOS transistor is serially connected between an input terminal (Pi) for inputting an input voltage and an output terminal (Po) for outputting an output voltage lower than the input voltage. The current detector detects a current flowing between the input terminal and the output terminal and outputs a detection signal representing the direction of the detected current. When a detection signal representing a first direction, which is the direction of a current flowing from the output terminal to the input terminal, is outputted, the off driving unit performs off-driving of the MOS transistor. At least while the detection signal representing the first direction is being outputted from the current detector, the back gate control unit applies the voltage of the drain side of the MOS transistor to the back gate of the MOS transistor.

Description

電流保護回路Current protection circuit 関連出願の相互参照Cross-reference of related applications
　本出願は、２０１６年１１月７日に出願された日本出願番号２０１６－２１７１６２号に基づくもので、ここにその記載内容を援用する。 This application is based on Japanese Patent Application No. 2016-217162 filed on November 7, 2016, the contents of which are incorporated herein by reference.
　本開示は、出力端子から入力端子へと流れる逆流から回路を保護する電流保護回路に関する。 This disclosure relates to a current protection circuit that protects a circuit from a backflow that flows from an output terminal to an input terminal.
　例えばシリーズレギュレータ形式の電源回路には、出力端子から入力端子へと流れる逆流から回路を保護するための電流保護回路を備えるものがある。このような逆流保護回路としては、主トランジスタと直列に逆流保護用のトランジスタを設ける構成（例えば、特許文献１参照）を挙げることができる。この場合、入出力端子の電位関係をコンパレータで検出し、コンパレータの出力に基づいて入出力端子の電位関係が逆転したことを検出すると、逆流保護用のトランジスタをオフ駆動することで、逆流の防止を実現している。 For example, some series regulator type power supply circuits include a current protection circuit for protecting the circuit from a backflow flowing from the output terminal to the input terminal. An example of such a backflow protection circuit is a configuration in which a backflow protection transistor is provided in series with the main transistor (see, for example, Patent Document 1). In this case, the potential relationship between the input and output terminals is detected by a comparator, and when the potential relationship between the input and output terminals is reversed based on the output of the comparator, the reverse current protection transistor is turned off to prevent back flow. Is realized.
特開２００４－３１２２３１号公報Japanese Patent Laid-Open No. 2004-312231
　上記した従来技術の構成では、電源回路の入力端子から出力端子に至る電源供給経路に対し、２つのトランジスタが直列に介在している。電源供給経路は、損失低減などの目的から低抵抗化が必要であるため、これらのトランジスタのサイズを大きくしなければならず、その結果、回路面積が増加することになる。 In the configuration of the conventional technique described above, two transistors are interposed in series with respect to the power supply path from the input terminal to the output terminal of the power supply circuit. Since the power supply path needs to have a low resistance for the purpose of reducing loss, the size of these transistors must be increased, resulting in an increase in circuit area.
　本開示の目的は、回路面積の増加を抑制しつつ、逆流から回路を保護することができる電流保護回路を提供することにある。 An object of the present disclosure is to provide a current protection circuit that can protect a circuit from backflow while suppressing an increase in circuit area.
　本開示の第一の態様において、電流保護回路は、ＭＯＳトランジスタ、電流検出部、オフ駆動部およびバックゲート制御部を備える。ＭＯＳトランジスタは、入力電圧を入力するための入力端子および入力電圧よりも低い出力電圧を出力するための出力端子の間に直列接続されている。なお、一般に、このような箇所に接続されるＭＯＳトランジスタは、Ｎチャネル型であれば、そのドレインが入力端子側に接続されるとともに、そのソースが出力端子側に接続される。また、Ｐチャネル型であれば、そのソースが入力端子側に接続されるとともに、そのドレインが出力端子側に接続される。 In the first aspect of the present disclosure, the current protection circuit includes a MOS transistor, a current detection unit, an off drive unit, and a back gate control unit. The MOS transistor is connected in series between an input terminal for inputting an input voltage and an output terminal for outputting an output voltage lower than the input voltage. In general, if the MOS transistor connected to such a location is an N-channel type, its drain is connected to the input terminal side and its source is connected to the output terminal side. In the case of the P channel type, the source is connected to the input terminal side, and the drain is connected to the output terminal side.
　電流検出部は、入力端子および出力端子の間に流れる電流を検出し、その検出した電流の向きを表す検出信号を出力する。オフ駆動部は、出力端子から入力端子へと流れる電流の向きである第１方向を表す検出信号が出力されると、ＭＯＳトランジスタをオフ駆動する。バックゲート制御部は、少なくとも電流検出部から第１方向を表す検出信号が出力される期間、ＭＯＳトランジスタのドレイン側の電圧をＭＯＳトランジスタのバックゲートに与える。 The current detection unit detects a current flowing between the input terminal and the output terminal, and outputs a detection signal indicating the direction of the detected current. When the detection signal indicating the first direction, which is the direction of the current flowing from the output terminal to the input terminal, is output, the off drive unit drives the MOS transistor off. The back gate control unit applies a voltage on the drain side of the MOS transistor to the back gate of the MOS transistor at least during a period in which the detection signal indicating the first direction is output from the current detection unit.
　このような構成において、出力端子から入力端子へと流れる逆流が発生すると、電流検出部は、出力端子から入力端子へと流れる電流の向きである第１方向（＝逆方向）を表す検出信号を出力する。オフ駆動部は、電流検出部から第１方向を表す検出信号が出力されると、ＭＯＳトランジスタをオフ駆動する。これにより、ＭＯＳトランジスタのチャネルを介した経路による逆流が阻止される。 In such a configuration, when a backflow that flows from the output terminal to the input terminal occurs, the current detection unit generates a detection signal that represents the first direction (= reverse direction) that is the direction of the current that flows from the output terminal to the input terminal. Output. The off drive unit drives the MOS transistor off when a detection signal representing the first direction is output from the current detection unit. As a result, backflow through the path through the channel of the MOS transistor is prevented.
　また、このとき、バックゲート制御部は、ＭＯＳトランジスタのドレイン側の電圧をＭＯＳトランジスタのバックゲートに与える。このようにすれば、ＭＯＳトランジスタがＮチャネル型である場合、ＭＯＳトランジスタのドレイン・ソース間に、ドレイン側つまり入力端子側をアノードとしたボディダイオードが形成された状態となる。また、ＭＯＳトランジスタがＰチャネル型である場合、ＭＯＳトランジスタのソース・ドレイン間に、ソース側つまり入力端子側をアノードとしたボディダイオードが形成された状態となる。そのため、ＭＯＳトランジスタのボディダイオードを介した経路による逆流も阻止される。 At this time, the back gate control unit applies the voltage on the drain side of the MOS transistor to the back gate of the MOS transistor. In this way, when the MOS transistor is an N-channel type, a body diode having the anode on the drain side, that is, the input terminal side, is formed between the drain and source of the MOS transistor. When the MOS transistor is a P-channel type, a body diode having an anode on the source side, that is, the input terminal side, is formed between the source and drain of the MOS transistor. For this reason, backflow through the path through the body diode of the MOS transistor is also prevented.
　このように、上記構成では、入力端子から出力端子に至る経路に直列に設けられた１つのＭＯＳトランジスタの駆動を制御するとともに、バックゲートを制御することにより、出力端子から入力端子へと流れる逆流の発生を防止している。したがって、上記構成によれば、回路面積の増加を抑制しつつ、逆流から回路を保護することができるという優れた効果が得られる。 As described above, in the above configuration, the backflow that flows from the output terminal to the input terminal is controlled by controlling the driving of one MOS transistor provided in series in the path from the input terminal to the output terminal and controlling the back gate. Is prevented. Therefore, according to the said structure, the outstanding effect that a circuit can be protected from a backflow is obtained, suppressing the increase in a circuit area.
　本開示についての上記目的およびその他の目的、特徴や利点は、添付の図面を参照しながら下記の詳細な記述により、より明確になる。その図面は、
図１は、第１実施形態に係る電源回路の構成を模式的に示す図であり、 図２は、第２実施形態に係る電源回路の構成を模式的に示す図であり、 図３は、第３実施形態に係る電源回路の構成を模式的に示す図であり、 図４は、第４実施形態に係る電源回路の構成を模式的に示す図である。 The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description with reference to the accompanying drawings. The drawing
FIG. 1 is a diagram schematically showing the configuration of the power supply circuit according to the first embodiment. FIG. 2 is a diagram schematically showing the configuration of the power supply circuit according to the second embodiment. FIG. 3 is a diagram schematically showing the configuration of the power supply circuit according to the third embodiment. FIG. 4 is a diagram schematically showing the configuration of the power supply circuit according to the fourth embodiment.
　以下、複数の実施形態について図面を参照して説明する。なお、各実施形態において実質的に同一の構成には同一の符号を付して説明を省略する。
　　　（第１実施形態）
　以下、第１実施形態について図１を参照して説明する。 Hereinafter, a plurality of embodiments will be described with reference to the drawings. In each embodiment, substantially the same components are denoted by the same reference numerals and description thereof is omitted.
(First embodiment)
The first embodiment will be described below with reference to FIG.
　図１に示す電源回路１は、例えば車両に搭載される電子制御装置（以下、ＥＣＵとも呼ぶ）において用いられる。電源回路１は、電源入力端子Ｐｉを通じて与えられる入力電圧ＡＶＤＤを降圧して電源出力端子Ｐｏから所望の電圧値を持つ出力電圧ＶＯＵＴとして出力するシリーズレギュレータ形式の電源回路である。なお、入力電圧ＡＶＤＤは、車載のバッテリ（図示略）から出力されるバッテリ電圧、または、そのバッテリ電圧を入力とする別の電源回路から出力される直流電圧である。 The power supply circuit 1 shown in FIG. 1 is used in, for example, an electronic control device (hereinafter also referred to as ECU) mounted on a vehicle. The power supply circuit 1 is a series regulator type power supply circuit that steps down the input voltage AVDD given through the power supply input terminal Pi and outputs it as an output voltage VOUT having a desired voltage value from the power supply output terminal Po. The input voltage AVDD is a battery voltage output from an in-vehicle battery (not shown) or a DC voltage output from another power supply circuit that receives the battery voltage.
　この場合、入力電圧ＡＶＤＤの定常値は例えば１２Ｖであり、出力電圧ＶＯＵＴの目標値は例えば５Ｖである。つまり、定常時、入力電圧ＡＶＤＤおよび出力電圧ＶＯＵＴは、「ＡＶＤＤ＞ＶＯＵＴ」という関係になっている。そのため、定常時、電源回路１では、電源入力端子Ｐｉから電源出力端子Ｐｏへと順方向に電流が流れる。 In this case, the steady value of the input voltage AVDD is 12V, for example, and the target value of the output voltage VOUT is 5V, for example. That is, in a steady state, the input voltage AVDD and the output voltage VOUT have a relationship of “AVDD> VOUT”. Therefore, in a steady state, in the power supply circuit 1, a current flows in the forward direction from the power input terminal Pi to the power output terminal Po.
　また、電源出力端子Ｐｏは、例えば配線などを通じてＥＣＵの外部に導出されており、その配線などが外部に存在する高電圧部分とショートする可能性がある。電源出力端子Ｐｏが高電圧部分とショートする故障が生じたとき（以下、異常時とも呼ぶ）、入力電圧ＡＶＤＤおよび出力電圧ＶＯＵＴは、「ＡＶＤＤ＜ＶＯＵＴ」という関係となる。そのため、異常時、電源回路１では、電源出力端子Ｐｏから電源出力端子Ｐｉへと逆方向に電流が流れるおそれがある。詳細は後述するが、本実施形態の電源回路１は、このような逆方向の電流（以下、逆流とも呼ぶ）から回路を保護するための保護機能を備えている。 Also, the power output terminal Po is led out of the ECU through, for example, wiring, and there is a possibility that the wiring or the like may be short-circuited with a high voltage portion existing outside. When a failure occurs in which the power supply output terminal Po is short-circuited with a high voltage portion (hereinafter also referred to as an abnormality), the input voltage AVDD and the output voltage VOUT have a relationship of “AVDD <VOUT”. Therefore, at the time of abnormality, in the power supply circuit 1, a current may flow in the reverse direction from the power supply output terminal Po to the power supply output terminal Pi. Although details will be described later, the power supply circuit 1 of the present embodiment includes a protection function for protecting the circuit from such a reverse current (hereinafter also referred to as a reverse flow).
　電源回路１は、トランジスタＴ１、Ｔ２、プリドライバ２、シャント抵抗Ｒｓ、コンパレータＣＰ１、反転バッファ３、４、電圧検出回路５、誤差アンプ６、バックゲート制御部７などを備えている。トランジスタＴ１は、Ｎチャネル型のパワーＭＯＳトランジスタである。 The power supply circuit 1 includes transistors T1 and T2, a pre-driver 2, a shunt resistor Rs, a comparator CP1, inversion buffers 3 and 4, a voltage detection circuit 5, an error amplifier 6, a back gate control unit 7, and the like. The transistor T1 is an N-channel power MOS transistor.
　トランジスタＴ１のドレインは、シャント抵抗Ｒｓを介して電源入力端子Ｐｉに接続されている。トランジスタＴ１のソースは、電源出力端子Ｐｏに接続されている。つまり、トランジスタＴ１は、電源入力端子Ｐｉおよび電源出力端子Ｐｏの間に直列に介在するものであり、主トランジスタに相当する。トランジスタＴ１のゲートには、プリドライバ２から出力されるゲート駆動信号Ｓｇが与えられている。なお、この場合、電源入力端子Ｐｉは入力端子に相当し、電源出力端子Ｐｏは出力端子に相当する。 The drain of the transistor T1 is connected to the power input terminal Pi via the shunt resistor Rs. The source of the transistor T1 is connected to the power output terminal Po. That is, the transistor T1 is interposed in series between the power input terminal Pi and the power output terminal Po, and corresponds to a main transistor. A gate drive signal Sg output from the pre-driver 2 is given to the gate of the transistor T1. In this case, the power input terminal Pi corresponds to an input terminal, and the power output terminal Po corresponds to an output terminal.
　電源入力端子Ｐｉおよび電源出力端子Ｐｏの間に直列に介在するシャント抵抗Ｒｓの一方の端子電圧（＝入力電圧ＡＶＤＤ）は、コンパレータＣＰ１の非反転入力端子に与えられる。シャント抵抗Ｒｓの他方の端子電圧（＝トランジスタＴ１のドレイン電圧）は、コンパレータＣＰ１の反転入力端子に与えられる。コンパレータＣＰ１の出力信号は、電源入力端子Ｐｉおよび電源出力端子Ｐｏの間を流れる電流の検出信号Ｓｃとして反転バッファ３、４に与えられる。 One terminal voltage (= input voltage AVDD) of the shunt resistor Rs interposed in series between the power input terminal Pi and the power output terminal Po is given to the non-inverting input terminal of the comparator CP1. The other terminal voltage of the shunt resistor Rs (= the drain voltage of the transistor T1) is applied to the inverting input terminal of the comparator CP1. The output signal of the comparator CP1 is supplied to the inverting buffers 3 and 4 as the detection signal Sc of the current flowing between the power input terminal Pi and the power output terminal Po.
　上記構成において、検出信号Ｓｃは、シャント抵抗Ｒｓの各端子電圧の大小関係に応じたレベルとなる。具体的には、検出信号Ｓｃは、シャント抵抗Ｒｓの一方の端子電圧が他方の端子電圧よりも大きい場合にはハイレベル（例えば５Ｖ）となり、シャント抵抗Ｒｓの他方の端子電圧が一方の端子電圧よりも大きい場合にはロウレベル（例えば０Ｖ）となる。このように、本実施形態では、シャント抵抗ＲｓおよびコンパレータＣＰ１により、電源入力端子Ｐｉおよび電源出力端子Ｐｏの間に流れる電流を検出し、その検出した電流の向きを表す検出信号Ｓｃを出力する電流検出部８が構成されている。 In the above configuration, the detection signal Sc has a level corresponding to the magnitude relationship between the terminal voltages of the shunt resistor Rs. Specifically, the detection signal Sc is at a high level (for example, 5 V) when one terminal voltage of the shunt resistor Rs is larger than the other terminal voltage, and the other terminal voltage of the shunt resistor Rs is one terminal voltage. If it is larger than the low level, it becomes a low level (for example, 0 V). As described above, in the present embodiment, the current that flows between the power input terminal Pi and the power output terminal Po is detected by the shunt resistor Rs and the comparator CP1, and the detection signal Sc that represents the direction of the detected current is output. A detection unit 8 is configured.
　本実施形態では、電源出力端子Ｐｏから電源出力端子Ｐｉへと流れる電流の向き、つまり逆方向の電流（逆電流）の向きを第１方向とし、電源入力端子Ｐｉから電源出力端子Ｐｏへと流れる電流の向き、つまり順方向の電流（順電流）の向きを第２方向とする。そのため、ロウレベルの検出信号Ｓｃが第１方向（逆方向）を表す検出信号に相当し、ハイレベルの検出信号Ｓｃが第２方向（順方向）を表す検出信号に相当する。 In the present embodiment, the direction of the current flowing from the power output terminal Po to the power output terminal Pi, that is, the direction of the reverse current (reverse current) is defined as the first direction, and the current flows from the power input terminal Pi to the power output terminal Po. The direction of the current, that is, the direction of the forward current (forward current) is defined as the second direction. Therefore, the low level detection signal Sc corresponds to a detection signal representing the first direction (reverse direction), and the high level detection signal Sc corresponds to a detection signal representing the second direction (forward direction).
　電圧検出回路５は、抵抗Ｒ１およびＲ２の直列回路により構成されている。その直列回路は、トランジスタＴ１のソース、つまり電源出力端子Ｐｏと、回路の基準電位ＧＮＤ（０Ｖ）が与えられるグランド端子Ｐｇとの間に接続されている。抵抗Ｒ１、Ｒ２の共通接続点の電圧、つまり出力電圧ＶＯＵＴを抵抗Ｒ１、Ｒ２により分圧して得られる検出電圧Ｖｄは、誤差アンプ６の反転入力端子に与えられている。 The voltage detection circuit 5 is composed of a series circuit of resistors R1 and R2. The series circuit is connected between the source of the transistor T1, that is, the power supply output terminal Po, and the ground terminal Pg to which the reference potential GND (0 V) of the circuit is applied. The voltage at the common connection point of the resistors R1 and R2, that is, the detection voltage Vd obtained by dividing the output voltage VOUT by the resistors R1 and R2, is applied to the inverting input terminal of the error amplifier 6.
　誤差アンプ６の非反転入力端子には、出力電圧ＶＯＵＴの目標値に対応した基準電圧Ｖｒが与えられている。誤差アンプ６は、基準電圧Ｖｒおよび検出電圧Ｖｄの差に応じた誤差信号Ｓｄを出力する。誤差信号Ｓｄは、プリドライバ２に与えられている。プリドライバ２の制御端子Ｐ１とグランド端子Ｐｇとの間には、トランジスタＴ２が接続されている。トランジスタＴ２は、Ｎチャネル型のＭＯＳトランジスタである。 The reference voltage Vr corresponding to the target value of the output voltage VOUT is given to the non-inverting input terminal of the error amplifier 6. The error amplifier 6 outputs an error signal Sd corresponding to the difference between the reference voltage Vr and the detection voltage Vd. The error signal Sd is given to the pre-driver 2. A transistor T2 is connected between the control terminal P1 of the pre-driver 2 and the ground terminal Pg. The transistor T2 is an N channel type MOS transistor.
　トランジスタＴ２のゲートには、反転バッファ３の出力信号が与えられている。そのため、トランジスタＴ２は、検出信号Ｓｃがロウレベルのときにオンされ、検出信号Ｓｃがハイレベルのときにオフされる。制御端子Ｐ１は、プリドライバ２の内部においてプルアップされている。したがって、制御端子Ｐ１の電圧レベルは、検出信号ＳｃがハイレベルとなってトランジスタＴ２がオフされるとハイレベルとなり、検出信号ＳｃがロウレベルとなってトランジスタＴ２がオンされるとロウレベルとなる。 The output signal of the inverting buffer 3 is given to the gate of the transistor T2. Therefore, the transistor T2 is turned on when the detection signal Sc is at a low level, and is turned off when the detection signal Sc is at a high level. The control terminal P1 is pulled up inside the pre-driver 2. Therefore, the voltage level of the control terminal P1 becomes high level when the detection signal Sc becomes high level and the transistor T2 is turned off, and becomes low level when the detection signal Sc becomes low level and the transistor T2 is turned on.
　プリドライバ２は、制御端子Ｐ１の電圧レベルがハイレベルである場合、誤差信号Ｓｄに対応したゲート駆動信号Ｓｇを出力する。これにより、出力電圧ＶＯＵＴが目標値に一致するようにトランジスタＴ１の駆動がフィードバック制御される。また、プリドライバ２は、制御端子Ｐ１の電圧レベルがロウレベルである場合、例えば０Ｖのゲート駆動信号Ｓｇを出力することにより、トランジスタＴ１をオフ駆動する。本実施形態では、プリドライバ２、反転バッファ３およびトランジスタＴ２により、オフ駆動部９が構成されている。 The pre-driver 2 outputs a gate drive signal Sg corresponding to the error signal Sd when the voltage level of the control terminal P1 is high. Thereby, the drive of the transistor T1 is feedback controlled so that the output voltage VOUT matches the target value. Further, when the voltage level of the control terminal P1 is low level, the pre-driver 2 outputs the gate drive signal Sg of 0V, for example, to drive the transistor T1 off. In the present embodiment, the pre-driver 2, the inverting buffer 3, and the transistor T2 constitute an off drive unit 9.
　バックゲート制御部７は、電流検出部８から出力される検出信号Ｓｃに応じてトランジスタＴ１のバックゲートに与える電圧を制御する。具体的には、バックゲート制御部７は、ハイレベルの検出信号Ｓｃが出力される期間、トランジスタＴ１のバックゲートをソース側、つまり電源出力端子Ｐｏに接続する。これにより、電源入力端子Ｐｉから電源出力端子Ｐｏへと流れる向きに電流が流れているとき、つまり定常時、トランジスタＴ１のバックゲートにはソース側の電圧、つまり出力電圧ＶＯＵＴが与えられる。 The back gate control unit 7 controls the voltage applied to the back gate of the transistor T1 in accordance with the detection signal Sc output from the current detection unit 8. Specifically, the back gate control unit 7 connects the back gate of the transistor T1 to the source side, that is, the power supply output terminal Po during a period in which the high level detection signal Sc is output. As a result, when a current flows in a direction flowing from the power input terminal Pi to the power output terminal Po, that is, in a steady state, the source side voltage, that is, the output voltage VOUT is applied to the back gate of the transistor T1.
　また、バックゲート制御部７は、ロウレベルの検出信号Ｓｃが出力される期間、トランジスタＴ１のバックゲートをドレイン側、つまり電源入力端子Ｐｉに接続する。これにより、電源出力端子Ｐｏから電源入力端子Ｐｉへと流れる向きに電流が流れているとき、つまり逆流時、トランジスタＴ１のバックゲートにはドレイン側の電圧、つまり入力電圧ＡＶＤＤが与えられる。 Further, the back gate control unit 7 connects the back gate of the transistor T1 to the drain side, that is, the power supply input terminal Pi during the period when the low level detection signal Sc is output. As a result, when a current flows in the direction of flowing from the power supply output terminal Po to the power supply input terminal Pi, that is, in a reverse flow, the drain side voltage, that is, the input voltage AVDD is applied to the back gate of the transistor T1.
　バックゲート制御部７の具体的な構成としては、例えば図１に示すような構成を採用することができる。すなわち、バックゲート制御部７は、トランジスタＴ３～Ｔ６および電流源１０を備えている。トランジスタＴ３は、Ｎチャネル型のＭＯＳトランジスタであり、そのソースはグランド端子Ｐｇに接続されている。トランジスタＴ３のドレインは、電流源１０を介して電源入力端子Ｐｉに接続されている。トランジスタＴ３のゲートには、反転バッファ４の出力信号が与えられている。 As a specific configuration of the back gate control unit 7, for example, a configuration as shown in FIG. 1 can be adopted. That is, the back gate control unit 7 includes transistors T3 to T6 and a current source 10. The transistor T3 is an N-channel MOS transistor, and its source is connected to the ground terminal Pg. The drain of the transistor T3 is connected to the power input terminal Pi via the current source 10. The output signal of the inverting buffer 4 is given to the gate of the transistor T3.
　トランジスタＴ４は、Ｐチャネル型のＭＯＳトランジスタであり、そのソースは電源入力端子Ｐｉに接続されている。トランジスタＴ４のゲートは、トランジスタＴ３のドレインに接続されている。トランジスタＴ４のドレインは、ノードＮ１に接続されている。ノードＮ１は、トランジスタＴ１のバックゲートに接続されている。 The transistor T4 is a P-channel MOS transistor, and its source is connected to the power input terminal Pi. The gate of the transistor T4 is connected to the drain of the transistor T3. The drain of the transistor T4 is connected to the node N1. Node N1 is connected to the back gate of transistor T1.
　トランジスタＴ５、Ｔ６は、いずれもＮチャネル型のＭＯＳトランジスタであり、それらのソースはノードＮ１に接続されている。トランジスタＴ５、Ｔ６の各ドレインは、電源出力端子Ｐｏに接続されている。トランジスタＴ５のゲートは、電源入力端子Ｐｉに接続されている。 The transistors T5 and T6 are both N-channel MOS transistors, and their sources are connected to the node N1. The drains of the transistors T5 and T6 are connected to the power output terminal Po. The gate of the transistor T5 is connected to the power input terminal Pi.
　トランジスタＴ６は、プリドライバ２によりオンオフ駆動される。具体的には、プリドライバ２は、制御端子Ｐ１の電圧レベルがハイレベルであるときに、トランジスタＴ６をオン駆動する。また、プリドライバ２は、制御端子Ｐ１の電圧レベルがロウレベルであるときに、トランジスタＴ６をオフ駆動する。 The transistor T6 is driven on and off by the pre-driver 2. Specifically, the pre-driver 2 turns on the transistor T6 when the voltage level of the control terminal P1 is high. The pre-driver 2 drives off the transistor T6 when the voltage level of the control terminal P1 is low.
　このような構成によれば、電流検出部８からハイレベルの検出信号Ｓｃが出力されると、トランジスタＴ３がオフすることによりトランジスタＴ４がオフされる。また、このとき、トランジスタＴ６はプリドライバ２によりオン駆動される。そして、これに伴い、トランジスタＴ５もオンされる。このような動作により、ノードＮ１が電源出力端子Ｐｏに接続され、トランジスタＴ１のバックゲートに出力電圧ＶＯＵＴが与えられる。 According to such a configuration, when the high-level detection signal Sc is output from the current detection unit 8, the transistor T4 is turned off, thereby turning off the transistor T4. At this time, the transistor T6 is turned on by the pre-driver 2. Accordingly, the transistor T5 is also turned on. By such an operation, the node N1 is connected to the power supply output terminal Po, and the output voltage VOUT is applied to the back gate of the transistor T1.
　また、電流検出部８からロウレベルの検出信号Ｓｃが出力されると、トランジスタＴ３がオンすることによりトランジスタＴ４がオンされる。また、このとき、トランジスタＴ６はプリドライバ２によりオフ駆動される。そして、これに伴い、トランジスタＴ５がオフされる。このような動作により、ノードＮ１が電源入力端子Ｐｉに接続され、トランジスタＴ１のバックゲートに入力電圧ＡＶＤＤが与えられる。 Further, when the low-level detection signal Sc is output from the current detection unit 8, the transistor T4 is turned on to turn on the transistor T4. At this time, the transistor T6 is driven off by the pre-driver 2. Accordingly, the transistor T5 is turned off. By such an operation, the node N1 is connected to the power supply input terminal Pi, and the input voltage AVDD is applied to the back gate of the transistor T1.
　上記構成において、トランジスタＴ１、バックゲート制御部７、電流検出部８およびオフ駆動部９により、電源出力端子Ｐｏから電源入力端子Ｐｉへと流れる逆流から電源回路１などの回路を保護するための保護機能を実現する電流保護回路１１が構成されている。 In the above configuration, the transistor T1, the back gate control unit 7, the current detection unit 8, and the off drive unit 9 protect the circuit such as the power supply circuit 1 from the backflow that flows from the power supply output terminal Po to the power supply input terminal Pi. A current protection circuit 11 that realizes the function is configured.
　次に、上記構成の電源回路１の動作について説明する。
　　［１］入力電圧ＡＶＤＤ＞出力電圧ＶＯＵＴのとき
　定常時、入力電圧ＡＶＤＤおよび出力電圧ＶＯＵＴは、「ＡＶＤＤ＞ＶＯＵＴ」という関係になる。このような場合、電流検出部８からハイレベルの検出信号Ｓｃが出力される。これに伴い、バックゲート制御部７は、トランジスタＴ１のバックゲートを電源出力端子Ｐｏに接続する。そして、オフ駆動部９を構成するプリドライバ２は、出力電圧ＶＯＵＴが目標値に一致するようにトランジスタＴ１を駆動する。 Next, the operation of the power supply circuit 1 having the above configuration will be described.
[1] When the input voltage AVDD> the output voltage VOUT: The input voltage AVDD and the output voltage VOUT are always in a relationship of “AVDD> VOUT”. In such a case, a high level detection signal Sc is output from the current detector 8. Accordingly, the back gate control unit 7 connects the back gate of the transistor T1 to the power output terminal Po. Then, the pre-driver 2 constituting the off drive unit 9 drives the transistor T1 so that the output voltage VOUT matches the target value.
　　［２］入力電圧ＡＶＤＤ＜出力電圧ＶＯＵＴのとき
　異常時、入力電圧ＡＶＤＤおよび出力電圧ＶＯＵＴは、「ＡＶＤＤ＜ＶＯＵＴ」という関係になる。このような場合、電流検出部８からロウレベルの検出信号Ｓｃが出力される。これに伴い、バックゲート制御部７は、トランジスタＴ１のバックゲートを電源入力端子Ｐｉに接続する。そして、オフ駆動部９を構成するプリドライバ２は、トランジスタＴ１をオフ駆動する。 [2] When the input voltage AVDD <the output voltage VOUT When an abnormality occurs, the input voltage AVDD and the output voltage VOUT have a relationship of “AVDD <VOUT”. In such a case, the low-level detection signal Sc is output from the current detection unit 8. Accordingly, the back gate control unit 7 connects the back gate of the transistor T1 to the power input terminal Pi. Then, the pre-driver 2 constituting the off drive unit 9 drives off the transistor T1.
　以上説明した本実施形態によれば、次のような効果が得られる。
　上記構成の電源回路１では、電源出力端子Ｐｏから電源入力端子Ｐｉへと流れる逆流が発生すると、電流検出部８は、ロウレベルの検出信号Ｓｃを出力する。オフ駆動部９を構成するプリドライバ２は、電流検出部８からロウレベルの検出信号Ｓｃが出力されると、誤差アンプ６から出力される誤差信号Ｓｄに関係なく、トランジスタＴ１を強制的にオフ駆動する。これにより、トランジスタＴ１のチャネルを介した経路による逆流が阻止される。 According to this embodiment described above, the following effects can be obtained.
In the power supply circuit 1 configured as described above, when a backflow that flows from the power supply output terminal Po to the power supply input terminal Pi occurs, the current detection unit 8 outputs a low-level detection signal Sc. When the low-level detection signal Sc is output from the current detection unit 8, the pre-driver 2 constituting the off-drive unit 9 forcibly drives the transistor T <b> 1 regardless of the error signal Sd output from the error amplifier 6. To do. Thereby, the backflow by the path | route via the channel of transistor T1 is blocked | prevented.
　また、電流検出部８からロウレベルの検出信号Ｓｃが出力されている期間、バックゲート制御部７は、トランジスタＴ１のドレイン側の電圧である入力電圧ＡＶＤＤをトランジスタＴ１のバックゲートに与える。このようにすれば、トランジスタＴ１のドレイン・ソース間に、ドレイン側つまり電源入力端子Ｐｉ側をアノードとしたボディダイオードが形成された状態となる。そのため、トランジスタＴ１のボディダイオードを介した経路による逆流も阻止される。 Further, during the period when the low-level detection signal Sc is output from the current detection unit 8, the back gate control unit 7 supplies the input voltage AVDD that is the voltage on the drain side of the transistor T1 to the back gate of the transistor T1. In this way, a body diode having the drain side, that is, the power input terminal Pi side as an anode, is formed between the drain and source of the transistor T1. For this reason, backflow through the path through the body diode of the transistor T1 is also prevented.
　このように、上記構成では、電源入力端子Ｐｉから電源出力端子Ｐｏに至る経路に直列に設けられた１つのトランジスタＴ１の駆動を制御するとともに、そのバックゲートを制御することにより、電源出力端子Ｐｏから電源入力端子Ｐｉへと流れる逆流の発生を防止している。したがって、本実施形態によれば、電源回路１の回路面積の増加を抑制しつつ、逆流から回路を保護することができるという優れた効果が得られる。 Thus, in the above configuration, the drive of one transistor T1 provided in series in the path from the power input terminal Pi to the power output terminal Po is controlled and the back gate is controlled to thereby control the power output terminal Po. Is prevented from flowing back to the power input terminal Pi. Therefore, according to the present embodiment, it is possible to obtain an excellent effect that the circuit can be protected from backflow while suppressing an increase in the circuit area of the power supply circuit 1.
　上述したように、上記構成では、異常時、プリドライバ２によりトランジスタＴ１がオフ駆動されることで逆流が流れなくなる。そうすると、電流検出部８から出力される検出信号Ｓｃがハイレベルに転じるため、プリドライバ２によりトランジスタＴ１がオン駆動されて再び逆流が流れ得る状態となる。そして、再び逆流が流れると、電流検出部８から出力される検出信号Ｓｃがロウレベルに転じるため、プリドライバ２によりトランジスタＴ１がオフ駆動される。上記構成では、異常時、つまり電源出力端子Ｐｏから電源入力端子Ｐｉへと逆流が流れ得る状態のとき、このようにトランジスタＴ１のオンオフが繰り返されることにより、その逆流から電源回路１を保護するようになっている。 As described above, in the above configuration, the reverse flow does not flow because the transistor T1 is driven off by the pre-driver 2 at the time of abnormality. Then, since the detection signal Sc output from the current detection unit 8 turns to a high level, the transistor T1 is turned on by the pre-driver 2 so that a reverse flow can flow again. When the reverse flow again flows, the detection signal Sc output from the current detection unit 8 turns to a low level, so that the transistor T1 is driven off by the pre-driver 2. In the above configuration, when an abnormal state occurs, that is, when a backflow can flow from the power supply output terminal Po to the power supply input terminal Pi, the transistor T1 is repeatedly turned on and off in this manner, so that the power supply circuit 1 is protected from the backflow. It has become.
　バックゲート制御部７は、少なくとも電流検出部８からロウレベルの検出信号Ｓｃが出力される期間、トランジスタＴ１のドレイン側の電圧をバックゲートに与えればよい。例えば、バックゲート制御部７は、常時、トランジスタＴ１のドレイン側の電圧をバックゲートに与えるようにしてもよい。このような構成によっても、上述した逆流を阻止する効果を得ることができる。ただし、この場合、トランジスタＴ１のドレイン・ソース間に、ドレイン側をアノードとしたボディダイオードが、常に形成された状態となる。そのため、定常時、トランジスタＴ１のボディダイオードを介した経路でも電流（順方向の電流）が流れることになり、その分だけ損失が増加する。 The back gate control unit 7 may apply the voltage on the drain side of the transistor T1 to the back gate at least during the period when the low level detection signal Sc is output from the current detection unit 8. For example, the back gate controller 7 may always apply the drain side voltage of the transistor T1 to the back gate. Even with such a configuration, the effect of preventing the above-described backflow can be obtained. However, in this case, a body diode whose drain side is the anode is always formed between the drain and source of the transistor T1. Therefore, in a steady state, a current (forward current) flows through the path through the body diode of the transistor T1, and the loss increases accordingly.
　そこで、本実施形態では、バックゲート制御部７は、電流検出部８からハイレベルの検出信号Ｓｃが出力される期間、トランジスタＴ１のバックゲートをソース側、つまり電源出力端子Ｐｏに接続する。このようにすれば、電源入力端子Ｐｉから電源出力端子Ｐｏへと順電流が流れる定常時には、トランジスタＴ１のドレイン・ソース間に、ソース側をアノードとしたボディダイオードが形成された状態となる。そのため、定常時、トランジスタＴ１のボディダイオードを介した経路で順方向の電流が流れることがなくなるため、損失が増加することを防止することができる。 Therefore, in the present embodiment, the back gate control unit 7 connects the back gate of the transistor T1 to the source side, that is, the power supply output terminal Po during the period when the high level detection signal Sc is output from the current detection unit 8. In this way, during the steady state in which forward current flows from the power supply input terminal Pi to the power supply output terminal Po, a body diode having the anode on the source side is formed between the drain and source of the transistor T1. Therefore, in a steady state, forward current does not flow through a path through the body diode of the transistor T1, so that an increase in loss can be prevented.
　　　（第２実施形態）
　以下、第２実施形態について図２を参照して説明する。
　図２に示すように、本実施形態の電源回路２１は、第１実施形態の電源回路１に対し、コンパレータＣＰ２１およびＤ型のフリップフロップ２２が追加されている点が異なる。コンパレータＣＰ２１の反転入力端子には出力電圧ＶＯＵＴが与えられ、その非反転入力端子には入力電圧ＡＶＤＤが与えられている。 (Second Embodiment)
The second embodiment will be described below with reference to FIG.
As shown in FIG. 2, the power supply circuit 21 of the present embodiment is different from the power supply circuit 1 of the first embodiment in that a comparator CP21 and a D-type flip-flop 22 are added. The output voltage VOUT is applied to the inverting input terminal of the comparator CP21, and the input voltage AVDD is applied to the non-inverting input terminal.
　そのため、コンパレータＣＰ２１の出力信号Ｓａは、入力電圧ＡＶＤＤが出力電圧ＶＯＵＴよりも高い場合にはハイレベルとなり、出力電圧ＶＯＵＴが入力電圧ＡＶＤＤよりも高い場合にはロウレベルとなる。コンパレータＣＰ２１は、入力電圧ＡＶＤＤおよび出力電圧ＶＯＵＴを検出する電圧検出部に相当する。 Therefore, the output signal Sa of the comparator CP21 is at a high level when the input voltage AVDD is higher than the output voltage VOUT, and is at a low level when the output voltage VOUT is higher than the input voltage AVDD. The comparator CP21 corresponds to a voltage detection unit that detects the input voltage AVDD and the output voltage VOUT.
　コンパレータＣＰ２１の出力信号Ｓａは、フリップフロップ２２のクロック端子に与えられている。フリップフロップ２２の入力端子Ｄには、ハイレベル（例えば＋５Ｖ）の信号が与えられている。フリップフロップ２２のリセット端子Ｒバーには、電流検出部８から出力される検出信号Ｓｃが与えられている。なお、図２では、リセット端子Ｒバーは、Ｒの上に「－」を付して示している。フリップフロップ２２の出力端子Ｑから出力される出力信号Ｓｆは、反転バッファ３、４に与えられている。 The output signal Sa of the comparator CP21 is given to the clock terminal of the flip-flop 22. A high level (for example, + 5V) signal is applied to the input terminal D of the flip-flop 22. A detection signal Sc output from the current detection unit 8 is given to the reset terminal R bar of the flip-flop 22. In FIG. 2, the reset terminal R bar is indicated by “-” on the R. The output signal Sf output from the output terminal Q of the flip-flop 22 is given to the inverting buffers 3 and 4.
　このような構成により、フリップフロップ２２は、電流検出部８から出力される検出信号Ｓｃがロウレベルになると、ロウレベルの出力信号Ｓｆを出力する。そして、その出力状態は、クロック端子に与えられるコンパレータＣＰ２１の出力信号Ｓａがロウレベルからハイレベルに転じるまで継続される。 With such a configuration, when the detection signal Sc output from the current detection unit 8 becomes low level, the flip-flop 22 outputs a low level output signal Sf. The output state continues until the output signal Sa of the comparator CP21 applied to the clock terminal changes from the low level to the high level.
　この場合、プリドライバ２の制御端子Ｐ１の電圧レベルは、出力信号Ｓｆがハイレベルのときにハイレベルとなり、出力信号Ｓｆがロウレベルのときにロウレベルとなる。そのため、プリドライバ２は、出力信号Ｓｆがハイレベルである場合、誤差信号Ｓｄに対応したゲート駆動信号Ｓｇを出力することでトランジスタＴ１を駆動する。また、プリドライバ２は、出力信号Ｓｆがロウレベルである場合、誤差信号Ｓｄに関係なく、トランジスタＴ１を強制的にオフ駆動する。 In this case, the voltage level of the control terminal P1 of the pre-driver 2 is high when the output signal Sf is high, and is low when the output signal Sf is low. Therefore, when the output signal Sf is at the high level, the pre-driver 2 drives the transistor T1 by outputting the gate drive signal Sg corresponding to the error signal Sd. Further, when the output signal Sf is at a low level, the pre-driver 2 forcibly turns off the transistor T1 regardless of the error signal Sd.
　また、この場合、バックゲート制御部７は、フリップフロップ２２の出力信号Ｓｆに応じてトランジスタＴ１のバックゲートに与える電圧を制御する。具体的には、バックゲート制御部７は、ハイレベルの出力信号Ｓｆが出力される期間、トランジスタＴ１のバックゲートを電源出力端子Ｐｏに接続することにより、トランジスタＴ１のバックゲートに出力電圧ＶＯＵＴを与える。また、バックゲート制御部７は、ロウレベルの出力信号Ｓｆが出力される期間、トランジスタＴ１のバックゲートを電源入力端子Ｐｉに接続することにより、トランジスタＴ１のバックゲートに入力電圧ＡＶＤＤを与える。 In this case, the back gate controller 7 controls the voltage applied to the back gate of the transistor T1 according to the output signal Sf of the flip-flop 22. Specifically, the back gate control unit 7 connects the back gate of the transistor T1 to the power supply output terminal Po during a period in which the high level output signal Sf is output, so that the output voltage VOUT is applied to the back gate of the transistor T1. give. Further, the back gate control unit 7 applies the input voltage AVDD to the back gate of the transistor T1 by connecting the back gate of the transistor T1 to the power supply input terminal Pi during the period when the low level output signal Sf is output.
　本実施形態では、プリドライバ２、反転バッファ３、トランジスタＴ２およびフリップフロップ２２によりオフ駆動部２３が構成されている。オフ駆動部２３は、ロウレベルの検出信号Ｓｃが出力された後、コンパレータＣＰ２１の出力信号Ｓａがロウレベルからハイレベルに転じることがなければトランジスタＴ１のオフ駆動を継続し、出力信号Ｓａがロウレベルからハイレベルに転じるとトランジスタＴ１のオフ駆動を解除するようになっている。また、本実施形態では、トランジスタＴ１、バックゲート制御部７、電流検出部８およびオフ駆動部２３により電流保護回路２４が構成されている。 In this embodiment, the pre-driver 2, the inverting buffer 3, the transistor T2, and the flip-flop 22 constitute an off drive unit 23. The off drive unit 23 continues the off drive of the transistor T1 if the output signal Sa of the comparator CP21 does not change from the low level to the high level after the low level detection signal Sc is output, and the output signal Sa changes from the low level to the high level. When the level is changed, the off-drive of the transistor T1 is released. In the present embodiment, the transistor T1, the back gate control unit 7, the current detection unit 8, and the off drive unit 23 constitute a current protection circuit 24.
　次に、上記構成の電源回路２１の動作について説明する。
　　［１］入力電圧ＡＶＤＤ＞出力電圧ＶＯＵＴのとき
　定常時、入力電圧ＡＶＤＤおよび出力電圧ＶＯＵＴは、「ＡＶＤＤ＞ＶＯＵＴ」という関係になる。このような場合、電流検出部８からハイレベルの検出信号Ｓｃが出力されるとともにコンパレータＣＰ２１の出力信号Ｓａがハイレベルとなる。これに伴い、フリップフロップ２２の出力信号Ｓｆがハイレベルとなるため、バックゲート制御部７は、トランジスタＴ１のバックゲートを電源出力端子Ｐｏに接続する。そして、オフ駆動部２３を構成するプリドライバ２は、出力電圧ＶＯＵＴが目標値に一致するようにトランジスタＴ１を駆動する。 Next, the operation of the power supply circuit 21 having the above configuration will be described.
[1] When the input voltage AVDD> the output voltage VOUT: The input voltage AVDD and the output voltage VOUT are always in a relationship of “AVDD> VOUT”. In such a case, the high-level detection signal Sc is output from the current detection unit 8, and the output signal Sa of the comparator CP21 is at the high level. Along with this, the output signal Sf of the flip-flop 22 becomes high level, so the back gate control unit 7 connects the back gate of the transistor T1 to the power supply output terminal Po. Then, the pre-driver 2 constituting the off drive unit 23 drives the transistor T1 so that the output voltage VOUT matches the target value.
　　［２］入力電圧ＡＶＤＤ＜出力電圧ＶＯＵＴのとき
　異常時、入力電圧ＡＶＤＤおよび出力電圧ＶＯＵＴは、「ＡＶＤＤ＜ＶＯＵＴ」という関係になる。このような場合、電流検出部８からロウレベルの検出信号Ｓｃが出力されるとともにコンパレータＣＰ２１の出力信号Ｓａがロウレベルとなる。これに伴い、フリップフロップ２２の出力信号Ｓｆがロウレベルとなるため、バックゲート制御部７は、トランジスタＴ１のバックゲートを電源入力端子Ｐｉに接続する。そして、オフ駆動部２３を構成するプリドライバ２は、トランジスタＴ１をオフ駆動する。 [2] When the input voltage AVDD <the output voltage VOUT When an abnormality occurs, the input voltage AVDD and the output voltage VOUT have a relationship of “AVDD <VOUT”. In such a case, the current detection unit 8 outputs the low level detection signal Sc and the output signal Sa of the comparator CP21 becomes the low level. As a result, the output signal Sf of the flip-flop 22 becomes low level, so the back gate control unit 7 connects the back gate of the transistor T1 to the power input terminal Pi. Then, the pre-driver 2 constituting the off drive unit 23 drives off the transistor T1.
　この場合、電源出力端子Ｐｏから電源入力端子Ｐｉへと逆流が流れ得る状態、つまり出力電圧ＶＯＵＴが入力電圧ＡＶＤＤより大きい状態が継続している場合、出力信号Ｓａがロウレベルからハイレベルに転じることがないため、プリドライバ２によるトランジスタＴ１のオフ駆動も継続される。一方、逆流が流れ得る状態が解消されると、つまり入力電圧ＡＶＤＤが出力電圧ＶＯＵＴより大きい状態になると、出力信号Ｓａがロウレベルからハイレベルに転じるため、プリドライバ２によるトランジスタＴ１のオフ駆動が解除される。 In this case, when the backflow can flow from the power output terminal Po to the power input terminal Pi, that is, when the output voltage VOUT is higher than the input voltage AVDD, the output signal Sa may change from the low level to the high level. Therefore, the off-drive of the transistor T1 by the pre-driver 2 is also continued. On the other hand, when the state in which the reverse flow can flow is eliminated, that is, when the input voltage AVDD becomes larger than the output voltage VOUT, the output signal Sa changes from the low level to the high level, and thus the pre-driver 2 releases the off drive of the transistor T1 Is done.
　本実施形態によっても第１実施形態と同様の効果が得られる。さらに、本実施形態では、オフ駆動部２３は、ロウレベルの検出信号Ｓｃが出力された後、コンパレータＣＰ２１の出力信号Ｓａがロウレベルからハイレベルに転じることがなければトランジスタＴ１のオフ駆動を継続し、出力信号Ｓａがロウレベルからハイレベルに転じるとトランジスタＴ１のオフ駆動を解除するようになっている。そのため、逆流が流れ得る状態、つまり「ＡＶＤＤ＜ＶＯＵＴ」の状態になってトランジスタＴ１がオフ駆動された場合、逆流が流れ得る状態が解消されない限り、トランジスタＴ１のオフ駆動が継続される。したがって、本実施形態では、逆流から回路を保護する際、トランジスタＴ１のオンオフが繰り返されることがないため、出力電圧ＶＯＵＴの変動を抑制することができる。 The same effect as the first embodiment can be obtained by this embodiment. Further, in the present embodiment, the off driving unit 23 continues the off driving of the transistor T1 unless the output signal Sa of the comparator CP21 changes from the low level to the high level after the low level detection signal Sc is output. When the output signal Sa changes from the low level to the high level, the transistor T1 is turned off. Therefore, when the transistor T1 is turned off in a state in which a reverse flow can flow, that is, in a state of “AVDD <VOUT”, the transistor T1 is continuously turned off unless the state in which the reverse flow can flow is eliminated. Therefore, in this embodiment, when the circuit is protected from the backflow, the transistor T1 is not repeatedly turned on and off, so that the fluctuation of the output voltage VOUT can be suppressed.
　　　（第３実施形態）
　以下、第３実施形態について図３を参照して説明する。
　図３に示すように、本実施形態の電源回路３１は、第１実施形態の電源回路１に対し、トランジスタＴ１に代えてトランジスタＴ３１を備えている点と、バックゲート制御部７に代えてバックゲート制御部３２を備えている点と、反転バッファ４が省かれている点と、が異なる。 (Third embodiment)
Hereinafter, a third embodiment will be described with reference to FIG.
As shown in FIG. 3, the power supply circuit 31 of the present embodiment is different from the power supply circuit 1 of the first embodiment in that a transistor T31 is provided instead of the transistor T1, and that the back gate control unit 7 The difference is that the gate control unit 32 is provided and the inversion buffer 4 is omitted.
　トランジスタＴ３１は、Ｐチャネル型のパワーＭＯＳトランジスタである。トランジスタＴ３１のソースは、シャント抵抗Ｒｓを介して電源入力端子Ｐｉに接続されている。トランジスタＴ３１のドレインは、電源出力端子Ｐｏに接続されている。つまり、トランジスタＴ３１は、電源入力端子Ｐｉおよび電源出力端子Ｐｏの間に直列に介在するものであり、主トランジスタに相当する。トランジスタＴ３１のゲートには、プリドライバ２から出力されるゲート駆動信号Ｓｇが与えられている。 The transistor T31 is a P-channel type power MOS transistor. The source of the transistor T31 is connected to the power input terminal Pi via the shunt resistor Rs. The drain of the transistor T31 is connected to the power output terminal Po. That is, the transistor T31 is interposed in series between the power input terminal Pi and the power output terminal Po, and corresponds to a main transistor. A gate drive signal Sg output from the pre-driver 2 is given to the gate of the transistor T31.
　バックゲート制御部３２は、電流検出部８から出力される検出信号Ｓｃに応じてトランジスタＴ３１のバックゲートに与える電圧を制御する。具体的には、バックゲート制御部３２は、ハイレベルの検出信号Ｓｃが出力される期間、トランジスタＴ３１のバックゲートをソース側、つまり電源入力端子Ｐｉに接続する。これにより、電源入力端子Ｐｉから電源出力端子Ｐｏへと流れる向きに電流が流れているとき、つまり定常時、トランジスタＴ３１のバックゲートにはソース側の電圧、つまり入力電圧ＡＶＤＤが与えられる。 The back gate control unit 32 controls the voltage applied to the back gate of the transistor T31 according to the detection signal Sc output from the current detection unit 8. Specifically, the back gate control unit 32 connects the back gate of the transistor T31 to the source side, that is, the power input terminal Pi during a period in which the high level detection signal Sc is output. As a result, when a current flows in a direction flowing from the power input terminal Pi to the power output terminal Po, that is, in a steady state, the source side voltage, that is, the input voltage AVDD is applied to the back gate of the transistor T31.
　また、バックゲート制御部３２は、ロウレベルの検出信号Ｓｃが出力される期間、トランジスタＴ３１のバックゲートをドレイン側、つまり電源出力端子Ｐｏに接続する。これにより、電源出力端子Ｐｏから電源入力端子Ｐｉへと流れる向きに電流が流れているとき、つまり逆流時、トランジスタＴ３１のバックゲートにはドレイン側の電圧、つまり出力電圧ＶＯＵＴが与えられる。 Further, the back gate control unit 32 connects the back gate of the transistor T31 to the drain side, that is, the power supply output terminal Po during the period when the low level detection signal Sc is output. As a result, when the current flows in the direction of flowing from the power supply output terminal Po to the power supply input terminal Pi, that is, in the reverse flow, the drain side voltage, that is, the output voltage VOUT is applied to the back gate of the transistor T31.
　バックゲート制御部３２の具体的な構成としては、例えば図２に示すような構成を採用することができる。すなわち、バックゲート制御部３２は、トランジスタＴ３３～Ｔ３６および電流源３３を備えている。トランジスタＴ３３は、Ｐチャネル型のＭＯＳトランジスタであり、そのソースは電源入力端子Ｐｉに接続されている。トランジスタＴ３３のドレインは、電流源３３を介してグランド端子Ｐｇに接続されている。トランジスタＴ３３のゲートには、検出信号Ｓｃが与えられている。 As a specific configuration of the back gate control unit 32, for example, a configuration as shown in FIG. 2 can be adopted. That is, the back gate control unit 32 includes transistors T33 to T36 and a current source 33. The transistor T33 is a P-channel MOS transistor, and its source is connected to the power input terminal Pi. The drain of the transistor T33 is connected to the ground terminal Pg through the current source 33. A detection signal Sc is supplied to the gate of the transistor T33.
　トランジスタＴ３４は、Ｎチャネル型のＭＯＳトランジスタであり、そのソースは電源出力端子Ｐｏに接続されている。トランジスタＴ３４のゲートは、トランジスタＴ３３のドレインに接続されている。トランジスタＴ３４のドレインは、ノードＮ３１に接続されている。ノードＮ３１は、トランジスタＴ３１のバックゲートに接続されている。 The transistor T34 is an N-channel MOS transistor, and its source is connected to the power output terminal Po. The gate of the transistor T34 is connected to the drain of the transistor T33. The drain of the transistor T34 is connected to the node N31. The node N31 is connected to the back gate of the transistor T31.
　トランジスタＴ３５、Ｔ３６は、いずれもＰチャネル型のＭＯＳトランジスタであり、それらのソースはノードＮ３１に接続されている。トランジスタＴ３５、Ｔ３６の各ドレインは、電源入力端子Ｐｉに接続されている。トランジスタＴ３５のゲートは、電源出力端子Ｐｏに接続されている。 The transistors T35 and T36 are both P-channel MOS transistors, and their sources are connected to the node N31. The drains of the transistors T35 and T36 are connected to the power input terminal Pi. The gate of the transistor T35 is connected to the power supply output terminal Po.
　トランジスタＴ３６は、プリドライバ２によりオンオフ駆動される。具体的には、プリドライバ２は、制御端子Ｐ１の電圧レベルがハイレベルであるときに、トランジスタＴ３６をオン駆動する。また、プリドライバ２は、制御端子Ｐ１の電圧レベルがロウレベルであるときに、トランジスタＴ３６をオフ駆動する。 The transistor T36 is driven on and off by the pre-driver 2. Specifically, the pre-driver 2 turns on the transistor T36 when the voltage level of the control terminal P1 is high. Further, the pre-driver 2 drives the transistor T36 off when the voltage level of the control terminal P1 is low.
　このような構成によれば、電流検出部８からハイレベルの検出信号Ｓｃが出力されると、トランジスタＴ３３がオフすることによりトランジスタＴ３４がオフされる。また、このとき、トランジスタＴ３６はプリドライバ２によりオン駆動される。そして、これに伴い、トランジスタＴ３５もオンされる。このような動作により、ノードＮ３１が電源入力端子Ｐｉに接続され、トランジスタＴ３１のバックゲートに入力電圧ＡＶＤＤが与えられる。 According to such a configuration, when the high-level detection signal Sc is output from the current detection unit 8, the transistor T33 is turned off, thereby turning off the transistor T34. At this time, the transistor T36 is turned on by the pre-driver 2. Accordingly, the transistor T35 is also turned on. By such an operation, the node N31 is connected to the power supply input terminal Pi, and the input voltage AVDD is applied to the back gate of the transistor T31.
　また、電流検出部８からロウレベルの検出信号Ｓｃが出力されると、トランジスタＴ３３がオンすることによりトランジスタＴ３４がオンされる。また、このとき、トランジスタＴ３６はプリドライバ２によりオフ駆動される。そして、これに伴い、トランジスタＴ３５がオフされる。このような動作により、ノードＮ３１が電源出力端子Ｐｏに接続され、トランジスタＴ３１のバックゲートに出力電圧ＶＯＵＴが与えられる。 Further, when the low level detection signal Sc is output from the current detection unit 8, the transistor T33 is turned on to turn on the transistor T34. At this time, the transistor T36 is driven off by the pre-driver 2. Accordingly, the transistor T35 is turned off. By such an operation, the node N31 is connected to the power supply output terminal Po, and the output voltage VOUT is given to the back gate of the transistor T31.
　上記構成において、トランジスタＴ３１、バックゲート制御部３２、電流検出部８およびオフ駆動部９により、電源出力端子Ｐｏから電源入力端子Ｐｉへと流れる逆流から電源回路３１などの回路を保護するための保護機能を実現する電流保護回路３４が構成されている。 In the above configuration, the transistor T31, the back gate control unit 32, the current detection unit 8, and the off drive unit 9 protect the circuit such as the power supply circuit 31 from the backflow that flows from the power supply output terminal Po to the power supply input terminal Pi. A current protection circuit 34 for realizing the function is configured.
　以上説明した本実施形態の構成によっても、第１実施形態と同様の作用および効果が得られる。すなわち、上記構成の電源回路３１では、第１実施形態の電源回路１と同様、電源出力端子Ｐｏから電源入力端子Ｐｉへと流れる逆流が発生すると、電流検出部８は、ロウレベルの検出信号Ｓｃを出力する。オフ駆動部９を構成するプリドライバ２は、電流検出部８からロウレベルの検出信号Ｓｃが出力されると、誤差アンプ６から出力される誤差信号Ｓｄに関係なく、トランジスタＴ３１を強制的にオフ駆動する。これにより、トランジスタＴ３１のチャネルを介した経路による逆流が阻止される。 Also by the configuration of the present embodiment described above, the same operation and effect as the first embodiment can be obtained. That is, in the power supply circuit 31 configured as described above, when a backflow that flows from the power supply output terminal Po to the power supply input terminal Pi occurs as in the power supply circuit 1 of the first embodiment, the current detection unit 8 generates the low level detection signal Sc. Output. When the low-level detection signal Sc is output from the current detection unit 8, the pre-driver 2 that configures the off-drive unit 9 forcibly drives the transistor T31 off regardless of the error signal Sd output from the error amplifier 6. To do. Thereby, the backflow by the path | route via the channel of transistor T31 is blocked | prevented.
　また、電流検出部８からロウレベルの検出信号Ｓｃが出力されている期間、バックゲート制御部３２は、トランジスタＴ３１のドレイン側の電圧である出力電圧ＶＯＵＴをトランジスタＴ３１のバックゲートに与える。このようにすれば、トランジスタＴ３１のドレイン・ソース間に、ソース側つまり電源入力端子Ｐｉ側をアノードとしたボディダイオードが形成された状態となる。そのため、トランジスタＴ３１のボディダイオードを介した経路による逆流も阻止される。 Further, during the period when the low-level detection signal Sc is output from the current detection unit 8, the back gate control unit 32 supplies the output voltage VOUT, which is the voltage on the drain side of the transistor T31, to the back gate of the transistor T31. In this way, a body diode having the anode on the source side, that is, the power input terminal Pi side, is formed between the drain and source of the transistor T31. For this reason, backflow by the path through the body diode of the transistor T31 is also prevented.
　このように、上記構成では、電源入力端子Ｐｉから電源出力端子Ｐｏに至る経路に直列に設けられた１つのトランジスタＴ３１の駆動を制御するとともに、そのバックゲートを制御することにより、電源出力端子Ｐｏから電源入力端子Ｐｉへと流れる逆流の発生を防止している。したがって、本実施形態によっても、第１実施形態と同様、電源回路３１の回路面積の増加を抑制しつつ、逆流から回路を保護することができるという優れた効果が得られる。 Thus, in the above configuration, the drive of one transistor T31 provided in series in the path from the power input terminal Pi to the power output terminal Po is controlled, and the back gate is controlled to control the power output terminal Po. Is prevented from flowing back to the power input terminal Pi. Therefore, also in the present embodiment, as in the first embodiment, an excellent effect that the circuit can be protected from the backflow while suppressing an increase in the circuit area of the power supply circuit 31 is obtained.
　　　（第４実施形態）
　以下、第４実施形態について図４を参照して説明する。
　図４に示すように、本実施形態の電源回路４１は、第１実施形態の電源回路１に対し、電流検出部８に代えて電流検出部４２を備えている点が異なる。電流検出部４２は、電流検出部８が備える構成に加え、さらにトランジスタＴ４１および電流源４３を備えている。 (Fourth embodiment)
Hereinafter, a fourth embodiment will be described with reference to FIG.
As shown in FIG. 4, the power supply circuit 41 of this embodiment is different from the power supply circuit 1 of the first embodiment in that a current detection unit 42 is provided instead of the current detection unit 8. The current detection unit 42 includes a transistor T41 and a current source 43 in addition to the configuration included in the current detection unit 8.
　この場合、トランジスタＴ１のドレインは、直接、電源入力端子Ｐｉに接続されている。トランジスタＴ４１は、Ｎチャネル型のＭＯＳトランジスタであり、そのドレインはシャント抵抗Ｒｓを介して電源入力端子Ｐｉに接続されている。トランジスタＴ４１のソースおよびゲートは共通接続されており、それら共通接続されたソースおよびゲートは、トランジスタＴ１のゲートに接続されるとともに電流源４３を介してグランド端子Ｐｇに接続されている。トランジスタＴ４１のバックゲートは、グランド端子Ｐｇに接続されている。 In this case, the drain of the transistor T1 is directly connected to the power input terminal Pi. The transistor T41 is an N-channel MOS transistor, and its drain is connected to the power input terminal Pi via the shunt resistor Rs. The source and gate of the transistor T41 are commonly connected, and the commonly connected source and gate are connected to the gate of the transistor T1 and to the ground terminal Pg via the current source 43. The back gate of the transistor T41 is connected to the ground terminal Pg.
　上記構成において、トランジスタＴ１およびトランジスタＴ４１は、カレントミラー回路を構成している。そのため、トランジスタＴ４１には、トランジスタＴ１に流れる電流に応じた電流（以下、検出電流と呼ぶ）が流れる。なお、検出電流は、トランジスタＴ１とトランジスタＴ４１のサイズ比などによって定まる。したがって、トランジスタＴ４１は、トランジスタＴ１に流れる電流に応じた検出電流を流す電流検出用トランジスタに相当する。つまり、本実施形態の電流検出部４２は、トランジスタＴ４１に流れる検出電流に基づいてトランジスタＴ１に流れる電流を検出するようになっている。 In the above configuration, the transistor T1 and the transistor T41 constitute a current mirror circuit. Therefore, a current (hereinafter referred to as a detection current) corresponding to the current flowing through the transistor T1 flows through the transistor T41. The detection current is determined by the size ratio of the transistor T1 and the transistor T41. Therefore, the transistor T41 corresponds to a current detection transistor that supplies a detection current corresponding to the current flowing through the transistor T1. That is, the current detection unit 42 of the present embodiment detects the current flowing through the transistor T1 based on the detection current flowing through the transistor T41.
　上記構成において、トランジスタＴ１、バックゲート制御部７、電流検出部４２およびオフ駆動部９により、電源出力端子Ｐｏから電源入力端子Ｐｉへと流れる逆流から電源回路４１などの回路を保護するための保護機能を実現する電流保護回路４４が構成されている。 In the above configuration, the transistor T1, the back gate control unit 7, the current detection unit 42, and the off drive unit 9 protect the circuit such as the power supply circuit 41 from the backflow that flows from the power supply output terminal Po to the power supply input terminal Pi. A current protection circuit 44 that realizes the function is configured.
　本実施形態によっても第１実施形態と同様の効果が得られる。さらに、本実施形態では、電源入力端子Ｐｉから電源出力端子Ｐｏへと至る電源供給経路にシャント抵抗Ｒｓが介在しない構成となっている。したがって、本実施形態によれば、電源供給経路の更なる低抵抗化を実現することが可能となり、その結果、電力損失を一層低減することができるとともに、電圧制御の精度を向上することができるといった効果が得られる。 The same effect as the first embodiment can be obtained by this embodiment. Further, in the present embodiment, the shunt resistor Rs is not interposed in the power supply path from the power input terminal Pi to the power output terminal Po. Therefore, according to the present embodiment, it is possible to further reduce the resistance of the power supply path, and as a result, it is possible to further reduce power loss and improve the accuracy of voltage control. The effect is obtained.
　　　（その他の実施形態）
　なお、本開示は上記し且つ図面に記載した各実施形態に限定されるものではなく、その要旨を逸脱しない範囲で任意に変形、組み合わせ、あるいは拡張することができる。 (Other embodiments)
The present disclosure is not limited to the embodiments described above and illustrated in the drawings, and can be arbitrarily modified, combined, or expanded without departing from the scope of the present disclosure.
　バックゲート制御部７、３２の具体的な構成としては、図１、図３などに示した構成に限らずともよく、所望する動作を実現可能な構成であれば適宜変更することができる。
　本開示は、車両に搭載される電子制御装置が備える電源回路に限らず、入力電圧を入力するための入力端子および入力電圧よりも低い出力電圧を出力するための出力端子を有する回路であって、出力端子から入力端子へと逆流が流れる可能性のある回路全般に適用することができる。 The specific configuration of the back gate control units 7 and 32 is not limited to the configuration shown in FIGS. 1 and 3 and the like, and can be appropriately changed as long as a desired operation can be realized.
The present disclosure is not limited to a power supply circuit included in an electronic control device mounted on a vehicle, and is a circuit having an input terminal for inputting an input voltage and an output terminal for outputting an output voltage lower than the input voltage. The present invention can be applied to all circuits in which a backflow may flow from the output terminal to the input terminal.
　本開示は、実施例に準拠して記述されたが、本開示は当該実施例や構造に限定されるものではないと理解される。本開示は、様々な変形例や均等範囲内の変形をも包含する。加えて、様々な組み合わせや形態、さらには、それらに一要素のみ、それ以上、あるいはそれ以下、を含む他の組み合わせや形態をも、本開示の範疇や思想範囲に入るものである。 Although the present disclosure has been described based on the embodiments, it is understood that the present disclosure is not limited to the embodiments and structures. The present disclosure includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more or less, are within the scope and spirit of the present disclosure.

Claims (6)

  1. 　入力電圧を入力するための入力端子（Ｐｉ）および前記入力電圧よりも低い出力電圧を出力するための出力端子（Ｐｏ）の間に直列接続されたＭＯＳトランジスタ（Ｔ１、Ｔ３１）と、
    　前記入力端子および前記出力端子の間に流れる電流を検出し、その検出した電流の向きを表す検出信号を出力する電流検出部（８、４２）と、
    　前記出力端子から前記入力端子へと流れる電流の向きである第１方向を表す前記検出信号が出力されると、前記ＭＯＳトランジスタをオフ駆動するオフ駆動部（９、２３）と、
    　少なくとも前記電流検出部から前記第１方向を表す前記検出信号が出力される期間、前記ＭＯＳトランジスタのドレイン側の電圧を前記ＭＯＳトランジスタのバックゲートに与えるバックゲート制御部（７、３２）と、
    　を備える電流保護回路。     MOS transistors (T1, T31) connected in series between an input terminal (Pi) for inputting an input voltage and an output terminal (Po) for outputting an output voltage lower than the input voltage;
    A current detector (8, 42) for detecting a current flowing between the input terminal and the output terminal and outputting a detection signal indicating the direction of the detected current;
    When the detection signal representing the first direction, which is the direction of the current flowing from the output terminal to the input terminal, is output, an off driving unit (9, 23) for driving the MOS transistor off;
    A back gate control unit (7, 32) that applies a voltage on the drain side of the MOS transistor to a back gate of the MOS transistor at least during a period in which the detection signal representing the first direction is output from the current detection unit;
    A current protection circuit comprising:
  2. 　前記バックゲート制御部は、
    　前記入力端子から前記出力端子へと流れる電流の向きである第２方向を表す前記検出信号が出力される期間、前記ＭＯＳトランジスタのソース側の電圧を前記ＭＯＳトランジスタのバックゲートに与える請求項１に記載の電流保護回路。     The back gate controller is
    2. The source-side voltage of the MOS transistor is applied to the back gate of the MOS transistor during a period in which the detection signal representing a second direction that is a direction of a current flowing from the input terminal to the output terminal is output. The current protection circuit described.
  3. 　さらに、前記入力電圧および前記出力電圧を検出する電圧検出部（ＣＰ２１）を備え、
    　前記オフ駆動部（２３）は、前記第１方向を表す前記検出信号が出力された後、前記電圧検出部の検出値に基づいて前記出力電圧が前記入力電圧よりも高いことを検出すると前記ＭＯＳトランジスタのオフ駆動を継続し、前記入力電圧が前記出力電圧よりも高いことを検出すると前記ＭＯＳトランジスタのオフ駆動を解除する請求項１または２に記載の電流保護回路。     Furthermore, a voltage detector (CP21) for detecting the input voltage and the output voltage is provided,
    When the off drive unit (23) detects that the output voltage is higher than the input voltage based on a detection value of the voltage detection unit after the detection signal representing the first direction is output, the MOS 3. The current protection circuit according to claim 1, wherein the transistor is continuously turned off and the MOS transistor is turned off when it is detected that the input voltage is higher than the output voltage. 4.
  4. 　前記電流検出部（８）は、前記入力端子および前記出力端子の間に直列に介在するシャント抵抗（Ｒｓ）を備え、前記シャント抵抗の端子電圧に基づいて前記電流を検出する請求項１から３のいずれか一項に記載の電流保護回路。 The current detector (8) includes a shunt resistor (Rs) interposed in series between the input terminal and the output terminal, and detects the current based on a terminal voltage of the shunt resistor. The current protection circuit according to any one of the above.
  5. 　前記電流検出部（４２）は、前記ＭＯＳトランジスタに流れる電流に応じた検出電流を流す電流検出用トランジスタ（Ｔ４１）を備え、前記電流検出用トランジスタに流れる検出電流に基づいて前記電流を検出する請求項１から３のいずれか一項に記載の電流保護回路。 The current detection unit (42) includes a current detection transistor (T41) for supplying a detection current corresponding to a current flowing through the MOS transistor, and detects the current based on the detection current flowing through the current detection transistor. Item 4. The current protection circuit according to any one of Items 1 to 3.
  6. 　前記入力端子は、入力電圧を所望の出力電圧に降圧して出力する電源回路（１）における前記入力電圧を入力するための電源入力端子（Ｐｉ）であり、
    　前記出力端子は、前記電源回路における前記出力電圧を出力するための電源出力端子（Ｐｏ）であり、
    　前記ＭＯＳトランジスタは、前記電源回路における前記電源入力端子および前記電源出力端子の間に直列に介在する主トランジスタとしても機能する請求項１から５のいずれか一項に記載の電流保護回路。     The input terminal is a power supply input terminal (Pi) for inputting the input voltage in the power supply circuit (1) for stepping down the input voltage to a desired output voltage and outputting it,
    The output terminal is a power supply output terminal (Po) for outputting the output voltage in the power supply circuit,
    6. The current protection circuit according to claim 1, wherein the MOS transistor also functions as a main transistor interposed in series between the power input terminal and the power output terminal in the power circuit.
PCT/JP2017/030927 2016-11-07 2017-08-29 Current protection circuit WO2018083870A1 (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008021166A (en) * 2006-07-13 2008-01-31 Ricoh Co Ltd Voltage regulator
JP2009301209A (en) * 2008-06-11 2009-12-24 Mitsumi Electric Co Ltd Power control semiconductor integrated circuit
JP2015090587A (en) * 2013-11-06 2015-05-11 株式会社デンソー Current protection circuit
JP2015116042A (en) * 2013-12-11 2015-06-22 株式会社オートネットワーク技術研究所 Dc voltage conversion device, and counter flow prevention method for the same
JP2016033774A (en) * 2014-07-31 2016-03-10 株式会社東芝 Regulator circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008021166A (en) * 2006-07-13 2008-01-31 Ricoh Co Ltd Voltage regulator
JP2009301209A (en) * 2008-06-11 2009-12-24 Mitsumi Electric Co Ltd Power control semiconductor integrated circuit
JP2015090587A (en) * 2013-11-06 2015-05-11 株式会社デンソー Current protection circuit
JP2015116042A (en) * 2013-12-11 2015-06-22 株式会社オートネットワーク技術研究所 Dc voltage conversion device, and counter flow prevention method for the same
JP2016033774A (en) * 2014-07-31 2016-03-10 株式会社東芝 Regulator circuit

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