WO2018076683A1 - 一种温度检测电路和方法 - Google Patents

一种温度检测电路和方法 Download PDF

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Publication number
WO2018076683A1
WO2018076683A1 PCT/CN2017/086008 CN2017086008W WO2018076683A1 WO 2018076683 A1 WO2018076683 A1 WO 2018076683A1 CN 2017086008 W CN2017086008 W CN 2017086008W WO 2018076683 A1 WO2018076683 A1 WO 2018076683A1
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current
voltage
nmos transistor
temperature coefficient
transistor
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PCT/CN2017/086008
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English (en)
French (fr)
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宋德夫
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深圳市中兴微电子技术有限公司
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Publication of WO2018076683A1 publication Critical patent/WO2018076683A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01K—MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR
    • G01K7/00—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements
    • G01K7/01—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements using semiconducting elements having PN junctions

Definitions

  • the present invention relates to temperature sensing technology, and more particularly to a temperature detecting circuit and method.
  • MOS-FET Metal-Oxide Semiconductor Field Effect Transistor
  • a flip signal that produces a high slew rate at the designed overtemperature point is an important indicator of the performance of an overtemperature protection circuit.
  • the comparator and the bandgap reference precision are constant, it is necessary to increase the temperature coefficient of the temperature detecting circuit to ensure the accuracy at the over-temperature point and the high switching speed of the protection signal. Therefore, designing a high-sensitivity temperature detecting circuit is one of the difficulties in over-temperature protection.
  • the temperature detecting circuit generally adopts the following three schemes:
  • Solution 3 As shown in FIG. 3, the temperature variation is detected by the negative temperature coefficient of the diode's turn-on voltage V BE , and a plurality of diodes are connected in series to increase the temperature coefficient.
  • the problem in each of the above three schemes is that in the first scheme, the temperature coefficient of the circuit mainly comes from the thermal voltage and However, the temperature coefficient is small, even if the temperature coefficient is increased by increasing the resistance of the resistor in the circuit, the temperature coefficient of the whole circuit is still small; in the second scheme, the temperature coefficient of the circuit is affected by the change of the resistance process parameter, which is easy to cause The deviation between the output theoretical value and the actual measured value is large; in addition, the constant current characteristics of the output stages of the two types of conventional temperature detecting circuits described in the first scheme and the second scheme are not good, and the voltage stability is poor; In the third, multiple diodes are needed, which greatly increases the chip area, and the series connection of such multiple diodes has a large limitation on the process. Therefore, there is an urgent need to develop a new, highly sensitive temperature sensing circuit suitable for use in integrated circuits.
  • the embodiments of the present invention provide a temperature detecting circuit and method, which can solve the deficiencies of the conventional temperature detecting circuit with low sensitivity, poor voltage stability, and being susceptible to changes in process parameters.
  • the embodiment of the invention provides a temperature detecting circuit, wherein the temperature detecting circuit comprises: a negative temperature coefficient voltage generating module and a voltage output module; wherein
  • the negative temperature coefficient voltage generating module is configured to generate a negative according to a change in ambient temperature a temperature coefficient voltage, and acquiring first and second currents of equal magnitude and direction according to the negative temperature coefficient voltage;
  • the voltage output module is configured to acquire a third current according to the first current and the second current, and acquire an output voltage according to the third current to acquire the ambient temperature based on the output voltage.
  • the negative temperature coefficient voltage generating module includes: a first MOS current mirror module, a second MOS current mirror module connected to the first MOS current mirror module, and a second MOS current mirror module a first load and a semiconductor device having a negative temperature coefficient;
  • the first MOS current mirror module is configured to make the first current and the second current flowing into the second MOS current mirror module equal in magnitude and in the same direction;
  • the second MOS current mirror module is configured to cause a first voltage on the first load and a negative temperature coefficient voltage on the semiconductor device having a negative temperature coefficient according to the first current and the second current Equal in size;
  • the semiconductor device having a negative temperature coefficient is configured to generate a negative temperature coefficient voltage and a negative temperature coefficient current equal to the second current according to a change in ambient temperature.
  • the voltage output module includes: a third MOS current mirror module connected to the negative temperature coefficient voltage generating module, and a second load connected to the third MOS current mirror module;
  • the third MOS current mirror module is configured to acquire a third current according to the first current and the second current, and apply the third current to the second load to obtain an output voltage.
  • the voltage output module further includes: a third load connected to the third MOS current mirror module, wherein the third current flows through the third load to generate a second voltage according to the second The voltage gets the output voltage.
  • the voltage output module further includes: a capacitor connected to the third MOS current mirror module, configured to filter the second voltage.
  • the semiconductor device having a negative temperature coefficient is a PNP type transistor or a diode.
  • the load is a resistor or a switched capacitor.
  • the first MOS current mirror module includes a first PMOS transistor and a second PMOS transistor;
  • the second MOS current mirror module includes a first NMOS transistor and a second NMOS transistor;
  • the third MOS current mirror module The third NMOS transistor includes: the semiconductor device having a negative temperature coefficient is a PNP type transistor; the first load is a first resistor, the second load is a second resistor, and the third load is a third resistor;
  • the source of the first PMOS transistor and the source of the second PMOS transistor are connected to the power supply voltage; the gate of the first PMOS transistor is connected to the gate of the second PMOS transistor and the drain of the first PMOS transistor is connected to the gate of the first PMOS transistor And a gate of the second PMOS transistor, so that the first PMOS transistor and the second PMOS transistor form a first PMOS current mirror; the drain of the first PMOS transistor is further connected to the drain of the first NMOS transistor; and the drain of the second PMOS transistor The pole is connected to the drain of the second NMOS transistor; the gate of the first NMOS transistor is connected to the gate of the second NMOS transistor; and the drain of the second NMOS transistor is connected to the gate of the first NMOS transistor and the gate of the second NMOS transistor, The first NMOS transistor and the second NMOS transistor form a first NMOS current mirror; one end of the first resistor is connected to the source of the first NMOS transistor, and the other end is grounded; the emitter of the P
  • a gate of the third NMOS transistor is connected to a drain of the second PMOS transistor, a gate of the first NMOS transistor, a gate of the second NMOS transistor, and a drain; one end of the second resistor is connected to a source of the third NMOS transistor The other end is grounded; one end of the third resistor is connected to the power supply voltage, and the other end is connected to the drain of the third NMOS transistor.
  • the resistance of the first resistor is equal to the resistance of the second resistor; or the resistance of the second resistor is N times the resistance of the first resistor, and N is a positive number.
  • the aspect ratio of the third NMOS transistor is equal to the aspect ratio of the first NMOS transistor; or the aspect ratio of the third NMOS transistor is the aspect ratio of the first NMOS transistor N Times, N is a positive number.
  • the embodiment of the invention further provides a temperature detecting method, the method comprising:
  • the negative temperature coefficient voltage generating module acquires a negative temperature coefficient voltage according to the change of the ambient temperature, and acquires the first current and the second current of the same size and the same direction according to the negative temperature coefficient voltage;
  • the voltage output module acquires a third current according to the first current and the second current, and acquires an output voltage according to the third current to acquire the ambient temperature based on the output voltage.
  • the negative temperature coefficient voltage generating module includes: a first MOS current mirror module, a second MOS current mirror module connected to the first MOS current mirror module, and a second MOS current mirror module a first load and a semiconductor device having a negative temperature coefficient;
  • the negative temperature coefficient voltage generating module acquires a negative temperature coefficient voltage according to the change of the ambient temperature, and acquires the first current and the second current of the same size and the same direction according to the negative temperature coefficient voltage, including:
  • the first MOS current mirror module equalizes and has the same magnitude of the first current and the second current flowing into the second MOS current mirror module;
  • the second MOS current mirror module equalizes a first voltage on the first load and a negative temperature coefficient voltage on the semiconductor device having a negative temperature coefficient according to the first current and the second current ;
  • the semiconductor device having a negative temperature coefficient generates a negative temperature coefficient voltage and a negative temperature coefficient current equal to the magnitude of the second current according to a change in ambient temperature.
  • the voltage output module includes: a third MOS current mirror module connected to the negative temperature coefficient voltage generating module, and a second load connected to the third MOS current mirror module;
  • the voltage output module acquires a third current according to the first current and the second current, and acquires an output voltage according to the third current, including:
  • the third MOS current mirror module acquires a third current according to the first current and the second current, and causes the third current to act on the second load to obtain an output voltage.
  • the temperature detecting circuit and method for the embodiment of the present invention comprise: a negative temperature coefficient voltage generating module and a voltage output module; and the negative temperature coefficient voltage generating module configured to generate a negative temperature coefficient according to a change in ambient temperature a voltage, and acquiring first and second currents of equal magnitude and direction according to the negative temperature coefficient voltage; the voltage output module configured to acquire a third current according to the first current and the second current, and according to The third current obtains the output voltage to obtain the ambient temperature based on the output voltage. It can be seen that the temperature detecting circuit provided by the embodiment of the present invention can convert the temperature changed inside the chip into a varying voltage to monitor the temperature change.
  • the output voltage and the temperature coefficient are only related to the ratio of the resistance in the temperature detecting circuit, which can eliminate the adverse effects caused by the drift of the process parameters and reduce the requirements on the process; meanwhile, the output stage of the temperature detecting circuit adopts a vertical cascade ( Cascode) structure, the resistance of the output is increased, which can effectively suppress the power supply The impact of changes in the output voltage.
  • the temperature coefficient and temperature sensitivity of the entire circuit can be further improved by controlling the ratio of the resistance in the temperature detecting circuit.
  • FIG. 1 is a schematic structural diagram of a temperature detecting circuit integrated in a bandgap reference in the prior art
  • FIG. 2 is a schematic structural diagram of a temperature detecting circuit designed by using a temperature characteristic of a carrier mobility u in a MOS transistor in the prior art
  • FIG. 3 is a schematic structural diagram of a temperature detecting circuit designed by using a plurality of diodes in series in a conventional technique
  • FIG. 4 is a schematic block diagram showing the structure of a temperature detecting circuit according to Embodiment 1 of the present invention.
  • FIG. 5 is a schematic flowchart of an implementation process of a temperature detecting method according to Embodiment 1 of the present invention.
  • FIG. 6 is a schematic structural diagram of a specific structure of a temperature detecting circuit according to Embodiment 2 of the present invention.
  • FIG. 7 is a schematic structural diagram of a specific structure of a temperature detecting circuit according to Embodiment 3 of the present invention.
  • FIG. 9 is a simulation result of an output voltage of a temperature detecting circuit according to a third embodiment of the present invention as a function of a power supply voltage
  • FIG. 10 is a schematic structural diagram of a specific structure of a temperature detecting circuit according to Embodiment 4 of the present invention.
  • FIG. 11 is a diagram showing simulation results of output voltages of temperature detecting circuits at different temperatures according to Embodiment 4 of the present invention.
  • FIG. 12 is a schematic structural diagram of a specific structure of a temperature detecting circuit according to Embodiment 5 of the present invention.
  • FIG. 13 is a schematic block diagram showing the structure of an over temperature protection circuit according to Embodiment 6 of the present invention.
  • the temperature detecting circuit 1 includes a negative temperature coefficient voltage generating module 11 and a voltage output module 12;
  • the negative temperature coefficient voltage generating module 11 is configured to generate a negative temperature coefficient voltage according to a change in ambient temperature, and obtain first and second currents of equal magnitude and same direction according to the negative temperature coefficient voltage;
  • the voltage output module 12 is configured to acquire a third current according to the first current and the second current, and acquire an output voltage according to the third current to acquire the ambient temperature based on the output voltage.
  • the negative temperature coefficient voltage generating module 11 includes: a first MOS current mirror module 111, a second MOS current mirror module 112 connected to the first MOS current mirror module 111, and the second MOS current mirror module. 112 connected first load 113 and semiconductor device 114 having a negative temperature coefficient;
  • the first MOS current mirror module 111 is configured to make the first current and the second current flowing into the second MOS current mirror module 112 equal in magnitude and in the same direction;
  • the second MOS current mirror module 112 is configured to cause a first voltage on the first load 113 and a negative on the semiconductor device 114 having a negative temperature coefficient according to the first current and the second current
  • the temperature coefficient voltages are equal in magnitude
  • the semiconductor device 114 having a negative temperature coefficient is configured to generate a negative temperature coefficient voltage and a negative temperature coefficient current equal to the magnitude of the second current according to a change in ambient temperature.
  • the voltage output module 12 includes: a third MOS current mirror module 121 connected to the negative temperature coefficient voltage generating module 11, and a second load 122 connected to the third MOS current mirror module 121;
  • the third MOS current mirror module 121 is connected to the first MOS current mirror module 111 and the second MOS current mirror module 112, and configured to acquire a third current according to the first current and the second current, and The third current is applied to the second load 122 to obtain an output voltage.
  • the voltage output module 12 may further include: a third load 123 connected to the third MOS current mirror module 121, the third current flowing through the third load 123 to generate a second voltage, according to The second voltage acquires an output voltage.
  • the voltage output module 12 may further include: a capacitor 124 connected to the third MOS current mirror module 121, configured to filter the second voltage.
  • the semiconductor device 124 having a negative temperature coefficient is a PNP type transistor or a diode;
  • the load is a resistance or a switched capacitor, that is, the first load 113, the second load 122, and the first
  • the third load 123 is a resistor or a switched capacitor;
  • the first MOS current mirror module 111 is a PMOS current mirror,
  • the second MOS current mirror module 112 is an NMOS current mirror,
  • the third MOS current mirror module 121 is a PMOS current mirror or an NMOS current mirror.
  • FIG. 5 is a schematic flowchart of an implementation of a temperature detecting method according to Embodiment 1 of the present invention, where the temperature detecting method includes:
  • Step 101 The negative temperature coefficient voltage generating module generates a negative temperature coefficient voltage according to the change of the ambient temperature, and acquires the first current and the second current of the same size and the same direction according to the negative temperature coefficient voltage;
  • Step 102 The voltage output module acquires a third current according to the first current and the second current, and acquires an output voltage according to the third current to acquire the ambient temperature based on the output voltage.
  • the negative temperature coefficient voltage generating module includes: a first MOS current mirror module, a second MOS current mirror module connected to the first MOS current mirror module, a first load connected to the second MOS current mirror module, and a semiconductor device having a negative temperature coefficient;
  • the negative temperature coefficient voltage generating module acquires a negative temperature coefficient voltage according to the change of the ambient temperature, and acquires the first current and the second current of the same size and the same direction according to the negative temperature coefficient voltage, including: a MOS current mirror module equalizing and aligning the first current and the second current flowing into the second MOS current mirror module; the second MOS current mirror module according to the first current and the second current Making a first voltage on the first load equal to a magnitude of a negative temperature coefficient voltage on the semiconductor device having a negative temperature coefficient; the semiconductor device having a negative temperature coefficient generates a negative temperature coefficient according to a change in ambient temperature a voltage, and a negative temperature coefficient current equal to the magnitude of the second current.
  • the voltage output module includes: a third MOS current mirror module connected to the negative temperature coefficient voltage generating module, and a second load connected to the third MOS current mirror module;
  • the voltage output module acquires the third power according to the first current and the second current And generating, according to the third current, an output voltage, comprising: the third MOS current mirror module acquiring a third current according to the first current, and causing the third current to act on the second load to obtain The output voltage.
  • the negative temperature coefficient voltage generating module can obtain the negative temperature coefficient voltage and the negative temperature coefficient current corresponding to the ambient temperature, and then obtain the output voltage corresponding to the ambient temperature through the voltage output module, based on The output voltage is acquired to the ambient temperature to achieve the purpose of temperature detection.
  • the implementation of the temperature detecting method provided by the embodiment of the present invention is implemented in a loop, and can be implemented by the above temperature detecting circuit.
  • the temperature detecting circuit includes: a first PMOS transistor PM1, a second PMOS transistor PM2, a first NMOS transistor NM1, and a second NMOS transistor NM2.
  • the PNP type transistor Q and the first resistor R1 form a negative temperature coefficient voltage generating module
  • the third NMOS transistor NM3, the second resistor R2, and the third resistor R3 constitute a voltage output module
  • connection relationship in the temperature detecting circuit shown in FIG. 6 is:
  • the source of the first PMOS transistor PM1 and the source of the second PMOS transistor PM2 are connected to the power supply voltage V dd ;
  • the gate of the first PMOS transistor PM1 is connected to the gate of the second PMOS transistor PM2 and
  • the drain of the first PMOS transistor PM1 is connected to the gate of the first PMOS transistor PM1 and the gate of the second PMOS transistor PM2, so that the first PMOS transistor PM1 and the second PMOS transistor PM2 constitute a first PMOS current mirror;
  • the drain of the tube PM1 is also connected to the drain of the first NMOS transistor NM1;
  • the drain of the second PMOS transistor PM2 is connected to the drain of the second NMOS transistor NM2;
  • the gate of the first NMOS transistor NM1 is connected to the gate of the second NMOS transistor NM2
  • the drain of the second NMOS transistor NM2 is connected to the gate of the first NMOS transistor NM1 and the gate of the second NMOS transistor NM2 such that the first NMOS
  • the gate of the third NMOS transistor NM3 is connected to the drain of the second PMOS transistor PM2, the gate of the first NMOS transistor NM1, the gate and the drain of the second NMOS transistor NM2, so that An NMOS transistor NM1 and a third NMOS transistor NM3 form a second NMOS current mirror; one end of the second resistor R2 is connected to the source of the third NMOS transistor, and the other end is grounded; one end of the third resistor R3 is connected to the power supply voltage V dd and the other end The drain of the third NMOS transistor NM3 is connected.
  • the first PMOS transistor PM1, the second PMOS transistor PM2, the first NMOS transistor NM1, the second NMOS transistor NM2, and the third NMOS transistor NM3 all operate in a saturation region; due to the PNP-type transistor Q The base and the collector are grounded, so that the PNP transistor Q is used as a diode after being turned on; the first PMOS current mirror formed by the first PMOS transistor PM1 and the second PMOS transistor PM2 ensures the first current I 1 and the first The two currents I 2 are equal in magnitude and in the same direction, that is, the first current I 1 flowing into the first NMOS transistor NM1 and the second current I 2 flowing into the second NMOS transistor NM2 are equal in magnitude and in the same direction; according to the first The action of the current I 1 and the second current I 2 , the first NMOS current mirror formed by the first NMOS transistor NM1 and the second NMOS transistor NM2 ensures the first voltage on the first resistor R1 and the negative temperature
  • the voltage after the PNP type transistor Q is turned on may be referred to as a negative temperature coefficient voltage, that is, with the environment. As the temperature rises, V BE decreases.
  • the temperature coefficient source of the PNP type transistor Q is known, according to the temperature coefficient source, it can be known that the PNP type transistor Q is on the change with the ambient temperature.
  • the negative temperature coefficient voltage is the magnitude of V BE ; it should be noted that the power supply voltage V dd in this embodiment is a direct current voltage.
  • the first current I 1 and the second current I 2 may be acquired according to the negative temperature coefficient voltage V BE ; the negative temperature coefficient voltage V BE may change as the ambient temperature changes, resulting in a circuit
  • the magnitudes of the first current I 1 and the second current I 2 also change accordingly; since the first NMOS transistor NM1 operates in the saturation region, the current flowing through the first resistor R1 and the first current I 1 are equal in magnitude and The direction is the same; in addition, the first voltage on the first resistor R1 and the negative temperature coefficient voltage V BE on the PNP transistor Q are the same; therefore, according to the negative temperature coefficient voltage V BE and the first resistor R1, a first current magnitude of I 1 can be obtained, can be further obtains a first output voltage V PTAT current according to the magnitude of I 1.
  • the magnitude of the third current I 3 in the circuit can be set by controlling the size of the first resistor R1 and the second resistor R2; when the resistance of the first resistor R1 is equal to the resistance of the second resistor R2 or the first When the width to length ratio of the NMOS transistor NM1 is equal to the width to length ratio of the third NMOS transistor NM3, there are:
  • V R3 represents the voltage on the third resistor, that is, the second voltage
  • V BE0 represents the voltage of the PNP transistor Q at an ambient temperature of T 0
  • T represents the current ambient temperature
  • K M represents the temperature coefficient of the PNP transistor Q Source, where a larger temperature coefficient source can be used, such as It can be seen from the above formula that the output voltage V PTAT and the temperature coefficient of the temperature detecting circuit can be adjusted by adjusting the size ratio between the first resistor R1 and the third resistor R3. And by matching the first resistor R1 and the third resistor R3 in the layout, the output drift due to the change of the resistance process parameter can be eliminated.
  • the temperature detecting circuit provided by the embodiment of the present invention acquires the output voltage V PTAT , the current ambient temperature T or the temperature variation difference TT 0 can be derived by using the above formula to implement temperature detection.
  • the second resistor R2 and the third NMOS transistor NM3 form a cascode structure, so that the output resistance R 0 of the output terminal formed by the third NMOS transistor NM3 and the second resistor R2 is greatly increased, that is,
  • R 0 G m3 ⁇ R2 ⁇ Rds3+Rds3+R3>>Rds3
  • Rds3 the output impedance of the third NMOS transistor NM3
  • G m3 is the third NMOS transistor NM3 of the transconductance.
  • the cascode structure in the embodiment of the present invention increases the output resistance of the output terminal by about G m3 ⁇ R2 times. Therefore, the output current source has Stronger ability to suppress power supply voltage fluctuations.
  • FIG. 7 is a schematic structural diagram of a temperature detecting circuit according to Embodiment 3 of the present invention.
  • the temperature detecting circuit includes: a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, and a first NMOS transistor NM1.
  • connection relationship in the temperature detecting circuit shown in FIG. 7 is:
  • the source of the first PMOS transistor PM1 and the source of the second PMOS transistor PM2 are connected to the power supply voltage V dd ;
  • the gate of the first PMOS transistor PM1 is connected to the gate of the second PMOS transistor PM2 and
  • the drain of the second PMOS transistor PM2 is connected to the gate of the first PMOS transistor PM1 and the gate of the second PMOS transistor PM2 such that the first PMOS transistor PM1 and the second PMOS transistor PM2 constitute a first PMOS current mirror;
  • the drain of the tube PM1 is connected to the drain of the first NMOS transistor NM1;
  • the drain of the second PMOS transistor PM2 is also connected to the drain of the second NMOS transistor NM2;
  • the gate of the first NMOS transistor NM1 is connected to the gate of the second NMOS transistor NM2
  • the drain of the first NMOS transistor NM1 is connected to the gate of the first NMOS transistor NM1 and the gate of the second NMOS transistor NM2 such that the first NMOS
  • the gate of the third PMOS transistor PM3 is connected to the gate of the first PMOS transistor PM1, the gate and the drain of the second PMOS transistor PM2, and the second NMOS transistor NM2 in the negative temperature coefficient voltage generating module.
  • the drain of the third PMOS transistor PM3 is connected to the power supply voltage V dd ; one end of the second resistor R2 is connected to the drain of the third PMOS transistor PM3, and the other end is grounded.
  • the first PMOS transistor PM1, the second PMOS transistor PM2, the third PMOS transistor PM3, the first NMOS transistor NM1, and the second NMOS transistor NM2 all operate in a saturation region; due to the PNP type transistor Q The base and the collector are grounded, so that the PNP transistor Q is used as a diode after being turned on; the first PMOS current mirror formed by the first PMOS transistor PM1 and the second PMOS transistor PM2 ensures the first current I 1 and the first The two currents I 2 are equal in magnitude and direction, that is, the first current I 1 flowing into the first NMOS transistor NM1 and the second current I 2 flowing into the second NMOS transistor NM2 are equal in magnitude and in the same direction; according to the first The action of the current I 1 and the second current I 2 , the first NMOS current mirror formed by the first NMOS transistor NM1 and the second NMOS transistor NM2 ensures the first voltage on the first resistor R1 and the negative temperature on the PNP transistor Q
  • the voltage after the PNP type transistor Q is turned on may be referred to as a negative temperature coefficient voltage, that is, with the environment. As the temperature rises, V BE decreases.
  • the temperature coefficient source of the PNP type transistor Q is known, according to the temperature coefficient source, it can be known that the PNP type transistor Q is on the change with the ambient temperature.
  • the negative temperature coefficient voltage is the magnitude of V BE ; it should be noted that the power supply voltage V dd in this embodiment is a direct current voltage.
  • the negative temperature coefficient voltage V BE changes, causing the magnitudes of the first current I 1 and the second current I 2 in the circuit to change accordingly; due to the second NMOS transistor
  • the NM2 operates in the saturation region such that the current flowing through the first resistor R1 and the second current I 2 are equal in magnitude and in the same direction; further, the first voltage on the first resistor R1 and the negative temperature coefficient voltage on the PNP transistor Q V bE of the same size; thus, according to the negative temperature coefficient of the voltage V bE of the first resistor R1, a second current magnitude I 2 can be obtained, thereby obtaining the output may be based on the size of the second current I 2 Voltage V CTAT .
  • FIG. 8 is a simulation result of the output voltage of the temperature detecting circuit according to the third embodiment of the present invention.
  • the output voltage V CTAT of the temperature detecting circuit provided in this embodiment is inversely proportional to the temperature T.
  • the curve V con is the relationship between the output voltage and the temperature of the existing temperature detecting circuit in FIG. 1 , and the temperature coefficient is 3.5 mV/° C.; the curves V CTAT1 , V CTAT3 , and V CTAT 5 are N of 1, 3, respectively.
  • the relative ratio between the second resistors R2, that is, N increases the temperature coefficient of the circuit.
  • the theoretical calculation curves of the time are highly consistent with the simulation curves V CTAT1 , V CTAT3 , V CTAT5 , and the maximum deviation is less than 2%.
  • FIG. 9 is a simulation result of the output voltage of the temperature detecting circuit according to the third embodiment of the present invention as a function of the power supply voltage.
  • the curve is output from bottom to top when N is 1, 3, and 5, respectively.
  • the voltage V CTAT changes with the power supply voltage V dd in the range of 0 to 8V; from the simulation results in Figure 9, it can be seen that the output voltage V CTAT changes although the power supply voltage V dd is in the range of 4 to 8V. It is too obvious, but there is a certain fluctuation. This is because the third PMOS transistor PM3 is used as the output current source in this embodiment.
  • the output voltage of the temperature detecting circuit provided by this embodiment is susceptible to the power supply voltage. Effect; in addition, since the upper threshold of the MOS transistor of the CMOS process (V thn ⁇ 1.9V,
  • the temperature detecting circuit includes: a first PMOS transistor PM1, a second PMOS transistor PM2, and a third PMOS. Tube PM3, first NMOS transistor NM1, second NMOS transistor NM2, third NMOS transistor NM3, fourth NMOS transistor NM4, PNP transistor Q, first resistor R1, second resistor R2, first capacitor C1, second capacitor C2; wherein the first PMOS transistor PM1, the second PMOS transistor PM2, the first NMOS transistor NM1, the second NMOS transistor NM2, the PNP transistor Q, and the first resistor R1 constitute a negative temperature coefficient voltage generating module, and the third PMOS transistor PM3 a third NMOS transistor NM3, a fourth NMOS transistor NM4, a second resistor R2, a first capacitor C1, and a second capacitor C2 constitute a voltage output module;
  • connection relationship in the temperature detecting circuit shown in FIG. 10 is:
  • the source of the first PMOS transistor PM1 and the source of the second PMOS transistor PM2 are connected to the power supply voltage V dd ;
  • the gate of the first PMOS transistor PM1 is connected to the gate of the second PMOS transistor PM2 and
  • the drain of the first PMOS transistor PM1 is connected to the gate of the first PMOS transistor PM1 and the gate of the second PMOS transistor PM2, so that the first PMOS transistor PM1 and the second PMOS transistor PM2 constitute a first PMOS current mirror;
  • the drain of the tube PM1 is also connected to the drain of the first NMOS transistor NM1;
  • the drain of the second PMOS transistor PM2 is connected to the drain of the second NMOS transistor NM2;
  • the gate of the first NMOS transistor NM1 is connected to the gate of the second NMOS transistor NM2
  • the drain of the second NMOS transistor NM2 is connected to the gate of the first NMOS transistor NM1 and the gate of the second NMOS transistor NM2, so that the first NMOS
  • the source of the third PMOS transistor PM3 is connected to the power supply voltage V dd ; the gate PM3 of the third PMOS transistor is connected to the gate of the third NMOS transistor NM3 and the gate of the third PMOS transistor PM3 and the third NMOS
  • the gate of the tube NM3 is connected to the first rectangular wave input terminal; the drain of the third PMOS transistor PM3 is connected to the drain of the third NMOS transistor NM3; the source of the third NMOS transistor NM3 is connected to the drain of the fourth NMOS transistor NM4;
  • One end of the first capacitor C1 is connected to the drain of the third PMOS transistor PM3 and the drain of the third NMOS transistor NM3, and the other end is grounded; the gate of the fourth NMOS transistor NM4 is connected to the first NMOS of the negative temperature coefficient voltage generating module.
  • one end of the second capacitor C2 is connected to the source of the third NMOS transistor NM3 and the drain of the fourth NMOS transistor NM4 The other end is grounded; one end of the second resistor R2 is connected to the source of the fourth NMOS transistor NM4, and the other end is grounded.
  • the first PMOS transistor PM1, the second PMOS transistor PM2, the first NMOS transistor NM1, the second NMOS transistor NM2, and the fourth NMOS transistor NM4 all operate in a saturation region, and the third PMOS
  • the tube PM3 and the third NMOS transistor NM3 all operate in the linear region; since the base and collector of the PNP transistor Q are grounded, the PNP transistor Q is used as a diode after being turned on; the first PMOS transistor PM1 and the second PMOS
  • the first PMOS current mirror formed by the tube PM2 ensures that the magnitudes of the first current and the second current are equal and the same direction, that is, the magnitude of the first current flowing into the first NMOS transistor NM1 and the second current flowing into the second NMOS transistor NM2
  • the first NMOS current mirror formed by the first NMOS transistor NM1 and the second NMOS transistor NM2 ensures the first voltage and the PNP type on the first resistor R1 according to the action of the first current and the second current
  • the magnitude of the third current is equal to the first current.
  • the size of the second resistor R2 is N times the resistance of the first resistor R1 or the width to length ratio of the fourth NMOS transistor NM4 is N times the width to length ratio of the first NMOS transistor NM1.
  • the magnitude of the third current is N times the magnitude of the first current.
  • the voltage after the PNP type transistor Q is turned on may be referred to as a negative temperature coefficient voltage, that is, with the environment. As the temperature rises, V BE decreases.
  • the temperature coefficient source of the PNP type transistor Q is known, according to the temperature coefficient source, it can be known that the PNP type transistor Q is on the change with the ambient temperature.
  • the negative temperature coefficient voltage is the magnitude of V BE ; it should be noted that the power supply voltage V dd in this embodiment is a direct current voltage.
  • the third PMOS transistor PM3, the third NMOS transistor NM3, and the first capacitor C1 constitute one switched capacitor, which is equivalent to one resistor; and the second capacitor C2 acts as a filter capacitor, and is configured to be on the switched capacitor The two voltages are filtered to better obtain the output voltage V out .
  • FIG. 11 is a simulation result of the output voltage of the temperature detecting circuit provided at different temperatures according to Embodiment 4 of the present invention, and FIG. 11 shows that the output voltage V out of the temperature detecting circuit provided in this embodiment is -20 ° C and 180 ° C, respectively.
  • the temperature detecting circuit provided by the embodiment uses the third PMOS transistor PM3, the third NMOS transistor NM3 and the first capacitor C1 to form a switched capacitor instead of the third resistor R3 in the second embodiment;
  • the area of the MOS tube is small, and the replacement of the resistor by the switched capacitor can save the layout area and reduce the manufacturing cost of the circuit.
  • the temperature detecting circuit includes: a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, and a fourth PMOS transistor PM4.
  • connection relationship in the temperature detecting circuit shown in FIG. 12 is:
  • the source of the first NMOS transistor NM1 and the source of the second NMOS transistor NM2 are respectively grounded; the gate of the first NMOS transistor NM1 is connected to the gate of the second NMOS transistor NM2 and the first NMOS The drain of the transistor NM1 is connected to the gate of the first NMOS transistor NM1 and the gate of the second NMOS transistor NM2 such that the first NMOS transistor NM1 and the second NMOS transistor NM2 constitute a first NMOS current mirror; the first PMOS transistor PM1 The gate is connected to the gate of the second PMOS transistor PM2 and the drain of the second PMOS transistor PM2 is connected to the gate of the first PMOS transistor PM1 and the gate of the second PMOS transistor PM2 to make the first PMOS transistor PM1 and the second PMOS
  • the tube PM2 constitutes a first PMOS current mirror; the drain of the first PMOS transistor PM1 is connected to the drain of the first NMOS transistor NM1; the drain of the second
  • the source of the fourth PMOS transistor PM4 is connected to the power supply voltage V dd ; the gate of the fourth PMOS transistor PM4 is connected to the gate of the fourth NMOS transistor NM4 and the gate of the fourth PMOS transistor PM4 and the fourth NMOS
  • the gate of the tube NM4 is respectively connected to the second rectangular wave input terminal; the drain of the fourth PMOS transistor PM4 is connected to the drain of the fourth NMOS transistor NM4; one end of the second capacitor C2 is connected to the drain of the fourth PMOS transistor PM4 and the fourth The drain of the NMOS transistor NM4 and the other end are grounded; the source of the fourth NMOS transistor NM4 is connected to the source of the sixth PMOS transistor PM6; the gate of the sixth PMOS transistor PM6 is connected to the gate of the first PMOS transistor PM1, and the second PMOS The gate and the drain of the tube PM2, the drain of the second NMOS transistor NM2; the drain of the sixth PMOS transistor PM6 is connected to the source of the fifth PMOS
  • the third PMOS transistor PM3, the third NMOS transistor NM3, and the first capacitor C1 constitute a first switched capacitor
  • the fourth PMOS transistor PM4, the fourth NMOS transistor NM4, and the second capacitor C2 constitute a second switched capacitor
  • the PM5, the fifth NMOS transistor NM5, and the third capacitor C3 constitute a third switched capacitor.
  • the first PMOS transistor PM1, the second PMOS transistor PM2, the sixth PMOS transistor PM6, the first NMOS transistor NM1, and the second NMOS transistor NM2 all operate in a saturation region
  • the tube PM3, the fourth PMOS transistor PM4, the fifth PMOS transistor PM5, the third NMOS transistor NM3, the fourth NMOS transistor NM4, and the fifth NMOS transistor NM5 all operate in a linear region; due to the base and collector connection of the PNP transistor Q
  • the power supply voltage V dd causes the PNP transistor Q to be used as a diode after being turned on;
  • the first NMOS current mirror formed by the first NMOS transistor NM1 and the second NMOS transistor NM2 ensures that the first current and the second current are equal in magnitude and The direction is the same, that is, the first current flowing into the first PMOS transistor PM1 and the second current flowing into the second PMOS transistor PM2 are equal in magnitude and the direction is the same; according to the action of the first current and
  • the magnitude of the third current Is equal to the magnitude of the first current
  • the equivalent resistance of the second switched capacitor is N times the equivalent resistance of the first switched capacitor or the aspect ratio of the sixth PMOS tube PM6 is the aspect ratio of the first PMOS tube PM1
  • the magnitude of the third current is N times the magnitude of the first current.
  • the voltage after the PNP type transistor Q is turned on may be referred to as a negative temperature coefficient voltage, that is, with the environment. As the temperature rises, V BE decreases.
  • the temperature coefficient source of the PNP type transistor Q is known, according to the temperature coefficient source, it can be known that the PNP type transistor Q is on the change with the ambient temperature.
  • the negative temperature coefficient voltage is the magnitude of V BE ; it should be noted that the power supply voltage V dd in this embodiment is a direct current voltage.
  • the PNP type transistor Q may be replaced by a diode; the first switching capacitor, the second switching capacitor, and the third switching capacitor may be PMOS transistors; the first capacitor C1 and the second capacitor C2
  • the three capacitor C3 can select different types of capacitors, such as MOS capacitors, as needed.
  • the switch capacitor is used in this embodiment to replace all the resistors; since the area of the resistor is large in the layout, and the area of the MOS tube is small in the layout, the use of the switched capacitor instead of the resistor can save the layout. Area, reducing the production cost of the circuit.
  • the over temperature protection circuit 2 includes: a comparison circuit 21 including a positive phase input terminal, an inverting input terminal, and an output terminal, and the a reference voltage supply circuit 22 connected to the non-inverting input terminal of the comparison circuit 21, a temperature detection circuit 23 connected to the inverting input terminal of the comparison circuit 21, and a control circuit 24 connected to the output terminal of the comparison circuit 21; ,
  • the reference voltage supply circuit 22 is configured to provide the comparison circuit 21 with a reference voltage corresponding to a preset maximum temperature value
  • the temperature detecting circuit 23 is configured to generate a voltage corresponding to the ambient temperature according to a change in an ambient temperature in the circuit to be tested;
  • the comparison circuit 21 is configured to compare the voltage input by the temperature detecting circuit 22 with the reference voltage input by the reference voltage supply circuit 22, and output a comparison result;
  • the control circuit 24 is configured to respond to the comparison result output by the comparison circuit 21 to control the circuit to be tested.
  • the comparison circuit 21 is configured to: when it is detected that the voltage input by the temperature detecting circuit 22 is greater than or equal to the reference voltage input by the reference voltage supply circuit 22, generate a circuit for stopping the circuit to be tested. And outputting the signal to the control circuit 24, so that the control circuit 24 performs a corresponding operation according to the signal of the stop operation to stop the circuit to be tested; when the temperature detecting circuit is detected When the input voltage is less than the reference voltage input by the reference voltage supply circuit 22, a signal is generated to cause the circuit under test to continue to operate, and the continuously operating signal is output to the control circuit 24 to cause the control circuit Performing a corresponding operation according to the signal of the continued operation to continue the operation of the circuit under test; or, when detecting that the voltage input by the temperature detecting circuit 22 is less than the reference voltage input by the reference voltage supply circuit 22, Any signal is generated to cause the circuit under test to continue to operate in its original state.
  • the temperature detecting circuit 23 may be any one of the above-described first to fifth temperature detecting circuits; the comparison circuit 21 may be a comparator.
  • the temperature detecting circuit includes: a negative temperature coefficient voltage generating module and a voltage output module; wherein the negative temperature coefficient voltage generating module is configured to generate a negative temperature coefficient voltage according to a change in ambient temperature, and according to The negative temperature coefficient voltage acquires a first current and a second current of equal magnitude and direction; the voltage output module is configured to acquire a third current according to the first current and the second current, and according to the third The current acquires an output voltage to acquire the ambient temperature based on the output voltage.
  • the temperature change inside the chip can be converted into a varying voltage to monitor the temperature change, and the output voltage and the temperature coefficient are only related to the ratio of the resistance in the temperature detecting circuit, which can eliminate the adverse effects caused by the drift of the process parameter.
  • the process requirements are reduced.
  • the output stage of the temperature detecting circuit adopts a vertical cascade structure to increase the resistance of the output terminal, and can effectively suppress the influence of the change of the power supply voltage on the output voltage.

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Abstract

一种温度检测电路（1），包括：负温度系数电压产生模块（11）、电压输出模块（12）；负温度系数电压产生模块（11），配置为根据环境温度的变化，产生负温度系数电压，并根据负温度系数电压获取大小相等、方向相同的第一电流和第二电流；电压输出模块（12），配置为根据第一电流和第二电流获取第三电流，并根据第三电流获取输出电压，以基于输出电压获取环境温度。

Description

一种温度检测电路和方法
相关申请的交叉引用
本申请基于申请号为201610933427.6、申请日为2016年10月31日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本发明涉及温度检测技术，尤其涉及一种温度检测电路和方法。
背景技术
随着集成电路芯片的特征尺寸越来越小和芯片集成度的迅速提高，使得器件密度、能耗密度和耗散功率都越来越大，热量发散到周围环境中的速度也越来越慢，芯片温度上升所产生的不良效果也越明显。已有研究表明，芯片温度平均每升高1℃，金属-氧化物半导体场效应管(Metal-Oxide Semiconductor Field Effect Transistor，MOS-FET)的驱动能力将下降约4％，连线延迟将增加5％，集成电路失效率将增加1倍。因此，为了保证电路性能和提高电路的可靠性，设计一种集成于集成电路比如电源管理芯片或者自动测试机(Automatic Test Equipment，ATE)中的温度检测电路具有重要的意义。
一般而言，在设计的过温点产生高转换速度的翻转信号是衡量过温保护电路性能的一个重要指标。当在比较器和带隙基准精度一定的情况下，需要通过提高温度检测电路的温度系数，从而保证在过温点的准确性以及产生保护信号的高转换速度。因此，设计高灵敏度的温度检测电路是过温保护的难点之一。
现有技术中，温度检测电路一般采用以下三种方案：
方案一：如图1所示，将温度检测电路集成在带隙基准中，即在设计带隙基准过程中，同时将温度检测电路嵌入设计于带隙基准中；其中，n≥4且为正整数；在实际应用中可选择n＝9，即有8个三极管并联在一起。
方案二：如图2所示，利用MOS管中载流子迁移率u的温度特性产生与绝对温度成正比(Proportional To Absolute Temperature，PTAT)的电压；
方案三：如图3所示，利用二极管的导通电压VBE的负温度系数来检测温度变化，并使多个二极管相串联来增大温度系数。
上述三种方案中分别存在的问题是：在方案一中，电路的温度系数主要来自于热电压且
Figure PCTCN2017086008-appb-000001
而此温度系数较小，即使通过增加电路中电阻的阻值来调大温度系数，电路整体的温度系数仍然较小；在方案二中，电路的温度系数受电阻工艺参数变化的影响，易造成输出理论值与实际测量值之间的偏差较大；此外，方案一和方案二中所描述的这两类传统的温度检测电路的输出级恒流特性不好，电压稳定性较差；在方案三中，需要采用多个二极管，这会使芯片面积大大增加，且这种多个二极管的串联形式对工艺会有较大的限制。因此，目前亟需研制适合应用于集成电路中的新型的、高灵敏度的温度检测电路。
发明内容
有鉴于此，本发明实施例提供了一种温度检测电路和方法，能够解决传统温度检测电路灵敏度低、电压稳定性差、且易受工艺参数变化影响的不足之处。
为达到上述目的，本发明的技术方案是这样实现的：
本发明实施例提供了一种温度检测电路，所述温度检测电路包括：负温度系数电压产生模块、电压输出模块；其中，
所述负温度系数电压产生模块，配置为根据环境温度的变化，产生负 温度系数电压，并根据所述负温度系数电压获取大小相等、方向相同的第一电流和第二电流；
所述电压输出模块，配置为根据所述第一电流和第二电流获取第三电流，并根据所述第三电流获取输出电压，以基于所述输出电压获取所述环境温度。
上述方案中，所述负温度系数电压产生模块包括：第一MOS电流镜模块、与所述第一MOS电流镜模块连接的第二MOS电流镜模块、与所述第二MOS电流镜模块连接的第一负载和具有负温度系数的半导体器件；
所述第一MOS电流镜模块，配置为使流入所述第二MOS电流镜模块的第一电流和第二电流的大小相等及方向相同；
所述第二MOS电流镜模块，配置为根据所述第一电流和所述第二电流使所述第一负载上的第一电压与所述具有负温度系数的半导体器件上的负温度系数电压的大小相等；
所述具有负温度系数的半导体器件，配置为根据环境温度的变化，生成负温度系数电压、以及与所述第二电流大小相等的负温度系数电流。
上述方案中，所述电压输出模块包括：与所述负温度系数电压产生模块连接的第三MOS电流镜模块、与所述第三MOS电流镜模块连接的第二负载；
所述第三MOS电流镜模块，配置为根据所述第一电流和第二电流获取第三电流，并使所述第三电流作用于所述第二负载以获取输出电压。
上述方案中，所述电压输出模块还包括：与所述第三MOS电流镜模块连接的第三负载，所述第三电流流过所述第三负载生成第二电压，以根据所述第二电压获取输出电压。
上述方案中，所述电压输出模块还包括：与所述第三MOS电流镜模块连接的电容，配置为对所述第二电压进行滤波。
上述方案中，所述具有负温度系数的半导体器件为PNP型三极管或二极管。
上述方案中，所述负载为电阻或开关电容。
上述方案中，所述第一MOS电流镜模块包括第一PMOS管、第二PMOS管；所述第二MOS电流镜模块包括第一NMOS管、第二NMOS管；所述第三MOS电流镜模块包括第三NMOS管；所述具有负温度系数的半导体器件为PNP型三极管；所述第一负载为第一电阻、第二负载为第二电阻、第三负载为第三电阻；
第一PMOS管的源极、第二PMOS管的源极连接电源电压；第一PMOS管的栅极连接第二PMOS管的栅极且第一PMOS管的漏极连接第一PMOS管的栅极和第二PMOS管的栅极，以使第一PMOS管和第二PMOS管构成第一PMOS电流镜；第一PMOS管的漏极还连接第一NMOS管的漏极；第二PMOS管的漏极连接第二NMOS管的漏极；第一NMOS管的栅极连接第二NMOS管的栅极且第二NMOS管的漏极连接第一NMOS管的栅极和第二NMOS管的栅极，以使第一NMOS管和第二NMOS管构成第一NMOS电流镜；第一电阻的一端连接第一NMOS管的源极、另一端接地；PNP型三极管的发射极连接第二NMOS管的源极、基极和集电极接地；
第三NMOS管的栅极连接所述第二PMOS管的漏极、第一NMOS管的栅极、第二NMOS管的栅极和漏极；第二电阻的一端连接第三NMOS管的源极、另一端接地；第三电阻的一端连接电源电压、另一端连接第三NMOS管的漏极。
上述方案中，所述第一电阻的阻值等于所述第二电阻的阻值；或，所述第二电阻的阻值为所述第一电阻的阻值的N倍，N为正数。
上述方案中，所述第三NMOS管的宽长比等于所述第一NMOS管的宽长比；或，所述第三NMOS管的宽长比为所述第一NMOS管的宽长比的N 倍，N为正数。
本发明实施例还提供了一种温度检测方法，所述方法包括：
负温度系数电压产生模块根据环境温度的变化，获取负温度系数电压，并根据所述负温度系数电压获取大小相等、方向相同的第一电流和第二电流；
电压输出模块根据所述第一电流和第二电流获取第三电流，并根据所述第三电流获取输出电压，以基于所述输出电压获取所述环境温度。
上述方案中，所述负温度系数电压产生模块包括：第一MOS电流镜模块、与所述第一MOS电流镜模块连接的第二MOS电流镜模块、与所述第二MOS电流镜模块连接的第一负载和具有负温度系数的半导体器件；
所述负温度系数电压产生模块根据环境温度的变化，获取负温度系数电压，并根据所述负温度系数电压获取大小相等、方向相同的第一电流和第二电流，包括：
所述第一MOS电流镜模块使流入所述第二MOS电流镜模块的第一电流和第二电流的大小相等及方向相同；
所述第二MOS电流镜模块根据所述第一电流和所述第二电流使所述第一负载上的第一电压与所述具有负温度系数的半导体器件上的负温度系数电压的大小相等；
所述具有负温度系数的半导体器件根据环境温度的变化，生成负温度系数电压、以及与所述第二电流大小相等的负温度系数电流。
上述方案中，所述电压输出模块包括：与所述负温度系数电压产生模块连接的第三MOS电流镜模块、与所述第三MOS电流镜模块连接的第二负载；
所述电压输出模块根据所述第一电流和第二电流获取第三电流，并根据所述第三电流获取输出电压，包括：
所述第三MOS电流镜模块根据所述第一电流和第二电流获取第三电流，并使所述第三电流作用于所述第二负载以获取输出电压。
本发明实施例提供的温度检测电路和方法，该温度检测电路包括：负温度系数电压产生模块、电压输出模块；所述负温度系数电压产生模块，配置为根据环境温度的变化，产生负温度系数电压，并根据所述负温度系数电压获取大小相等、方向相同的第一电流和第二电流；所述电压输出模块，配置为根据所述第一电流和第二电流获取第三电流，并根据所述第三电流获取输出电压，以基于所述输出电压获取所述环境温度；可见，本发明实施例提供的温度检测电路能把芯片内部变化的温度转化为变化的电压来进行监测温度变化，且输出电压以及温度系数只与该温度检测电路中电阻的比值有关，能消除工艺参数漂移所带来的不良影响，降低对工艺的要求；同时，该温度检测电路的输出级采用垂直级联(cascode)结构，使输出端的电阻增大，能有效的抑制电源电压的变化对输出电压的影响。
此外，还可进一步通过控制该温度检测电路中电阻的比值来提高整个电路的温度系数和温度灵敏度。
附图说明
图1为现有技术中集成在带隙基准中的温度检测电路的组成结构示意图；
图2为现有技术中采用MOS管中载流子迁移率u的温度特性来设计的温度检测电路的组成结构示意图；
图3为传统技术中采用多个二极管相串联来设计的温度检测电路的组成结构示意图；
图4为本发明实施例一提供的温度检测电路的结构示意框图；
图5为本发明实施例一提供的温度检测方法的实现流程示意图；
图6为本发明实施例二提供的温度检测电路的具体组成结构示意图；
图7为本发明实施例三提供的温度检测电路的具体组成结构示意图；
图8为本发明实施例三提供的温度检测电路的输出电压随温度变化的仿真结果图；
图9为本发明实施例三提供的温度检测电路的输出电压随电源电压变化的仿真结果图；
图10为本发明实施例四提供的温度检测电路的具体组成结构示意图；
图11为本发明实施例四提供的温度检测电路的输出电压在不同温度下的仿真结果图；
图12为本发明实施例五提供的温度检测电路的具体组成结构示意图；
图13为本发明实施例六提供的过温保护电路的结构示意框图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。
实施例一
图4为本发明实施例一提供的温度检测电路的结构示意框图，该温度检测电路1包括：负温度系数电压产生模块11、电压输出模块12；其中，
所述负温度系数电压产生模块11，配置为根据环境温度的变化，产生负温度系数电压，并根据所述负温度系数电压获取大小相等、方向相同的第一电流和第二电流；
所述电压输出模块12，配置为根据所述第一电流和第二电流获取第三电流，并根据所述第三电流获取输出电压，以基于所述输出电压获取所述环境温度。
其中，所述负温度系数电压产生模块11包括：第一MOS电流镜模块111、与所述第一MOS电流镜模块111连接的第二MOS电流镜模块112、与所述第二MOS电流镜模块112连接的第一负载113和具有负温度系数的半导体器件114；
所述第一MOS电流镜模块111，配置为使流入所述第二MOS电流镜模块112的第一电流和第二电流的大小相等及方向相同；
所述第二MOS电流镜模块112，配置为根据所述第一电流和所述第二电流使所述第一负载113上的第一电压与所述具有负温度系数的半导体器件114上的负温度系数电压的大小相等；
所述具有负温度系数的半导体器件114，配置为根据环境温度的变化，生成负温度系数电压、以及与所述第二电流大小相等的负温度系数电流。
所述电压输出模块12包括：与所述负温度系数电压产生模块11连接的第三MOS电流镜模块121、与所述第三MOS电流镜模块121连接的第二负载122；
所述第三MOS电流镜模块121，与所述第一MOS电流镜模块111和所述第二MOS电流镜模块112连接，配置为根据所述第一电流和第二电流获取第三电流，并使所述第三电流作用于所述第二负载122以获取输出电压。
进一步地，所述电压输出模块12还可包括：与所述第三MOS电流镜模块121连接的第三负载123，所述第三电流流过所述第三负载123生成第二电压，以根据所述第二电压获取输出电压。
进一步地，所述电压输出模块12还可包括：与所述第三MOS电流镜模块121连接的电容124，配置为对所述第二电压进行滤波。
这里，所述具有负温度系数的半导体器件124为PNP型三极管或二极管；所述负载为电阻或开关电容，即所述第一负载113、第二负载122、第 三负载123为电阻或开关电容；所述第一MOS电流镜模块111为PMOS电流镜、第二MOS电流镜模块112为NMOS电流镜、第三MOS电流镜模块121为PMOS电流镜或NMOS电流镜。
图5为本发明实施例一提供的温度检测方法的实现流程示意图，该温度检测方法包括：
步骤101：负温度系数电压产生模块根据环境温度的变化，产生负温度系数电压，并根据所述负温度系数电压获取大小相等、方向相同的第一电流和第二电流；
步骤102：电压输出模块根据所述第一电流和第二电流获取第三电流，并根据所述第三电流获取输出电压，以基于所述输出电压获取所述环境温度。
所述负温度系数电压产生模块包括：第一MOS电流镜模块、与所述第一MOS电流镜模块连接的第二MOS电流镜模块、与所述第二MOS电流镜模块连接的第一负载和具有负温度系数的半导体器件；
其中，所述负温度系数电压产生模块根据环境温度的变化，获取负温度系数电压，并根据所述负温度系数电压获取大小相等、方向相同的第一电流和第二电流，包括：所述第一MOS电流镜模块使流入所述第二MOS电流镜模块的第一电流和第二电流的大小相等及方向相同；所述第二MOS电流镜模块根据所述第一电流和所述第二电流使所述第一负载上的第一电压与所述具有负温度系数的半导体器件上的负温度系数电压的大小相等；所述具有负温度系数的半导体器件根据环境温度的变化，生成负温度系数电压、以及与所述第二电流大小相等的负温度系数电流。
所述电压输出模块包括：与所述负温度系数电压产生模块连接的第三MOS电流镜模块、与所述第三MOS电流镜模块连接的第二负载；
其中，所述电压输出模块根据所述第一电流和第二电流获取第三电 流，并根据所述第三电流获取输出电压，包括：所述第三MOS电流镜模块根据所述第一电流获取第三电流，并使所述第三电流作用于所述第二负载以获取输出电压。
本发明实施例中，通过负温度系数电压产生模块能够获取到与环境温度对应的负温度系数电压和负温度系数电流，然后通过电压输出模块获取到与所述环境温度对应的输出电压，以基于所述输出电压获取到所述环境温度，从而实现温度检测的目的。
需要说明的是，本发明实施例提供的温度检测方法的实现是循环实现的，可以通过上述温度检测电路实现。
实施例二
图6为本发明实施例二提供的温度检测电路的具体组成结构示意图，该温度检测电路包括：第一PMOS管PM1、第二PMOS管PM2、第一NMOS管NM1、第二NMOS管NM2、第三NMOS管NM3、PNP型三极管Q、第一电阻R1、第二电阻R2、第三电阻R3；其中，第一PMOS管PM1、第二PMOS管PM2、第一NMOS管NM1、第二NMOS管NM2、PNP型三极管Q、第一电阻R1构成负温度系数电压产生模块，第三NMOS管NM3、第二电阻R2、第三电阻R3构成电压输出模块；
其中，图6所示的温度检测电路中的连接关系为：
在负温度系数电压产生模块中，第一PMOS管PM1的源极、第二PMOS管PM2的源极连接电源电压Vdd；第一PMOS管PM1的栅极连接第二PMOS管PM2的栅极且第一PMOS管PM1的漏极连接第一PMOS管PM1的栅极和第二PMOS管PM2的栅极，以使第一PMOS管PM1和第二PMOS管PM2构成第一PMOS电流镜；第一PMOS管PM1的漏极还连接第一NMOS管NM1的漏极；第二PMOS管PM2的漏极连接第二NMOS管NM2的漏极；第一NMOS管NM1的栅极连接第二NMOS管NM2的栅极且第二NMOS 管NM2的漏极连接第一NMOS管NM1的栅极和第二NMOS管NM2的栅极，以使第一NMOS管NM1和第二NMOS管NM2构成第一NMOS电流镜；第一电阻R1的一端连接第一NMOS管NM1的源极、另一端接地；PNP型三极管Q的发射极连接第二NMOS管NM2的源极，而PNP型三极管Q的基极和集电极接地；
在电压输出模块中，第三NMOS管NM3的栅极连接所述第二PMOS管PM2的漏极、第一NMOS管NM1的栅极、第二NMOS管NM2的栅极和漏极，以使第一NMOS管NM1和第三NMOS管NM3构成第二NMOS电流镜；第二电阻R2的一端连接第三NMOS管的源极、另一端接地；第三电阻R3的一端连接电源电压Vdd、另一端连接第三NMOS管NM3的漏极。
这里，所述电路在正常工作时，第一PMOS管PM1、第二PMOS管PM2、第一NMOS管NM1、第二NMOS管NM2、第三NMOS管NM3都工作在饱和区；由于PNP型三极管Q的基极和集电极接地，从而使PNP型三极管Q在导通后当作二极管使用；第一PMOS管PM1和第二PMOS管PM2所构成的第一PMOS电流镜保证第一电流I1和第二电流I2的大小相等、方向相同，即使得流入第一NMOS管NM1的第一电流I1和流入第二NMOS管NM2的第二电流I2的大小相等及方向相同；根据所述第一电流I1和第二电流I2的作用，第一NMOS管NM1和第二NMOS管NM2所构成的第一NMOS电流镜保证第一电阻R1上的第一电压和PNP型三极管Q上的负温度系数电压相同；第一NMOS管NM1和第三NMOS管NM3所构成第二NMOS电流镜能够实现“拷贝”第一电流I1，获取到第三电流I3，并使I3＝I1或I3＝NI1，N表示第二电阻R2的阻值与第一电阻R1的阻值之间的比值或第三NMOS管NM3的宽长比与第一NMOS管NM1的宽长比之间的比值。
这里，当第二电阻R2的阻值等于第一电阻R1的阻值或者第三NMOS管NM3的宽长比等于第一NMOS管NM1的宽长比时，则I3＝I1；当第二电阻R2的阻值为第一电阻R1的阻值的N倍或者第三NMOS管NM3的宽长比为第一NMOS管NM1的宽长比的N倍时，则I3＝NI1。
这里，由于PNP型三极管Q具有负温度系数的特性，则所述PNP型三极管Q导通后的电压即基极与发射极之间的电压VBE可称为负温度系数电压，即随着环境温度的升高，VBE随之减小；同时，由于所述PNP型三极管Q的温度系数源已知，则根据所述温度系数源可获知随着环境温度的变化，PNP型三极管Q上的负温度系数电压即VBE的大小；需要说明的是，本实施例中的电源电压Vdd为直流电压。
这里，根据所述负温度系数电压VBE可获取所述第一电流I1和第二电流I2；随着环境温度的变化，所述负温度系数电压VBE会发生变化，导致电路中所述第一电流I1和第二电流I2的大小也相应会发生变化；由于第一NMOS管NM1工作在饱和区，使得流过第一电阻R1的电流和第一电流I1的大小相等及方向相同；此外，第一电阻R1上的第一电压和PNP型三极管Q上的负温度系数电压VBE的大小相同；因此，根据所述负温度系数电压VBE与所述第一电阻R1，可获得第一电流I1的大小，进而可根据所述第一电流I1的大小求取输出电压VPTAT。
在图6中，可通过控制第一电阻R1、第二电阻R2的大小以设置电路中第三电流I3的大小；当第一电阻R1的阻值等于第二电阻R2的阻值或第一NMOS管NM1的宽长比等于第三NMOS管NM3的宽长比时，则有：
Figure PCTCN2017086008-appb-000002
Figure PCTCN2017086008-appb-000003
Figure PCTCN2017086008-appb-000004
其中，VR3表示第三电阻上的电压即第二电压；VBE0表示PNP型三极管Q在环境温度为T0时的电压；T表示当前的环境温度；KM表示PNP型三极管Q的温度系数源，这里可以采用较大的温度系数源，比如采用
Figure PCTCN2017086008-appb-000005
由上述公式可知，通过调节第一电阻R1与第三电阻R3之间的大小比值可实现调节该温度检测电路的输出电压VPTAT与温度系数
Figure PCTCN2017086008-appb-000006
并且通过版图中第一电阻R1和第三电阻R3做匹配可消除由于电阻工艺参数变化引起的输出量漂移。
这里，根据本发明实施例提供的温度检测电路获取到输出电压VPTAT后，可利用上述公式推导出当前的环境温度T或温度变化差T-T0，以实现温度检测。
此外，第二电阻R2与第三NMOS管NM3构成cascode结构，使得由第三NMOS管NM3和第二电阻R2所构成的输出端的输出电阻R0大大增加，即：
R0＝Gm3×R2×Rds3+Rds3+R3>>Rds3
其中，Rds3是第三NMOS管NM3的输出阻抗，Gm3是第三NMOS管NM3的跨导。
这里，相比采用单个MOS管作为恒流源的传统温度检测电路而言，本发明实施例中采用cascode结构后使得输出端的输出电阻增大了约Gm3×R2倍，因此，输出电流源具有更强的抑制电源电压波动的能力。
实施例三
图7为本发明实施例三提供的温度检测电路的具体组成结构示意图，该温度检测电路包括：第一PMOS管PM1、第二PMOS管PM2、第三PMOS管PM3、第一NMOS管NM1、第二NMOS管NM2、PNP型三极管Q、第 一电阻R1、第二电阻R2；其中，第一PMOS管PM1、第二PMOS管PM2、第一NMOS管NM1、第二NMOS管NM2、PNP型三极管Q、第一电阻R1构成负温度系数电压产生模块，第三PMOS管PM3、第二电阻R2构成电压输出模块；
其中，图7所示的温度检测电路中的连接关系为：
在负温度系数电压产生模块中，第一PMOS管PM1的源极、第二PMOS管PM2的源极连接电源电压Vdd；第一PMOS管PM1的栅极连接第二PMOS管PM2的栅极且第二PMOS管PM2的漏极连接第一PMOS管PM1的栅极和第二PMOS管PM2的栅极，以使第一PMOS管PM1和第二PMOS管PM2构成第一PMOS电流镜；第一PMOS管PM1的漏极连接第一NMOS管NM1的漏极；第二PMOS管PM2的漏极还连接第二NMOS管NM2的漏极；第一NMOS管NM1的栅极连接第二NMOS管NM2的栅极且第一NMOS管NM1的漏极连接第一NMOS管NM1的栅极和第二NMOS管NM2的栅极，以使第一NMOS管NM1和第二NMOS管NM2构成第一NMOS电流镜；PNP型三极管Q的发射极连接第一NMOS管NM1的源极，而PNP型三极管Q的基极和集电极分别接地；第一电阻R1的一端连接第二NMOS管NM2的源极、另一端接地；
在电压输出模块中，第三PMOS管PM3的栅极连接所述负温度系数电压产生模块中第一PMOS管PM1的栅极、第二PMOS管PM2的栅极和漏极、第二NMOS管NM2的漏极；第三PMOS管PM3的源极连接电源电压Vdd；第二电阻R2的一端连接第三PMOS管PM3的漏极、另一端接地。
这里，所述电路在正常工作时，第一PMOS管PM1、第二PMOS管PM2、第三PMOS管PM3、第一NMOS管NM1、第二NMOS管NM2都工作在饱和区；由于PNP型三极管Q的基极和集电极接地，从而使PNP型三极管Q在导通后当作二极管使用；第一PMOS管PM1和第二PMOS 管PM2所构成的第一PMOS电流镜保证第一电流I1和第二电流I2的大小相等和方向相同，即使得流入第一NMOS管NM1的第一电流I1和流入第二NMOS管NM2的第二电流I2的大小相等及方向相同；根据所述第一电流I1和第二电流I2的作用，第一NMOS管NM1和第二NMOS管NM2所构成的第一NMOS电流镜保证第一电阻R1上的第一电压和PNP型三极管Q上的负温度系数电压相同；第一PMOS管PM1和第三PMOS管PM3所构成第二PMOS电流镜能够实现“拷贝”电流I1，获取到第三电流I3，并使I3＝I1或I3＝NI1，N表示第二电阻R2的阻值与第一电阻R1的阻值之间的比值或第三PMOS管PM3的宽长比与第一PMOS管PM1的宽长比之间的比值。
这里，当第二电阻R2的阻值等于第一电阻R1的阻值或者第三PMOS管PM3的宽长比等于第一PMOS管PM1的宽长比时，则I3＝I1；当第二电阻R2的阻值为第一电阻R1的阻值的N倍或者第三PMOS管PM3的宽长比为第一PMOS管PM1的宽长比的N倍时，则I3＝NI1。
这里，由于PNP型三极管Q具有负温度系数的特性，则所述PNP型三极管Q导通后的电压即基极与发射极之间的电压VBE可称为负温度系数电压，即随着环境温度的升高，VBE随之减小；同时，由于所述PNP型三极管Q的温度系数源已知，则根据所述温度系数源可获知随着环境温度的变化，PNP型三极管Q上的负温度系数电压即VBE的大小；需要说明的是，本实施例中的电源电压Vdd为直流电压。
这里，随着环境温度的变化，所述负温度系数电压VBE会发生变化，导致电路中所述第一电流I1和第二电流I2的大小也相应会发生变化；由于第二NMOS管NM2工作在饱和区，使得流过第一电阻R1的电流和第二电流I2的大小相等及方向相同；此外，第一电阻R1上的第一电压和PNP型三极管Q上的负温度系数电压VBE的大小相同；因此，根据所述负温度系数电压VBE与 所述第一电阻R1，可获得第二电流I2的大小，进而可根据所述第二电流I2的大小求取输出电压VCTAT。
图8为本发明实施例三提供的温度检测电路的输出电压随温度变化的仿真结果图，从图8中可以看出，本实施例提供的温度检测电路的输出电压VCTAT与温度T成反比；其中，曲线Vcon为图1中现有的温度检测电路的输出电压与温度之间的关系，温度系数为3.5mV/℃；曲线VCTAT1、VCTAT3、VCTAT5分别是N为1、3、5时，本实施例提供的温度检测电路的输出电压VCTAT在温度为-20～180℃范围内的变化情况，N＝R2/R1；由于在一定范围内可通过调整第一电阻R1和第二电阻R2之间的相对比值即N来提高电路的温度系数，从图中可以看出，当N＝5时，该温度检测电路的温度系数为11.2mV/℃，是图1中现有的温度检测电路的温度系数的3倍多；曲线Vdes1、Vdes3、Vdes5分别是N为1、3、5且VBE＝700mV、
Figure PCTCN2017086008-appb-000007
时的理论计算曲线，各自与仿真曲线VCTAT1、VCTAT3、VCTAT5的吻合程度较高，最大偏差小于2％。
图9为本发明实施例三提供的温度检测电路的输出电压随电源电压变化的仿真结果图，从图9中可以看出，曲线自下而上分别是N为1、3、5时，输出电压VCTAT随电源电压Vdd在0～8V范围内时的变化情况；从图9中的仿真结果可以看出，电源电压Vdd在4～8V范围内时，输出电压VCTAT的变化虽然不太明显，但存在一定的波动，这是因为本实施例中采用第三PMOS管PM3作为输出电流源，与实施例二相比，本实施例提供的温度检测电路的输出电压易受电源电压的影响；此外，由于CMOS工艺下的MOS管的阈值较高(Vthn≈1.9V，|Vthp|≈2V)，因此在电源电压Vdd小于2V时，该电路工作截止。
实施例四
图10为本发明实施例四提供的温度检测电路的具体组成结构示意图，该温度检测电路包括：第一PMOS管PM1、第二PMOS管PM2、第三PMOS 管PM3、第一NMOS管NM1、第二NMOS管NM2、第三NMOS管NM3、第四NMOS管NM4、PNP型三极管Q、第一电阻R1、第二电阻R2、第一电容C1、第二电容C2；其中，第一PMOS管PM1、第二PMOS管PM2、第一NMOS管NM1、第二NMOS管NM2、PNP型三极管Q、第一电阻R1构成负温度系数电压产生模块，第三PMOS管PM3、第三NMOS管NM3、第四NMOS管NM4、第二电阻R2、第一电容C1、第二电容C2构成电压输出模块；
其中，图10所示的温度检测电路中的连接关系为：
在负温度系数电压产生模块中，第一PMOS管PM1的源极、第二PMOS管PM2的源极连接电源电压Vdd；第一PMOS管PM1的栅极连接第二PMOS管PM2的栅极且第一PMOS管PM1的漏极连接第一PMOS管PM1的栅极和第二PMOS管PM2的栅极，以使第一PMOS管PM1和第二PMOS管PM2构成第一PMOS电流镜；第一PMOS管PM1的漏极还连接第一NMOS管NM1的漏极；第二PMOS管PM2的漏极连接第二NMOS管NM2的漏极；第一NMOS管NM1的栅极连接第二NMOS管NM2的栅极且第二NMOS管NM2的漏极连接第一NMOS管NM1的栅极和第二NMOS管NM2的栅极，以使第一NMOS管NM1和第二NMOS管NM2构成第一NMOS电流镜；第一电阻R1的一端连接第一NMOS管NM1的源极、另一端接地；PNP型三极管Q的发射极连接第二NMOS管NM2的源极，而PNP型三极管Q的基极和集电极接地；
在电压输出模块中，第三PMOS管PM3的源极连接电源电压Vdd；第三PMOS管的栅极PM3连接第三NMOS管NM3的栅极且第三PMOS管PM3的栅极和第三NMOS管NM3的栅极都连接第一矩形波输入端；第三PMOS管PM3的漏极连接第三NMOS管NM3的漏极；第三NMOS管NM3的源极连接第四NMOS管NM4的漏极；第一电容C1的一端连接第三PMOS 管PM3的漏极和第三NMOS管NM3的漏极、另一端接地；第四NMOS管NM4的栅极连接所述负温度系数电压产生模块中第一NMOS管NM1的栅极、第二NMOS管NM2的栅极和漏极、第二PMOS管PM2的漏极；第二电容C2的一端连接第三NMOS管NM3的源极和第四NMOS管NM4的漏极、另一端接地；第二电阻R2的一端连接第四NMOS管NM4的源极、另一端接地。
这里，在所述电路在正常工作时，第一PMOS管PM1、第二PMOS管PM2、第一NMOS管NM1、第二NMOS管NM2、第四NMOS管NM4都工作在饱和区，而第三PMOS管PM3、第三NMOS管NM3都工作在线性区；由于PNP型三极管Q的基极和集电极接地，使PNP型三极管Q在导通后当作二极管使用；第一PMOS管PM1和第二PMOS管PM2所构成的第一PMOS电流镜保证第一电流和第二电流的大小相等和方向相同，即使得流入第一NMOS管NM1的第一电流和流入第二NMOS管NM2的第二电流的大小相等及方向相同；根据所述第一电流和第二电流的作用，第一NMOS管NM1和第二NMOS管NM2所构成的第一NMOS电流镜保证第一电阻R1上的第一电压和PNP型三极管Q上的负温度系数电压相同；第一NMOS管NM1和第四NMOS管NM4所构成第二NMOS电流镜能够实现“拷贝”第一电流，获取到第三电流，并使第三电流的大小等于第一电流的大小或者第三电流的大小为第一电流的大小的N倍，N表示第二电阻R2的阻值与第一电阻R1的阻值之间的比值或第四NMOS管NM4的宽长比与第一NMOS管NM1的宽长比之间的比值。
这里，当第二电阻R2的阻值等于第一电阻R1的阻值或者第四NMOS管NM4的宽长比等于第一NMOS管NM1的宽长比时，则第三电流的大小等于第一电流的大小；当第二电阻R2的阻值为第一电阻R1的阻值的N倍或者第四NMOS管NM4的宽长比为第一NMOS管NM1的宽长比的N倍 时，则第三电流的大小为第一电流的大小的N倍。
这里，由于PNP型三极管Q具有负温度系数的特性，则所述PNP型三极管Q导通后的电压即基极与发射极之间的电压VBE可称为负温度系数电压，即随着环境温度的升高，VBE随之减小；同时，由于所述PNP型三极管Q的温度系数源已知，则根据所述温度系数源可获知随着环境温度的变化，PNP型三极管Q上的负温度系数电压即VBE的大小；需要说明的是，本实施例中的电源电压Vdd为直流电压。
这里，第三PMOS管PM3、第三NMOS管NM3和第一电容C1构成一个开关电容，等效于一个电阻；并且，第二电容C2当作滤波电容，配置为对所述开关电容上的第二电压进行滤波，以更好的获取输出电压Vout。
图11为本发明实施例四提供的温度检测电路的输出电压在不同温度下的仿真结果图，图11展示了本实施例提供的温度检测电路的输出电压Vout分别在-20℃和180℃下的仿真曲线，从图11中可以看出，该温度检测电路在180℃时的输出电压明显高于在-20℃时的输出电压，与设计相符。
与实施例二相比，本实施例提供的温度检测电路采用第三PMOS管PM3、第三NMOS管NM3和第一电容C1构成一个开关电容，以取代实施例二中的第三电阻R3；由于在版图中MOS管的面积小，采用开关电容替代电阻更能节省版图面积，减少电路的制作成本。
实施例五
图12为本发明实施例五提供的温度检测电路的具体组成结构示意图，该温度检测电路包括：第一PMOS管PM1、第二PMOS管PM2、第三PMOS管PM3、第四PMOS管PM4、第五PMOS管PM5、第六PMOS管PM6、第一NMOS管NM1、第二NMOS管NM2、第三NMOS管NM3、第四NMOS管NM4、第五NMOS管NM5、PNP型三极管Q、第一电容C1、第二电容C2、第三电容C3；其中，第一PMOS管PM1、第二PMOS管PM2、第三 PMOS管PM3、第一NMOS管NM1、第二NMOS管NM2、第三NMOS管NM3、PNP型三极管Q、第一电容C1构成负温度系数电压产生模块，第四PMOS管PM4、第五PMOS管PM5、第六PMOS管PM6、第四NMOS管NM4、第五NMOS管NM5、第二电容C2、第三电容C3构成电压输出模块；
其中，图12所示的温度检测电路中的连接关系为：
在负温度系数电压产生模块中，第一NMOS管NM1的源极和第二NMOS管NM2的源极分别接地；第一NMOS管NM1的栅极连接第二NMOS管NM2的栅极且第一NMOS管NM1的漏极连接第一NMOS管NM1的栅极和第二NMOS管NM2的栅极，以使第一NMOS管NM1和第二NMOS管NM2构成第一NMOS电流镜；第一PMOS管PM1的栅极连接第二PMOS管PM2的栅极且第二PMOS管PM2的漏极连接第一PMOS管PM1的栅极和第二PMOS管PM2的栅极，以使第一PMOS管PM1和第二PMOS管PM2构成第一PMOS电流镜；第一PMOS管PM1的漏极连接第一NMOS管NM1的漏极；第二PMOS管PM2的漏极连接第二NMOS管NM2的漏极；PNP型三极管Q的发射极连接第二PMOS管PM2的源极，而PNP型三极管Q的基极和集电极连接电源电压Vdd；第一PMOS管PM1的源极连接第三NMOS管NM3的源极；第三NMOS管NM3的栅极连接第三PMOS管PM3的栅极且第三NMOS管NM3的栅极和第三PMOS管PM3的栅极分别连接第一矩形波输入端；第三NMOS管NM3的漏极连接第三PMOS管PM3的漏极；第三PMOS管PM3的源极连接电源电压Vdd；第一电容C1的一端连接第三NMOS管NM3的漏极和第三PMOS管PM3的漏极、另一端接地；
在电压输出模块中，第四PMOS管PM4的源极连接电源电压Vdd；第四PMOS管PM4的栅极连接第四NMOS管NM4的栅极且第四PMOS管PM4的栅极和第四NMOS管NM4的栅极分别连接第二矩形波输入端；第四 PMOS管PM4的漏极连接第四NMOS管NM4的漏极；第二电容C2的一端连接第四PMOS管PM4的漏极和第四NMOS管NM4的漏极、另一端接地；第四NMOS管NM4的源极连接第六PMOS管PM6的源极；第六PMOS管PM6的栅极连接第一PMOS管PM1的栅极、第二PMOS管PM2的栅极和漏极、第二NMOS管NM2的漏极；第六PMOS管PM6的漏极连接第五PMOS管PM5的源极；第五PMOS管PM5的栅极连接第五NMOS管NM5的栅极且第五PMOS管PM5的栅极和第五NMOS管NM5的栅极分别连接第三矩形波输入端；第五PMOS管PM5的漏极连接第五NMOS管NM5的漏极；第五NMOS管NM5的源极接地；第三电容C3的一端连接第五PMOS管PM5的漏极和第五NMOS管NM5的漏极、另一端接地。
这里，第三PMOS管PM3、第三NMOS管NM3和第一电容C1构成第一开关电容；第四PMOS管PM4、第四NMOS管NM4和第二电容C2构成第二开关电容；第五PMOS管PM5、第五NMOS管NM5和第三电容C3构成第三开关电容。
这里，在所述电路在正常工作时，第一PMOS管PM1、第二PMOS管PM2、第六PMOS管PM6、第一NMOS管NM1、第二NMOS管NM2都工作在饱和区，而第三PMOS管PM3、第四PMOS管PM4、第五PMOS管PM5、第三NMOS管NM3、第四NMOS管NM4、第五NMOS管NM5都工作在线性区；由于PNP型三极管Q的基极和集电极接电源电压Vdd，使PNP型三极管Q在导通后当作二极管使用；第一NMOS管NM1和第二NMOS管NM2所构成的第一NMOS电流镜保证第一电流和第二电流的大小相等和方向相同，即使得流入第一PMOS管PM1的第一电流和流入第二PMOS管PM2的第二电流的大小相等及方向相同；根据所述第一电流和第二电流的作用，第一PMOS管PM1和第二PMOS管PM2所构成的第一PMOS电流镜保证第一开关电容上的第一电压和PNP型三极管Q上的负温 度系数电压相同；第一PMOS管PM1和第六PMOS管PM6所构成第二PMOS电流镜能够实现“拷贝”第一电流，获取到第三电流，并使第三电流的大小等于第一电流的大小或者第三电流的大小为第一电流的大小的N倍，N表示第二开关电容的等效电阻值与第一开关电容的等效电阻值之间的比值或第六PMOS管PM6的宽长比与第一PMOS管PM1的宽长比之间的比值。
这里，当第二开关电容的等效电阻值等于第一开关电容的等效电阻值或者第六PMOS管PM6的宽长比等于第一PMOS管PM1的宽长比时，则第三电流的大小等于第一电流的大小；当第二开关电容的等效电阻值为第一开关电容的等效电阻值的N倍或者第六PMOS管PM6的宽长比为第一PMOS管PM1的宽长比的N倍时，则第三电流的大小为第一电流的大小的N倍。
这里，由于PNP型三极管Q具有负温度系数的特性，则所述PNP型三极管Q导通后的电压即基极与发射极之间的电压VBE可称为负温度系数电压，即随着环境温度的升高，VBE随之减小；同时，由于所述PNP型三极管Q的温度系数源已知，则根据所述温度系数源可获知随着环境温度的变化，PNP型三极管Q上的负温度系数电压即VBE的大小；需要说明的是，本实施例中的电源电压Vdd为直流电压。
这里，所述PNP型三极管Q可用二极管替代；第一开关电容、第二开关电容、第三开关电容中当作开关的NMOS管都可以是PMOS管；第一电容C1、第二电容C2、第三电容C3可以根据需要选择不同类型的电容，例如MOS电容。
与实施例二相比，本实施例中采用开关电容取代了所有电阻；由于在版图中电阻的面积很大，而在版图中MOS管的面积很小，因此采用开关电容取代电阻能够更加节省版图面积，减少电路的制作成本。
实施例六
图13为本发明实施例六提供的过温保护电路的结构示意框图，该过温保护电路2包括：包括一正相输入端、一反相输入端以及一输出端的比较电路21、与所述比较电路21的正相输入端连接的基准电压提供电路22、与所述比较电路21的反相输入端连接的温度检测电路23、与所述比较电路21的输出端连接的控制电路24；其中，
所述基准电压提供电路22，配置为为比较电路21提供预设最大温度值所对应的基准电压；
所述温度检测电路23，配置为根据待测电路中环境温度的变化，生成与所述环境温度对应的电压；
比较电路21，配置为将所述温度检测电路22输入的电压与所述基准电压提供电路22输入的基准电压进行比较，并输出比较结果；
控制电路24，配置为响应所述比较电路21输出的比较结果，以控制所述待测电路。
其中，所述比较电路21，配置为：当检测到所述温度检测电路22输入的电压大于或等于所述基准电压提供电路22输入的基准电压时，产生一个使所述待测电路停止工作的信号，并将该停止工作的信号输出至控制电路24，以使所述控制电路24根据该停止工作的信号执行相应的操作从而使所述待测电路停止工作；当检测到所述温度检测电路22输入的电压小于所述基准电压提供电路22输入的基准电压时，产生一个使所述待测电路继续工作的信号，并将该继续工作的信号输出至控制电路24，以使所述控制电路24根据该继续工作的信号执行相应的操作从而使所述待测电路继续工作；或者，当检测到所述温度检测电路22输入的电压小于所述基准电压提供电路22输入的基准电压时，不产生任何信号，以使所述待测电路继续保持原来的状态工作。
这里，所述温度检测电路23可以是上述实施例一至五中任意一种温度检测电路；所述比较电路21可以是比较器。
以上所述，仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。凡在本发明的精神和范围之内所作的任何修改、等同替换和改进等，均包含在本发明的保护范围之内。
工业实用性
本发明实施例所提供的温度检测电路包括：负温度系数电压产生模块、电压输出模块；其中，所述负温度系数电压产生模块，配置为根据环境温度的变化，产生负温度系数电压，并根据所述负温度系数电压获取大小相等、方向相同的第一电流和第二电流；所述电压输出模块，配置为根据所述第一电流和第二电流获取第三电流，并根据所述第三电流获取输出电压，以基于所述输出电压获取所述环境温度。如此，能把芯片内部变化的温度转化为变化的电压来进行监测温度变化，且输出电压以及温度系数只与该温度检测电路中电阻的比值有关，能消除工艺参数漂移所带来的不良影响，降低对工艺的要求；同时，该温度检测电路的输出级采用垂直级联结构，使输出端的电阻增大，能有效的抑制电源电压的变化对输出电压的影响。

Claims (13)

  1. 一种温度检测电路，所述温度检测电路包括：负温度系数电压产生模块、电压输出模块；其中，
    所述负温度系数电压产生模块，配置为根据环境温度的变化，产生负温度系数电压，并根据所述负温度系数电压获取大小相等、方向相同的第一电流和第二电流；
    所述电压输出模块，配置为根据所述第一电流和第二电流获取第三电流，并根据所述第三电流获取输出电压，以基于所述输出电压获取所述环境温度。
  2. 根据权利要求1所述的温度检测电路，其中，
    所述负温度系数电压产生模块包括：第一MOS电流镜模块、与所述第一MOS电流镜模块连接的第二MOS电流镜模块、与所述第二MOS电流镜模块连接的第一负载和具有负温度系数的半导体器件；
    所述第一MOS电流镜模块，配置为使流入所述第二MOS电流镜模块的第一电流和第二电流的大小相等及方向相同；
    所述第二MOS电流镜模块，配置为根据所述第一电流和所述第二电流使所述第一负载上的第一电压与所述具有负温度系数的半导体器件上的负温度系数电压的大小相等；
    所述具有负温度系数的半导体器件，配置为根据环境温度的变化，生成负温度系数电压、以及与所述第二电流大小相等的负温度系数电流。
  3. 根据权利要求1所述的温度检测电路，其中，
    所述电压输出模块包括：与所述负温度系数电压产生模块连接的第三MOS电流镜模块、与所述第三MOS电流镜模块连接的第二负载；
    所述第三MOS电流镜模块，配置为根据所述第一电流和第二电流获取第三电流，并使所述第三电流作用于所述第二负载以获取输出电压。
  4. 根据权利要求3所述的温度检测电路，其中，所述电压输出模块还包括：与所述第三MOS电流镜模块连接的第三负载，所述第三电流流过所述第三负载生成第二电压，以根据所述第二电压获取输出电压。
  5. 根据权利要求4所述的温度检测电路，其中，所述电压输出模块还包括：与所述第三MOS电流镜模块连接的电容，配置为对所述第二电压进行滤波。
  6. 根据权利要求2所述的温度检测电路，其中，所述具有负温度系数的半导体器件为PNP型三极管或二极管。
  7. 根据权利要求2至4任一项所述的温度检测电路，其中，所述负载为电阻或开关电容。
  8. 根据权利要求7所述的温度检测电路，其中，
    所述第一MOS电流镜模块包括第一PMOS管、第二PMOS管；所述第二MOS电流镜模块包括第一NMOS管、第二NMOS管；所述第三MOS电流镜模块包括第三NMOS管；所述具有负温度系数的半导体器件为PNP型三极管；所述第一负载为第一电阻、第二负载为第二电阻、第三负载为第三电阻；
    第一PMOS管的源极、第二PMOS管的源极连接电源电压；第一PMOS管的栅极连接第二PMOS管的栅极且第一PMOS管的漏极连接第一PMOS管的栅极和第二PMOS管的栅极，以使第一PMOS管和第二PMOS管构成第一PMOS电流镜；第一PMOS管的漏极还连接第一NMOS管的漏极；第二PMOS管的漏极连接第二NMOS管的漏极；第一NMOS管的栅极连接第二NMOS管的栅极且第二NMOS管的漏极连接第一NMOS管的栅极和第二NMOS管的栅极，以使第一NMOS管和第二NMOS管构成第一NMOS电流镜；第一电阻的一端连接第一NMOS管的源极、另一端接地；PNP型三极管的发射极连接第二NMOS管的源极、基极和集电极接地；
    第三NMOS管的栅极连接所述第二PMOS管的漏极、第一NMOS管的栅极、第二NMOS管的栅极和漏极；第二电阻的一端连接第三NMOS管的源极、另一端接地；第三电阻的一端连接电源电压、另一端连接第三NMOS管的漏极。
  9. 根据权利要求8所述的温度检测电路，其中，所述第一电阻的阻值等于所述第二电阻的阻值；或，所述第二电阻的阻值为所述第一电阻的阻值的N倍，N为正数。
  10. 根据权利要求8或9所述的温度检测电路，其中，所述第三NMOS管的宽长比等于所述第一NMOS管的宽长比；或，所述第三NMOS管的宽长比为所述第一NMOS管的宽长比的N倍，N为正数。
  11. 一种温度检测方法，所述方法包括：
    负温度系数电压产生模块根据环境温度的变化，获取负温度系数电压，并根据所述负温度系数电压获取大小相等、方向相同的第一电流和第二电流；
    电压输出模块根据所述第一电流和第二电流获取第三电流，并根据所述第三电流获取输出电压，以基于所述输出电压获取所述环境温度。
  12. 根据权利要求11所述的温度检测方法，其中，
    所述负温度系数电压产生模块包括：第一MOS电流镜模块、与所述第一MOS电流镜模块连接的第二MOS电流镜模块、与所述第二MOS电流镜模块连接的第一负载和具有负温度系数的半导体器件；
    所述负温度系数电压产生模块根据环境温度的变化，获取负温度系数电压，并根据所述负温度系数电压获取大小相等、方向相同的第一电流和第二电流，包括：
    所述第一MOS电流镜模块使流入所述第二MOS电流镜模块的第一电流和第二电流的大小相等及方向相同；
    所述第二MOS电流镜模块根据所述第一电流和所述第二电流使所述第一负载上的第一电压与所述具有负温度系数的半导体器件上的负温度系数电压的大小相等；
    所述具有负温度系数的半导体器件根据环境温度的变化，生成负温度系数电压、以及与所述第二电流大小相等的负温度系数电流。
  13. 根据权利要求11所述的温度检测方法，其中，
    所述电压输出模块包括：与所述负温度系数电压产生模块连接的第三MOS电流镜模块、与所述第三MOS电流镜模块连接的第二负载；
    所述电压输出模块根据所述第一电流和第二电流获取第三电流，并根据所述第三电流获取输出电压，包括：
    所述第三MOS电流镜模块根据所述第一电流和第二电流获取第三电流，并使所述第三电流作用于所述第二负载以获取输出电压。
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