WO2018072439A1 - 一种测试信号产生方法及装置、计算机存储介质 - Google Patents

一种测试信号产生方法及装置、计算机存储介质 Download PDF

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WO2018072439A1
WO2018072439A1 PCT/CN2017/085226 CN2017085226W WO2018072439A1 WO 2018072439 A1 WO2018072439 A1 WO 2018072439A1 CN 2017085226 W CN2017085226 W CN 2017085226W WO 2018072439 A1 WO2018072439 A1 WO 2018072439A1
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data
read
cache
test
address
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French (fr)
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任域皞
杨丽宁
孙建伟
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Sanechips Technology Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/36—Data generation devices, e.g. data inverters

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  • the present invention relates to the field of system-on-chip (SoC) testing technology, and in particular, to a test signal generating method and apparatus, and a computer storage medium.
  • SoC system-on-chip
  • SoCs in engineering design simplifies design, increases system stability, and reduces product costs.
  • design cost and test cost increase day by day.
  • SoC's testability becomes a very important part of the design work. It provides strong support for shortening the product launch cycle and timely identifying and finding problems.
  • a unit that can generate a test signal that is, a Test Signal Generator (TSG)
  • TSG Test Signal Generator
  • the formula method generates a pseudo-random sequence through the configured initial value and the generator polynomial, and generates a test signal by processing the pseudo-random sequence.
  • the test signal generated by this method is very limited, the signal source can only be generated according to the established configuration, and the signals have correlation. Flexible test data cannot be generated based on user needs.
  • the storage method stores the user-defined test data in a hardware storage resource, and cyclically reads out the data therein to generate a test data source.
  • the length of the test signal is one.
  • at least two data frame long periods are required. This method requires a large amount of storage resources, and these storage resources cannot be reused by other functional units, which brings huge cost to the storage, area, and power consumption of the SOC.
  • an embodiment of the present invention provides a test signal generating method and apparatus, and a computer storage medium.
  • Corresponding test data is read from the memory and stored in the cache according to the first set of data information; according to the second set of data information, corresponding test data is read from the cache and the test data is read Make the output.
  • the configuring the first set of data information and the second set of data information for the test data in the register includes:
  • the first set of data information is configured in the register for the test data as follows: data first address, data length;
  • the second set of data information is configured for the test data in the register as follows: the frame header delay amount and the frame header period.
  • the configuring the first set of data information and the second set of data information for the test data in the register includes:
  • the first set of data information and the second set of data information are arranged in a register.
  • the reading the corresponding test data from the memory and storing the data in the cache includes:
  • test data is read from the memory and stored in the cache.
  • the reading, according to the second group of data information, reading corresponding test data from the cache and outputting the test data includes:
  • Synchronizing information is determined according to the frame header delay amount and the frame header period; based on the synchronization information, corresponding test data is read from the cache and the test data is output.
  • the corresponding test data is read from the memory and stored in the cache, including:
  • the current data read address is the data end address
  • the current data read address is set to the data first address of the register configuration as the next data read address; if the current data read address is not the data end address, the current data is read. The address is incremented by 1 as the next data read address;
  • the test data carried in the read response is stored in the cache.
  • the cache is composed of a ping-pong register
  • test data carried in the read response is stored in the cache, including:
  • test data carried in each read response is stored in the ping-pong register in a ping-pong operation.
  • a configuration unit configured to configure a first set of data information and a second set of data information for the test data in the register
  • a cache write control unit configured to read corresponding test data from the memory according to the first group of data information and store the data in the cache
  • a cache read control unit configured to read from the cache according to the second set of data information Corresponding test data is taken and outputted.
  • the configuration unit is further configured to configure, in the register, the first group of data information for the test data: a data first address and a data length; and configuring, in the register, the second group of data information for the test data: a frame Head delay and frame header period.
  • the configuration unit is further configured to parse the bus information to obtain the first group of data information and the second group of data information; and configure the first group of data information and the second group of data information In the register.
  • the cache write control unit is further configured to determine whether the cache space is full; when the cache space is not full, the test data is read from the memory and stored in the cache.
  • the cache read control unit is further configured to: determine synchronization information according to the frame header delay amount and the frame header period; and read the corresponding test from the cache based on the synchronization information. The data is output and the test data is output.
  • the cache write control unit is further configured to set a data read address as the data first address configured in the register, to detect whether the cache space is full, and when the cache space is not full, Sending a read request for the current data read address to the memory; if the current data read address is the data end address, setting the current data read address to the data first address of the register configuration as the next data read address; if the current data If the read address is not the data end address, the current data read address is incremented by 1 as the next data read address; detecting whether the memory returns a read response for the current data read address, when the memory returns a read address for the current data. When the response is read, the test data carried in the read response is stored in the cache.
  • the cache is composed of a ping-pong register
  • the cache write control unit is further configured to store the test data carried in each read response into the ping-pong register in a ping-pong operation.
  • the computer storage medium provided by the embodiment of the present invention stores a computer program configured to execute the above test signal generating method.
  • the first group of data information and the second group of data information are configured for the test data in the register; according to the first group of data information, the corresponding test data is read from the memory and stored in the cache. And reading corresponding test data from the cache and outputting the test data according to the second set of data information.
  • the test data is stored in the memory outside the TSG, and the user can flexibly configure the test data, and the flexibility of the test signal is generated for the TSG and the storage resource of the TSG.
  • the interactive test signal generation method not only saves hardware storage resources, but also flexibly configures test data according to user requirements.
  • FIG. 1 is a schematic flow chart of a method for generating a test signal according to an embodiment of the present invention
  • FIG. 2 is a block diagram of a SoC test data generation based on software and hardware interaction according to an embodiment of the present invention
  • FIG. 3 is a schematic flowchart of writing data in a memory to a cache according to an embodiment of the present invention
  • FIG. 4 is a first schematic structural diagram of a test signal generating apparatus according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram 2 of a test signal generating apparatus according to an embodiment of the present invention.
  • the main object of embodiments of the present invention is to provide a method and apparatus for generating a test signal in a SOC system design.
  • the method of the embodiment of the invention enables the hardware module to read the test data of the external storage module (that is, the memory) in real time and efficiently by means of software and hardware interaction, thereby saving hardware storage resources and allowing the user to flexibly configure the test data, including Data power, waveform, length, etc. Solved the flexible configuration and consumption of hardware storage resources of traditional TSG test data in SOC design The problem.
  • FIG. 1 is a schematic flowchart of a method for generating a test signal according to an embodiment of the present invention. As shown in FIG. 1 , a test signal generating method in this example is applied to a test signal generating device, where the test signal generating method includes the following steps:
  • Step 101 Configure a first set of data information and a second set of data information for the test data in the register.
  • the test signal generating device opens the register, the buffer space, and the read/write control unit of the buffer space.
  • the memory referred to in the embodiment of the present invention is located outside the test signal generating device, and the user can flexibly configure the test data in the memory through software, including: data power, waveform, length, and the like.
  • the test signal generating device only needs to read and output the test data from the memory according to the configuration information.
  • the configuring the first set of data information and the second set of data information for the test data in the register includes:
  • the first set of data information is configured in the register for the test data as follows: data first address, data length;
  • the second set of data information is configured for the test data in the register as follows: the frame header delay amount and the frame header period.
  • the configuring the first set of data information and the second set of data information for the test data in the register includes:
  • the first set of data information and the second set of data information are arranged in a register.
  • Step 102 Read corresponding test data from the memory according to the first group of data information and store the data in the cache. According to the second group of data information, read corresponding test data from the cache and The test data is output.
  • the corresponding test data is read from the memory and stored in the cache.
  • test data is read from the memory and stored in the cache.
  • the reading, according to the second group of data information, reading corresponding test data from the cache and outputting the test data includes:
  • Synchronizing information is determined according to the frame header delay amount and the frame header period; based on the synchronization information, corresponding test data is read from the cache and the test data is output.
  • the corresponding test data is read from the memory and stored in the cache, including:
  • the current data read address is the data end address
  • the current data read address is set to the data first address of the register configuration as the next data read address; if the current data read address is not the data end address, the current data is read. The address is incremented by 1 as the next data read address;
  • the test data carried in the read response is stored in the cache.
  • the cache is composed of a ping-pong register
  • test data carried in the read response is stored in the cache, including:
  • test data carried in each read response is stored in the ping-pong register in a ping-pong operation.
  • test signal generation method of the embodiment of the present invention is further described in detail below in conjunction with the TSG application scenario.
  • FIG. 2 is a SoC test data product based on software and hardware interaction according to an embodiment of the present invention.
  • the block diagram is shown in Figure 2.
  • the right side of the bus is the TSG hardware architecture, and the right side of the bus is the external memory of the TSG hardware architecture and the corresponding software.
  • the embodiment of the invention improves the TSG hardware architecture as follows:
  • the open buffer space and the cache space read and write control unit for writing test data read from the memory to the cache and reading from the cache.
  • a register file that describes test data information (ie, the first set of data information and the second set of data information), the first set of data information including the data first address (Addr), the data length (len)
  • the second set of data information includes: frame header delay amount (fr_dly), frame header period (fr_cyc), and the TSG configuration register is set by software.
  • TSG hardware architecture Open the synchronous control interface to receive the data frame header in the register file to synchronize the TSG to start outputting test data to the subsequent hardware structure. If there is no external header driving information, the unit that generates the header can be opened in the TSG structure.
  • test signal generating method of the embodiment of the present invention includes the following steps:
  • Step 1 The software writes the test data configured by the user to the memory space through the bus;
  • Step 2 The software configures the register to the TSG through the bus, and enables the TSG;
  • Step 3 The TSG reads the test data from the memory as a test data source and outputs it to the subsequent module.
  • Step 1 of the above solution is specifically stated as:
  • Step 1.1 The user configures the register and the register address through the software
  • Step 1.2 The software writes the register to the hardware by address through the bus;
  • Step 1.3 The hardware parses the configuration information in the register through the register address.
  • Step 3 of the above scenario contains two parallel operational processes:
  • Process 3.1 After the TSG is enabled, it is determined whether the cache is full. When not full, the test data is read from the memory space and stored in the cache;
  • test data is read from the cache, according to The timing of the downstream module requires output.
  • the process 3.1 and the process 3.2 in the step 3 are operated simultaneously.
  • the data write cache of the read memory space specifically includes:
  • Step 3.1.1 The data read address is set to the data first address of the register configuration
  • Step 3.1.2 Check if the cache is full. If it is not full, go to step 3.1.3, otherwise go to step 3.1.2.
  • Step 3.1.3 Determine whether the current data read address is the data end address. If not, go to step 3.1.4. If yes, go to step 3.1.5.
  • Step 3.1.4 Initiate a read request for the current data read address to the memory, and +1 the current data address.
  • Step 3.1.5 Initiate a read request for the current data read address to the memory, and change the current data read address to the data first address of the register configuration.
  • Step 3.1.6 Check if the memory returns test data. If not, go to step 3.1.6. Otherwise, go to step 3.1.7.
  • Step 3.1.7 Write the test data to the cache space and perform step 3.1.2.
  • the user can flexibly configure the test data, including the digital waveform of the test data and the data length.
  • the solution supports users to flexibly configure the data source. Therefore, the data verification supports multiple verification methods, which improves the flexibility of data verification.
  • the method for generating test signals according to the present invention is not limited to SOC design, and can be widely applied in other communication systems and digital IC designs.
  • FIG. 4 is a schematic structural diagram 1 of a test signal generating apparatus according to an embodiment of the present invention, as shown in FIG. 4 As shown, the device includes:
  • the configuration unit 41 is configured to configure, in the register, the first set of data information and the second set of data information for the test data;
  • the cache write control unit 42 is configured to read corresponding test data from the memory according to the first group of data information and store the data in the cache;
  • the cache read control unit 43 is configured to read corresponding test data from the cache and output the test data according to the second set of data information.
  • the configuration unit 41 is further configured to configure, in the register, the first group of data information for the test data: a data first address and a data length; and configuring, in the register, the following second group of data information for the test data: Frame header delay and frame header period.
  • the configuration unit 41 is further configured to parse the bus information to obtain a first group of data information and a second group of data information; and the first group of data information and the second group of data information Configured in a register.
  • the cache write control unit 42 is further configured to determine whether the cache space is full; when the cache space is not full, the test data is read from the memory and stored in the cache.
  • the cache read control unit 43 is further configured to determine synchronization information according to the frame header delay amount and the frame header period; and read corresponding information from the cache based on the synchronization information. Test the data and output the test data.
  • the cache write control unit 42 is further configured to set a data read address as the data first address configured in the register; to detect whether the cache space is full; when the cache space is not full Sending a read request for the current data read address to the memory; if the current data read address is the data end address, setting the current data read address to the data first address of the register configuration as the next data read address; The data read address is not the data end address, then the current data read address is incremented by 1 as the next data read address; Whether the memory returns a read response for the current data read address, and when the memory returns a read response to the current data read address, the test data carried by the read response is stored in the cache.
  • the cache is composed of a ping-pong register
  • the cache write control unit 42 is further configured to store the test data carried in each read response into the ping-pong register in a ping-pong operation.
  • test signal generating apparatus shown in FIG. 4
  • the functions of the units in the test signal generating apparatus shown in FIG. 4 can be realized by a program running on the processor, or can be realized by a specific logic circuit.
  • each unit in the test signal generating device may be performed by a central processing unit (CPU) located in the test signal generating device, or a microprocessor (MPU, Micro Processor Unit). ), or a digital signal processor (DSP, Digital Signal Processor), or Field Programmable Gate Array (FPGA).
  • CPU central processing unit
  • MPU Micro Processor Unit
  • DSP Digital Signal Processor
  • FPGA Field Programmable Gate Array
  • FIG. 5 is a schematic structural diagram of a test signal generating apparatus according to an embodiment of the present invention.
  • the apparatus includes: an abb module, a wr_ctrl module, an rd_ctrl module, and a cache module composed of a ping-pong register.
  • the test signal generating method of the embodiment of the present invention includes the following steps:
  • Step 1 The software writes the test data to the memory.
  • Step 2 The apb module configures the TSG by parsing the bus information.
  • the configured registers include the data first address, the data length, the frame header delay amount, and the frame header period.
  • Step 3 The TSG reads the test data from the memory and outputs it to the subsequent hardware module.
  • step 3 contains two parallel operations:
  • Process 3.1 After the TSG is enabled, it is determined whether the cache is full, and if not full, the test data is read from the memory space and stored in the cache;
  • test data is read from the cache.
  • the process 3.1 and the process 3.2 in the step 3 are operated simultaneously.
  • the data write cache of the read memory space specifically includes:
  • Step 3.1.1 The data read address is set to the data first address of the register configuration
  • Step 3.1.2 Check if the Ping_reg register is full. If it is not full, go to step 3.1.3. Otherwise, go to step 3.1.7.
  • Step 3.1.3 Initiate a read request for the current data read address to the memory.
  • Step 3.1.4 If the current data read address is the data end address, the data degree address is changed to the data first address of the register configuration, otherwise the data read address is +1.
  • Step 3.1.5 Check if the memory returns test data. If not, go to step 3.1.5, otherwise go to step 3.1.6.
  • Step 3.1.6 Write the test data to the Ping_reg register and go to step 3.1.7.
  • Step 3.1.7 Check if the Pang_reg register is full. If it is not full, go to step 3.1.8. Otherwise, go to step 3.1.7.
  • Step 3.1.8 Initiate a read request for the current data read address to the memory.
  • Step 3.1.9 If the current data read address is the data end address, the data read address is changed to the data first address of the register configuration, otherwise the data read address is +1.
  • Step 3.1.10 Check if the memory returns test data. If not, go to step 3.1.10, otherwise go to step 3.1.2.
  • the output of the data of the read buffer space to the subsequent module specifically includes:
  • Step 3.2.1 Detect whether there is a data frame header (as synchronization information). If the synchronization information arrives, go to step 3.2.2, otherwise go to step 3.2.1.
  • Step 3.2.2 Determine if Ping_reg is empty. If it is not empty, read the data in the Ping_reg register and output it to the latter module. Otherwise, go to step 3.2.3.
  • Step 3.2.3 Determine if Pang_reg is empty. If it is not empty, read the data in the Pang_reg register and output it to the subsequent module. Otherwise, go to step 3.2.2.
  • the above solution of the embodiment of the present invention provides a method and device for generating test data in the SoC system test.
  • This method based on hardware and software interaction effectively saves hardware storage resources and allows users to flexibly configure test data.
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device. Instructions are provided for implementation The steps of a function specified in a block or blocks of a flow or a flow and/or a block diagram of a flow chart.
  • the embodiment of the present invention further provides a computer storage medium, wherein a computer program is configured, and the computer program is configured to execute the test signal generating method of the embodiment of the present invention.
  • the first group of data information and the second group of data information are configured for the test data in the register; according to the first group of data information, the corresponding test data is read from the memory and stored in the cache. And reading corresponding test data from the cache and outputting the test data according to the second set of data information.
  • the test data is stored in the memory outside the TSG, and the user can flexibly configure the test data, and the flexibility of the test signal is generated for the TSG and the storage resource of the TSG.
  • the interactive test signal generation method not only saves hardware storage resources, but also flexibly configures test data according to user requirements.

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Abstract

本发明公开了一种测试信号产生方法及装置、计算机存储介质，包括：在寄存器中为测试数据配置第一组数据信息和第二组数据信息；依据所述第一组数据信息，从内存中读取相应的测试数据并存入缓存中；依据所述第二组数据信息，从所述缓存中读取相应的测试数据并对所述测试数据进行输出。

Description

一种测试信号产生方法及装置、计算机存储介质
相关申请的交叉引用
本申请基于申请号为201610920467.7、申请日为2016年10月21日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本发明涉及系统芯片(SoC，System on Chip)测试技术领域，尤其涉及一种测试信号产生方法及装置、计算机存储介质。
背景技术
在工程设计中引入SoC可以简化设计，增加系统稳定性，降低产品成本。然而随着SoC规模增大，设计成本和测试成本与日俱增，SoC的可测试性成为设计工作中非常重要的内容，它为缩短产品上市周期，及时定位发现问题提供有力支撑。为了满足SoC的可测试性，必须在SoC原型设计中增加可以产生测试信号的单元，即测试信号产生模块(TSG，Test Signal Generator)。
传统的TSG通过两种方式产生测试信号，公式法或存储法。其中：
公式法通过配置的初始值和生成多项式产生伪随机序列，通过对伪随机序列的处理来产生测试信号。这种方法产生的测试信号十分有限，信号源只能按照既定的配置产生，信号之间具有相关性。不能根据用户需求产生灵活的测试数据。
存储法即将用户定义的测试数据存储在硬件存贮资源中，循环读出其中的数据产生测试数据源。然而为保证测试的完整性，测试信号的长度一 般至少需要两个数据帧长的周期，这种方法需要耗费大量的存储资源，这些存储资源也不能被其他功能单元复用，对SOC的存储，面积，功耗等带来巨大成本。
发明内容
为解决上述技术问题，本发明实施例提供了一种测试信号产生方法及装置、计算机存储介质。
本发明实施例提供的测试信号产生方法，包括：
在寄存器中为测试数据配置第一组数据信息和第二组数据信息；
依据所述第一组数据信息，从内存中读取相应的测试数据并存入缓存中；依据所述第二组数据信息，从所述缓存中读取相应的测试数据并对所述测试数据进行输出。
本发明实施例中，所述在寄存器中为测试数据配置第一组数据信息和第二组数据信息，包括：
在寄存器中为测试数据配置如下第一组数据信息：数据首地址、数据长度；
在寄存器中为测试数据配置如下第二组数据信息：帧头延时量和帧头周期。
本发明实施例中，所述在寄存器中为测试数据配置第一组数据信息和第二组数据信息，包括：
对总线信息进行解析，得到第一组数据信息和第二组数据信息；
将所述第一组数据信息和所述第二组数据信息配置在寄存器中。
本发明实施例中，所述从内存中读取相应的测试数据并存入缓存中，包括：
判断缓存空间是否已存满；
当所述缓存空间未存满时，从内存中读取测试数据并存入缓存中。
本发明实施例中，所述依据所述第二组数据信息，从所述缓存中读取相应的测试数据并对所述测试数据进行输出，包括：
依据所述帧头延时量和帧头周期时，确定同步信息；基于所述同步信息，从所述缓存中读取相应的测试数据并对所述测试数据进行输出。
本发明实施例中，所述依据所述第一组数据信息，从内存中读取相应的测试数据并存入缓存中，包括：
将数据读地址设置为寄存器中配置的所述数据首地址；
检测缓存空间是否已存满；
当所述缓存空间未存满时，向内存发送针对当前数据读地址的读请求；
如果当前数据读地址是数据末尾地址，则将当前数据读地址设置为寄存器配置的所述数据首地址，作为下一次的数据读地址；如果当前数据读地址不是数据末尾地址，则将当前数据读地址加1后作为下一次的数据读地址；
检测所述内存是否返回针对当前数据读地址的读响应，当所述内存返回针对当前数据读地址的读响应时，将读响应携带的测试数据存入缓存中。
本发明实施例中，所述缓存由乒乓寄存器组成；
相应地，所述将读响应携带的测试数据存入缓存中，包括：
采用乒乓操作的方式将每次读响应携带的测试数据存入所述乒乓寄存器中。
本发明实施例提供的测试信号产生装置，包括：
配置单元，配置为在寄存器中为测试数据配置第一组数据信息和第二组数据信息；
缓存写控制单元，配置为依据所述第一组数据信息，从内存中读取相应的测试数据并存入缓存中；
缓存读控制单元，配置为依据所述第二组数据信息，从所述缓存中读 取相应的测试数据并对所述测试数据进行输出。
本发明实施例中，所述配置单元，还配置为在寄存器中为测试数据配置如下第一组数据信息：数据首地址、数据长度；在寄存器中为测试数据配置如下第二组数据信息：帧头延时量和帧头周期。
本发明实施例中，所述配置单元，还配置为对总线信息进行解析，得到第一组数据信息和第二组数据信息；将所述第一组数据信息和所述第二组数据信息配置在寄存器中。
本发明实施例中，所述缓存写控制单元，还配置为判断缓存空间是否已存满；当所述缓存空间未存满时，从内存中读取测试数据并存入缓存中。
本发明实施例中，所述缓存读控制单元，还配置为依据所述帧头延时量和帧头周期时，确定同步信息；基于所述同步信息，从所述缓存中读取相应的测试数据并对所述测试数据进行输出。
本发明实施例中，所述缓存写控制单元，还配置为将数据读地址设置为寄存器中配置的所述数据首地址；检测缓存空间是否已存满；当所述缓存空间未存满时，向内存发送针对当前数据读地址的读请求；如果当前数据读地址是数据末尾地址，则将当前数据读地址设置为寄存器配置的所述数据首地址，作为下一次的数据读地址；如果当前数据读地址不是数据末尾地址，则将当前数据读地址加1后作为下一次的数据读地址；检测所述内存是否返回针对当前数据读地址的读响应，当所述内存返回针对当前数据读地址的读响应时，将读响应携带的测试数据存入缓存中。
本发明实施例中，所述缓存由乒乓寄存器组成；
相应地，所述缓存写控制单元，还配置为采用乒乓操作的方式将每次读响应携带的测试数据存入所述乒乓寄存器中。
本发明实施例提供的计算机存储介质存储有计算机程序，该计算机程序配置为执行上述测试信号产生方法。
本发明实施例的技术方案中，在寄存器中为测试数据配置第一组数据信息和第二组数据信息；依据所述第一组数据信息，从内存中读取相应的测试数据并存入缓存中；依据所述第二组数据信息，从所述缓存中读取相应的测试数据并对所述测试数据进行输出。上述方案中，测试数据存储在TSG外部的内存中，用户可以对测试数据进行灵活配置，针对TSG产生测试信号的灵活性和TSG的存储资源这一问题，本发明实施例所提出的基于软硬件交互的测试信号产生方法既节省了硬件存储资源，也可以根据用户需求灵活配置测试数据。
附图说明
附图以示例而非限制的方式大体示出了本文中所讨论的各个实施例。
图1为本发明实施例的测试信号产生方法的流程示意图；
图2为本发明实施例的基于软硬件交互的SoC测试数据产生框图；
图3为本发明实施例的将内存中的数据写入缓存的流程示意图；
图4为本发明实施例的测试信号产生装置的结构组成示意图一；
图5为本发明实施例的测试信号产生装置的结构示意图二。
具体实施方式
为了能够更加详尽地了解本发明实施例的特点与技术内容，下面结合附图对本发明实施例的实现进行详细阐述，所附附图仅供参考说明之用，并非用来限定本发明实施例。
本发明实施例的主要目的是提供一种SOC系统设计中产生测试信号的方法及装置。本发明实施例的方法通过软硬件交互的方式，使硬件模块能够实时高效的读取外部存储模块(也即内存)的测试数据，节约了硬件存储资源的同时允许用户可以灵活配置测试数据，包括数据功率、波形、长度等。解决了SOC设计中传统TSG测试数据灵活配置和消耗硬件存储资源 的问题。
图1为本发明实施例的测试信号产生方法的流程示意图，如图1所示，本示例中的测试信号产生方法应用于测试信号产生装置中，所述测试信号产生方法包括以下步骤：
步骤101：在寄存器中为测试数据配置第一组数据信息和第二组数据信息。
本发明实施例中，测试信号产生装置开放寄存器、缓存空间、以及所述缓存空间的读写控制单元。此外，本发明实施例所指的内存位于测试信号产生装置以外，用户可以通过软件的方式在内存中灵活配置测试数据，包括：数据功率、波形、长度等。测试信号产生装置只需要从内存中依据配置信息进行测试数据的读取与输出即可。
本发明实施例中，所述在寄存器中为测试数据配置第一组数据信息和第二组数据信息，包括：
在寄存器中为测试数据配置如下第一组数据信息：数据首地址、数据长度；
在寄存器中为测试数据配置如下第二组数据信息：帧头延时量和帧头周期。
本发明实施例中，所述在寄存器中为测试数据配置第一组数据信息和第二组数据信息，包括：
对总线信息进行解析，得到第一组数据信息和第二组数据信息；
将所述第一组数据信息和所述第二组数据信息配置在寄存器中。
步骤102：依据所述第一组数据信息，从内存中读取相应的测试数据并存入缓存中；依据所述第二组数据信息，从所述缓存中读取相应的测试数据并对所述测试数据进行输出。
本发明实施例中，所述从内存中读取相应的测试数据并存入缓存中， 包括：
判断缓存空间是否已存满；
当所述缓存空间未存满时，从内存中读取测试数据并存入缓存中。
本发明实施例中，所述依据所述第二组数据信息，从所述缓存中读取相应的测试数据并对所述测试数据进行输出，包括：
依据所述帧头延时量和帧头周期时，确定同步信息；基于所述同步信息，从所述缓存中读取相应的测试数据并对所述测试数据进行输出。
本发明实施例中，所述依据所述第一组数据信息，从内存中读取相应的测试数据并存入缓存中，包括：
将数据读地址设置为寄存器中配置的所述数据首地址；
检测缓存空间是否已存满；
当所述缓存空间未存满时，向内存发送针对当前数据读地址的读请求；
如果当前数据读地址是数据末尾地址，则将当前数据读地址设置为寄存器配置的所述数据首地址，作为下一次的数据读地址；如果当前数据读地址不是数据末尾地址，则将当前数据读地址加1后作为下一次的数据读地址；
检测所述内存是否返回针对当前数据读地址的读响应，当所述内存返回针对当前数据读地址的读响应时，将读响应携带的测试数据存入缓存中。
上述方案中，所述缓存由乒乓寄存器组成；
相应地，所述将读响应携带的测试数据存入缓存中，包括：
采用乒乓操作的方式将每次读响应携带的测试数据存入所述乒乓寄存器中。
下面结合TSG应用场景对本发明实施例的测试信号产生方法做进一步详细描述。
参照图2，图2为本发明实施例的基于软硬件交互的SoC测试数据产 生框图，如图2所示，总线右侧为TSG硬件架构，总线右侧为TSG硬件架构的外部内存以及相应的软件。本发明实施例对TSG硬件架构作了如下改进：
1)在TSG硬件架构中：开放缓存空间和缓存空间的读写控制单元，用以将从内存中读取的测试数据写入缓存和从缓存中读出。
2)在TSG硬件架构中：开放描述测试数据信息(也即第一组数据信息和第二组数据信息)的寄存器堆，第一组数据信息包括数据首地址(Addr)、数据长度(len)；第二组数据信息包括：帧头延时量(fr_dly)、帧头周期(fr_cyc)，通过软件为TSG配置寄存器。
3)在TSG硬件架构中：开放同步控制接口，以接收寄存器堆内的数据帧头来同步TSG开始向后级硬件结构输出测试数据。如果没有外部的帧头驱动信息，可以在TSG结构中开放产生帧头的单元。
基于图2所示的框架结构，本发明实施例的测试信号产生方法包括以下步骤：
步骤1：软件通过总线将用户配置的测试数据写入内存空间；
步骤2：软件通过总线给TSG配置寄存器，并使能TSG；
步骤3：TSG从内存中读取测试数据作为测试数据源输出给后级模块。
上述方案中步骤1具体表述为：
步骤1.1：用户通过软件配置寄存器及寄存器地址；
步骤1.2：软件通过总线将寄存器按地址写入硬件；
步骤1.3：硬件通过寄存器地址解析寄存器中的配置信息。
上述方案中步骤3包含两个并行的操作流程：
流程3.1：TSG使能后判断缓存是否已存满，未存满则从内存空间读取测试数据，存入缓存；
流程3.2：TSG检测到同步驱动信息后，从缓存中读取测试数据，按照 后级模块的时序要求输出。
上述方案中，步骤3中的流程3.1和流程3.2是同时操作的。参照图3，步骤3所述的流程3.1中，读取内存空间的数据写入缓存具体包括：
步骤3.1.1：数据读地址置为寄存器配置的数据首地址；
步骤3.1.2：检测缓存是否存满，若未存满，执行步骤3.1.3，否则执行步骤3.1.2。
步骤3.1.3：判断当前数据读地址是否为数据末尾地址，若否，则执行步骤3.1.4，若是，则执行步骤3.1.5。
步骤3.1.4：向内存发起当前数据读地址的读请求，将当前数据度地址+1。
步骤3.1.5：向内存发起当前数据读地址的读请求，将当前数据读地址变更为寄存器配置的数据首地址。
步骤3.1.6：检测内存是否返回测试数据，若未返回，执行步骤3.1.6，否则执行步骤3.1.7。
步骤3.1.7：将测试数据写入缓存空间，执行步骤3.1.2。
从上述方案可以看出，采用本发明实施例的测试信号产生方法，与传统的SOC测试信号产生模块相比，至少具有以下有益效果：
1、用户可以灵活配置测试数据，包括测试数据的数字波形，数据长度。
2、相比传统公式法生成数据的TSG，本方案支持用户灵活配置数据源，因此在数据校验是支持多种校验方式，提高了数据校验的灵活性。
3、相比传统存储法生成数据的TSG，保证数据灵活可配的同事，节省了相应数据源大小的硬件存储空间，节约了SOC设计资源。
4、本发明所述的产生测试信号的方法，不局限于SOC设计，在其他通信系统，数字IC设计中可广泛应用。
图4为本发明实施例的测试信号产生装置的结构组成示意图一，如图4 所示，所述装置包括：
配置单元41，配置为在寄存器中为测试数据配置第一组数据信息和第二组数据信息；
缓存写控制单元42，配置为依据所述第一组数据信息，从内存中读取相应的测试数据并存入缓存中；
缓存读控制单元43，配置为依据所述第二组数据信息，从所述缓存中读取相应的测试数据并对所述测试数据进行输出。
本发明实施例中，所述配置单元41，还配置为在寄存器中为测试数据配置如下第一组数据信息：数据首地址、数据长度；在寄存器中为测试数据配置如下第二组数据信息：帧头延时量和帧头周期。
本发明实施例中，所述配置单元41，还配置为对总线信息进行解析，得到第一组数据信息和第二组数据信息；将所述第一组数据信息和所述第二组数据信息配置在寄存器中。
本发明实施例中，所述缓存写控制单元42，还配置为判断缓存空间是否已存满；当所述缓存空间未存满时，从内存中读取测试数据并存入缓存中。
本发明实施例中，所述缓存读控制单元43，还配置为依据所述帧头延时量和帧头周期时，确定同步信息；基于所述同步信息，从所述缓存中读取相应的测试数据并对所述测试数据进行输出。
本发明实施例中，所述缓存写控制单元42，还配置为将数据读地址设置为寄存器中配置的所述数据首地址；检测缓存空间是否已存满；当所述缓存空间未存满时，向内存发送针对当前数据读地址的读请求；如果当前数据读地址是数据末尾地址，则将当前数据读地址设置为寄存器配置的所述数据首地址，作为下一次的数据读地址；如果当前数据读地址不是数据末尾地址，则将当前数据读地址加1后作为下一次的数据读地址；检测所 述内存是否返回针对当前数据读地址的读响应，当所述内存返回针对当前数据读地址的读响应时，将读响应携带的测试数据存入缓存中。
本发明实施例中，所述缓存由乒乓寄存器组成；
相应地，所述缓存写控制单元42，还配置为采用乒乓操作的方式将每次读响应携带的测试数据存入所述乒乓寄存器中。
本领域技术人员应当理解，图4所示的测试信号产生装置中的各单元的实现功能可参照前述测试信号产生方法的相关描述而理解。图4所示的测试信号产生装置中的各单元的功能可通过运行于处理器上的程序而实现，也可通过具体的逻辑电路而实现。
在实际应用中，所述测试信号产生装置中的各个单元所实现的功能，均可由位于测试信号产生装置中的中央处理器(CPU，Central Processing Unit)、或微处理器(MPU，Micro Processor Unit)、或数字信号处理器(DSP，Digital Signal Processor)、或现场可编程门阵列(FPGA，Field Programmable Gate Array)等实现。
图5为本发明实施例的测试信号产生装置的结构示意图二，如图5所示，所述装置包括：apb模块，wr_ctrl模块，rd_ctrl模块和由乒乓寄存器组成的缓存模块。基于此结构，本发明实施例的测试信号产生方法包括以下步骤：
步骤1：软件将测试数据写入内存。
步骤2：apb模块通过解析总线信息对TSG进行寄存器配置，配置的寄存器包括数据首地址、数据长度、帧头延时量和帧头周期。
步骤3：TSG从内存中读取测试数据输出给后级硬件模块。
其中，步骤3包含两个并行操作流程：
流程3.1：TSG使能后判断缓存是否存满，未存满则从内存空间读取测试数据，存入缓存；
流程3.2：TSG检测到同步信息后，从缓存中读取测试数据。
上述方案中，步骤3中的流程3.1和流程3.2是同时操作的。步骤3所述的流程3.1中，读取内存空间的数据写入缓存具体包括：
步骤3.1.1：数据读地址置为寄存器配置的数据首地址；
步骤3.1.2：检测Ping_reg寄存器是否存满，若未存满，执行步骤3.1.3，否则执行步骤3.1.7。
步骤3.1.3：向内存发起当前数据读地址的读请求。
步骤3.1.4：若当前数据读地址是数据末尾地址，则将数据度地址变更为寄存器配置的数据首地址，否则将数据读地址+1。
步骤3.1.5：检测内存是否返回测试数据，若未返回，执行步骤3.1.5，否则执行步骤3.1.6。
步骤3.1.6：将测试数据写入Ping_reg寄存器，执行步骤3.1.7。
步骤3.1.7：检测Pang_reg寄存器是否存满，若未存满，执行步骤3.1.8，否则执行步骤3.1.7。
步骤3.1.8：向内存发起当前数据读地址的读请求。
步骤3.1.9：若当前数据读地址是数据末尾地址，则将数据读地址变更为寄存器配置的数据首地址，否则将数据读地址+1。
步骤3.1.10：检测内存是否返回测试数据，若未返回，执行步骤3.1.10，否则执行步骤3.1.2。
上述方案中步骤3所述的流程3.2，读取缓存空间的数据输出给后级模块具体包括：
步骤3.2.1：检测是否有数据帧头(作为同步信息)到来，如果同步信息到来，执行步骤3.2.2，否则执行步骤3.2.1。
步骤3.2.2：判断Ping_reg是否为空，如果非空，读取Ping_reg寄存器中的数据输出给后模块，否则执行步骤3.2.3。
步骤3.2.3：判断Pang_reg是否为空，如果非空，读取Pang_reg寄存器中的数据输出给后级模块，否则执行步骤3.2.2。
本发明实施例的上述方案，在SoC系统测试中提供了一种产生测试数据的方法及装置。这种基于软硬件交互的方法有效节约了硬件存储资源，同时可以允许用户对测试数据灵活配置。
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用硬件实施例、软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现 在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
相应地，本发明实施例还提供一种计算机存储介质，其中存储有计算机程序，该计算机程序配置为执行本发明实施例的测试信号产生方法。
以上所述，仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。
工业实用性
本发明实施例的技术方案，在寄存器中为测试数据配置第一组数据信息和第二组数据信息；依据所述第一组数据信息，从内存中读取相应的测试数据并存入缓存中；依据所述第二组数据信息，从所述缓存中读取相应的测试数据并对所述测试数据进行输出。上述方案中，测试数据存储在TSG外部的内存中，用户可以对测试数据进行灵活配置，针对TSG产生测试信号的灵活性和TSG的存储资源这一问题，本发明实施例所提出的基于软硬件交互的测试信号产生方法既节省了硬件存储资源，也可以根据用户需求灵活配置测试数据。

Claims (15)

  1. 一种测试信号产生方法，所述方法包括：
    在寄存器中为测试数据配置第一组数据信息和第二组数据信息；
    依据所述第一组数据信息，从内存中读取相应的测试数据并存入缓存中；依据所述第二组数据信息，从所述缓存中读取相应的测试数据并对所述测试数据进行输出。
  2. 根据权利要求1所述的测试信号产生方法，其中，所述在寄存器中为测试数据配置第一组数据信息和第二组数据信息，包括：
    在寄存器中为测试数据配置如下第一组数据信息：数据首地址、数据长度；
    在寄存器中为测试数据配置如下第二组数据信息：帧头延时量和帧头周期。
  3. 根据权利要求1所述的测试信号产生方法，其中，所述在寄存器中为测试数据配置第一组数据信息和第二组数据信息，包括：
    对总线信息进行解析，得到第一组数据信息和第二组数据信息；
    将所述第一组数据信息和所述第二组数据信息配置在寄存器中。
  4. 根据权利要求1所述的测试信号产生方法，其中，所述从内存中读取相应的测试数据并存入缓存中，包括：
    判断缓存空间是否已存满；
    当所述缓存空间未存满时，从内存中读取测试数据并存入缓存中。
  5. 根据权利要求2所述的测试信号产生方法，其中，所述依据所述第二组数据信息，从所述缓存中读取相应的测试数据并对所述测试数据进行输出，包括：
    依据所述帧头延时量和帧头周期时，确定同步信息；基于所述同步信息，从所述缓存中读取相应的测试数据并对所述测试数据进行输出。
  6. 根据权利要求2所述的测试信号产生方法，其中，所述依据所述第一组数据信息，从内存中读取相应的测试数据并存入缓存中，包括：
    将数据读地址设置为寄存器中配置的所述数据首地址；
    检测缓存空间是否已存满；
    当所述缓存空间未存满时，向内存发送针对当前数据读地址的读请求；
    如果当前数据读地址是数据末尾地址，则将当前数据读地址设置为寄存器配置的所述数据首地址，作为下一次的数据读地址；如果当前数据读地址不是数据末尾地址，则将当前数据读地址加1后作为下一次的数据读地址；
    检测所述内存是否返回针对当前数据读地址的读响应，当所述内存返回针对当前数据读地址的读响应时，将读响应携带的测试数据存入缓存中。
  7. 根据权利要求6所述的测试信号产生方法，其中，所述缓存由乒乓寄存器组成；
    相应地，所述将读响应携带的测试数据存入缓存中，包括：
    采用乒乓操作的方式将每次读响应携带的测试数据存入所述乒乓寄存器中。
  8. 一种测试信号产生装置，所述装置包括：
    配置单元，配置为在寄存器中为测试数据配置第一组数据信息和第二组数据信息；
    缓存写控制单元，配置为依据所述第一组数据信息，从内存中读取相应的测试数据并存入缓存中；
    缓存读控制单元，配置为依据所述第二组数据信息，从所述缓存中读取相应的测试数据并对所述测试数据进行输出。
  9. 根据权利要求8所述的测试信号产生装置，其中，所述配置单元，还配置为在寄存器中为测试数据配置如下第一组数据信息：数据首地址、数据长度；在寄存器中为测试数据配置如下第二组数据信息：帧头延时量和帧头周期。
  10. 根据权利要求8所述的测试信号产生装置，其中，所述配置单元，还配置为对总线信息进行解析，得到第一组数据信息和第二组数据信息；将所述第一组数据信息和所述第二组数据信息配置在寄存器中。
  11. 根据权利要求8所述的测试信号产生装置，其中，所述缓存写控制单元，还配置为判断缓存空间是否已存满；当所述缓存空间未存满时，从内存中读取测试数据并存入缓存中。
  12. 根据权利要求9所述的测试信号产生装置，其中，所述缓存读控制单元，还配置为依据所述帧头延时量和帧头周期时，确定同步信息；基于所述同步信息，从所述缓存中读取相应的测试数据并对所述测试数据进行输出。
  13. 根据权利要求9所述的测试信号产生装置，其中，所述缓存写控制单元，还配置为将数据读地址设置为寄存器中配置的所述数据首地址；检测缓存空间是否已存满；当所述缓存空间未存满时，向内存发送针对当前数据读地址的读请求；如果当前数据读地址是数据末尾地址，则将当前数据读地址设置为寄存器配置的所述数据首地址，作为下一次的数据读地址；如果当前数据读地址不是数据末尾地址，则将当前数据读地址加1后作为下一次的数据读地址；检测所述内存是否返回针对当前数据读地址的读响应，当所述内存返回针对当前数据读地址的读响应时，将读响应携带的测试数据存入缓存中。
  14. 根据权利要求13所述的测试信号产生装置，其中，所述缓存由乒乓寄存器组成；
    相应地，所述缓存写控制单元，还配置为采用乒乓操作的方式将每次读响应携带的测试数据存入所述乒乓寄存器中。
  15. 一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，该计算机可执行指令配置为执行权利要求1-7任一项所述的邻测试信号产生方法。
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