WO2018072345A1 - 微发光二极管及其制造方法和显示器 - Google Patents

微发光二极管及其制造方法和显示器 Download PDF

Info

Publication number
WO2018072345A1
WO2018072345A1 PCT/CN2017/070195 CN2017070195W WO2018072345A1 WO 2018072345 A1 WO2018072345 A1 WO 2018072345A1 CN 2017070195 W CN2017070195 W CN 2017070195W WO 2018072345 A1 WO2018072345 A1 WO 2018072345A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
gan
electrode
emitting diode
junction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2017/070195
Other languages
English (en)
French (fr)
Inventor
梁博
王威
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Technology Co Ltd
Priority to US15/327,133 priority Critical patent/US10319876B2/en
Publication of WO2018072345A1 publication Critical patent/WO2018072345A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/013—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials
    • H10H20/0133—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials
    • H10H20/01335—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials the light-emitting regions comprising nitride materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/811—Bodies having quantum effect structures or superlattices, e.g. tunnel junctions
    • H10H20/812—Bodies having quantum effect structures or superlattices, e.g. tunnel junctions within the light-emitting regions, e.g. having quantum confinement structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/819—Bodies characterised by their shape, e.g. curved or truncated substrates
    • H10H20/821—Bodies characterised by their shape, e.g. curved or truncated substrates of the light-emitting regions, e.g. non-planar junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/822—Materials of the light-emitting regions
    • H10H20/824—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP
    • H10H20/825—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP containing nitrogen, e.g. GaN
    • H10H20/8252—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP containing nitrogen, e.g. GaN characterised by the dopants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/83—Electrodes
    • H10H20/832—Electrodes characterised by their material
    • H10H20/833—Transparent materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/10—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00
    • H10H29/14—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00 comprising multiple light-emitting semiconductor components
    • H10H29/142—Two-dimensional arrangements, e.g. asymmetric LED layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/819—Bodies characterised by their shape, e.g. curved or truncated substrates

Definitions

  • the present invention relates to the field of semiconductor technologies, and in particular, to a micro light emitting diode, a method of manufacturing the same, and a display.
  • the structure of the micro LED display is a miniaturized LED array, which is to thin, miniaturize and array the LED structure design, and reduce the pixel distance from millimeter to micrometer, and the large-scale outdoor LED. Like the display screen, each pixel can be addressed and driven separately.
  • the micro-light-emitting diode display has the advantages of better material stability and longer life.
  • the micro-light-emitting diode light-emitting unit has two basic structures, a planar structure and a vertical structure.
  • the vertical-structured micro-light-emitting diode can provide a larger light-emitting area and increase the output coupling efficiency than the planar light-emitting diode.
  • the vertical structure of the micro-light-emitting diode makes it difficult to adjust the color of the micro-light-emitting diode, and the monochromaticity is easily deteriorated.
  • the technical problem to be solved by the present invention is to provide a micro light-emitting diode and a method of manufacturing the same that can increase luminous efficiency and improve the problem of monochromaticity in the prior art.
  • the first technical solution adopted by the present invention is to provide a method for preparing a micro light emitting diode, comprising: providing a substrate; depositing on the substrate to form a first buffer layer; Etching is performed at a predetermined position to expose the substrate at a predetermined position; hollow microtubes/nanotubes are grown at predetermined positions of the substrate to obtain a buffer layer cylinder; and an n-GaN layer is grown on the outer wall of the buffer layer column; Depositing on the n-GaN layer to form a second buffer layer; etching the second buffer layer to expose a portion of the n-GaN layer; sequentially forming a multiple quantum well layer and a p-GaN layer on the n-GaN layer to obtain a PN Forming a layer of the junction; forming a first electrode outside the constituent layer of the PN junction, and removing the buffer After the pillars are formed, a second electrode is formed inside the constituent layer of the a first buffer layer; Etching is
  • the substrate is a Si-doped n-GaN/Al 2 O 3 substrate
  • the first buffer layer is a SiO 2 layer
  • the predetermined position of the substrate is a periodic lattice structure to achieve uniform arrangement of the hollow microtube/nanotube structure.
  • the buffer layer cylinder is a ZnO micro tube/nanotube.
  • forming a second buffer layer on the n-GaN layer; etching the second buffer layer to expose a portion of the n-GaN layer comprises: etching a portion of the SiO 2 after depositing SiO 2 on the n-GaN layer, To expose a portion of n-GaN; after depositing PMMA on SiO 2 , the upper portion of PMMA is etched to expose a portion of n-GaN.
  • the following processing is further performed between each two adjacent layers: forming a third buffer layer to cover the structure blocking the lower layer; A portion of the third buffer layer is etched away.
  • n-GaN layer, the multiple quantum well layer, and the p-GaN layer have different heights exposed.
  • the multiple quantum well layer is a ⁇ -In x Ga 1-x N/ ⁇ -GaN multiple quantum well layer
  • p-GaN is a Mg-doped p-GaN layer.
  • forming the multiple quantum well layer and the p-GaN layer sequentially on the n-GaN layer comprises: annealing in an inert gas atmosphere.
  • forming the first electrode outside the constituent layer body of the PN junction comprises: coating and solidifying the PI liquid on the constituent layer body of the substrate and the PN junction; etching the PI liquid at the upper end of the constituent layer body of the PN junction, exposing A layer body of the PN junction; a metal Ni/Au layer and an Ag layer are deposited on the substrate and the constituent layer of the PN junction to obtain a first electrode.
  • forming the second electrode inside the constituent layer body of the PN junction includes: removing the substrate; etching away the first buffer layer and the buffer layer pillar as the sacrificial layer; and flipping the constituent layer body of the PN junction, A metal Ti/Au layer and an ITO layer are deposited to obtain a second electrode.
  • the second technical solution adopted by the present invention is to provide a micro illuminating
  • the diode includes: a first electrode and a second electrode sleeved on the first electrode, and insulating between the first electrode and the second electrode; and a layer body of the PN junction filled between the first electrode and the second electrode,
  • the constituent layer body of the PN junction further includes an n-GaN layer, a multiple quantum well layer, and a p-GaN layer sequentially grown from the inside to the outside.
  • the micro light emitting diode is a tubular structure.
  • n-GaN layer, the multiple quantum well layer, and the p-GaN layer sequentially grown inside and outside are exposed to different heights.
  • the first electrode is a metal Ni/Au layer and an Ag layer; and the second electrode is a metal Ti/Au layer and an ITO layer.
  • the multiple quantum well layer is a ⁇ -In x Ga 1-x N/ ⁇ -GaN multiple quantum layer, and the p-GaN is a Mg-doped p-GaN layer.
  • the third technical solution adopted by the present invention is to provide a micro light emitting diode display comprising: the micro light emitting diode as described above.
  • the micro light emitting diode is a tubular structure.
  • n-GaN layer, the multiple quantum well layer, and the p-GaN layer sequentially grown inside and outside are exposed to different heights.
  • the first electrode is a metal Ni/Au layer and an Ag layer; and the second electrode is a metal Ti/Au layer and an ITO layer.
  • the multiple quantum well layer is a ⁇ -In x Ga 1-x N/ ⁇ -GaN multiple quantum layer; p-GaN is a Mg-doped p-GaN layer.
  • the beneficial effects of the present invention are: after sequentially forming a layer body of a PN junction on the outer wall of the buffer layer column, forming a first electrode outside the constituent layer body of the PN junction, and removing the buffer layer cylinder and forming a layer of the PN junction A second electrode is formed on the inner side of the body, and the first electrode and the second electrode are insulated from each other outside the constituent layers of the PN junction, and the micro-light emitting diode formed is a tubular structure.
  • the tubular micro-light emitting diode structure can effectively reduce the impedance of the constituent layer path between the first electrode and the second electrode via the PN junction, thereby improving the conductivity and increasing the luminous efficiency of the micro-light emitting diode; meanwhile, the micro tube/nanotube Structure increases the effective effect of the PN junction The area increases the current density, thereby effectively improving the luminous efficiency of the micro-light emitting diode and improving the monochromaticity of the micro-light emitting diode.
  • FIG. 1 is a schematic flow chart of a first embodiment of a method for fabricating a micro light emitting diode according to the present invention
  • step S11 in FIG. 1 is a schematic flow chart of step S11 in FIG. 1;
  • step S12 in FIG. 1 is a schematic flow chart of step S12 in FIG. 1;
  • step S13 in FIG. 1 is a schematic flow chart of step S13 in FIG. 1;
  • FIG. 5 is a schematic flowchart of step S130 in FIG. 4;
  • FIG. 6 is a schematic flow chart of step S131 in FIG. 4;
  • FIG. 7 is a schematic flow chart of a second embodiment of a method for fabricating a micro light emitting diode according to the present invention.
  • FIG. 8 is a schematic structural view of an embodiment of a micro light emitting diode according to the present invention.
  • FIG. 9 is a schematic structural view of a micro light emitting diode display of the present invention.
  • a schematic flowchart of a first embodiment of a micro light emitting diode according to the present invention includes:
  • the buffer layer cylinder is formed by low temperature growth or etching. Among them, the buffer layer cylinder can effectively solve the difficulties caused by the mismatch between the lattice constant and the thermal expansion coefficient between the base material and the n-GaN layer material, and at the same time, can also play an auxiliary support role for forming the layer layer of the PN junction. .
  • S12 Forming a layer body of a PN junction in sequence on the outer wall of the buffer layer column.
  • a layer body of a PN junction is sequentially formed on the outer wall of the buffer layer by MOCVD (Metal-organic Chemical Vapor Deposition), and the layer body surrounds the buffer layer column.
  • MOCVD Metal-organic Chemical Vapor Deposition
  • the first electrode is formed outside the constituent layer body of the PN junction, and the constituent layer of the PN junction is removed after the buffer layer cylinder is removed.
  • a second electrode is formed on the inner side of the body, and the first electrode and the second electrode are insulated from each other outside the constituent layers of the PN junction, and the micro-light emitting diode formed is a tubular structure.
  • the tubular micro-light emitting diode structure can effectively reduce the impedance of the constituent layer path between the first electrode and the second electrode via the PN junction, thereby improving the conductivity and increasing the luminous efficiency of the micro-light emitting diode; meanwhile, the micro tube/nanotube
  • the structure increases the effective working area of the PN junction and increases the current density, thereby effectively improving the luminous efficiency of the micro light emitting diode and improving the monochromaticity of the micro light emitting diode.
  • step 11 in FIG. 1 includes:
  • the base material may be sapphire (Al 2 O 3 ), silicon (Si) or silicon carbide (SiC), preferably, Si-doped n-GaN/Al 2 O 3 is used as MOVPE (Metal-organic Vapor-phase Epitaxy) Substrate.
  • MOVPE Metal-organic Vapor-phase Epitaxy
  • the first buffer layer is a SiO 2 layer, and is deposited on a Si-doped n-GaN/Al 2 O 3 substrate by PECVD (Plasma Enhanced Chemical Vapor Deposition) to form an SiO 2 layer.
  • the SiO 2 layer may have a thickness of 50 to 200 nm, for example, 100 nm.
  • S112 etching a predetermined position of the first buffer layer to expose the substrate at a predetermined position.
  • the desired SiO 2 pattern is formed by homogenizing, exposing, developing, etching, etc., for growing the buffer layer cylinder at a specific position, wherein the pattern shape can be set according to the buffer layer shape surface of the subsequent desired growth. There are no restrictions.
  • the buffer layer pillar material may be AlN (aluminum nitride), GaN (gallium nitride), SiC (silicon carbide), and ZnO (zinc oxide).
  • the buffer layer pillar is a ZnO microtube/nanotube.
  • ZnO microtubes/nanotubes are grown at predetermined positions on the substrate by means of PVD (Physical Vapor Deposition), and a plurality of ZnO microtube/nanotube structures are spaced apart from each other, wherein the ZnO microtube/nanotube structure shape The shape is the same as that of the SiO 2 pattern.
  • a plurality of ZnO microtube/nanotube structures can be a periodic lattice structure, achieving uniform arrangement of a plurality of ZnO microtube/nanotube structures, and ensuring uniform distribution of a plurality of ZnO microtubes/nanotubes In order to ensure uniform light emission of the micro light-emitting diode.
  • step 12 in FIG. 1 includes:
  • S120 growing an n-GaN layer on the outer wall of the ZnO microtube/nanotube.
  • the n-GaN layer is grown on the outer wall of the ZnO microtube/nanotube by MOCVD (Metal-organic Chemical Vapor Deposition) or the like.
  • S121 depositing on the n-GaN layer to form a second buffer layer; etching the second buffer layer to expose a portion of the n-GaN layer.
  • Depositing on the n-GaN layer to form the second buffer layer includes depositing a certain thickness of SiO 2 on the n-GaN layer, and in an application, the thickness may be 50 to 200 nm, for example, 50 nm, and the upper portion of the SiO 2 Etching, exposing a portion of n-GaN; covering a certain thickness of PMMA (polymethyl methacrylate, polymethyl methacrylate, commonly known as plexiglass) to cover ZnO/n-GaN/SiO 2 , in one application, the thickness of PMMA is 1um, etch away the upper part of PMMA.
  • PMMA polymethyl methacrylate, polymethyl methacrylate, commonly known as plexiglass
  • the SiO 2 layer and the PMMA layer function as a mask, and only a part of the n-GaN layer is blocked after etching, and does not remain in the final micro-light emitting diode structure.
  • a multiple quantum well layer and a p-GaN layer are sequentially formed on the exposed portion of the n-GaN layer.
  • S122 sequentially forming a multiple quantum well layer and a p-GaN layer on the n-GaN layer.
  • the following processing is further performed between each two adjacent layers: forming a third buffer layer to cover the structure blocking the lower layer; A portion of the third buffer layer is etched away to form a p-GaN layer on the exposed portion of the multiple quantum well layer.
  • the first buffer layer, the second buffer layer, and the third buffer layer make the exposed heights of the n-GaN/multiple quantum well layer/p-GaN layer formed from the inside to the outside different.
  • MQWs is ⁇ -In x Ga 1-x N/ ⁇ -GaN MQWs
  • p-GaN is a Mg-doped p-GaN layer.
  • Forming the MQWs and p-GaN layers sequentially on the n-GaN layer includes annealing in an inert gas atmosphere, such as nitrogen.
  • step 13 in FIG. 1 includes:
  • a second electrode is formed inside the constituent layer body of the PN junction.
  • the first electrode is a deposited metal Ni/Au layer and an Ag layer
  • the second electrode is a deposited metal Ti/Au layer and an ITO layer.
  • step S130 in FIG. 4 further includes:
  • S1300 coating and curing the PI liquid on the constituent layer of the substrate and the PN junction.
  • a PI (Polyimide) liquid is applied onto the constituent layer of the substrate and the PN junction and cured, and the inside of the constituent layer of the first electrode and the PN junction formed on the outer side of the constituent layer body for isolating the PN junction is formed.
  • the second electrode insulates the first electrode and the second electrode and plays a fixed role to control the direction of the light of the micro LED.
  • the thickness of the metal Ni/Au layer may be 5-20 nm, such as 10 nm, and the thickness of the Ag layer is a few microns.
  • step S131 in FIG. 4 further includes:
  • S1312 The constituent layer body of the PN junction is inverted, and a metal Ti/Au layer and an ITO layer are deposited to obtain a second electrode.
  • the thickness of the metal Ti/Au layer is 2 to 5 nm
  • the thickness of the ITO layer is 800 to 1200 nm.
  • each layer in the above description, the deposition method of each layer, and the material of the metal electrode layer are merely examples, and the practical application can be determined as needed.
  • the N-type semiconductor layer and the P-type semiconductor layer material may be a combination of InGaN, AlGaInP, GaAlAs, or any combination thereof, but are not limited thereto.
  • the first electrode is formed outside the constituent layer body of the PN junction, and the layer layer of the PN junction is removed after the buffer layer cylinder is removed.
  • a second electrode is formed on the inner side to form a micro-light emitting diode having a metal electrode and a hollow microtube/nanotube structure.
  • the micro-light-emitting diode uses a hollow geometric shape to prepare a metal electrode, which effectively reduces the impedance between the metal electrodes, thereby improving the conductivity and increasing the luminous efficiency of the micro-light-emitting diode.
  • the structure of the micro-tube/nanotube increases the effective PN junction.
  • the action area increases the current density, thereby effectively improving the luminous efficiency of the micro-light emitting diode and improving the monochromaticity of the micro-light emitting diode.
  • FIG. 7 is a schematic flow chart of a second embodiment of a method for fabricating a micro light emitting diode according to the present invention, including:
  • S73 etching a predetermined position of the first buffer layer to expose the base at a predetermined position.
  • a buffer layer cylinder is grown at a predetermined position of the substrate.
  • S75 The n-GaN layer is grown in the outer layer of the buffer layer column.
  • the thickness of each layer, the deposition mode of each layer, and the metal electrode layer material are only examples, and the practical application can be determined according to needs.
  • the n-type semiconductor layer and the p-type semiconductor layer material may be a combination of InGaN, AlGaInP, GaAlAs, or any two thereof, but are not limited thereto.
  • FIG. 8 is a schematic structural diagram of an embodiment of a micro light emitting diode according to the present invention, including: first electric The pole 81, the second electrode 82, the PI layer 83, and the PN junction constitute a layer body 84.
  • the second electrode 82 is sleeved on the first electrode 81; the PI layer 83 is located above the second electrode 82 to insulate between the first electrode 81 and the second electrode 82; and the constituent layer 84 of the PN junction is filled in the first electrode 81 Between the second electrode 82 and the second electrode 82.
  • the first electrode is a deposited metal Ti/Au layer and an ITO layer; the second electrode is a metal Ni/Au layer 820 and an Ag layer 821; the constituent layer body 84 of the PN junction further includes sequentially growing an n-GaN layer 840 from the inside out. , a multiple quantum well layer 841, and a p-GaN layer 842.
  • the n-type semiconductor layer and the p-type semiconductor layer material may be a combination of InGaN, AlGaInP, GaAlAs, or any two thereof, but are not limited thereto.
  • a schematic structural view of an embodiment of a micro-light-emitting diode display according to the present invention includes: a substrate 90; a sub-pixel region 91 disposed on the substrate 90; and a micro-light-emitting diode 92 disposed in the sub-pixel region 91.
  • the sub-pixel regions 91 are arranged in an array; the structure of the micro-light-emitting diodes 92 is as shown in FIG. 8 .
  • the size and relative positional relationship of the sub-pixel region 91 and the micro-light-emitting diode 92 in the figure are merely illustrative, and the actual application can be determined as needed.

Landscapes

  • Led Devices (AREA)

Abstract

一种微发光二极管及其制备方法和显示器，该方法包括：形成缓冲层柱体(s11)；在缓冲层柱体外壁依次形成PN结的构成层体(s12)；在PN结的构成层体外侧形成第一电极，且去掉缓冲层柱体后，在PN结的构成层体内侧形成第二电极，第一电极和第二电极在PN结的构成层之外相互绝缘(s13)。通过上述方法制成的微发光二极管为管状结构，管状的微发光二极管结构能有效降低第一电极和第二电极之间经由PN结的构成层通路的阻抗，从而提高导电率，增加微发光二极管的发光效率；同时，其微米管/纳米管的结构增加了PN结的有效作用面积，增加电流密度，从而有效提高微发光二极管的发光效率，改善微发光二极管的单色性。

Description

微发光二极管及其制造方法和显示器 【技术领域】
本发明涉及半导体技术领域，尤其涉及一种微发光二极管及其制造方法和显示器。
【背景技术】
微发光二极管(Micro LED)显示器的结构是微型化LED阵列，也就是将LED结构设计进行薄膜化、微小化与阵列化，将像素点距离从毫米级降低至微米级，同大尺度的户外LED显示屏一样，每一个像素可定址、单独驱动点亮；而与同样是自发光显示的OLED显示器相比，微发光二极管显示器还具有材料稳定性更好、寿命更长等优点。
目前，微发光二极管发光单元有两种基本结构，平面结构和垂直结构，垂直结构的微发光二极管与平面结构的微发光二极管相比，可以提供更大发光面积，增加输出耦合效率。不过垂直结构的微发光二极管由于其复杂的几何结构，使得调节微发光二极管的颜色成为难点，且单色性容易变差。
【发明内容】
本发明主要解决的技术问题是提供一种微发光二极管及其制造方法，能够增加发光效率和改善现有技术中单色性的问题。
为了解决上述技术问题，本发明采用的第一个技术方案是：提供一种微发光二极管的制备方法，包括：提供一基底；在基底上沉积而形成第一缓冲层；对第一缓冲层的预定位置进行蚀刻，以在预定位置暴露出所述基底；在基底的预定位置处生长出中空微米管/纳米管，以得到缓冲层柱体；在缓冲层柱体外壁生长n-GaN层；在n-GaN层上沉积而形成第二缓冲层；对第二缓冲层进行蚀刻以暴露出一部分n-GaN层；在n-GaN层上依次形成多重量子阱层、p-GaN层，以得到PN结的构成层体；在PN结的构成层体外侧形成第一电极，且去掉缓冲 层柱体后，在PN结的构成层体内侧形成第二电极，第一电极和第二电极之间绝缘。
其中，基底是Si掺杂的n-GaN/Al2O3基底，第一缓冲层是SiO2层。
其中，基底的预定位置是周期性点阵结构，以实现中空微米管/纳米管结构的均匀设置。
其中，缓冲层柱体是ZnO微米管/纳米管。
其中，在n-GaN层上沉积而形成第二缓冲层；对第二缓冲层进行蚀刻以暴露出一部分n-GaN层包括：在n-GaN层上沉积SiO2后，蚀刻上面一部分SiO2，以露出一部分n-GaN；在SiO2上沉积PMMA后，蚀刻上面一部分PMMA，以露出一部分n-GaN。
其中，在n-GaN层上依次形成多重量子阱层、p-GaN层过程中，在每两相邻层之间均进一步进行以下处理：形成第三缓冲层以覆盖遮挡较下层的结构；刻蚀掉一部分第三缓冲层。
其中，n-GaN层、多重量子阱层、p-GaN层暴露出的高度不同。
其中，多重量子阱层是μ-InxGa1-xN/μ-GaN多重量子阱层，p-GaN是掺Mg的p-GaN层。
其中，在n-GaN层上依次形成多重量子阱层、p-GaN层后包括：在惰性气体氛围中退火。
其中，在PN结的构成层体外侧形成第一电极包括：在基底及PN结的构成层体上涂布并固化PI液；将PN结的构成层体的上端的PI液蚀刻掉，暴露出PN结的构成层体；在基底及PN结的构成层体上沉积金属Ni/Au层和Ag层，以得到第一电极。
去掉缓冲层柱体后，在PN结的构成层体内侧形成第二电极包括：去掉基底；刻蚀掉作为牺牲层的第一缓冲层和缓冲层柱体；将PN结的构成层体翻转，并沉积金属Ti/Au层和ITO层，以得到第二电极。
为解决上述技术问题，本发明采用的第二个技术方案是：提供一种微发光 二极管，包括：第一电极和套设于第一电极的第二电极，且第一电极和第二电极之间绝缘；填充于第一电极和第二电极之间的PN结的构成层体，其中，PN结的构成层体进一步包括：由内向外依次生长的n-GaN层、多重量子阱层、p-GaN层。
其中，微发光二极管是管状结构。
其中，内向外依次生长的n-GaN层、多重量子阱层、p-GaN层暴露出的高度不同。
其中，第一电极是金属Ni/Au层和Ag层；第二电极是金属Ti/Au层和ITO层。
其中，多重量子阱层是μ-InxGa1-xN/μ-GaN多重量子层，p-GaN是掺Mg的p-GaN层。
为解决上述技术问题，本发明采用的第三个技术方案是：提供一种微发光二极管显示器，包括：如上所述的微发光二极管。
其中，微发光二极管是管状结构。
其中，内向外依次生长的n-GaN层、多重量子阱层、p-GaN层暴露出的高度不同。
其中，第一电极是金属Ni/Au层和Ag层；第二电极是金属Ti/Au层和ITO层。
其中，多重量子阱层是μ-InxGa1-xN/μ-GaN多重量子层；p-GaN是掺Mg的p-GaN层。
本发明的有益效果是：通过在缓冲层柱体外壁依次形成PN结的构成层体后，在PN结的构成层体外侧形成第一电极，且去掉缓冲层柱体后在PN结的构成层体内侧形成第二电极，第一电极和第二电极在PN结的构成层之外相互绝缘，其制成的微发光二极管为管状结构。管状的微发光二极管结构能有效降低第一电极和第二电极之间经由PN结的构成层通路的阻抗，从而提高导电率，增加微发光二极管的发光效率；同时，其微米管/纳米管的结构增加了PN结的有效作用 面积，增加电流密度，从而有效提高微发光二极管的发光效率，改善微发光二极管的单色性。
【附图说明】
图1是本发明微发光二极管制造方法第一实施例的流程示意图；
图2是图1中步骤S11的流程示意图；
图3是图1中步骤S12的流程示意图；
图4是图1中步骤S13的流程示意图；
图5是图4中步骤S130的流程示意图；
图6是图4中步骤S131的流程示意图；
图7是本发明微发光二极管制造方法第二实施例的流程示意图；
图8是本发明微发光二极管一实施例的结构示意图；
图9是本发明微发光二极管显示器的结构示意图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。
如图1所示，本发明微发光二极管第一实施例的流程示意图，包括：
S11：形成缓冲层柱体。
采用低温生长或蚀刻等方式形成缓冲层柱体。其中，缓冲层柱体既能有效解决基底材料和n-GaN层材料之间晶格常数和热膨胀系数失配造成的困难，同时，也能为形成PN结的构成层体起到辅助支撑的作用。
S12：在缓冲层柱体外壁依次形成PN结的构成层体。
通过MOCVD(Metal-organic Chemical Vapor Deposition，金属有机化合物化学气相沉淀)等方式在缓冲层柱体外壁依次形成PN结的构成层体，层体包围缓冲层柱体。
S13：在PN结的构成层体外侧形成第一电极，且去掉缓冲层柱体后，在PN结的构成层体内侧形成第二电极，第一电极和第二电极之间绝缘。
可以看出，本实施例通过在缓冲层柱体外壁依次形成PN结的构成层体后，在PN结的构成层体外侧形成第一电极，且去掉缓冲层柱体后在PN结的构成层体内侧形成第二电极，第一电极和第二电极在PN结的构成层之外相互绝缘，其制成的微发光二极管为管状结构。管状的微发光二极管结构能有效降低第一电极和第二电极之间经由PN结的构成层通路的阻抗，从而提高导电率，增加微发光二极管的发光效率；同时，其微米管/纳米管的结构增加了PN结的有效作用面积，增加电流密度，从而有效提高微发光二极管的发光效率，改善微发光二极管的单色性。
如图2所示，在具体实施例中，图1中步骤11的流程包括：
S110：提供一基底。基底材料可以是蓝宝石(Al2O3)、硅(Si)或者碳化硅(SiC)，优选地，使用Si掺杂的n-GaN/Al2O3作为MOVPE(Metal-organic Vapor-phase Epitaxy)基底。
S111：在基底上沉积而形成第一缓冲层。第一缓冲层是SiO2层，通过PECVD(Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学气相沉积法)在Si掺杂的n-GaN/Al2O3基底上沉积而形成SiO2层，在一应用例中，SiO2层的厚度可以为50～200nm，例如100nm。
S112：对第一缓冲层的预定位置进行蚀刻，以在预定位置暴露出基底。通过匀胶、曝光、显影、刻蚀等方式制作出所需的SiO2图案，以供在特定位置生长缓冲层柱体，其中图案形状可根据后续所需生长的缓冲层柱体形状面设定，具体不作限制。
S113：在基底的预定位置处生长出缓冲层柱体。缓冲层柱体材料可以是AlN(氮化铝)、GaN(氮化镓)、SiC(碳化硅)和ZnO(氧化锌)，优选地，缓冲层柱体是ZnO微米管/纳米管。通过PVD(Physical Vapor Deposition，物理气相沉积)等方式在基底的预定位置生长ZnO微米管/纳米管，且多个ZnO微米管/纳米 管结构间相互间隔设置，其中ZnO微米管/纳米管结构形状与SiO2图案的形状相同。在一应用例中，多个ZnO微米管/纳米管结构可为周期性点阵结构，实现多个ZnO微米管/纳米管结构的均匀设置，保证多个ZnO微米管/纳米管结构分布的均匀，从而保证微发光二极管的出光均匀。
如图3所示，在具体实施例中，图1中步骤12包括：
S120：在ZnO微米管/纳米管外壁生长n-GaN层。通过MOCVD(Metal-organic Chemical Vapor Deposition，金属有机化合物化学气象沉淀)等方式在ZnO微米管/纳米管外壁生长n-GaN层。
S121：在n-GaN层上沉积而形成第二缓冲层；对第二缓冲层进行蚀刻以暴露出一部分n-GaN层。在n-GaN层上沉积而形成第二缓冲层包括：在n-GaN层上沉积一定厚度的SiO2，在一应用例中，厚度可以为50～200nm，例如为50nm，并将上面一部分SiO2刻蚀，露出一部分n-GaN；用一定厚度的PMMA(polymethyl methacrylate，聚甲基丙烯酸甲酯，俗称有机玻璃)覆盖遮挡ZnO/n-GaN/SiO2，在一应用例中，PMMA的厚度为1um，刻蚀掉上面一部分PMMA。其中，SiO2层和PMMA层起掩模的作用，蚀刻后只遮挡一部分n-GaN层，不保留在最终微发光二极管结构中。多重量子阱层、p-GaN层依次形成于n-GaN层暴露的部分上。
S122：在n-GaN层上依次形成多重量子阱层、p-GaN层。通过MOCVD在n-GaN层上依次形成多重量子阱层、p-GaN层过程中，在每两相邻层之间均进一步进行以下处理：形成第三缓冲层以覆盖遮挡较下层的结构；刻蚀掉一部分第三缓冲层，以在多重量子阱层暴露的部分上形成p-GaN层。
在本实施例中，第一缓冲层、第二缓冲层和第三缓冲层使得由内而外形成的n-GaN/多重量子阱层/p-GaN层所暴露出的高度不同。
其中，MQWs是μ-InxGa1-xN/μ-GaN MQWs，p-GaN是掺Mg的p-GaN层。在n-GaN层上依次形成MQWs、p-GaN层后包括：在惰性气体氛围中退火，如：氮气。
如图4所示，在具体实施例中，图1中步骤13包括：
S130：在PN结的构成层体外侧形成第一电极。
S131：去掉缓冲层柱体后，在PN结的构成层体内侧形成第二电极。其中，第一电极为沉积的金属Ni/Au层和Ag层，第二电极为沉积的金属Ti/Au层和ITO层。
如图5所示，在具体实施例中，图4中步骤S130进一步包括：
S1300：在基底及PN结的构成层体上涂布并固化PI液。在基底及PN结的构成层体上涂布PI(Polyimide，聚酰亚胺)液并使其固化，用于隔绝PN结的构成层体外侧形成第一电极和PN结的构成层体内侧形成第二电极，使第一电极和第二电极绝缘，且起到固定的作用，从而控制微发光二极管光的方向。
S1301：将PN结的构成层体的上端的PI液蚀刻掉，暴露出PN结的构成层体。
S1302：在基底及PN结的构成层体上沉积金属Ni/Au层和Ag层，以得到第一电极。在一实施例中，金属Ni/Au层的厚度可以为5～20nm，例如10nm，Ag层的厚度为几个微米。
如图6所示，，在具体实施例中，图4中步骤S131进一步包括：
S1310：去掉基底。
S1311：刻蚀掉作为牺牲层的第一缓冲层和缓冲层柱体。从而形成中空的ZnO微米管/纳米管结构。
S1312：将PN结的构成层体翻转，并沉积金属Ti/Au层和ITO层，以得到第二电极。在一应用例中，金属Ti/Au层的厚度为2～5nm，ITO层的厚度为800～1200nm。
上述说明中各层的厚度、各层的沉积方式以及金属电极层材料仅为示例，实际应用可根据需要决定。
在其他实施例中，N型半导体层和P型半导体层材料可以是InGaN、AlGaInP、GaAlAs或其任一两者之间的组合，但不仅限于此。
通过上述实施例的实施，在缓冲层柱体外壁依次形成PN结的构成层体后，在PN结的构成层体外侧形成第一电极，且去掉缓冲层柱体后在PN结的构成层体内侧形成第二电极，从而制成具有金属电极与中空的微米管/纳米管结构的微发光二极管。微发光二极管利用中空的几何形貌制备金属电极，有效降了金属电极间的阻抗，从而提高导电率，增加微发光二极管的发光效率；同时，其微米管/纳米管的结构增加了PN结有效作用面积，增高电流密度，从而有效提高微发光二极管的发光效率，改善微发光二极管单色性。
如图7所示，本发明微发光二极管制造方法的第二实施例的流程示意图，包括：
S71：提供一基底。
S72：在基底上沉积而形成第一缓冲层。
S73：对第一缓冲层的预定位置进行蚀刻，以在预定位置暴露出基地。
S74：在基底的预定位置处生长出缓冲层柱体。
S75：在缓冲层柱体外币生长n-GaN层。
S76：在n-GaN层上依次形成多重量子阱层、p-GaN层。
S77：在基底及PN结的构成层体上涂布并固化PI液，将PN结的构成层体的上端的PI液蚀刻掉，暴露出PN结的构成层体。
S78：在基底及PN结的构成层体上形成第一电极。
S79：去掉基底，刻蚀掉作为牺牲层的第一缓冲层和缓冲层柱体后，将PN结的构成层体翻转，在PN结的构成层体内侧形成第二电极。
本实施例中各层的材料、功能、厚度具体可参考本发明微发光二极管制造方法第一实施例中的描述，在此不再重复。其中，各层的厚度、各层的沉积方式以及金属电极层材料仅为示例，实际应用可根据需要决定。在其他实施例中，n型半导体层和p型半导体层材料可以是InGaN、AlGaInP、GaAlAs或其任一两者之间的组合，但不仅限于此。
如图8所示，本发明微发光二极管一实施例的结构示意图，包括：第一电 极81、第二电极82、PI层83、PN结的构成层体84。
第二电极82套设于第一电极81；PI层83位于第二电极82的上方，使得第一电极81和第二电极82之间绝缘；PN结的构成层体84填充于第一电极81和第二电极82之间。
第一电极为沉积的金属Ti/Au层和ITO层；第二电极为金属Ni/Au层820和Ag层821；PN结的构成层体84进一步包括由内而外依次生长n-GaN层840、多重量子阱层841、p-GaN层842。
本实施例中各层的材料、功能、厚度具体可参考本发明微发光二极管制造方法第一实施例中的描述，在此不再重复。其中，各层的厚度、大小及位置仅为示意，实际应用可根据需要决定。在其他实施例中，n型半导体层和p型半导体层材料可以是InGaN、AlGaInP、GaAlAs或其任一两者之间的组合，但不仅限于此。
如图9所示，本发明微发光二极管显示器一实施例的结构示意图，包括：基板90；设置于基板90上的子像素区域91；设置于子像素区域91内的微发光二极管92。
其中，子像素区域91阵列排布；微发光二极管92的结构如图8所示。
图中子像素区域91和微发光二极管92的大小以及相对位置关系仅为示意，实际应用可根据需要决定。
在此基础上，以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明书及附图内容所作的等效结构或等效流程变换，例如各实施例之间技术特征的相互结合，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种微发光二极管的制备方法，其中，包括：
    提供一基底；
    在所述基底上沉积而形成第一缓冲层；
    对所述第一缓冲层的预定位置进行蚀刻，以在所述预定位置暴露出所述基底；
    在所述基底的所述预定位置处生长出中空微米管/纳米管，以得到缓冲层柱体；
    在所述缓冲层柱体外壁生长n-GaN层；
    在所述n-GaN层上沉积而形成第二缓冲层；
    对所述第二缓冲层进行蚀刻以暴露出一部分所述n-GaN层；
    在所述n-GaN层上依次形成多重量子阱层、p-GaN层，以得到PN结的构成层体；
    在所述PN结的构成层体外侧形成第一电极，且去掉所述缓冲层柱体后，在所述PN结的构成层体内侧形成第二电极，所述第一电极和第二电极在所述PN结的构成层之外相互绝缘。
  2. 根据权利要求1所述的方法，其中，所述基底是Si掺杂的n-GaN/Al2O3基底，所述第一缓冲层是SiO2层。
  3. 根据权利要求1所述的方法，其中，所述基底的所述预定位置是周期性点阵结构，以实现所述中空微米管/纳米管结构的均匀设置。
  4. 根据权利要求1所述的方法，其中，所述缓冲层柱体是ZnO微米管/纳米管。
  5. 根据权利要求1所述的方法，其中，所述在所述n-GaN层上沉积而形成第二缓冲层；对所述第二缓冲层进行蚀刻以暴露出一部分所述n-GaN层包括：
    在所述n-GaN层上沉积SiO2后，蚀刻上面一部分所述SiO2，以露出一部分 所述n-GaN；
    在所述SiO2上沉积PMMA后，蚀刻上面一部分所述PMMA，以露出一部分所述n-GaN。
  6. 根据权利要求1所述的方法，其中，所述在所述n-GaN层上依次形成多重量子阱层、p-GaN层过程中，在每两相邻层之间均进一步进行以下处理：
    形成第三缓冲层以覆盖遮挡较下层的结构；
    刻蚀掉一部分所述第三缓冲层。
  7. 根据权利要求6所述的方法，其中，所述n-GaN层、所述多重量子阱层、所述p-GaN层暴露出的高度不同。
  8. 根据权利要求1所述的方法，其中，所述多重量子阱层是μ-InxGa1-xN/μ-GaN多重量子层，所述p-GaN是掺Mg的p-GaN层。
  9. 根据权利要求1所述的方法，其中，所述在n-GaN层上依次形成多重量子阱层、p-GaN层后包括：在惰性气体氛围中退火。
  10. 根据权利要求1所述的方法，其中，
    所述在所述PN结的构成层体外侧形成第一电极包括：
    在所述基底及所述PN结的构成层体上涂布并固化PI液；
    将所述PN结的构成层体的上端的所述PI液蚀刻掉，暴露出所述PN结的构成层体；
    在所述基底及所述PN结的构成层体上沉积金属Ni/Au层和Ag层，以得到所述第一电极；
    所述去掉所述缓冲层柱体后，在所述PN结的构成层体内侧形成第二电极包括：
    去掉所述基底；
    刻蚀掉作为牺牲层的所述第一缓冲层和所述缓冲层柱体；
    将所述PN结的构成层体翻转，并沉积金属Ti/Au层和ITO层，以得到所述第二电极。
  11. 一种微发光二极管，其中，包括：
    第一电极和套设于所述第一电极的第二电极，且所述第一电极和第二电极之间绝缘；
    填充于所述第一电极和所述第二电极之间的PN结的构成层体，其中，所述PN结的构成层体进一步包括：由内向外依次生长的n-GaN层、多重量子阱层、p-GaN层。
  12. 根据权利要求11所述的微发光二极管，其中，所述微发光二极管是管状结构。
  13. 根据权利要求11所述的微发光二极管，其中，所述内向外依次生长的n-GaN层、多重量子阱层、p-GaN层暴露出的高度不同。
  14. 根据权利要求11所述的微发光二极管，其中，所述第一电极是金属Ni/Au层和Ag层；所述第二电极是金属Ti/Au层和ITO层。
  15. 根据权利要求11所述的微发光二极管，其中，所述多重量子阱层是μ-InxGa1-xN/μ-GaN多重量子层，所述p-GaN是掺Mg的p-GaN层。
  16. 一种微发光二极管显示器，其中，所述微发光二极管显示器包括如权利要求11所述的微发光二极管。
  17. 根据权利要求16的微发光二极管显示器，其中，所述微发光二极管是管状结构。
  18. 根据权利要求16的微发光二极管显示器，其中，所述内向外依次生长的n-GaN层、多重量子阱层、p-GaN层暴露出的高度不同。
  19. 根据权利要求16的微发光二极管显示器，其中，所述第一电极是金属Ni/Au层和Ag层；所述第二电极是金属Ti/Au层和ITO层。
  20. 根据权利要求16的微发光二极管显示器，其中，所述多重量子阱层是μ-InxGa1-xN/μ-GaN多重量子层；所述p-GaN是掺Mg的p-GaN层。
PCT/CN2017/070195 2016-10-19 2017-01-05 微发光二极管及其制造方法和显示器 Ceased WO2018072345A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/327,133 US10319876B2 (en) 2016-10-19 2017-01-05 Method of forming micro light emitting diode

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610910337.5 2016-10-19
CN201610910337.5A CN106229394B (zh) 2016-10-19 2016-10-19 微发光二极管及其制造方法和显示器

Publications (1)

Publication Number Publication Date
WO2018072345A1 true WO2018072345A1 (zh) 2018-04-26

Family

ID=58077045

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/070195 Ceased WO2018072345A1 (zh) 2016-10-19 2017-01-05 微发光二极管及其制造方法和显示器

Country Status (3)

Country Link
US (1) US10319876B2 (zh)
CN (1) CN106229394B (zh)
WO (1) WO2018072345A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111341766A (zh) * 2020-02-27 2020-06-26 惠州中京电子科技有限公司 一种mini LED 主板制作方法

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106229394B (zh) * 2016-10-19 2019-06-07 武汉华星光电技术有限公司 微发光二极管及其制造方法和显示器
CN106784203B (zh) 2017-03-31 2019-01-04 深圳市华星光电技术有限公司 一种像素结构及制造方法
CN109448564B (zh) * 2019-01-04 2021-01-29 京东方科技集团股份有限公司 一种显示面板及其制作方法、显示装置
CN109979378B (zh) * 2019-05-15 2020-12-04 京东方科技集团股份有限公司 像素驱动电路和显示面板
CN110690245B (zh) * 2019-10-16 2022-03-25 福州大学 基于异形纳米led晶粒的发光显示器件

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1979705A (zh) * 2005-12-06 2007-06-13 佳能株式会社 纳米线电容器及相关电路器件
US20080305568A1 (en) * 2007-06-11 2008-12-11 National Chiao Tung University Method for promoting light emission efficiency of LED using nanorods structure
CN102593305A (zh) * 2012-03-21 2012-07-18 电子科技大学 发光二极管表面金属周期性亚波长结构及其制备方法
CN103337512A (zh) * 2013-04-17 2013-10-02 大连理工大学 一种具有环形圈包层结构的纳米线晶体管
CN103988321A (zh) * 2011-12-27 2014-08-13 夏普株式会社 制造具有平坦表面的三维氮化镓结构的方法和使用具有平坦表面的三维氮化镓（GaN）柱状物结构的发光二极管（LED）
US20150118777A1 (en) * 2013-10-31 2015-04-30 Yeon Woo Seo Nano-structure semiconductor light emitting device
CN106229394A (zh) * 2016-10-19 2016-12-14 武汉华星光电技术有限公司 微发光二极管及其制造方法和显示器

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102544279B (zh) * 2010-12-28 2016-11-09 鸿富锦精密工业（深圳）有限公司 发光二极管及其形成方法
TW201314956A (zh) * 2011-09-30 2013-04-01 Chi Mei Lighting Tech Corp 發光二極體及其製造方法
KR101967836B1 (ko) * 2012-12-14 2019-04-10 삼성전자주식회사 3차원 발광 소자 및 그 제조방법
KR102022266B1 (ko) * 2013-01-29 2019-09-18 삼성전자주식회사 나노구조 반도체 발광소자 제조방법
CN104112802A (zh) * 2014-06-26 2014-10-22 山西飞虹微纳米光电科技有限公司 一种AlGaInP发光二极管外延片及其制备方法
US9892944B2 (en) 2016-06-23 2018-02-13 Sharp Kabushiki Kaisha Diodes offering asymmetric stability during fluidic assembly
CN105932121A (zh) * 2016-05-05 2016-09-07 太原理工大学 一种三维led外延结构及其制备方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1979705A (zh) * 2005-12-06 2007-06-13 佳能株式会社 纳米线电容器及相关电路器件
US20080305568A1 (en) * 2007-06-11 2008-12-11 National Chiao Tung University Method for promoting light emission efficiency of LED using nanorods structure
CN103988321A (zh) * 2011-12-27 2014-08-13 夏普株式会社 制造具有平坦表面的三维氮化镓结构的方法和使用具有平坦表面的三维氮化镓（GaN）柱状物结构的发光二极管（LED）
CN102593305A (zh) * 2012-03-21 2012-07-18 电子科技大学 发光二极管表面金属周期性亚波长结构及其制备方法
CN103337512A (zh) * 2013-04-17 2013-10-02 大连理工大学 一种具有环形圈包层结构的纳米线晶体管
US20150118777A1 (en) * 2013-10-31 2015-04-30 Yeon Woo Seo Nano-structure semiconductor light emitting device
CN106229394A (zh) * 2016-10-19 2016-12-14 武汉华星光电技术有限公司 微发光二极管及其制造方法和显示器

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111341766A (zh) * 2020-02-27 2020-06-26 惠州中京电子科技有限公司 一种mini LED 主板制作方法
CN111341766B (zh) * 2020-02-27 2023-12-22 惠州中京电子科技有限公司 一种mini LED主板制作方法

Also Published As

Publication number Publication date
US10319876B2 (en) 2019-06-11
CN106229394A (zh) 2016-12-14
US20180212096A1 (en) 2018-07-26
CN106229394B (zh) 2019-06-07

Similar Documents

Publication Publication Date Title
WO2018072345A1 (zh) 微发光二极管及其制造方法和显示器
CN103608937B (zh) 超小型led元件及其制造方法
KR100682872B1 (ko) 고효율 반도체 발광 소자 및 그 제조방법
CN102403428B (zh) Ⅲ族氮化物纳米棒发光装置及其制造方法
CN112823421B (zh) Led阵列
CN106549031B (zh) 一种基于体GaN材料的单片集成器件及其制备方法
JP2010512017A (ja) 電流拡散層を含む発光ダイオードの製造方法
CN104766910B (zh) 一种GaN纳米线及其制备方法
WO2004001920A1 (ja) GaN系半導体素子
US20100155767A1 (en) Light emitting device using a micro-rod and method of manufacturing a light emitting device
CN104465929B (zh) 内嵌有源层的三族氮化物微纳发光器件及制备方法
CN104659163A (zh) 发光二极管及其形成方法
CN115064624A (zh) 一种发光二极管及制作方法
JP2015142020A (ja) ロッド型発光素子の製造方法、及びロッド型発光素子
JP4757586B2 (ja) 化合物半導体基板、化合物半導体デバイス及び化合物半導体基板の製造方法
US11450747B2 (en) Semiconductor structure with an epitaxial layer
WO2022077254A1 (zh) 微型led结构的制作方法
TWI504019B (zh) 發光二極體晶片的製造方法
KR100701094B1 (ko) 발광 다이오드 및 그 제조 방법
CN104600145A (zh) 一种带有漏电限制层的光电器件及制备方法
JP2024159042A (ja) 半導体発光素子
WO2019113814A1 (zh) 衬底及衬底结构以及制作工艺
WO2024190641A1 (ja) 半導体発光素子、および半導体発光素子の製造方法
CN120090046A (zh) 一种具有模式控制的vcsel器件及其制备方法
KR101181018B1 (ko) 주기적 편향구조가 내재된 발광소자 및 그 제조방법

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 15327133

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17861768

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17861768

Country of ref document: EP

Kind code of ref document: A1