WO2018063164A1 - Mémoire vive résistive à base de diode - Google Patents

Mémoire vive résistive à base de diode Download PDF

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Publication number
WO2018063164A1
WO2018063164A1 PCT/US2016/054009 US2016054009W WO2018063164A1 WO 2018063164 A1 WO2018063164 A1 WO 2018063164A1 US 2016054009 W US2016054009 W US 2016054009W WO 2018063164 A1 WO2018063164 A1 WO 2018063164A1
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WO
WIPO (PCT)
Prior art keywords
rram
semiconductor layer
layer
electrode
oxide layer
Prior art date
Application number
PCT/US2016/054009
Other languages
English (en)
Inventor
Abhishek A. Sharma
Van H. Le
Gilbert Dewey
Rafael Rios
Jack T. Kavalieros
Shriram SHIVARAMAN
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Intel Corporation
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Application filed by Intel Corporation filed Critical Intel Corporation
Priority to PCT/US2016/054009 priority Critical patent/WO2018063164A1/fr
Publication of WO2018063164A1 publication Critical patent/WO2018063164A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/50—Resistive cell structure aspects
    • G11C2213/56—Structure including two electrodes, a memory active layer and a so called passive or source or reservoir layer which is NOT an electrode, wherein the passive or source or reservoir layer is a source of ions which migrate afterwards in the memory active layer to be only trapped there, to form conductive filaments there or to react with the material of the memory active layer in redox way
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/72—Array wherein the access device being a diode

Definitions

  • Embodiments of the present disclosure relate generally to the technical field of electronic circuits, and more particularly to resistive random access memory (RRAM).
  • RRAM resistive random access memory
  • Resistive random access memory is an emerging technology for next generation non-volatile (NV) random-access memory (RAM).
  • a RRAM memory cell may include a RRAM storage cell coupled to a selector.
  • NV non-volatile random-access memory
  • a RRAM memory cell may be area inefficient.
  • the Si transistor used as the selector may leak static power.
  • FIG. 1 schematically illustrates a three-dimensional view of a resistive random access memory (RRAM) array including multiple RRAM memor cells, in accordance with various embodiments.
  • RRAM resistive random access memory
  • FIG. 2 schematically illustrates a three-dimensional view of another RRAM array including a RRAM memory cell, in accordance with various embodiments.
  • FIG. 3 schematically illustrates a cross sectional view of a RRAM memory cell which is a RRAM storage cell including a diode as a selector, in accordance with various embodiments.
  • FIG. 4 schematically illustrates a cross sectional view of another RRAM memory cell which is a RRAM storage cell including a diode as a selector, in accordance with various embodiments.
  • FIG. 5 illustrates an example system configured to employ the apparatuses and methods described herein, in accordance with various embodiments.
  • FIG. 6 illustrates an example process for manufacturing a RRAM memory cell, in accordance with various embodiments.
  • Resistive random access memory is an emerging technology for next generation non-volatile (NV) random-access memory (RAM).
  • a RRAM array may include multiple RRAM memory cells.
  • a RRAM memory cell may also be called a RRAM device,
  • a RRAM memor cell may include a RRAM storage cell coupled to a selector.
  • a RRAM: memory cell may store data based on the resistance values of the RRAM storage ceil within the RRAM memory cell.
  • a RRAM memory cell may be programmed to a particular resistance value to store a logic value, e.g., "0" or " 1". The stored logic value of a RRAM memory cell may be read, for example, by determining current through the selected RRAM memory cell responsive to a voltage applied to the RRAM memory cell.
  • a RRAM memory cell may have various structures, including different RRAM storage ceils coupled to different selectors.
  • a RRAM memory ceil may inciude a 1T1R (one transistor/one resistor) configuration, or a 1D1R (one diode/one resistor) configuration.
  • a RRAM memory cell may include a RRAM storage cell coupled to a transistor as a selector.
  • a RRAM memory cell may include a RRAM storage cell coupled to a diode as a selector.
  • a RRAM memory cell in the 1T1R configuration may have a better access control during read/write, while having larger size and not being suitable for stacked structure.
  • a RRAM memory cell in the IDIR configuration may result in a denser structure compared to a RRAM memory cell in the 1T1R configuration.
  • the RRAM memory cell in the IDIR configuration with a diode selector may still be area inefficient.
  • a RRAM storage cell may include a nucleation layer, also known as an oxygen exchange layer (OEL), for switching at low powers. Without the OEL, a RRAM storage cell may operate at high voltages and currents.
  • An OEL may often be implemented using metals or other switching oxides, which may reduce the endurance of a RRAM device.
  • a metal OEL may not regulate oxygen exchange as readily because of the existence of abundant oxygen within the metal.
  • a switching oxide based OEL may drift over time due to irreversible change in its own oxygen content.
  • a RRAM storage cell may include a semiconductor layer as an OEL.
  • the RRAM storage ceil may include a resistive material layer and a semiconductor layer as an OEL between a first electrode and a second electrode.
  • an electrode may be referred to as a terminal, or a contact.
  • the semiconductor layer may have metal-oxygen bonds, making the OEL robust to oxygen drift.
  • the semiconductor layer based OEL may have a higher activation energy for oxygen exchange compared to a metal OEL, hence guarding the RRAM storage cell against hastened endurance failure that other OELs induce, Accordingly, a RRAM storage cell including a semiconductor layer as an OEL may have reduced power consumption, and improved endurance properties compared to a RRAM storage ceil with a metal or switching oxide as an OEL.
  • the RRAM storage cell may contain a Schottky diode formed by the semiconductor layer of the RRAM storage cell and an electrode of the RRAM storage cell adjacent to the semiconductor layer.
  • the Schottky diode may function as a selector, hence the RRAM storage cell becomes a RRAM memory cell with the Schottky diode as a selector.
  • Such a RRAM memory cell may be very compact since it is a RRAM storage ceil itself without any additional structure or material.
  • the Schottky diode contained in the RRAM storage cell may have low leakage.
  • the RRAM memory ceil may be a part of a RRAM array, where an electrode of the RRAM: storage cell may be a word line of the RRAM: array and another electrode of the RRAM storage cell may be a bit line of the RRAM array.
  • the RRAM memory cell e.g., the RRAM storage cell
  • the RRAM memory cell may be a back- end device integrated in a vertical stack, without occupying as much area as a Si transistor or Si diode does.
  • the RRAM memory cell may be formed on a substrate, where other devices may be formed within the substrate as the front-end devices.
  • phrases “A and/or B” and “A or B” mean (A), (B), or (A and B).
  • phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).
  • the description may use perspective-based descriptions such as top/bottom, side, on, above, below, beneath, lower, upper, over, under, and the like. Such descriptions are merely used to facilitate the discussion and are not intended to restrict the application of embodiments described herein to any particular orientation. It will be understood that those perspective-based descriptions are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in a figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, for example, the term “below” can encompass both an orientation that is above, as well as, below. The device may be otherwise oriented (rotated 90 degrees or viewed or referenced at other orientations) and the perspective- based descriptions used herein should be interpreted accordingly.
  • circuitry may refer to, be part of, or include an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group), and/or memory (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable hardware components that provide the described functionality.
  • ASIC Application Specific Integrated Circuit
  • computer-implemented method may refer to any method executed by one or more processors, a computer system having one or more processors, a mobile device such as a smartphone (which may include one or more processors), a tablet, a laptop computer, a set-top box, a gaming console, and so forth.
  • Coupled may mean one or more of the following. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements indirectly contact each other, but yet still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled with each other.
  • directly coupled may mean that two or more elements are in direct contact.
  • FIG. 1 schematically illustrates a three-dimensional view of a RRAM array 100, including multiple RRAM memory cells, e.g., a RRAM memory cell 102, a RRAM memory cell 114, a RRAM memory ceil 1 16, and a RRAM memory cell 1 18, in accordance with various embodiments.
  • RRAM memory cells e.g., a RRAM memory cell 102, a RRAM memory cell 114, a RRAM memory ceil 1 16, and a RRAM memory cell 1 18, in accordance with various embodiments.
  • the RRAM array 100 may be a two terminal cross-point array having RRAM memory cells located at the intersections of a number of word lines, e.g., a word line 109 and a word line 1 13, and a number of bit lines, e.g., a bit line 101 and a bit line i l l .
  • the word line 109 and the word line 1 13 may be parallel to each other.
  • the word line 09 and word line 13 may be orthogonal to the bit line 101 and the bit line 111, which may be parallel to each other.
  • the RRAM memory cell 102 may be coupled in series with other RRAM memory cells, e.g., the RRAM memory cell 1 14, of the same row, and may be coupled in parallel with the RRAM memory cells of the other rows, e.g., the RRAM memory cell 116 and the RRAM memory cell 118.
  • the RRAM array 100 may include any suitable number of one or more RRAM memory cells. Although the RRAM array 100 is shown in Figure I with two rows that each includes two RRAM! memory cells coupled in series, other embodiments may include other numbers of rows and/or numbers of RRAM memory cells within a row. In some embodiments, the number of rows may be different from the number of columns in a RRAM array . Each row of the RRAM array may have a same number of RRAM memory cells. Additionally, or alternatively, different rows may have different numbers of RRAIVI memory cells.
  • multiple RRAM memory cells such as the RRAM memory cell 102, the RRAM memory ceil 114, the RRAM memory cell 116, and the RRAM memory ceil 1 18, may have a similar configuration, such as the 1D1R configuration.
  • the RRAM memory cell 102 may be a RRAM storage cell.
  • the RRAM memory cell 102 may include an electrode, e.g., the bit line 101, a switching oxide layer 105 on the electrode, a semiconductor layer 107 on the switching oxide layer 105, and an electrode, e.g., the word line 109, adjacent to the semiconductor layer 107.
  • the so formed RRAM memory cell 102 is itself a RRAM storage cell.
  • the switching oxide layer 105 may be a resistive material layer of the RRAM storage ceil, e.g., the RRAM memory cell 102.
  • a switching oxide layer may be referred to as a resistive material layer herein.
  • the semiconductor layer 107 may be an OEL of the RRAM storage cell, e.g., the RRAM memory cell 102.
  • the electrode e.g., the word line 109, and the semiconductor layer 107 adjacent to the electrode, may form a diode 104 to be a selector of the RRAM memory cell 102.
  • the RRAM memory cell 102 integrates a selector, the diode 104 which is a Schottky diode, into its storage cell.
  • a RRAM storage cell may be referred to simply as a storage cell herein.
  • the diode 104 may be a selector for the RRAM memory ceil 102.
  • the diode 104 may select the storage cell, which is the RRAM memory cell 102.
  • a signal from the word line 109 may pass through the diode 104, further through the switching oxide layer 105, and reaching the other electrode, which is the bit line 101.
  • the RRAM memory cell 102 may be switchabie between two or more resistance values upon application of an electric current or voltage.
  • the RRAM memory cell 102 may have a first resistance value to store a logic 0, and may have a second resistance value to store a logic 1.
  • the resistance difference between the two resistance values may be one or more orders of magnitude.
  • the RRAM memory cells e.g., the RRAM memory cell 102, the
  • RRAM memory cell 1 14, the RRAM: memory cell 116, and the RRAM memory cell 118, included in the RRAM array 100 may be formed in back-end-of-iine (BEOL) processing. Accordingly, the RRAM array 100 may be formed in higher metal layers, e.g., metal layer three and/or metal layer four, of the integrated circuit above the active substrate region, and may not occupy the active substrate area that is occupied by conventional transistors or memory devices.
  • Figure 2 schematically illustrates a three-dimensional view of another RRAM array 200 including a RRAM memory cell 202, in accordance with various embodiments. In embodiments, the RRAM memory cell 202 may be similar to the RRAM memory ceil 102 in Figure I . There may be more RRAM memory cells in the RRAM array 200, not shown in Figure 2 for simplicity reasons.
  • the RRAM memory cell 202 may be a RRAM storage cell itself, and may include an electrode (e.g., the bit line 201), a switching oxide layer 205 on the electrode, a semiconductor layer 207 on the switching oxide layer 205, and another electrode (e.g., the word line 209), adjacent to the semiconductor layer 207.
  • the RRAM memory cell 202 may include another semiconductor layer 203 between the switching oxide layer 205 and the bit line 201.
  • the switching oxide layer 205 may be a resistive material layer of the RRAM storage cell, i.e., the RRAM memory cell 202.
  • the semiconductor layer 207 and the semiconductor layer 203 may be OELs of the RRAM storage cell.
  • the electrode e.g., the word line 209
  • the semiconductor layer 207 adjacent to the electrode may form a diode 204 to be a selector of the RRAM memory cell 202.
  • the RRAM memory cell 202 integrates the diode 204, which is a Schottky diode into its storage ceil.
  • FIG 3 schematically illustrates a cross sectional view of a RRAM memory cell 302 which is a RRAM storage cell including a diode 304 as a selector, in accordance with various embodiments.
  • the RRAM memory cell 302 may be similar to the RRAM memory ceil 02 in Figure 1 .
  • the RRAM memory cell 302 is a RRAM storage cell, which may include an electrode 301 (also referred to as contact 301), a resistive material layer 305 on the electrode 301, a semiconductor layer 307 on the resistive material layer 305, and an electrode 309 (also referred to as contact 309) adjacent to the semiconductor layer 307.
  • the semiconductor layer 307 may be an OEL of the RRAM storage ceil.
  • the semiconductor layer 307 and the electrode 309 adjacent to the semiconductor layer 307 may form a diode 304 (e.g., a Schottky diode).
  • the RRAM memory cell 302 may be a back end device formed on a substrate 350.
  • the RRM memory cell 302 may be in contact with an electrode 337 within the substrate 350.
  • An electrode may also be referred to as a contact herein.
  • the substrate 350 may be a silicon substrate, a silicon on insulator (SOI) substrate, or a silicon on sapphire (SOS) substrate, among various other substrate materials.
  • the electrode 301 and/or the electrode 309 may include gold (Au), platinum (Pt), ruthenium (Ru), iridium (Ir), titanium (Ti), aluminum (Al), copper (Cu), tantalum (Ta), tungsten (W), indium-tantalum alloy (Ir-Ta), indium-tin oxide (ITO), TaN, TiN, TiAIN, TiW, or Hf.
  • the thickness of the electrode 301 and/or the electrode 309 may be between a range about 100-500 nm.
  • the semiconductor layer 307 may include ZnO, InOx, GaOx, IGZO, IZO, ITO, SnOx, Cu20, CuO, CoO, amorphous Si, amorphous Ge, poly silicon, some other semiconducting oxide material, a transition metal chaicogenide, or a transition metal oxide.
  • the thickness of the semiconductor layer 307 may be between a range about 20-100 nm.
  • the semiconductor layer may have metal-oxygen bonds that make the OEL of the RRAM storage ceil robust to oxygen ion drift.
  • the diode 304 including the electrode 309 and the semiconductor layer 307 adjacent to the electrode 309, is a two terminal Schottky diode that conducts primarily in one direction. It may have a low resistance value to the flow of current in a first direction (also referred to as the forward direction), and a high resistance value in a second direction (also referred to as the rearward direction) that is opposite the first direction.
  • a metal-semiconductor junction may be formed between the electrode 309 and the adjacent semiconductor layer 307, creating a Schottky barrier.
  • the electrode 309 may act as the anode, and the semiconductor layer 307 may act as the cathode of the diode 304, so that a current flows from the electrode 309 to the semiconductor layer 307, but not from the semiconductor layer 307 to the electrode 309, Therefore the diode 304 may function as a selector of the RRAM memory ceil 302.
  • the diode 304 may have a low forward voltage drop and a fast switching action. When sufficient forward voltage is applied, a current flows in the forward direction from the electrode 309 to the semiconductor layer 307. Being a Schottky diode, the diode 304 may have a forward voltage around 150 - 450 mV, while a silicon diode has a typical forward voltage of 600-700 mV. Accordingly, the diode 304 and the RRAM memory ceil 302 may have lower power consumption compared to a RRAM memory cell using a silicon diode.
  • the resistive material layer 305 may include HfOx, TaOx, HfTaOx, Te, Ge, Si, chaicogenide, a transition metal oxide, or a transition metal chaicogenide. Additionally or alternatively, in some embodiments, the resistive material layer 305 may include one or more oxide of W, Ta, Ti, Ni, Co, Hf, Ru, Zr, Zn, Fe, Sn, Ai, Cu, Ag, Mo, Cr. In some embodiments, silicon may be included in the resistive material layer 305 to form a composite material. The thickness of the resistive material layer 305 may be between a range about 20-100 nm.
  • the material in the resistive material layer 305 may be formed in an initial state with a first resistance value, e.g., a relatively low-resistance state such as 10 3 ohms.
  • a first voltage e.g., a set operating voltage, such as 3 V
  • the resistive material layer 305 may switch to a stable second resistance value, e.g., a high-resistance state, such as 10 7 ohms, which is maintained even after the voltage is removed.
  • This resistance switching may be reversible such that subsequent application of an appropriate current or a second voltage can serve to return the resistive material layer 305 to a stable first resistance value which is maintained even after the voltage or current is removed.
  • the first resistance value may be a high-resistance value rather than a low- resistance value.
  • a set process may refer to switching the resistive material layer 305 from a first resistance value to a second resistance value, while a reset process may refer to switching the resistive material layer 305 from the second resistance value to the first resistance value.
  • the set process may be referred to as a "forming" process, while the reset process may be referred to as a "re-forming" process.
  • oxygen ions may move from the resistive material layer 305 to the semiconductor layer 307, which is the OEL of the storage cell.
  • an oxygen ion concentration may be formed at the interface between the semiconductor layer 307 and the electrode 309 adjacent to the semiconductor layer 307.
  • the Schottky barrier between the semiconductor layer 307 and the electrode 309 may increase the resistance value. Accordingly, the resistance value of the storage cell also becomes higher.
  • the resistance of the storage cell goes through a set process to switch from a first resistance value to a second resistance value.
  • a first bit data e.g., " 1" or "0" is written to the RRAM storage cell, i.e., the RRAM memory cell 302.
  • FIG 4 schematically illustrates a cross sectional view of another RRAM memory cell 402, which is a RRAM storage cell including a diode 404 as a selector, in accordance with various embodiments.
  • the RRAM memory cell 402 may be similar to the RRAM memory cell 202 in Figure 2.
  • the RRAM memory ceil 402 is a RRAM storage cell, which may include an electrode 401, a resistive material layer 405 on the electrode 401 , a semiconductor layer 407 on the resistive material layer 405, and an electrode 409 adjacent to the semiconductor layer 407.
  • the RRAM memory cell 402 may include another semiconductor layer 403 between the switching oxide layer 405 and the electrode 401.
  • the semiconductor layer 407 and the semiconductor layer 403 may be OELs of the RRAM storage cell.
  • the semiconductor layer 407 and the electrode 409 adjacent to the semiconductor layer 407 may form a diode 404, which is a Schottky diode.
  • the RRAM memory cell 402 is a RRAM storage cell with an integrated diode 404 that may function as a selector for the RRAM memor' cell 402.
  • the RRAM memory ceil 402 may be a back end device formed on a substrate 450, and in contact with an electrode 437 within the substrate 450.
  • the substrate 450 may be a silicon substrate, a SOI substrate, or a silicon on sapphire (SOS) substrate, among various other substrate material ,
  • Figure 5 illustrates an example system configured to employ the apparatuses and methods described herein, in accordance with various embodiments.
  • Figure 5 illustrates an example computing device 500 that may employ the apparatuses and/or methods described herein (e.g., the RRAM array 100, the RRAM array 200, the RRAM memory cell 302, and the RRAM memory cell 402), in accordance with various embodiments.
  • computing device 500 may include a number of components, such as one or more processor(s) 504 (one
  • the one or more processors) 504 each may include one or more processor cores.
  • the at least one communication chip 506 may be physically and electrically coupled to the one or more processor(s) 504.
  • the communication chip 506 may be part of the one or more processors) 504.
  • computing device 500 may include printed circuit board (PCB) 502.
  • PCB printed circuit board
  • the one or more proeessor(s) 504 and communication chip 506 may be disposed thereon.
  • the various components may be coupled without the employment of PCB 502.
  • computing device 500 may include other components that may or may not be physically and electrically coupled to the PCB 502. These other components include, but are not limited to, memory controller, volatile memory (e.g., dynamic random access memory (DRAM) 514), non-volatile memory such as read only memory (ROM) 518, random access memory (RAM) 516, flash memory, storage device (e.g., a hard-disk drive (HDD)), an I/O controller 530, a digital signal processor (not shown), a crypto processor (not shown), a graphics processor 526, one or more antenna 532, a display (not shown), a touch screen display 520, a touch screen controller 528, a battery 544, an audio codec (not shown), a video codec (not shown), a global positioning system (GPS) device 520, a compass, sensors 542, a microphone 538, jacks 540, an accelerometer (not shown), a gyroscope (not shown), a speaker 534
  • volatile memory
  • the one or more processor(s) 504, various memories such as DRAM 514, RAM 516, ROM 518, and other flash memory, and/or storage device may include associated firmware (not shown) storing programming instructions configured to enable computing device 500, in response to execution of the programming instructions by one or more processor(s) 504, to practice all or selected aspects of the methods described herein. In various embodiments, these aspects may additionally or alternatively be implemented using hardware separate from the one or more processor(s) 504, DRAM 514, RAM 516, ROM 518, and other flash memory, or storage device.
  • one or more components of the computing device 500 may be any one or more components of the computing device 500.
  • RRAM array that employ one or more RRAM memory cells as described herein.
  • the RRAM array with one or more RRAM memory cells may be included in processor 504, controller 530, and/or another component of computing device 500.
  • one or more components of the computing device 500 such as DRAM 514, RAM 516, ROM 518, and other flash memory, or storage device, may include the RRAM array 100, the RRAM array 200, the RRAM memory cell 302, and/or the RRAM memory cell 402 described herein.
  • the communication chips 506 may enable wired and/or wireless communications for the transfer of data to and from the computing device 500.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip 506 may implement any of a number of wireless standards or protocols, including but not limited to IEEE 702.20, Long Term Evolution (LTE), LTE Advanced (LTE-A), General Packet Radio Service (GPRS), Evolution Data Optimized (Ev-DO), Evolved High Speed Packet Access (HSPA+), Evolved High Speed Downlink Packet Access (HSDPA+), Evolved High Speed Uplink Packet Access (HSUPA+), Global System for Mobile Communications (GSM), Enhanced Data rates for GSM Evolution (EDGE), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Worldwide Interoperability for Microwave Access (WIMAX), Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • IEEE 702.20 Long Term Evolution (LTE), LTE Advanced (LTE-A), General Packet Radio Service (GPRS), Evolution Data Optimized (Ev-DO), E
  • the computing device 500 may include a plurality of communication chips 506.
  • a first communication chip 506 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth
  • a second communication chip 506 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiM AX, LTE, Ev-DO, and others.
  • the computing device 500 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a computing tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit (e.g., a gaming console or automotive entertainment unit), a digital camera, an appliance, a portable music player, or a digital video recorder.
  • the computing device 500 may be any other electronic device that processes data.
  • Figure 6 illustrates an example process for manufacturing a REAM memory cell, in accordance with various embodiments.
  • various processes may be used to form a RRAM array, e.g., the REAM array 100 of Figure 1, the RRAM array 200 of Figure 2, a RRAM memory cell, e.g., the RRAM memory cell 102 of Figure 1, the RRAM memory cell 202 of Figure 2, the RRAM memory cell 302 of Figure 3, or the RRAM memory cell 402 of Figure 4.
  • a process 600 may be used to form a RRAM memory ceil, e.g., the RRAM memory cell 102 of Figure 1, or the RRAM memory cell 302 of Figure 3.
  • Operation 601 may be performed to form an electrode on a substrate, such as to form the electrode 301 on the substrate 350.
  • Operation 603 may be performed to form a resistive switching material layer on the electrode, such as to form the resistive switching material layer 305 on the electrode 301.
  • Operation 605 may be performed to form a semiconductor layer on the resistive switching material layer, such as to form the semiconductor layer 307 on the resistive switching material layer 305.
  • Operation 607 may be performed to form another electrode on the semiconductor layer, such as to form the electrode 309 on the semiconductor layer 307.
  • a RRAM memory cell e.g., the RRAM memory cell 302 may be formed by the operation 601, the operation 603, the operation 605, and the operation 607.
  • Example 1 may include a resistive random access memory (RRAM) device, comprising: a semiconductor substrate; a first electrode on the semiconductor substrate; a switching oxide layer on the first electrode, wherein the switching oxide layer is a resistive material layer of a RRAM storage cell; a semiconductor layer on the switching oxide layer, wherein the
  • RRAM resistive random access memory
  • semiconductor layer is an oxygen exchange lay er of the RRAM storage cell; and a second electrode adjacent to semiconductor layer, wherein the semiconductor layer and the second electrode form a Schottky diode.
  • Example 2 may include the RRAM device of example 1 and/or some other examples herein, wherein the semiconductor layer includes ZnO, InOx, GaOx, IGZO, IZO, ITO, SnOx,
  • Example 3 may include the RRAM device of example 1 and/or some other examples herein, wherein the switching oxide layer includes HfOx, TaOx, HfTaOx, Te, Ge, Si, or chalcogenide.
  • Example 4 may include the RRAM device of example 1 and/or some other examples herein, wherein the switching oxide layer includes a transition metal oxide or a transition metal chalcogenide.
  • Example 5 may include the RRAM device of example 1 and/or some other examples herein, wherein the first electrode or the second electrode includes gold (Au), platinum (Pt), ruthenium (Ru), iridium (Ir), titanium (Ti), aluminum (Al), copper (Cu), tantalum (Ta), tungsten (W), iridium -tantalum alloy (Ir-Ta), indium-tin oxide (ITO), TaN, TiN, TiAlN, Ti W, or Hf.
  • the first electrode or the second electrode includes gold (Au), platinum (Pt), ruthenium (Ru), iridium (Ir), titanium (Ti), aluminum (Al), copper (Cu), tantalum (Ta), tungsten (W), iridium -tantalum alloy (Ir-Ta), indium-tin oxide (ITO), TaN, TiN, TiAlN, Ti W, or Hf.
  • Example 6 may include the RRAM device of example 1 and/or some other examples herein, wherein the semiconductor layer is a first semiconductor layer, and the RRAM device further includes: a second semiconductor layer between the first electrode and the switching oxide layer, wherein the second semiconductor layer is a part of the RRA : storage cell.
  • Example 7 may include the RRAM device of example 1 and/or some other examples herein, wherein the switching oxide layer, or the semiconductor layer has a thickness in a range of about 1-20 nm.
  • Example 8 may include a resistive random access memory (RRAM) array, comprising: a bit line; a plurality of RRAM memory cells, wherein a RRAM memory ceil of the plurality of RRAM memory cells includes a Schottky diode and a RRAM storage cell, and further includes: a switching oxide layer coupled to the bit line, wherein the switching oxide layer is a resistive material layer of the RRAM storage cell: a semiconductor layer on the switching oxide layer, wherein the semiconductor layer is an oxygen exchange layer of the RRAM storage cell; and a word line adjacent to the semiconductor layer, wherein the semiconductor layer and the word line form the Schottky diode.
  • RRAM resistive random access memory
  • Example 9 may include the RRAM array of example 8 and/or some other examples herein, wherein the semiconductor layer includes ZnO, InOx, GaOx, IGZO, IZO, ITO, SnOx, Cu20, CuO, CoO, amorphous Si, amorphous Ge, polysilicon, a transition metal chalcogenide, or a transition metal oxide.
  • the semiconductor layer includes ZnO, InOx, GaOx, IGZO, IZO, ITO, SnOx, Cu20, CuO, CoO, amorphous Si, amorphous Ge, polysilicon, a transition metal chalcogenide, or a transition metal oxide.
  • Example 0 may include the RRAIVi array of example 8 and/or some other examples herein, wherein the switching oxide layer includes HfOx, TaOx, HfTaOx, Te, Ge, Si, or chalcogenide.
  • Example 1 1 may include the RRAM array of example 8 and/or some other examples herein, wherein the switching oxide layer includes a transition metal oxide or a transition metal chalcogenide.
  • Example 12 may include the RRAM array of example 8 and/or some other examples herein, wherein the word line or the bit line includes gold (Au), platinum (Pt), ruthenium (Ru), iridium (Ir), titanium (Ti), aluminum (Al), copper (Cu), tantalum (Ta), tungsten (W), iridium- tantalum alloy (Ir-Ta), indium-tin oxide (ITO), TaN, TIN, TiAIN, TiW, or Hf.
  • the word line or the bit line includes gold (Au), platinum (Pt), ruthenium (Ru), iridium (Ir), titanium (Ti), aluminum (Al), copper (Cu), tantalum (Ta), tungsten (W), iridium- tantalum alloy (Ir-Ta), indium-tin oxide (ITO), TaN, TIN, TiAIN, TiW, or Hf.
  • the word line or the bit line includes gold (Au), platinum (Pt), ruthenium (Ru
  • Example 13 may include the R AM array of example 8 and/or some other examples herein, wherein the semiconductor layer is a first semiconductor layer, and the RRAM memory cell further includes: a second semiconductor layer between the bit line and the switching oxide layer, wherein the second semiconductor layer is a part of the RRAM storage cell.
  • Example 14 may include the RRAM array of example 8 and/or some other examples herein, wherein the switching oxide layer or the semiconductor layer has a thickness in a range of about 1-20 nm.
  • Example 15 may include a computing device, comprising: a circuit board; and a memory device coupled to the circuit board and including a plurality of RRAM memory cells, wherein a RRAM memory cell of the plurality of RRAM memor ⁇ ' cells includes a Schottky diode and a RRAM storage cell, and further includes: a bit line of the memory device; a switching oxide layer coupled to the bit line, wherein the switching oxide layer is a resistive material layer of the RRAM storage cell, a semiconductor layer on the switching oxide layer, wherein the
  • semiconductor layer is an oxygen exchange layer of the RRAM storage cell; and a word line adjacent to the semiconductor layer, wherein the semiconductor layer and the word line form the Schottky diode.
  • Example 16 may include the computing device of example 15 and/or some other examples herein, wherein the semiconductor layer includes ZnO, InOx, GaOx, IGZO, IZO, ITO, SnOx, Cu20, CuO, CoO, amorphous Si, amorphous Ge, polysilicon, a transition metal chalcogenide, or a transition metal oxide.
  • Example 7 may include the computing device of example 5 and/or some other examples herein, wherein the switching oxide layer includes HfOx, TaOx, HfTaOx, Te, Ge, Si, or chalcogenide.
  • Example 18 may include the computing device of example 15 and/or some other examples herein, wherein the switching oxide layer includes a transition metal oxide or a transition metal chalcogenide.
  • Example 19 may include the computing device of example 15 and/or some other examples herein, wherein the word line or the bit line includes gold (Au), platinum (Pt), ruthenium (Ru), iridium (Ir), titanium (Ti), aluminum (Al), copper (Cu), tantalum (Ta), tungsten (W), iridium-tantalum alloy (Ir-Ta), indium-tin oxide ( ⁇ ), TaN, TiN, TiAlN, TiW, or Hf.
  • the word line or the bit line includes gold (Au), platinum (Pt), ruthenium (Ru), iridium (Ir), titanium (Ti), aluminum (Al), copper (Cu), tantalum (Ta), tungsten (W), iridium-tantalum alloy (Ir-Ta), indium-tin oxide ( ⁇ ), TaN, TiN, TiAlN, TiW, or Hf.
  • Example 20 may include the computing device of example 15 and/or some other examples herein, wherein the semiconductor layer is a first semiconductor layer, and the RRAM memory cell further comprises: a second semiconductor layer between the first electrode and the switching oxide layer, wherein the second semiconductor layer is a part of the RRAM storage cell.
  • Example 21 may include the computing device of example 15 and/or some other examples herein, wherein the switching oxide layer, or the semiconductor layer has a thickness in a range of about 1-20 nm.
  • Example 22 may include the computing device of example 15 and/or some other examples herein, wherein the computing device is a wearable device or a mobile computing device, the wearable device or the mobile computing device including one or more of an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, or a camera coupled with the circuit board.
  • the computing device is a wearable device or a mobile computing device, the wearable device or the mobile computing device including one or more of an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, or a camera coupled with the

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Abstract

Des modes de réalisation comprennent une cellule de mémoire à mémoire vive résistive (RRAM) qui est la même qu'une cellule de stockage RRAM. La cellule de stockage à mémoire vive résistive (RRAM), a une couche de matériau résistive et une couche semi-conductrice entre deux électrodes, la couche semi-conductrice servant de couche OEL. En outre, la couche semi-conductrice et une électrode de la cellule de stockage RRAM adjacente à la couche semi-conductrice forment une diode Schottky, qui peut être utilisée en tant que sélecteur pour la cellule de mémoire RRAM. Une ligne de mots d'un réseau RRAM et une ligne de bits du réseau RRAM peuvent être les deux électrodes de la cellule de stockage RRAM.
PCT/US2016/054009 2016-09-27 2016-09-27 Mémoire vive résistive à base de diode WO2018063164A1 (fr)

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JP2020136681A (ja) * 2019-02-20 2020-08-31 国立大学法人北見工業大学 半導体メモリセル構造、半導体記憶装置及び半導体メモリセル構造の製造方法
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