US20140269001A1

US20140269001A1 - Amorphous silicon rram with non-linear device and operation

Info

Publication number: US20140269001A1
Application number: US14/106,288
Authority: US
Inventors: Tanmay Kumar
Original assignee: Crossbar Inc
Current assignee: Crossbar Inc
Priority date: 2011-06-30
Filing date: 2013-12-13
Publication date: 2014-09-18
Also published as: WO2013003856A2; WO2013003856A3; US20130003436A1; US8659929B2

Abstract

A non-volatile memory device includes a resistive switching device having a first electrode, a second electrode, and a resistive switching element, wherein the resistive switching element comprises a silicon material disposed in an overlapping region between the first electrode and the second electrode, wherein the second electrode comprises at least a metal material physically and electrically in contact with the resistive switching material, wherein the resistive switching element is characterized by a resistance depending on an electric field in the resistive switching element, and a non-linear device coupled between the first electrode and the resistive switching element , wherein the non-linear device is configured to conduct electric current when a voltage greater than a first voltage is applied to the second electrode, wherein the resistive switching device is configured to change from a first state to a second state in response to the first voltage.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

The present application claims priority to and is a continuation of U.S. application Ser. No. 13/174,264, filed Jun. 30, 2011, which is herein incorporated by reference for all purposes.

STATEMENTS RELATED TO GOVERNMENT OR FEDERALLY FUNDED RESEARCH

Not Applicable

BACKGROUND

The present invention is generally related to resistive switching devices. More particularly, embodiments according to the present invention provide a method and a structure for forming a resistive switching device coupled to a non-linear device. The present invention can be applied to non-volatile memory devices but it should be recognized that the present invention can have a much broader range of applicability.
The inventors of the present invention have recognized the success of semiconductor devices has been mainly driven by an intensive transistor down-scaling process. However, as field effect transistors (FETs) approach sizes less than 100 nm, physical problems such as short channel effect begin to hinder proper device operation. For transistor based memories, such as those commonly known as Flash memories, other performance degradations or problems may occur as device sizes shrink. With Flash memories, a high voltage is usually required for programming of such memories, however, as device sizes shrink, the high programming voltage can result in dielectric breakdown and other problems. Similar problems can occur with other types of non-volatile memory devices other than Flash memories.
The inventors of the present invention recognize that many other types of non-volatile random access memory (RAM) devices have been explored as next generation memory devices, such as: ferroelectric RAM (Fe RAM); magneto-resistive RAM (MRAM); organic RAM (ORAM); phase change RAM (PCRAM); and others.
A common drawback with these memory devices include that they often require new materials that are incompatible with typical CMOS manufacturing. As an example of this, Organic RAM or ORAM requires organic chemicals that are currently incompatible with large volume silicon-based fabrication techniques and foundries. As another example of this, Fe-RAM and MRAM devices typically require materials using a high temperature anneal step, and thus such devices cannot be normally be incorporated with large volume silicon-based fabrication techniques.
Additional drawbacks with these devices include that such memory cells often lack one or more key attributes required of non-volatile memories. As an example of this, Fe-RAM and MRAM devices typically have fast switching (e.g. “0” to “1”) characteristics and good programming endurance, however, such memory cells are difficult to scale to small sizes. In another example of this, for ORAM devices reliability of such memories is often poor. As yet another example of this, switching of PCRAM devices typically includes Joules heating and undesirably require high power consumption.
From the above, a new semiconductor device structure and integration is desirable.

BRIEF SUMMARY OF THE PRESENT INVENTION

The present invention is generally related to resistive switching devices. More particularly, embodiments according to the present invention provide a method and a structure for forming a resistive switching device coupled to a non-linear device. The present invention can be applied to non-volatile memory devices but it should be recognized that the present invention can have a much broader range of applicability.
In a specific embodiment, a non-volatile memory device is provided. The non-volatile memory device includes a resistive switching device. In a specific embodiment, the resistive switching device includes a first electrode, a second electrode, and a resistive switching element disposed in an intersection region between the first electrode and the second electrode. The resistive switching element can include a silicon material in a specific embodiment. In a specific embodiment, the second electrode includes at least a metal material physically and electrically in contact with the resistive switching material. In a specific embodiment, the non-volatile memory device includes a non-linear device disposed in between the first electrode and the resistive switching element and serially connected to the resistive switching element. The non-linear device is configured to conduct electric current when a voltage greater than a first voltage is applied to the second electrode. The first voltage causes the resistive switching device to change from a first state to a second state in a specific embodiment. Depending on the embodiment, the first state can be a high resistance state and the second state can be a low resistance state. Alternatively, the first state can be a low resistance state and the second state can be a high resistance state.
In a specific embodiment, a method of programming a memory cell in an array of non-volatile memory devices is provided. The method includes providing a plurality of memory cells arranged in an array. Each of the plurality of memory cells includes a resistive switching device and a non-linear device serially coupled to the resistive switching device. In a specific embodiment, the resistive switching device includes at least a first electrode, a second electrode, and a resistive switching material. The resistive switching material includes a silicon material in a specific embodiment. The first electrode includes at least a silver material in a specific embodiment. The non-linear device is disposed between the second electrode and the resistive switching material in a specific embodiment. In a specific embodiment, each of the memory cells has a first current flowing in the respective resistive switching device. The first current can be a dark current in each of the device in a specific embodiment. The method includes selecting a first memory cell and applying a first voltage to the first memory cell. The first voltage is configured to cause the non-linear device, e.g., punch-through diode, to conduct current and to cause the resistive switching device associated with the first memory cell to change from the first state to a second while the first current from other memory cells is blocked from flowing in the first memory cell by a second voltage drop across the respective non-linear device in other memory cells.
According to one aspect of the invention, a non-volatile memory device is described. One device includes a resistive switching device comprising a first electrode, a second electrode, and a resistive switching element, wherein the resistive switching element comprises a silicon material disposed in an overlapping region between the first electrode and the second electrode, wherein the second electrode comprises at least a metal material physically and electrically in contact with the resistive switching material, wherein the resistive switching element is characterized by a resistance depending on an electric field in the resistive switching element. A device may include a non-linear device coupled between the first electrode and the resistive switching element, wherein the non-linear device is configured to conduct electric current when a voltage greater than a first voltage is applied to the second electrode. In various embodiments, the resistive switching device is configured to change from a first state to a second state in response to the first voltage.
According to another aspect of the invention, a method of programming a memory cell in an array of non-volatile memory devices is described. One technique includes providing a plurality of memory cells arranged in an array, wherein each of the plurality of memory cells comprises a resistive switching device and a non-linear device serially coupled to the resistive switching device, wherein each of the memory cells have a first current flowing in respective resistive switching devices, wherein the resistive switching device comprise at least a first electrode, a second electrode, and a resistive switching material, wherein the resistive switching material comprises a silicon material, wherein the first electrode comprises at least a silver material, and wherein the non-linear device is disposed in between the second electrode and the resistive switching material. A process may include selecting a first memory cell, and applying a first voltage to the first memory cell, wherein the first voltage is greater than a voltage to cause the non-linear device to conduct a first current and to cause the resistive switching device associated with the first memory cell to change from a first state to a second state, while a first current from other memory cells is blocked from flowing in the first memory cell by a second voltage drop across respective non-linear devices associated with other memory cells.
Many benefits can be achieved by ways of present invention over conventional techniques. Embodiments according to the present invention provide a device structure and a programming method for a non-volatile memory device. The device structure includes a non-linear device to suppress leakage current from interfering with write, erase as well as read operations in a specific embodiment. Depending on the embodiment, one or more of these benefits may be achieved. One skilled in the art would recognize other variations, modifications, and alternatives.

SUMMARY OF THE DRAWINGS

In order to more fully understand the present invention, reference is made to the accompanying drawings. Understanding that these drawings are not to be considered limitations in the scope of the invention, the presently described embodiments and the presently understood best mode of the invention are described with additional detail through use of the accompanying drawings in which:

FIG. 1 is a simplified diagram illustrating a resistive switching device according to an embodiment of the present invention.

FIG. 2 is a simplified diagram illustrating a resistive switching device arranged in a crossbar configuration according to an embodiment of the present invention.

FIGS. 3, 4, and 5 are simplified diagrams illustrating a resistive switching mechanism of the resistive switching device according to an embodiment of the present invention.

FIG. 6 is a simplified diagram illustrating a portion of a crossbar array and a leakage current path according to an embodiment of the present invention.

FIG. 7 is a simplified diagram illustrating a current-voltage characteristic of a conventional rectifying device.

FIG. 8 is a simplified diagram illustrating a non-linear device according to an embodiment of the present invention.

FIG. 9 is a simplified diagram illustrating a current-voltage characteristic of the non-linear device according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

The present invention is directed to switching devices. More particularly, embodiments of the present invention provide a method and device structure for a resistive switching device coupled to a non-linear device, e.g., diode, to prevent leakage current for proper operations of the resistive switching device. Embodiments of the present invention have been applied to a crossbar array of non-volatile memory device using a silicon material as resistive switching material. But it should be recognized that embodiments of the present invention have a broader range of applicability.
High density and low cost storage devices are in ever increasing demand due to the growth in consumer devices common in the market place. Current non-volatile memory devices including Flash are probably approaching an end to further scaling due to fundamental limitations in the devices. It is predicted that current charge storage in a floating gate or a dielectric material in Flash may not be possible in device size less that about 10 nm. A new category of devices using an interconnected crossbar configuration that can be vertically integrated in a three dimensional manner provides a high device density not achievable in current memory devices.
However, leakage current from cells in an interconnected crossbar array can affect proper operations (read, write, or erase) of the device. To suppress the leakage current and to isolate a cell from the leakage current, certain rectifiers can be used. A conventional rectifier usually limits current to flow in a single direction, and can only work for a forward bias operation or a reverse bias operation and not for both. Thus conventional rectifiers are of limited applicability. Certain switching devices can have symmetrical current-voltage (IV) behavior, but such devices do not generally work well in a crossbar array. Other rectifying devices may have a low on-state current but can have poor data retention characteristics. Embodiments of the present invention provide a device structure that includes at least a non-linear device and related methods for a resistive switching device that is rectifying and yet allows current to flow in forward bias as well as in reverse bias operations.
FIG. 1 is a simplified diagram illustrating a resistive switching device 100 according to an embodiment of the present invention. The resistive switching device includes a first electrode 102, a second electrode 106, and a resistive switching material 104 sandwiched between the first electrode and the second electrode. As merely an example, the first electrode can be a first conductor material. The first electrode 102 can include a first conductive material such as a first metal material or a doped semiconductor material. In a specific embodiment, the first metal material can be tungsten, aluminum, copper or other suitable metal that is compatible with CMOS fabrication techniques. In a specific embodiment, the first electrode is elongated in shape and extends in a first direction.
The resistive switching material 104 can include a suitable insulator material having a resistance that can be altered upon application of an electric field to the insulator material. In a specific embodiment, the resistive switching material can include a silicon material. For example, the silicon material can be an amorphous silicon material, a microcrystalline silicon material, a macro crystalline silicon material, a silicon germanium material including any combination of these materials, or the like. In an embodiment, the silicon material includes an amorphous silicon material.
The second electrode 106 can comprise a second conductive material and can have a portion that includes a second metal material. The second metal material can be aluminum, nickel, silver, gold, palladium, platinum, or another similar metal or combination of metals. The second metal material typically is characterized by a suitable diffusivity into the resistive switching material in a specific embodiment. In a specific embodiment, the second electrode 106 is elongated in shape and extends in a second direction that is orthogonal to the first direction, as illustrated in FIG. 2. In a specific embodiment, the second metal material includes a silver material.
In certain embodiments, the resistive switching device further includes a contact material 108 disposed between the metal material of the first electrode 102 and the amorphous silicon material 104. The contact material is believed to provide a suitable interfacial defect characteristic for desirable switching behavior for the resistive switching device. For amorphous silicon material as the resistive switching material, the contact material can be p+ polysilicon material, p+ silicon germanium material, or the like. In certain embodiments, the contact material can be optional. The resistive switching device can be disposed in an N by M crossbar array with pillars of resistive switching material 104 located at the crossings of the array, to form a high density interconnected array of non-volatile memory cells.
FIGS. 3-5 are simplified diagrams illustrating operations of a resistive switching device. As shown in FIG. 3, the second metal material forms a metal region 302 in a portion of the resistive switching material 104 when a first positive voltage 304 greater than a threshold voltage is applied to the second electrode 106. The threshold voltage is the forming voltage for the resistive switching device. In this configuration, the resistive switching device is at a high resistance state, otherwise known as an erase state, or an “OFF” state.
As shown in FIG. 4, the metal region may further form a filament region 402. The filament region 402 may be characterized by a length, a first distance between metal particles, a second distance between the filament and the first electrode 102, and the like. In FIG. 4, the filament extends in a direction 404 towards the first electrode 102 when a second positive bias voltage 406 is applied to the second electrode 106. In this configuration the resistive switching device 104 is in a low resistance state, otherwise known as a programmed or “ON” state, allowing current to flow through the resistive switching device 104.
As illustrated in FIG. 5, the filament structure 402 retracts in a direction 502 away from first electrode 102, when a negative bias voltage 504 or an erase voltage is applied to the second electrode 106. In this configuration, the resistive switching device 104 is reverted back to the high resistance state illustrated in FIG. 3. Accordingly, as shown in FIGS. 3-5. the resistive switching device 100 is considered a two-terminal or a bipolar device.
Due to the interconnectivity of a crossbar structure, when an operating voltage (e.g. e.g. the second positive bias voltage 406) is applied to a selected cell, leakage current from un-selected cells can form a leakage path, that affects operations of the selected cell. Leakage current from the selected cell can also affect the states of unselected cells in the leakage path. As an example of this, in a situation where a selected cell is at a high conductance state, leakage current from the high conductance cell can erase an unselected cell also in the high conductance state in the leakage path.
FIG. 6 is a simplified diagram illustrating a crossbar array of memory cells 600. Four cells 602, 604, 608, and 610 are illustrated. Cell 602 includes a first bottom electrode 612, a first top electrode 614, and a first resistive switching region 618. Cell 604 shares the same first bottom electrode 612 as cell 602, and includes a second top electrode 616 and a second resistive switching region 620. Cell 608 shares the same first top electrode 614 as cell 602, and includes a third bottom electrode 622 and a third resistive switching region 624. Cell 610 shares the same first top electrode 616 as cell 602, and the same bottom electrode 622 as cell 608 and a fourth resistive switching region 628.
An example of a programming operation of an embodiment will now be described with respect to FIG. 6 using cell 602 as a target cell for programming. In the programming operation, a positive bias voltage applied to first top electrode 614 causes cell 602 to be in a low resistance state, such that an ‘ON’ state current flows in cell 602 during a subsequent read operation. If cell 604 is in a low resistance (e.g. programmed state) , current leaking from cell 602 can cause cell 604 to be unintentionally erased. Similarly, if cell 602 is in a programmed state and to be erased, a negative voltage applied to first top electrode 614 can cause cell 608 to be unintentionally erased when cell 608 is in a low resistance state.
In various embodiments, to prevent or reduce the incidence of the leakage current from affecting operations of the selected cell or to maintain a state of an unselected cell, a rectifier or a diode may be incorporated into the design.
FIG. 7 illustrates a conventional diode 700 and an IV characteristic 702 of the conventional diode. Because a conventional diode limits current flow only in one direction, the conventional diode can only reduce reverse current flow for either a program operation (e.g. positive voltage) or an erase operation (e.g. negative voltage) , but typically not for both. In particular, if the conventional diode allows current to flow in a forward bias (for example, in a programming operation), the conventional diode may experience breakdown in reversed bias or during an erase operation when a current starts to flow. Similarly, a conventional diode configured to operate for a negative bias erase function may experience breakdown during a positive bias program function. After breakdown, the conventional diode becomes defective and non-functional.
Embodiments according to the present invention provide a device coupled to a resistive switching device, as described above, that addresses this breakdown issue. In various embodiments, the non-linear device is a two terminal device configured to prevent leakage current from unselected cells to interfere with proper operation of a selected cell under conditions of forward bias as well as reversed bias. The non-linear device also prevents leakage current from a selected cell during, for example programming, from unintentionally erasing one or more unselected cells or unintentionally programming one or more unselected cells. In various embodiments, the non-linear device is serially connected to the resistive switching device and can be disposed between the first electrode (FIG. 1, 106) and the resistive switching element (FIG. 1, 104) in a specific embodiment. In other embodiments, the non-linear device can be disposed between the second electrode 106 and the resistive switching element (104, 108). In a specific embodiment, the non-linear device is configured to conduct electric current when an operating voltage is applied to, for example, the second electrode 106 of the resistive switching device 100. The operating voltage includes a forward biased programming voltage and a reverse biased erase voltage in a specific embodiment.
Referring to FIG. 8, in a specific embodiment, the non-linear device 800 includes a first impurity region 802, a second impurity region 804, and a third impurity region 806 sandwiched between the first impurity region 802 and the second impurity region 806. In various embodiments, the first impurity region 802 and the second impurity region 804 have the same charge polarity characteristic and have substantially the same impurity concentration. The third impurity region 806 has an opposite charge polarity characteristic and a lower impurity concentration than the first impurity region 802 and the second impurity region 804. For example, as shown in FIG. 8, the non-linear device can have a pnp configuration or an npn configuration depending on the embodiment.
In operation, the non-linear device 800 is configured to conduct electric current when a voltage greater than a first voltage, or “punch-through” voltage, is applied. This type of diode may be referred to as a punch-through diode. The first voltage further causes the resistive switching device to change from a first state (e.g. non-conductive) to a second state (e.g. conductive). For example, the first state can be an off state or a high resistance state and the second state can be a programmed state or a low resistance state. In various embodiments, the first voltage can be a programming voltage or a read voltage depending on the embodiment. Embodiments according to the present invention can be applied to a one-time programmable memory device configured in an array, for example in a crossbar array.
Referring again to FIG. 8, in various embodiments, the non-linear device 800 includes a first depletion region 808 formed from the first impurity region 802 and the third impurity region 806, and a second depletion region 810 formed from the second impurity region 804 and the third impurity region 806. When a first voltage is applied to a selected cell, (for example, in a programming operation or an erase operation), the first depletion region 808 and the second depletion region 810 expand, as illustrated. At a high enough voltage (for example, the first voltage), the two depletion regions (808 and 810) merge, so that a further increase in applied voltage would allow a current to flow and cause switching in the resistive switching device. In such a case, as voltage drop across an unselected cell is low, depletion regions of a non-linear device of the unselected cell do not expand, and little if any current flows through the unselected cell. An exemplified current-voltage (IV) characteristic of the non-linear device is illustrated in FIG. 9.
Other embodiments of the present invention may include variations to what is illustrated and described above. For example, the non-linear device can have an insulator material sandwiched between a first metal and a second metal or having a metal-insulator-metal (MIM) configuration. The non-linear device can also have a first insulator material and a second insulator material sandwiched between the first metal and the second metal or a metal-insulator-insulator-metal (M-I-I-M) configuration depending on the application. Again, the diode having MIM or MIIM configuration can be disposed between the resistive switching element and the first electrode. And alternatively, the non-linear device having MIM or MIIM configuration can be disposed between the resistive switching element and the second electrode, depending on the application.
The present invention has been exemplified using silver electrode and amorphous silicon material as resistive switching material. The non-linear device can be applied to any two terminal devices to prevent leakage current from proper operation of the two terminal device. Therefore though the present invention has been described using various examples and embodiments, it is also understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or alternatives in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application and scope of the appended claims.

Claims

1-22. (canceled)

23. A method for a memory device from an array of memory devices comprising a first bottom electrode and a second bottom electrode, a first top electrode and a second top electrode, a first memory cell disposed between the first bottom electrode and the first top electrode, a second memory cell disposed between the first bottom electrode and the second top electrode, a third memory cell disposed between the second bottom electrode and the first top electrode, and a fourth memory cell disposed between the second bottom electrode and the second top electrode, wherein each memory device from the array of memory devices comprises a resistive switching material in series with a non-linear device, wherein the non-linear device includes a substantially conductive and a substantially non-conductive state, the method including:

applying a read voltage between the first top electrode and the first bottom electrode to cause a non-linear device of the first memory cell to be in the substantially conductive state, wherein a non-linear device of the second memory cell remains in the substantially non-conductive state, wherein a non-linear device of the third memory cell remains in the substantially non-conductive state, and wherein a non-linear device of the second memory cell remains in the substantially non-conductive state; and

determining a current flow between the first top electrode and the first bottom electrode in response to the read voltage.

24. The method of claim 23 wherein determining the current flow comprises: determining a current flow through the resistive switching material in response to the read voltage.

25. The method of claim 24

wherein the current flow through the resistive switching material is high when the resistive switching material is in a programmed state; and

wherein the current flow through the resistive switching material is low when the resistive switching material is in an erase state.

26. The method of claim 23 further comprising applying an erase voltage between the first top electrode and the first bottom electrode to cause the non-linear device of the first memory cell to be in the substantially conductive state and to cause a resistive switching material in the first memory cell to enter or maintain an erase state in response to the erase voltage, wherein the non-linear device of the second memory cell remains in the substantially non-conductive state, wherein the non-linear device of the third memory cell remains in the substantially non-conductive state, and wherein the non-linear device of the fourth memory cell remains in the substantially non-conductive state.

27. The method of claim 23 further comprising applying a programming voltage between the first top electrode and the first bottom electrode to cause the non-linear device of the first memory cell to be in the substantially conductive state and to cause a resistive switching material in the first memory cell to enter or maintain a programmed state in response to the programming voltage, wherein the non-linear device of the second memory cell remains in the substantially non-conductive state, wherein the non-linear device of the third memory cell remains in the substantially non-conductive state, and wherein the non-linear device of the fourth memory cell remains in the substantially non-conductive state.

28. The method of claim 23 wherein the resistive switching material is selected from a group consisting of: an amorphous silicon material, a microcrystalline silicon material, a macro crystalline silicon material, a silicon germanium material.

29. The method of claim 23 wherein the first top electrode is selected from a group consisting of: aluminum, nickel, silver, gold, palladium, and platinum.

30. The method of claim 23 further comprising applying the read voltage between the second top electrode and the first bottom electrode to cause the non-linear device of the second memory cell to be in the substantially conductive state, wherein the non-linear device of the first memory cell remains in the substantially non-conductive state, wherein the non-linear device of the third memory cell remains in the substantially non-conductive state, and wherein the non-linear device of the second memory cell remains in the substantially non-conductive state; and

determining a current flow between the second top electrode and the first bottom electrode in response to the read voltage.

31. The method of claim 23 further comprising applying the erase voltage between the first top electrode and the second bottom electrode to cause the non-linear device of the third memory cell to be in the substantially conductive state and to cause the resistive switching material in the third memory cell to enter or maintain an erase state in response to the erase voltage, wherein the non-linear device of the second memory cell remains in the substantially non-conductive state, wherein the non-linear device of the first memory cell remains in the substantially non-conductive state, and wherein the non-linear device of the fourth memory cell remains in the substantially non-conductive state.

32. The method of claim 23 further comprising applying the programming voltage between the second top electrode and the second bottom electrode to cause a non-linear device of the fourth memory cell to be in the substantially conductive state and to cause a resistive switching material in the fourth memory cell to enter or maintain a programmed state in response to the programming voltage, wherein the non-linear device of the second memory cell remains in the substantially non-conductive state, wherein the non-linear device of the third memory cell remains in the substantially non-conductive state, and wherein the non-linear device of the first memory cell remains in the substantially non-conductive state.

33. A device including an array of memory devices comprising

a plurality of bottom electrodes including a first bottom electrode and a second bottom electrode;

a plurality of top electrodes comprising a metal material including a first top electrode comprising and a second top electrode;

a plurality of memory cells disposed between the plurality of bottom electrodes and the plurality of top electrodes, wherein the plurality of memory cells includes a first memory cell, a second memory cell, a third memory cell and a fourth memory cell, wherein each memory cell from the plurality of memory cells comprises a resistive switching material layer coupled in series with a non-linear device, wherein the resistive switching material layer is electrically connected to the metal material of one of the plurality of top electrodes, wherein the resistive switching material is associated with a variable resistance, wherein the non-linear device is associated with a substantially conductive or a substantially non-conductive state, wherein the first memory cell is disposed between the first bottom electrode and the first top electrode, wherein the second memory cell is disposed between the first bottom electrode and the second top electrode, wherein the third memory cell is disposed between the second bottom electrode and the first top electrode, and wherein the fourth memory cell is disposed between the second bottom electrode and the second top electrode;

wherein when a read voltage is applied between the first top electrode and the first bottom electrode, a non-linear device of the first memory cell is in the substantially conductive state, a non-linear device of the second memory cell is in the substantially non-conductive state, a non-linear device of the third memory cell is in the substantially non-conductive state, a non-linear device of the fourth memory cell is in the substantially non-conductive state, and a current flows between the first top electrode and the first bottom electrode in response to a resistance of a resistive switching material layer of the first memory cell.

34. The device of claim 33 wherein the current flow between the first top electrode and the first bottom electrode is higher when the resistive switching material layer of the first memory cell is in a programmed state than when the resistive switching material layer of the first memory cell is in an erase state.

35. The device of claim 33 wherein when a program voltage is applied between to the first top electrode and the first bottom electrode, the non-linear device of the first memory cell is in the substantially conductive state, the non-linear device of the second memory cell is in the substantially non-conductive state, the non-linear device of the third memory cell is in the substantially non-conductive state, the non-linear device of the fourth memory cell is in the substantially non-conductive state, and the resistive switching material layer of the first memory cell enters or maintains the programmed state.

36. The device of claim 35 wherein when an erase voltage is applied between to the first top electrode and the first bottom electrode, the non-linear device of the first memory cell is in the substantially conductive state, the non-linear device of the second memory cell is in the substantially non-conductive state, the non-linear device of the third memory cell is in the substantially non-conductive state, the non-linear device of the fourth memory cell is in the substantially non-conductive state, and the resistive switching material layer of the first memory cell enters or maintains the erase state.

37. The device of claim 36 wherein the programmed state of the resistive switching material layer of the first memory cell is associated with a lower resistance than the erase state of the resistive switching material layer of the first memory cell.

38. The device of claim 33 wherein the resistive switching material layer comprises a material selected from a group consisting of: an amorphous silicon material, a microcrystalline silicon material, a macro crystalline silicon material, a silicon germanium material.

39. The device of claim 33 wherein the metal material of the plurality of top electrodes are selected from a group consisting of: aluminum, nickel, silver, gold, palladium, and platinum.

40. The device of claim 33 wherein the non-linear device comprises a metal-insulator-metal configuration.

41. The device of claim 40 wherein the non-line device of the first memory cell is disposed between the resistive switching material layer of the first memory cell and the first bottom electrode.

42. The device of claim 33 wherein the non-linear device comprises a metal-insulator-insulator-metal configuration.

43. A method for a memory device from an array of memory cells comprising a plurality of bottom electrodes including bottom electrode and a second bottom electrode, a plurality of top electrodes including a first top electrode and a second top electrode, wherein memory cells from the array of memory cells each comprise a resistive switching material in series with a non-linear device, wherein each memory device from the array of memory devices comprises a resistive switching material in series with a non-linear device, wherein the array of memory cells includes a first memory cell disposed between the first bottom electrode and the first top electrode, a second memory cell disposed between the first bottom electrode and the second top electrode, a third memory cell disposed between the second bottom electrode and the first top electrode, and a fourth memory cell disposed between the second bottom electrode and the second top electrode, wherein the non-linear device is characterized by a substantially conductive or a substantially non-conductive state, the method including:

applying a programming voltage between the first top electrode and the first bottom electrode to cause a non-linear device of the first memory cell to be in the substantially conductive state and to cause the resistive switching material in the first memory cell to enter or maintain a programmed state in response to the programming voltage, wherein a non-linear device of the second memory cell remains in the substantially non-conductive state, wherein a non-linear device of the third memory cell remains in the substantially non-conductive state, and wherein a non-linear device of the fourth memory cell remains in the substantially non-conductive state.

44. The method of claim 43 further comprising:

applying an erase voltage between the first top electrode and the first bottom electrode to cause a non-linear device of the first memory cell to be in the substantially conductive state and to cause the resistive switching material in the first memory cell to enter or maintain an erase state in response to the erase voltage, wherein the non-linear device of the second memory cell remains in the substantially non-conductive state, wherein the non-linear device of the third memory cell remains in the substantially non-conductive state, and wherein the non-linear device of the fourth memory cell remains in the substantially non-conductive state.