WO2018059232A1 - 锁相放大器测试结构和方法 - Google Patents

锁相放大器测试结构和方法 Download PDF

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WO2018059232A1
WO2018059232A1 PCT/CN2017/101493 CN2017101493W WO2018059232A1 WO 2018059232 A1 WO2018059232 A1 WO 2018059232A1 CN 2017101493 W CN2017101493 W CN 2017101493W WO 2018059232 A1 WO2018059232 A1 WO 2018059232A1
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signal
amplifier
lock
noise
switch
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PCT/CN2017/101493
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English (en)
French (fr)
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邓仕发
潘奕
李辰
丁庆
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深圳市太赫兹科技创新研究院
深圳市太赫兹系统设备有限公司
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Publication of WO2018059232A1 publication Critical patent/WO2018059232A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere

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  • the present invention relates to the field of amplifier testing technology, and in particular to a lock phase amplifier testing structure and method.
  • the lock-in amplifier of the coherent detection technology is usually used for measurement.
  • the general test method uses the chopper to perform the modulation measurement.
  • the chopper cannot flexibly simulate the noise of multiple frequency bands and a wide range of amplitudes.
  • the signal has great limitations on the performance test of the lock-in amplifier.
  • a lock-in amplifier test structure comprising a lock-in amplifier and a test signal generating device and a reference signal generating device for testing a lock-in amplifier parameter, the test signal generating device being connected to a signal input end of a lock-in amplifier, the reference The signal generating device is connected to the reference signal end of the lock-in amplifier, wherein the test signal generating device comprises:
  • a signal source module for generating a pure signal
  • noise module for generating noise
  • An adding circuit wherein the two input terminals are respectively connected to the signal source module and the noise module, and are used for superposing the pure signal and the noise to obtain a test signal for inputting the lock-in amplifier;
  • the branch of the signal source module connected to the adding circuit is provided with a first switch, and the branch of the noise module connected to the adding circuit is provided with a second switch.
  • the pure signal amplitude and frequency produced by the signal source module are adjustable.
  • the signal source module includes a first adjustable resistor, a second adjustable resistor, a first sine wave generating circuit, and a first operational amplifier, the first adjustable resistor and the first sine wave generating circuit The input terminal is connected, the second adjustable resistor is connected to an output end of the first sine wave generating circuit, and the second adjustable resistor is connected to a positive input terminal of the first operational amplifier.
  • the noise signal amplitude and frequency produced by the noise module are adjustable.
  • the noise module includes a third adjustable resistor, a fourth adjustable resistor, a second sine wave generating circuit, and a second operational amplifier, the third adjustable resistor and the second sine wave generating circuit.
  • the input terminal is connected
  • the fourth adjustable resistor is connected to the output end of the second sine wave generating circuit
  • the fourth adjustable resistor is connected to the positive input terminal of the second operational amplifier.
  • the first switch is a single pole double throw switch, wherein the fixed end of the single pole double throw switch is connected to the input end of the adding circuit, and one of the two select terminals is connected to the output end of the signal source module, and the other is grounded.
  • the second switch is a single pole double throw switch, wherein the fixed end of the single pole double throw switch is connected to the input end of the adding circuit, and one of the two select terminals is connected to the output end of the noise module and the other is grounded.
  • the adding circuit includes a third operational amplifier, a fourth operational amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor, and the selected end of the first resistor Connecting the first switch, the other end is connected to the positive input terminal of the third operational amplifier, the selected end of the second resistor is connected to the second switch, and the other end is connected to the third operation a positive input end of the amplifier, a selected end of the third resistor is connected to a negative input terminal of the third operational amplifier, and the other end is grounded, and a selected end of the fourth resistor is connected to a positive input terminal of the third operational amplifier Connected, the other end is grounded, the fifth resistor is connected in parallel with the third operational amplifier, and the fourth operational amplifier is connected to the output of the third operational amplifier.
  • a test method for a lock-in amplifier comprising:
  • the correction parameters of the post filter in the lock-in amplifier are obtained, and according to The correction parameter corrects the post filter
  • test signal output by the test signal generating device is an alias signal of pure signal and noise
  • the step of acquiring the correction parameters of the post filter in the lock-in amplifier in the pure noise mode comprises:
  • the correction parameters of the post filter are calculated based on the amplitude and frequency of the plurality of output signals at different time constants.
  • the pure signal and the noise signal are selected by the first switch and the second switch, the pure signal and the noise signal are superimposed by the adding circuit, and the output superimposed signal is input to the lock-in amplifier for testing.
  • the test signal can be made pure noise or aliased signal, so that the noise immunity of the lock-in amplifier can be tested in different noise frequency ranges and amplitude ranges, and the noise distribution of the reference signal with very close frequency is obtained.
  • the measurement of other parameters of the lock-in amplifier is obtained.
  • FIG. 1 is a structural block diagram of a test structure of a lock-in amplifier in an embodiment.
  • FIG. 2 is a block diagram showing the structure of a test signal generating device in a test structure of a lock-in amplifier according to an embodiment
  • FIG. 3 is a circuit diagram of a test signal generating device in a test structure of a lock-in amplifier in an embodiment
  • FIG. 4 is a schematic flow chart of a test method of a lock-in amplifier in an embodiment
  • FIG. 5 is a flow chart showing the steps of acquiring the correction parameters of the post filter in the lock-in amplifier in the pure noise mode in an embodiment.
  • FIG. 1 is a structural block diagram of a test structure of a lock-in amplifier in an embodiment.
  • a lock-in amplifier 300, a test signal generating device 100 for testing the lock-in amplifier parameters, and a reference signal generating device 200 are included.
  • the test signal generating device 100 is connected to a signal input terminal of the lock-in amplifier 300
  • the reference signal generating device 200 is connected to a reference signal terminal of the lock-in amplifier 300.
  • the original signal is output after the debugging of the lock-in amplifier 300.
  • Lock-in amplifiers are usually used to detect weak signals. Generally, a chopper system is used to modulate the signal under test into a periodic signal with correlation before and after.
  • the lock-in amplifier inputs the AC signal, the output is the DC signal, the input and output are proportional, and the proportional coefficient is the total gain of the lock-in amplifier.
  • the last detected signal is proportional to the amplitude of the input signal.
  • the common method of debugging test is to use chopper for modulation measurement, but the chopper can not flexibly simulate noise signals of various frequency bands and wide range amplitudes, which has great limitations on the performance test of lock-in amplifiers.
  • the test signal generating device 100 includes a signal source module 120, a noise module 140, and an adding circuit 160.
  • the test signal generating device 100 is for generating a test signal.
  • the signal source module 120 is used to generate a pure signal.
  • the noise module 140 is used to generate a noise signal.
  • the two input terminals of the adding circuit 160 are respectively connected to the signal source module 120 and the noise module 140 for superimposing the pure signal and noise to obtain a test signal for input to the lock-in amplifier.
  • the pure signal and the noise signal are selected by the first switch and the second switch, the pure signal and the noise signal are superimposed by the adding circuit, and the output superimposed signal is input to the lock-in amplifier for testing.
  • the test signal can be made pure noise or aliased signal, so that the noise immunity of the lock-in amplifier can be tested in different noise frequency ranges and amplitude ranges, and the wide-range debugging noise signal frequency band and amplitude can be realized. value.
  • the pure signal amplitude and frequency produced by the signal source module are adjustable.
  • it can be realized by an adjustable resistor, and the set signal frequency is output, and then the signal is attenuated by the attenuator to make the original signal reach the set amplitude.
  • the attenuator to make the original signal reach the set amplitude.
  • the signal source module 120 includes the first An adjustable resistor R1, a second adjustable resistor R2, a first sine wave generating circuit 122, and a first operational amplifier 124, wherein the first adjustable resistor R1 is connected to an input end of the first sine wave generating circuit 122, The second adjustable resistor R2 is connected to the output of the first sine wave generating circuit 122, and the second adjustable resistor R2 is connected to the positive input terminal of the first operational amplifier 124.
  • the sine wave generating circuit outputs a signal of a preset frequency.
  • the adjustable resistor can be replaced by a digital potentiometer based on the PC end.
  • the preset original signal frequency is 10KHz
  • the first adjustable resistor R1 is adjusted to cause the circuit to output a 10KHz sine wave signal with an amplitude of 10V.
  • the amplitude modulation is performed by the attenuation circuit.
  • the second adjustable resistor R2 is adjusted to attenuate the signal by 1/50 times.
  • the front-end isolation is performed by the follower and input to the non-inverting input of the adder operational amplifier.
  • the noise signal amplitude and frequency produced by the noise module are adjustable.
  • the adjustable resistor can be used to adjust the adjustable resistor, and then the sine wave generating circuit outputs the set noise signal frequency, and then the signal is attenuated by the attenuator to make the noise signal reach the set amplitude.
  • the noise module 140 includes a third adjustable resistor R3, a fourth adjustable resistor R4, a second sine wave generating circuit 142, and a second operational amplifier 144, and the third adjustable resistor R3.
  • the fourth adjustable resistor R4 is connected to an output end of the second sine wave generating circuit 142, the fourth adjustable resistor R4 and the second operational amplifier 144 The positive input is connected.
  • the sine wave generating circuit outputs a signal of a preset frequency.
  • the adjustable resistor can be replaced by a digital potentiometer based on the PC end.
  • the third adjustable resistor R3 is adjusted to output a signal of a preset frequency.
  • the preset noise signal frequency is 1 MHz
  • the fourth adjustable resistor R4 is adjusted, and the circuit outputs a signal of 1 MHz with an amplitude of 10V.
  • the amplitude adjustment is performed by the attenuation circuit.
  • the fourth adjustable resistor R4 is adjusted, and the noise signal is attenuated by 1/50 times, isolated by the follower, and output to the adder operational amplifier.
  • the non-inverting output The signal generated by the signal generation circuit can also be directly input through an external signal source.
  • the adding circuit 160 may include a third operational amplifier 162, a fourth operational amplifier 164, a first resistor R5, a second resistor R6, a third resistor R7, a fourth resistor R8, and a fifth resistor R9.
  • the first end of the first resistor R5 is connected to the first switch K1, the other end is connected to the positive input terminal of the third operational amplifier 162, and the selected end of the second resistor R6 is connected at one end.
  • the second switch K2 is connected, and the other end is connected to the positive input terminal of the third operational amplifier 162.
  • the selected end of the third resistor R7 is connected to the negative input terminal of the third operational amplifier 162, and the other end is grounded.
  • the selected end of the fourth resistor R8 is connected to the positive input terminal of the third operational amplifier 162.
  • the other end is grounded, the fifth resistor R9 is connected in parallel with the third operational amplifier 162, and the fourth operational amplifier 164 is connected to the output of the third operational amplifier 162.
  • the third operational amplifier 162 is formed by the adding circuit 160 to superimpose the original signal and the noise signal to form a noise source signal, and the noise source signal output signal is as shown in the formula (1):
  • the lock-in amplifier test structure may further include a first switch K1 and a second switch K2, wherein the first switch K1 is a single-pole double-throw switch, wherein the fixed end of the single-pole double-throw switch is connected to the input end of the adding circuit, and two One of the selection terminals is connected to the output of the signal source module and the other is grounded.
  • the second switch K2 is a single-pole double-throw switch, wherein the fixed end of the single-pole double-throw switch is connected to the input end of the adding circuit, and one of the two selecting ends is connected to the output end of the noise module, and the other is grounded.
  • the first switch K1 can be selected between the original signal and the ground plane, and the second switch K2 can be selected between the noise signal and the ground plane. It can form three different test modes: pure noise mode, pure signal mode and aliased signal mode. At the same time, the first switch K1 and the second switch K2 can be replaced by a multi-way switch.
  • test method 4 is a flow chart showing a test method of a lock-in amplifier in an embodiment.
  • the test method is based on the test structure of Figure 1, the steps of which include:
  • Step S402 Control the branch where the first switch is disconnected and the branch where the second switch is connected, so that the test signal output by the test signal generating device is pure noise.
  • Step S404 acquires a correction parameter of the post filter in the lock-in amplifier in the pure noise mode, and corrects the post filter according to the correction parameter.
  • Step S402 controls the branch where the first switch is connected and the branch where the second switch is connected, so that the test signal output by the test signal generating device is an alias signal of pure signal and noise.
  • Step S406 tests the parameters of the lock-in amplifier.
  • test preparation is required before the test, and the phase lock amplification circuit and the test circuit are to be used.
  • the reference signal source is connected as shown in Figure 1.
  • the frequency of the original signal in the test circuit is set to 10KHz, and the amplitude is adjusted according to the test.
  • the output signal of the reference source has the same frequency as the frequency.
  • the second switch when the first switch is turned off, the pure noise mode is entered at this time.
  • the correction parameters of the post filter in the lock-in amplifier are acquired, and the post filter is corrected according to the correction parameter.
  • the second switch is connected and the first switch is closed, the aliasing mode is entered, so that the test signal output by the test signal generating device is an alias signal of pure signal and noise.
  • the parameters of the lock-in amplifier are tested. Observe the noise distribution when the frequency is very close to the reference signal.
  • the parameters of the phase locker include sensitivity, overload level, resolution, dynamic range, etc.
  • the circuit enters the pure signal mode, the input signal and the reference signal of the lock-in amplifier are pure sinusoidal signals, and the phase shift of the adjustment reference signal and the original signal is 0°.
  • the value of the output signal is the maximum value, which is proportional to the amplitude of the original signal.
  • the pure signal and the noise signal are selected by the first switch and the second switch, the pure signal and the noise signal are superimposed by the adding circuit, and the output superimposed signal is input to the lock-in amplifier for testing.
  • the test signal can be made pure noise or aliased signal, so that the noise immunity of the lock-in amplifier can be tested in different noise frequency ranges and amplitude ranges, and the noise distribution of the reference signal with very close frequency is obtained.
  • V FS Full Scale Sensitivity
  • Overload level V OVL Record the input level value when the lock-in amplifier is overloaded or critically overloaded.
  • Input dynamic range DR IN The decibel number of the lock-in amplifier's overload level V OVL to the minimum resolution V MDS ratio, as shown in Equation 4:
  • Output dynamic range DR OUT Record the number of decibels between the full scale sensitivity V FS and the minimum resolution V MDS ratio, as shown in Equation 5:
  • Dynamic reserve DR Record the number of decibels of the overload level V OVL and the full scale sensitivity V FS ratio, as shown in Equation 6:
  • FIG. 5 is a flow chart showing the steps of acquiring the correction parameters of the post filter in the lock-in amplifier in the pure noise mode in an embodiment. include:
  • Step S502 sets the amplitude of the noise to 200 millivolts.
  • Step S504 turns off the post filter of the lock-in amplifier, changes the noise frequency in a range of 5 kHz to 15 kHz under a fixed time constant, and uses a digital multimeter to measure the amplitude and frequency of the output signal to obtain multiple The amplitude and frequency of the output signal.
  • Step S506 changes the time constant, and repeats the above steps to obtain the amplitude and frequency of the plurality of output signals.
  • Step S508 calculates a correction parameter of the post filter according to the amplitude and frequency of the plurality of output signals under different time constants.
  • the circuit When the second switch is connected, when the first switch is turned off, the circuit operates in a pure noise mode.
  • the amplitude of the noise is set to 200 millivolts, and the post filter of the lock-in amplifier is turned off.
  • the noise frequency is changed in the range of 5 kHz to 15 kHz, and the amplitude and frequency of the output signal are measured using a digital multimeter to obtain the amplitude and frequency of the plurality of output signals.
  • the steps of S502 and S504 are repeated to obtain the amplitude and frequency of the plurality of output signals.
  • the correction parameters of the post filter are calculated to further adjust the circuit parameters to make the output more stable.

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Abstract

一种锁相放大器（300）测试结构，其测试信号发生装置（100）包括：信号源模块（120），用于产生纯信号；噪声模块（140），用于产生噪声；加法电路（160），两个输入端分别连接信号源模块（120）和噪声模块（140），用于将纯信号和噪声叠加获得测试信号以输入锁相放大器（300）；其中，信号源模块（120）与加法电路（160）连接的支路上设有第一开关（K1），噪声模块（140）与加法电路（160）连接的支路上设有第二开关(K2)。锁相放大器（300）测试结构通过控制开关，能使得测试信号为纯噪声或者混叠信号，这样在不同的噪声频带范围及幅值范围内对锁相放大器（300）的抗噪声能力进行测试，得到频率很接近的参考信号的噪声分布情况，同时对锁相放大器（300）其他参数的测量。

Description

锁相放大器测试结构和方法 技术领域
本发明涉及放大器测试技术领域，特别是涉及一种锁相放大器测试结构和方法。
背景技术
随着信息时代的发展，许多科研信息需要检测的手段获取。而需要的检测的信号非常微弱的时候，常常会被淹没在噪声中，普通的信号处理方法不足以提取微弱的信号。在微弱信号的检测系统中，通常采用相干检测技术的锁相放大器来测量，一般的测试方法使用斩波器进行调制测量，然而斩波器无法灵活的模拟多种频段及宽范围幅值的噪声信号，对锁相放大器的性能调试测试具有很大的局限性。
发明内容
基于此，有必要针对调试的频段及幅值范围较窄，对锁相放大器的调试局限性大问题，提供一种锁相放大器测试结构和方法。
一种锁相放大器测试结构，包括锁相放大器和对锁相放大器参数进行测试的测试信号发生装置和参考信号发生装置，所述测试信号发生装置与锁相放大器的信号输入端连接，所述参考信号发生装置与锁相放大器的参考信号端连接，其特征在于，所述测试信号发生装置包括：
信号源模块，用于产生纯信号；
噪声模块，用于产生噪声；
加法电路，两个输入端分别连接所述信号源模块和噪声模块，用于将所述纯信号和噪声叠加获得测试信号以输入所述锁相放大器；
其中，所述信号源模块与加法电路连接的支路上设有第一开关，所述噪声模块与加法电路连接的支路上设有第二开关。
在其中一个实施例中，信号源模块产生的纯信号幅度和频率可调。
在其中一个实施例中，信号源模块包括第一可调电阻、第二可调电阻、第一正弦波产生电路以及第一运算放大器，所述第一可调电阻与第一正弦波产生电路的输入端连接，所述第二可调电阻与第一正弦波产生电路的输出端连接，所述第二可调电阻与所述第一运算放大器的正极输入端连接。
在其中一个实施例中，噪声模块产生的噪声信号幅度和频率可调。
在其中一个实施例中，噪声模块包括第三可调电阻、第四可调电阻、第二正弦波产生电路以及第二运算放大器，所述的第三可调电阻与第二正弦波产生电路的输入端连接，所述第四可调电阻与第二正弦波产生电路的输出端连接，所述的第四可调电阻与所述第二运算放大器的正极输入端连接。
在其中一个实施例中，第一开关为单刀双掷开关，其中单刀双掷开关的固定端与加法电路的输入端连接，两个选择端其中一个连接信号源模块的输出端、另一个接地。
在其中一个实施例中，第二开关为单刀双掷开关，其中单刀双掷开关的固定端与加法电路的输入端连接，两个选择端其中一个连接噪声模块的输出端、另一个接地。
在其中一个实施例中，加法电路包括第三运算放大器、第四运算放大器，第一电阻、第二电阻、第三电阻、第四电阻和第五电阻，所述的第一电阻的选择端一端连接所述的第一开关，另一端连接所述的第三运算放大器的正极输入端，所述的第二电阻的选择端一端连接所述的第二开关，另一端连接所述的第三运算放大器的正极输入端，所述的第三电阻的选择端一端与第三运算放大器的负极输入端连接，另一端接地，所述的第四电阻的选择端一端与第三运算放大器的正极输入端连接，另一端接地，所述的第五电阻与所述的第三运算放大器并联连接，所述的第四运算放大器与第三运算放大器的输出端连接。
一种锁相放大器的测试方法，包括：
控制第一开关断开所在支路、第二开关连通所在支路，使测试信号发生装置输出的测试信号为纯噪声；
在纯噪声模式下，获取锁相放大器中的后置滤波器的修正参数，并根据所 述修正参数对后置滤波器进行修正；
控制第一开关连通所在支路、第二开关连通所在支路，使测试信号发生装置输出的测试信号为纯信号和噪声的混叠信号；
测试锁相放大器的参数。
在其中一个实施例中，在纯噪声模式下，获取锁相放大器中的后置滤波器的修正参数的步骤包括：
将噪声的幅值设为200毫伏；
关闭锁相放大器的后置滤波器，在固定的时间常数下，在5千赫兹～15千赫兹的范围内改变噪声频率，并使用数字万用表测量输出信号的幅值和频率，获取多个输出信号的幅值和频率；
改变时间常数，重复上述步骤获取多个输出信号的幅值和频率；
根据不同时间常数下的多个输出信号的幅值和频率，计算后置滤波器的修正参数。
上述锁相放大器测试结构和方法，纯信号与噪声信号经过第一开关和第二开关选择以后，再通过加法电路将纯信号与噪声信号叠加，将输出的叠加信号输入至锁相放大器中进行测试。通过控制开关，能使得测试信号为纯噪声或者混叠信号，这样在不同的噪声频带范围及幅值范围内对锁相放大器的抗噪声能力进行测试，得到频率很接近的参考信号的噪声分布情况，同时对锁相放大器其他参数的测量。
附图说明
图1为一实施例中锁相放大器测试结构的结构框图。
图2为一实施例中锁相放大器测试结构中测试信号发生装置结构框图；
图3为一实施例中锁相放大器测试结构中测试信号发生装置的电路图；
图4为一实施例中锁相放大器的测试方法的流程示意图；
图5为一实施例中纯噪音模式下获取锁相放大器中的后置滤波器的修正参数的步骤的流程示意图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
图1为一实施例中锁相放大器测试结构的结构框图。包括锁相放大器300、对锁相放大器参数进行测试的测试信号发生装置100和参考信号发生装置200。测试信号发生装置100与锁相放大器300的信号输入端连接，所述参考信号发生装置200与锁相放大器300的参考信号端连接。原始信号经过锁相放大器300的调试以后得到输出信号。锁相放大器通常是用来检测微弱信号，一般采用斩波系统将被测信号调制成具有前后相关性的周期信号。锁相放大器输入的是交流信号，输出的是直流信号，输入输出成比例，比例系数为锁相放大器的总增益。最后检测的是与输入信号幅值成正比的信号。调试测试常用的方法是使用斩波器进行调制测量，但斩波器无法灵活的模拟多种频段及宽范围幅值的噪声信号，对锁相放大器的性能调试测试具有很大的局限性。
图2为一实施例中锁相放大器测试结构中测试信号发生装置100的结构框图。测试信号发生装置100包括了信号源模块120、噪声模块140和加法电路160。测试信号发生装置100用于产生测试信号。其中信号源模块120用于产生纯信号。噪声模块140用于产生噪声信号。加法电路160的两个输入端分别连接所述信号源模块120和噪声模块140，用于将所述纯信号和噪声叠加获得测试信号以输入所述锁相放大器。
上述锁相放大器测试结构，纯信号与噪声信号经过第一开关和第二开关选择以后，再通过加法电路将纯信号与噪声信号叠加，将输出的叠加信号输入至锁相放大器中进行测试。通过控制开关，能使得测试信号为纯噪声或者混叠信号，这样能在不同的噪声频带范围及幅值范围内对锁相放大器的抗噪声能力进行测试，实现能宽范围调试噪声信号频段和幅值。
在其中一个实施例中，信号源模块产生的纯信号幅度和频率可调。例如可以通过可调电阻来实现，输出设定的信号频率，然后经衰减器进行信号衰减，使原始信号达到设定的幅值。具体地，如图3所示，信号源模块120包括第一 可调电阻R1、第二可调电阻R2、第一正弦波产生电路122以及第一运算放大器124，所述第一可调电阻R1与第一正弦波产生电路122的输入端连接，所述第二可调电阻R2与第一正弦波产生电路122的输出端连接，所述第二可调电阻R2与所述第一运算放大器124的正极输入端连接。正弦波产生电路输出预设频率的信号。其中可调电阻可以替换成基于PC端通过数字电位器调节。例如，预设的原始信号频率为10KHz，调节第一可调电阻R1使电路输出10KHz的正弦波信号，幅值为10V。再经过衰减电路进行调幅，如需输出幅值为200mV的原始信号，则调节第二可调电阻R2，对信号进行1/50倍衰减。经跟随器进行前后级隔离，输入至加法器运算放大器的同相输入端。
在其中一个实施例中，噪声模块产生的噪声信号幅度和频率可调。例如可以通过可调电阻来实现，调节可调电阻，再经过正弦波发生电路，输出设定的噪声信号频率，然后经衰减器进行信号衰减，使噪声信号达到设定的幅值。具体地，如图3所示，噪声模块140包括了第三可调电阻R3、第四可调电阻R4、第二正弦波产生电路142以及第二运算放大器144，所述第三可调电阻R3与第二正弦波产生电路142的输入端连接，所述第四可调电阻R4与第二正弦波产生电路142的输出端连接，所述第四可调电阻R4与所述第二运算放大器144的正极输入端连接。正弦波产生电路输出预设频率的信号。其中可调电阻可以替换成基于PC端通过数字电位器调节。对于噪声信号，调节第三可调电阻R3，输出预设频率的信号。例如，预设的噪声信号频率为1MHz，调节第四可调电阻R4，电路输出1MHz的信号，幅值为10V。经衰减电路进行幅值调节，如需输出幅值为200mV的噪声信号，则调节第四可调电阻R4，对噪声信号进行1/50倍衰减，经跟随器进行隔离，输出至加法器运算放大器的同相输出端。信号产生电路产生的信号也可通过外部信号源直接输入。
具体地，如图3所示，加法电路160可以包括第三运算放大器162、第四运算放大器164，第一电阻R5、第二电阻R6、第三电阻R7、第四电阻R8和第五电阻R9，所述的第一电阻R5的选择端一端连接所述的第一开关K1，另一端连接所述的第三运算放大器162的正极输入端，所述的第二电阻R6的选择端一端连接所述的第二开关K2，另一端连接所述的第三运算放大器162的正极输入端， 所述的第三电阻R7的选择端一端与第三运算放大器162的负极输入端连接，另一端接地，所述的第四电阻R8的选择端一端与第三运算放大器162的正极输入端连接，另一端接地，所述的第五电阻R9与所述的第三运算放大器162并联连接，所述的第四运算放大器164与第三运算放大器162的输出端连接。其中第三运算放大器162组成加法电路160将原始信号和噪声信号相叠加组成噪声源信号，噪声源信号输出信号如式(1)所示：
Figure PCTCN2017101493-appb-000001
其中，需调节RRP的值，满足式(2)所示；
R1//R2//RRP＝R3//RF    (2)
进一步地，上述锁相放大器测试结构还可以包括第一开关K1和第二开关K2，第一开关K1为单刀双掷开关，其中单刀双掷开关的固定端与加法电路的输入端连接，两个选择端其中一个连接信号源模块的输出端、另一个接地。第二开关K2为单刀双掷开关，其中单刀双掷开关的固定端与加法电路的输入端连接，两个选择端其中一个连接噪声模块的输出端、另一个接地。第一开关K1可在原始信号和地平面之间选择，第二开关K2可在噪声信号和地平面之间选择。可构成纯噪声模式、纯信号模式及混叠信号模式三种不同的测试模式。同时第一开关K1和第二开关K2都可以用多路选通器来替代。
图4为一实施例中锁相放大器的测试方法的流程示意图。该测试方法基于图1的测试结构，其步骤包括：
步骤S402：控制第一开关断开所在支路、第二开关连通所在支路，使测试信号发生装置输出的测试信号为纯噪声。
步骤S404在纯噪声模式下，获取锁相放大器中的后置滤波器的修正参数，并根据所述修正参数对后置滤波器进行修正。
步骤S402控制第一开关连通所在支路、第二开关连通所在支路，使测试信号发生装置输出的测试信号为纯信号和噪声的混叠信号。
步骤S406测试锁相放大器的参数。
在本实施例中，在测试之前需要做测试准备，将锁相放大电路、测试电路 及参考信号源按如图1所示连接，测试电路中的原始信号的频率设置为10KHz，幅值根据测试进行调整。参考信号源的输出信号的频率与的频率一样。当第二开关连通的时候，第一开关断开时，此时进入了纯噪音模式。进入步骤S404，获取锁相放大器中的后置滤波器的修正参数，并根据所述修正参数对后置滤波器进行修正。而当第二开关连通，第一开关闭合的时候，进入混叠模式，使测试信号发生装置输出的测试信号为纯信号和噪声的混叠信号。进入步骤S406，测试锁相放大器的参数。观察频率非常接近参考信号时的噪声分布情况。锁相器的参数包括了灵敏度、过载电平、分辨率、动态范围等进行测量。
同时在第二开关闭合，第一开关连通的时候，电路进入纯信号模式，锁相放大器的输入信号和参考信号为纯正的正弦信号，调整参考信号与原始信号的相移位为0°。此时输出信号的值为最大值，与原始信号幅值成正比例关系。修订参数为k，利用公式输出信号U0＝k·USIGNAL(3)，改变USIGNAL原始信号的幅值VSIGNAL，重复上述过程，记录信号输出UO及修正参数k，求平均修正参数，再代入公式中计算。
上述锁相放大器测试方法，纯信号与噪声信号经过第一开关和第二开关选择以后，再通过加法电路将纯信号与噪声信号叠加，将输出的叠加信号输入至锁相放大器中进行测试。通过控制开关，能使得测试信号为纯噪声或者混叠信号，这样在不同的噪声频带范围及幅值范围内对锁相放大器的抗噪声能力进行测试，得到频率很接近的参考信号的噪声分布情况，同时对锁相放大器其他参数的测量:
满刻度灵敏度VFS：记录输出达到满刻度时，输入端的电平值。
过载电平VOVL：记录锁相放大器出现过载或临界过载时的输入电平值。
分辨率VMDS：逐渐减少输出信号的幅值，记录输出能辨识的最小输入信号。
输入动态范围DRIN：锁相放大器的过载电平VOVL与最小分辨率VMDS比值的分贝数，如式4所示：
Figure PCTCN2017101493-appb-000002
输出动态范围DROUT：记录满刻度灵敏度VFS与最小分辨率VMDS比值的分贝数，如式5所示：
Figure PCTCN2017101493-appb-000003
动态储备DR：记录过载电平VOVL与满刻度灵敏度VFS比值的分贝数，如式6所示：
Figure PCTCN2017101493-appb-000004
图5为一实施例中纯噪音模式下获取锁相放大器中的后置滤波器的修正参数的步骤的流程示意图。包括：
步骤S502将噪声的幅值设为200毫伏。
步骤S504关闭锁相放大器的后置滤波器，在固定的时间常数下，在5千赫兹～15千赫兹的范围内改变噪声频率，并使用数字万用表测量输出信号的幅值和频率，获取多个输出信号的幅值和频率。
步骤S506改变时间常数，重复上述步骤获取多个输出信号的幅值和频率。
步骤S508根据不同时间常数下的多个输出信号的幅值和频率，计算后置滤波器的修正参数。
当第二开关连通的时候，第一开关断开时，电路工作于纯噪声模式，在本实施例中，将噪声的幅值设为200毫伏，关闭锁相放大器的后置滤波器，在固定的时间常数下，在5千赫兹～15千赫兹的范围内改变噪声频率，并使用数字万用表测量输出信号的幅值和频率，获取多个输出信号的幅值和频率。再改变时间常数，重复S502和S504的步骤获取多个输出信号的幅值和频率。根据不同时间常数下的多个输出信号的幅值和频率，计算后置滤波器的修正参数，来进一步调节电路参数，使输出更加稳定。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技 术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

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  1. 一种锁相放大器测试结构，包括锁相放大器和对锁相放大器参数进行测试的测试信号发生装置和参考信号发生装置，所述测试信号发生装置与锁相放大器的信号输入端连接，所述参考信号发生装置与锁相放大器的参考信号端连接，其特征在于，所述测试信号发生装置包括：
    信号源模块，用于产生纯信号；所述纯信号的频率与参考信号的频率一样；
    噪声模块，用于产生噪声；所述噪声模块产生的噪声信号幅度和频率可调，且输出设定幅度和频率的噪声；
    加法电路，两个输入端分别连接所述信号源模块和噪声模块，用于将所述纯信号和噪声叠加获得测试信号以输入所述锁相放大器；
    其中，所述信号源模块与加法电路连接的支路上设有第一开关，所述噪声模块与加法电路连接的支路上设有第二开关。
  2. 根据权利要求1所述的锁相放大器测试结构，其特征在于，所述信号源模块产生的纯信号幅度和频率可调。
  3. 根据权利要求2所述的锁相放大器测试结构，其特征在于，所述信号源模块包括第一可调电阻、第二可调电阻、第一正弦波产生电路以及第一运算放大器，所述第一可调电阻与第一正弦波产生电路的输入端连接，所述第二可调电阻与第一正弦波产生电路的输出端连接，所述第二可调电阻与所述第一运算放大器的正极输入端连接。
  4. 根据权利要求1所述的锁相放大器测试结构，其特征在于，所述噪声模块包括第三可调电阻、第四可调电阻、第二正弦波产生电路以及第二运算放大器，所述的第三可调电阻与第二正弦波产生电路的输入端连接，所述第四可调电阻与第二正弦波产生电路的输出端连接，所述的第四可调电阻与所述第二运算放大器的正极输入端连接。
  5. 根据权利要求1所述的锁相放大器测试结构，其特征在于，所述第一开关为单刀双掷开关，其中单刀双掷开关的固定端与加法电路的输入端连接，两个选择端其中一个连接信号源模块的输出端、另一个接地。
  6. 根据权利要求1所述的锁相放大器测试结构，其特征在于，所述第二开关为单刀双掷开关，其中单刀双掷开关的固定端与加法电路的输入端连接，两个选择端其中一个连接噪声模块的输出端、另一个接地。
  7. 根据权利要求1所述的锁相放大器测试结构，其特征在于，所述加法电路包括第三运算放大器、第四运算放大器，第一电阻、第二电阻、第三电阻、第四电阻和第五电阻，所述的第一电阻的选择端一端连接所述的第一开关，另一端连接所述的第三运算放大器的正极输入端，所述的第二电阻的选择端一端连接所述的第二开关，另一端连接所述的第三运算放大器的正极输入端，所述的第三电阻的选择端一端与第三运算放大器的负极输入端连接，另一端接地，所述的第四电阻的选择端一端与第三运算放大器的正极输入端连接，另一端接地，所述的第五电阻与所述的第三运算放大器并联连接，所述的第四运算放大器与第三运算放大器的输出端连接。
  8. 一种锁相放大器的测试方法，基于权利要求1～7任一项所述的测试结构，包括：
    控制第一开关断开所在支路、第二开关连通所在支路，使测试信号发生装置输出的测试信号为纯噪声；
    在纯噪声模式下，获取锁相放大器中的后置滤波器的修正参数，并根据所述修正参数对后置滤波器进行修正；
    控制第一开关连通所在支路、第二开关连通所在支路，使测试信号发生装置输出的测试信号为纯信号和噪声的混叠信号；
    测试锁相放大器的参数。
  9. 根据权利要求8所述的锁相放大器的测试方法，其特征在于，所述在纯噪声模式下，获取锁相放大器中的后置滤波器的修正参数的步骤包括：
    将噪声的幅值设为200毫伏；
    关闭锁相放大器的后置滤波器，在固定的时间常数下，在5千赫兹～15千赫兹的范围内改变噪声频率，并使用数字万用表测量输出信号的幅值和频率，获取多个输出信号的幅值和频率；
    改变时间常数，重复上述步骤获取多个输出信号的幅值和频率；
    根据不同时间常数下的多个输出信号的幅值和频率，计算后置滤波器的修正参数。
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