Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
  • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
  • H03H7/24—Frequency- independent attenuators
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
  • H03H11/00—Networks using active elements
  • H03H11/02—Multiple-port networks
  • H03H11/24—Frequency-independent attenuators
  • H03H11/245—Frequency-independent attenuators using field-effect transistor
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
  • H01P1/00—Auxiliary devices
  • H01P1/22—Attenuating devices
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
  • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
  • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
  • H03F1/0277—Selecting one or more amplifiers from a plurality of amplifiers
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
  • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
  • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
  • H03F3/195—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
  • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
  • H03F3/211—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/72—Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03G—CONTROL OF AMPLIFICATION
  • H03G1/00—Details of arrangements for controlling amplification
  • H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
  • H03G1/0017—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid-state elements
  • H03G1/0029—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid-state elements using field-effect transistors [FET]
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03G—CONTROL OF AMPLIFICATION
  • H03G1/00—Details of arrangements for controlling amplification
  • H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
  • H03G1/0088—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal using discontinuously variable devices, e.g. switch-operated
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03G—CONTROL OF AMPLIFICATION
  • H03G3/00—Gain control in amplifiers or frequency changers
  • H03G3/20—Automatic control
  • H03G3/30—Automatic control in amplifiers having semiconductor devices
  • H03G3/3036—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers
  • H03G3/3042—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers in modulators, frequency-changers, transmitters or power amplifiers
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03G—CONTROL OF AMPLIFICATION
  • H03G3/00—Gain control in amplifiers or frequency changers
  • H03G3/20—Automatic control
  • H03G3/30—Automatic control in amplifiers having semiconductor devices
  • H03G3/3052—Automatic control in amplifiers having semiconductor devices in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver
  • H03G3/3063—Automatic control in amplifiers having semiconductor devices in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver using at least one transistor as controlling device, the transistor being used as a variable impedance device
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
  • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
  • H03H7/24—Frequency- independent attenuators
  • H03H7/25—Frequency- independent attenuators comprising an element controlled by an electric or magnetic variable
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2200/00—Indexing scheme relating to amplifiers
  • H03F2200/294—Indexing scheme relating to amplifiers the amplifier being a low noise amplifier [LNA]
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2200/00—Indexing scheme relating to amplifiers
  • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
  • H03F2203/72—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
  • H03F2203/7215—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal the gated amplifier being switched on or off by a switch at the input of the amplifier
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
  • H03F2203/72—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
  • H03F2203/7221—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal the gated amplifier being switched on or off by a switch at the output of the amplifier
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03G—CONTROL OF AMPLIFICATION
  • H03G2201/00—Indexing scheme relating to subclass H03G
  • H03G2201/10—Gain control characterised by the type of controlled element
  • H03G2201/106—Gain control characterised by the type of controlled element being attenuating element
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04B—TRANSMISSION
  • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
  • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
  • H04B1/40—Circuits

Definitions

• the present disclosure relates to attenuators for electronic applications.
• a to-be-transmitted signal can be amplified by a power amplifier, and a received signal can be amplified by a low-noise amplifier.
• one or more attenuators can be implemented along either or both of the foregoing transmit and receive paths as needed or desired to attenuate the respective signal(s).
• the present disclosure relates to a radio-frequency (RF) attenuator circuit that includes one or more attenuation blocks arranged in series between an input node and an output node, with each attenuation block including a local bypass path.
• the RF attenuator circuit further includes a global bypass path implemented between the input node and the output node.
• the RF attenuator circuit further includes a phase compensation circuit configured to compensate for an off-capacitance effect associated with at least one of the global bypass path and the one or more local bypass paths.
• the global bypass path can include a global bypass switching transistor configured to be on when in a global bypass mode and off when in a global attenuation mode, such that the global bypass switching transistor provides a global off-capacitance when in the global attenuation mode.
• the phase compensation circuit can include a global phase compensation circuit configured to compensate for the global off-capacitance when the radio-frequency attenuator circuit is in the global attenuation mode.
• the global phase compensation circuit can include a first global compensation resistance and a second global compensation resistance arranged in series between the input node and the output node, and a global compensation capacitance implemented between a ground and a node between the first and second global compensation resistances.
• the global off-capacitance of the global bypass switching transistor can result in a phase lead change, and the global phase compensation circuit can be configured to provide a phase lag change to compensate for the phase lead change.
• the first and second global compensation resistances can have substantially the same value.
• RL load impedance
• RGI the first global compensation resistance
• CG the global compensation capacitance.
• the values of the first global compensation resistance and the global compensation capacitance can be selected such that magnitude of the phase lag change is substantially the same as magnitude of the phase lead change.
• the value of the global compensation capacitance can be selected such that a global gain of the attenuator circuit is approximately flat over a selected frequency range.
• the global compensation capacitance can be configured to be affected substantially the same as the global bypass switching transistor by one or more process variations.
• the global compensation capacitance can be configured as a transistor-like device.
• Each of the transistorlike device of the global compensation capacitance and the global bypass switching transistor can be implemented as a MOSFET device.
• the local bypass path can include a local bypass switching transistor configured to be on when in a local bypass mode and off when in a local attenuation mode, such that the local bypass switching transistor provides a local off-capacitance when in the local attenuation mode.
• the phase compensation circuit can include a local phase compensation circuit configured to compensate for the local off-capacitance when the radio-frequency attenuator circuit is in the local attenuation mode.
• the attenuation block can be configured as a pi-attenuator having a local resistance, a first shunt path implemented between one end of the local resistance and a ground, and a second shunt path implemented between the end of the local resistance and the ground, with each of the first and second shunt paths including a shunt resistance.
• the local phase compensation circuit can include a first local compensation capacitance arranged to be electrically parallel with the first shunt resistance, and a second local compensation capacitance arranged to be electrically parallel with the second shunt resistance.
• the local off-capacitance of the local bypass switching transistor can result in a phase lead change
• the local phase compensation circuit can be configured to provide a phase lag change to compensate for the phase lead change.
• the first and second shunt resistances can have substantially the same value
• the first and second local compensation capacitances can have substantially the same value.
• the phase lag change can be by an amount calculated as ⁇ where ⁇ is 2 ⁇ times frequency, RL is load impedance,
• Ri is the local resistance
• Cc is the first local compensation capacitance
• R2 is an equivalent resistance of a parallel arrangement of the first shunt resistance and the load impedance.
• the value of the first local compensation capacitance can be selected such that magnitude of the phase lag change is substantially the same as magnitude of the phase lead change.
• the value of the local compensation capacitance can be selected such that a local gain of the attenuation block is approximately flat over a selected frequency range.
• each of the first and second local compensation capacitances can be configured to be affected substantially the same as the local bypass switching transistor by one or more process variations.
• Each of the first and second local compensation capacitances can be configured as a transistor-like device.
• Each of the transistor-like device of the first and second local compensation capacitances and the local bypass switching transistor can be implemented as a MOSFET device.
• the one or more attenuation blocks can include a plurality of attenuation blocks having binary-weighted attenuation values.
• the present disclosure relates to a semiconductor die having a radio-frequency circuit.
• the semiconductor die includes a semiconductor substrate, and an attenuator circuit implemented on the semiconductor substrate.
• the attenuator circuit includes one or more attenuation blocks arranged in series between an input node and an output node, with each attenuation block including a local bypass path.
• the attenuator circuit further includes a global bypass path implemented between the input node and the output node.
• the attenuator circuit further includes a phase compensation circuit configured to compensate for an off-capacitance effect associated with at least one of the global bypass path and the one or more local bypass paths.
• the present disclosure relates to a radio-frequency module that includes a packaging substrate configured to receive a plurality of components, and a radio-frequency attenuator circuit implemented on the packaging substrate.
• the attenuator circuit includes one or more attenuation blocks arranged in series between an input node and an output node, with each attenuation block including a local bypass path.
• the attenuator circuit further includes a global bypass path implemented between the input node and the output node.
• the attenuator circuit further includes a phase compensation circuit configured to compensate for an off-capacitance effect associated with at least one of the global bypass path and the one or more local bypass paths.
• some or all of the radio-frequency attenuator circuit can be implemented on a semiconductor die. In some embodiments, substantially all of the radio-frequency attenuator circuit can be implemented on the semiconductor die.
• the radio-frequency module can be configured to process a received radio-frequency signal.
• the radio-frequency module can be a diversity receive module.
• the radio-frequency module can further include a controller in communication with the radio-frequency attenuator circuit and configured to provide a control signal for operation of the radio-frequency attenuator circuit.
• the controller can be configured to provide, for example, a Mobile Industry Processor Interface control signal.
• the present disclosure relates to a wireless device that includes an antenna configured to receive a radio-frequency signal, a transceiver in communication with the antenna, and a signal path between the antenna and the transceiver.
• the wireless device further includes a radio-frequency attenuator circuit implemented along the signal path.
• the attenuator circuit includes one or more attenuation blocks arranged in series between an input node and an output node, with each attenuation block including a local bypass path.
• the attenuator circuit further includes a global bypass path implemented between the input node and the output node.
• the attenuator circuit further includes a phase compensation circuit configured to compensate for an off-capacitance effect associated with at least one of the global bypass path and the one or more local bypass paths.
• the wireless device can further include a controller in communication with the radio-frequency attenuator circuit and configured to provide a control signal for operation of the radio-frequency attenuator circuit.
• the controller can be configured to provide, for example, a Mobile Industry Processor Interface control signal.
• the present disclosure relates to a signal attenuator circuit that includes one or more local attenuation blocks arranged in series between an input node and an output node, with each attenuation block including a local bypass path.
• the signal attenuation circuit further includes a global bypass path implemented between the input node and the output node.
• the signal attenuation circuit further includes a global phase compensation circuit configured to compensate for an off-capacitance effect associated with the global bypass path.
• the present disclosure relates to a signal attenuator circuit that includes one or more local attenuation blocks arranged in series between an input node and an output node, with each attenuation block including a local bypass path.
• the signal attenuator circuit further includes a global bypass path implemented between the input node and the output node.
• the signal attenuator circuit further includes a local phase compensation circuit associated at least one of the one or more local attenuation blocks.
• the local phase compensation circuit is configured to compensate for an off-capacitance effect associated with the respective local bypass path.
• the present disclosure relates to a signal attenuator circuit that includes one or more local attenuation blocks arranged in series between an input node and an output node, with each attenuation block including a local bypass path.
• the signal attenuator circuit further includes a global bypass path implemented between the input node and the output node.
• the signal attenuator circuit further includes a global phase compensation circuit configured to compensate for an off-capacitance effect associated with the global bypass path.
• the signal attenuator circuit further includes a local phase compensation circuit associated at least one of the one or more local attenuation blocks.
• the local phase compensation circuit is configured to compensate for an off -capacitance effect associated with the respective local bypass path.
• the present disclosure relates to a semiconductor die that includes a semiconductor substrate, and a signal attenuator circuit implemented on the semiconductor substrate.
• the signal attenuator circuit includes one or more local attenuation blocks arranged in series between an input node and an output node, with each attenuation block including a local bypass path.
• the signal attenuator circuit further includes a global bypass path implemented between the input node and the output node.
• the signal attenuator further includes a global phase compensation circuit configured to compensate for an off-capacitance effect associated with the global bypass path.
• the present disclosure relates to a semiconductor die that includes a semiconductor substrate, and a signal attenuator circuit implemented on the semiconductor substrate.
• the signal attenuator circuit includes one or more local attenuation blocks arranged in series between an input node and an output node, with each attenuation block including a local bypass path.
• the signal attenuator circuit further includes a global bypass path implemented between the input node and the output node.
• the signal attenuator circuit further includes a local phase compensation circuit associated at least one of the one or more local attenuation blocks.
• the local phase compensation circuit is configured to compensate for an off-capacitance effect associated with the respective local bypass path.
• the present disclosure relates to a semiconductor die that includes a semiconductor substrate, and a signal attenuator circuit implemented on the semiconductor substrate.
• the signal attenuator circuit includes one or more local attenuation blocks arranged in series between an input node and an output node, with each attenuation block including a local bypass path.
• the signal attenuator circuit further includes a global bypass path implemented between the input node and the output node, and a global phase compensation circuit configured to compensate for an off-capacitance effect associated with the global bypass path.
• the signal attenuator circuit further includes a local phase compensation circuit associated at least one of the one or more local attenuation blocks.
• the local phase compensation circuit is configured to compensate for an off-capacitance effect associated with the respective local bypass path.
• the present disclosure relates to a radio-frequency module that includes a packaging substrate configured to receive a plurality of components, and a signal attenuator circuit implemented on the packaging substrate.
• the signal attenuator circuit includes one or more local attenuation blocks arranged in series between an input node and an output node, with each attenuation block including a local bypass path.
• the signal attenuator circuit further includes a global bypass path implemented between the input node and the output node.
• the signal attenuator further includes a global phase compensation circuit configured to compensate for an off-capacitance effect associated with the global bypass path.
• the present disclosure relates to a radio-frequency module that includes a packaging substrate configured to receive a plurality of components, and a signal attenuator circuit implemented on the packaging substrate.
• the signal attenuator circuit includes one or more local attenuation blocks arranged in series between an input node and an output node, with each attenuation block including a local bypass path.
• the signal attenuator circuit further includes a global bypass path implemented between the input node and the output node.
• the signal attenuator circuit further includes a local phase compensation circuit associated at least one of the one or more local attenuation blocks.
• the local phase compensation circuit is configured to compensate for an off-capacitance effect associated with the respective local bypass path.
• the present disclosure relates to a radio-frequency module that includes a packaging substrate configured to receive a plurality of components, and a signal attenuator circuit implemented on the packaging substrate.
• the signal attenuator circuit includes one or more local attenuation blocks arranged in series between an input node and an output node, with each attenuation block including a local bypass path.
• the signal attenuator circuit further includes a global bypass path implemented between the input node and the output node, and a global phase compensation circuit configured to compensate for an off-capacitance effect associated with the global bypass path.
• the signal attenuator circuit further includes a local phase compensation circuit associated at least one of the one or more local attenuation blocks.
• the local phase compensation circuit is configured to compensate for an off-capacitance effect associated with the respective local bypass path.
• the present disclosure relates to a wireless device that includes an antenna configured to receive a radio-frequency signal, a transceiver in communication with the antenna, a signal path between the antenna and the transceiver.
• the wireless device further includes a signal attenuator circuit implemented along the signal path.
• the signal attenuator circuit includes one or more local attenuation blocks arranged in series between an input node and an output node, with each attenuation block including a local bypass path.
• the signal attenuator circuit further includes a global bypass path implemented between the input node and the output node.
• the signal attenuator further include a global phase compensation circuit configured to compensate for an off-capacitance effect associated with the global bypass path.
• the present disclosure relates to a wireless device that includes an antenna configured to receive a radio-frequency signal, a transceiver in communication with the antenna, a signal path between the antenna and the transceiver.
• the wireless device further includes a signal attenuator circuit implemented along the signal path.
• the signal attenuator circuit includes one or more local attenuation blocks arranged in series between an input node and an output node, with each attenuation block including a local bypass path.
• the signal attenuator circuit further includes a global bypass path implemented between the input node and the output node.
• the signal attenuator circuit further includes a local phase compensation circuit associated at least one of the one or more local attenuation blocks.
• the local phase compensation circuit is configured to compensate for an off-capacitance effect associated with the respective local bypass path.
• the present disclosure relates to a wireless device that includes an antenna configured to receive a radio-frequency signal, a transceiver in communication with the antenna, a signal path between the antenna and the transceiver.
• the wireless device further includes a signal attenuator circuit implemented along the signal path.
• the signal attenuator circuit includes one or more local attenuation blocks arranged in series between an input node and an output node, with each attenuation block including a local bypass path.
• the signal attenuator circuit further includes a global bypass path implemented between the input node and the output node, and a global phase compensation circuit configured to compensate for an off-capacitance effect associated with the global bypass path.
• the signal attenuator circuit further includes a local phase compensation circuit associated at least one of the one or more local attenuation blocks.
• the local phase compensation circuit is configured to compensate for an off -capacitance effect associated with the respective local bypass path.
• Figure 1 depicts an attenuator circuit configured to receive a signal at an input node and generate an attenuated signal at an output node.
• Figure 2 shows a block diagram of an attenuation circuit having a bypass path, a global phase compensation circuit, and a local phase compensation circuit.
• Figure 3 shows an attenuation circuit that can be a more specific example of the attenuation circuit of Figure 2.
• Figure 4 shows an individual local attenuation block that can represent each of the three example attenuation blocks of Figure 3.
• Figure 5 shows a circuit representation of the example attenuation block of Figure 4, in which the various switching transistors are represented as either off-capacitance(s) or on-resistance(s).
• Figure 6 shows an attenuation circuit similar to the example of Figure 3, but with the local attenuation blocks collectively depicted together.
• Figure 7 shows a circuit representation of the global bypass path and the global phase compensation circuit of Figure 6.
• Figure 8 shows a circuit representation that is similar to the circuit representation of Figure 5.
• Figure 9 shows an example of how process variation can impact phase changes in an attenuator circuit, and how such phase changes can be compensated.
• Figure 10 shows an example of a global bypass operating mode for the attenuation circuit of Figure 3.
• Figure 1 1 shows an example of an attenuation operating mode for the attenuation circuit of Figure 3, in which attenuation is being provided by the first attenuation block, and each of the second and third attenuation blocks is being bypassed.
• Figure 12 shows another example of an attenuation operating mode for the attenuation circuit of Figure 3, in which attenuation is being provided by the second and third attenuation blocks, and the first attenuation block is being bypassed.
• Figure 13 shows that in some embodiments, the global bypass switch transistor can have width and length dimensions, and for a given length, insertion loss at the global bypass switch transistor (when ON) generally decreases when the quantity width increases.
• Figure 14 shows that a mismatch level of the attenuation circuit can vary significantly from some uniform level when the size of the global bypass switch transistor increases.
• Figure 15 shows a plot of an attenuation level that decreases from a desired level, as the transistor size increases.
• Figure 16 shows that in some embodiments, an attenuation level can decrease from a desired level sooner as the transistor size is increased, for a higher frequency.
• Figure 17A shows a local compensation path that includes a local compensation capacitance.
• Figure 17B shows that in some embodiments, the capacitance of Figure 17A can be implemented as a transistor device configured to provide a desired capacitance value.
• Figure 18 shows that in some embodiments, an attenuation circuit having one or more features as described herein can be controlled by a controller.
• Figure 19 shows that in some embodiments, some or all of an attenuation circuit having one or more features as described herein can be implemented on a semiconductor die.
• Figure 20 shows an example where some or all of an attenuation circuit having one or more features as described herein can be implemented on a packaged module, and such a packaged module can include a semiconductor die similar to the example of Figure 19.
• Figure 21 shows another example where some or all of an attenuation circuit having one or more features as described herein can be implemented on a packaged module, and such a packaged module can include a plurality of semiconductor die.
• Figure 22 shows non-limiting examples of how an attenuator having one or more features as described herein can be implemented in a radio- frequency system.
• Figure 23 shows an example of a diversity receive module that includes an attenuator having one or more features as described herein.
• Figure 24 depicts an example wireless device having one or more advantageous features described herein.
• circuits, devices and methods related to attenuators that can be utilized in, for example, radio- frequency (RF) applications.
• RF radio- frequency
• Figure 1 depicts an attenuator circuit 100 configured to receive an RF signal at an input node (IN) and generate an attenuated RF signal at an output node (OUT).
• Such an attenuator circuit can include one or more features as described herein so as to provide desirable functionalities such as phase shift compensation, gain compensation, and low loss bypass capability.
• phase compensation can provide, for example, an approximately zero phase shift resulting from an attenuation block and/or the attenuator circuit itself.
• gain compensation can provide, for example, an approximately flat gain over a frequency range.
• the attenuation circuit 100 of Figure 1 can include a global compensation scheme and/or a local compensation scheme to address the phase variation problem.
• such compensation schemes can be configured to address sources of such phase variations.
• such compensation schemes can also provide an approximately flat gain over a relatively wide frequency range.
• such compensation schemes can also provide a bypass path having relatively low loss which is desirable for keeping signal attenuation to a minimum under some situations (e.g., when an attenuation path is not being used).
• an attenuation circuit can also be referred to as an attenuator assembly or simply an attenuator. Description of such an attenuation circuit, attenuator assembly, attenuator, etc. can apply to one or more attenuation blocks (also referred to herein as local attenuation), overall attenuation circuit (also referred to herein as global attenuation), or any combination thereof.
• Figure 2 shows a block diagram of an attenuation circuit 100 configured to receive an RF signal at its input node (IN) and provide an output RF signal at its output node (OUT).
• Such an output RF signal can be attenuated by one or more attenuation values, or be substantially the same as the input RF signal (e.g., through bypass functionality) when attenuation is not desired. Examples of how such attenuation values and bypass functionality can be implemented are described herein in greater detail. Also described herein are examples of how phase compensation can be implemented at a local attenuation level, at a global level, or any combination thereof.
• the input (IN) and output (OUT) nodes of the attenuation circuit 100 can be coupled through one or more attenuation blocks 102a, 102b, 102c, or through a bypass path 106.
• each of two switches S1 , S2 can be closed, and the bypass path 106 can be configured appropriately.
• each of the switches S1 , S2 can be opened, and the bypass path 106 can be configured appropriately. Examples of such attenuation blocks and bypass path are described herein in greater detail.
• an attenuation path is depicted as having three example attenuation blocks A, B and C.
• one or more features of the present disclosure can also be implemented in attenuation circuits having more or less numbers of attenuation blocks. It will also be understood that attenuation circuits having one or more features as described herein can operate in reverse.
• the first example attenuation block 102a is shown to provide A dB attenuation.
• the second and third attenuation blocks 102b, 102c are shown to provide B dB and C dB attenuations, respectively.
• a number of total attenuation values (e.g., A dB, B dB, C dB, A+B dB, A+C dB, B+C dB, A+B+C dB) can be achieved utilizing such attenuation blocks.
• each of the attenuation blocks 102a, 102b, 102c is shown to include a respective local phase compensation circuit (104a, 104b or 104c). Examples related to such local phase compensation circuits are described herein in greater detail.
• all of the attenuation blocks are shown to have respective local phase compensation circuits. However, it will be understood that in some embodiments, one or more attenuation blocks may or may not have such local phase compensation circuit(s).
• the attenuation circuit 100 is also shown to include a global phase compensation circuit 108.
• a global phase compensation circuit can be implemented between nodes that are before (1 10) and after (1 12) the attenuation blocks (102a, 102b, 102c). Examples related to such a global phase compensation circuit are described herein in greater detail.
• Attenuation blocks (e.g., 102a, 102b, 102c of Figure 2) having one or more features as described herein can be implemented in a binary-weighted configuration. Examples related to such a binary-weighted configuration are described in U.S. Patent Application No. 15/687,476, entitled BINARY-WEIGHTED ATTENUATOR HAVING COMPENSATION CIRCUIT, the disclosure of which is filed on even date herewith and hereby incorporated by reference herein in its entirety and to be considered part of the specification of the present application.
• FIG. 3 shows an attenuation circuit 100 that can be a more specific example of the attenuation circuit 100 of Figure 2.
• switches S1 and S2 can be implemented as, for example, field-effect transistors (FETs). Accordingly, S1 can be implemented between the input node (IN) and a first node 1 10, and S2 can be implemented between the output node (OUT) and a second node 1 12.
• FETs field-effect transistors
• each of three attenuation blocks 102a, 102b, 102c is shown to include a pi-attenuator configuration and a local bypass path (105a, 105b or 105c).
• the first attenuation block 102a is shown to include resistances R1 A, R2A, R3A arranged in a pi-configuration.
• the resistance R1A is shown to be implemented between input and output nodes of the first attenuation block 102a.
• the resistance R2A is shown to be implemented between the input node and ground; similarly, the resistance R3A is shown to be implemented between the output node and ground.
• a switching FET M2A can be provided between the input node and one end of the resistance R2A, with the other end of the resistance R2A being coupled to ground.
• a switching FET M3A can be provided between the output node and one end of the resistance R3A, with the other end of the resistance R3A being coupled to ground.
• Such switching FETs can be turned ON when attenuation is enabled for the first attenuation block 102a, and be turned OFF when attenuation is bypassed through the local bypass path 105a.
• Such a local bypass path (105a) can include, for example, a switching FET M1A which can be turned OFF when attenuation is enabled for the first attenuation block 102a, and be turned ON when attenuation is bypassed through the local bypass path 105a.
• a switching FET M1A which can be turned OFF when attenuation is enabled for the first attenuation block 102a, and be turned ON when attenuation is bypassed through the local bypass path 105a.
• a capacitance C2A can be provided so as to be electrically parallel with the resistance R2A.
• a capacitance C3A can be provided so as to be electrically parallel with the resistance R3A.
• such capacitances can be selected to compensate for phase-shifting that occurs when an RF signal is passed through the attenuation block.
• such capacitances can also allow the attenuation block to provide a desirably flat gain profile over a relatively wide frequency range.
• the second attenuation block 102b is shown to include resistances R1 B, R2B, R3B arranged in a pi-configuration.
• the resistance R1 B is shown to be implemented between input and output nodes of the second attenuation block 102b.
• the resistance R2B is shown to be implemented between the input node and ground; similarly, the resistance R3B is shown to be implemented between the output node and ground.
• a switching FET M2B can be provided between the input node and one end of the resistance R2B, with the other end of the resistance R2B being coupled to ground.
• a switching FET M3B can be provided between the output node and one end of the resistance R3B, with the other end of the resistance R3B being coupled to ground.
• Such switching FETs (M2B and M3B) can be turned ON when attenuation is enabled for the second attenuation block 102b, and be turned OFF when attenuation is bypassed through the local bypass path 105b.
• Such a local bypass path (105b) can include, for example, a switching FET M1 B which can be turned OFF when attenuation is enabled for the second attenuation block 102b, and be turned ON when attenuation is bypassed through the local bypass path 105b.
• a capacitance C2B can be provided so as to be electrically parallel with the resistance R2B.
• a capacitance C3B can be provided so as to be electrically parallel with the resistance R3B.
• such capacitances can be selected to compensate for phase-shifting that occurs when an RF signal is passed through the attenuation block.
• such capacitances can also allow the attenuation block to provide a desirably flat gain profile over a relatively wide frequency range.
• the third attenuation block 102c is shown to include resistances R1 c, R2c, R3c arranged in a pi-configuration.
• the resistance R1 c is shown to be implemented between input and output nodes of the third attenuation block 102c.
• the resistance R2c is shown to be implemented between the input node and ground; similarly, the resistance R3c is shown to be implemented between the output node and ground.
• a switching FET M2c can be provided between the input node and one end of the resistance R2c, with the other end of the resistance R2c being coupled to ground.
• a switching FET M3c can be provided between the output node and one end of the resistance R3c, with the other end of the resistance R3c being coupled to ground.
• Such switching FETs can be turned ON when attenuation is enabled for the third attenuation block 102c, and be turned OFF when attenuation is bypassed through the local bypass path 105c.
• Such a local bypass path (105c) can include, for example, a switching FET M1 c which can be turned OFF when attenuation is enabled for the third attenuation block 102c, and be turned ON when attenuation is bypassed through the local bypass path 105c.
• a capacitance C2c can be provided so as to be electrically parallel with the resistance R2c.
• a capacitance C3c can be provided so as to be electrically parallel with the resistance R3c.
• capacitances can be selected to compensate for phase-shifting that occurs when an RF signal is passed through the attenuation block.
• capacitances can also allow the attenuation block to provide a desirably flat gain profile over a relatively wide frequency range.
• each of the attenuation blocks 102a, 102b, 102c the presence of the capacitances C2 and C3 in parallel with their respective resistances R2 and R3 allows phase compensation as described herein. As also described herein, such phase compensation can also depend on values of the resistances R2 and R3, as well as on-resistance values (Ron) of the switching transistors M2 and M3. Accordingly, it will be understood that a box indicated as 104a, 104b or 104c includes some or all of circuit elements of a respective local phase compensation circuit, or includes some or all of circuit elements that can influence such local phase compensation.
• a bypass path 106 can be provided between the input node (IN) and the output node (OUT) so as to allow an RF signal to bypass the foregoing attenuation blocks (102a, 102b, 102c).
• a bypass path also bypasses the switches S1 and S2 to not incur any losses that may be associated with such switches.
• the bypass path 106 can include a switching FET SBypass implemented to be turned ON when bypassing of the attenuation blocks (102a, 102b, 102c) is desired. In such a state, each of the switches S1 and S2 can be turned OFF. The switching FET SBypass can be turned OFF when attenuation through one or more of the attenuation blocks is desired. In such a state, each of the switches S1 and S2 can be turned ON.
• a global phase compensation circuit 108 can be provided to compensate for a phase shift that can result from the foregoing bypass circuit 106.
• a phase shift that can result from the foregoing bypass circuit 106.
• an off-capacitance value Coff is present; and such Coff can cause a phase shift in the RF signal being attenuated.
• the global phase compensation circuit 108 can include first and second resistances RGI and RG2 implemented between the first and second nodes 1 10, 1 12. Further, a capacitance CG can be provided between ground and a node between RGI and RG2. Examples of how such resistance values and capacitance value can be selected to provide desirable phase compensation are described herein in greater detail.
• some or all of the various switching FETs can be implemented as, for example, silicon-on-insulator (SOI) devices. It will be understood that while such various switching FETs are depicted as being NFETs, one or more features of the present disclosure can also be implemented utilizing other types of FETs. It will also be understood that the various switches in the example of Figure 3 can also be implemented as other types of transistors, including non-FET transistors.
• SOI silicon-on-insulator
• Figures 4 and 5 show an example of how phase compensation can be implemented for a given local attenuation block 102.
• Figures 6 and 7 show an example of how global phase compensation can be implemented.
• Figure 4 shows an individual local attenuation block 102, and such an attenuation block can represent each of the three example attenuation blocks 102a, 102b, 102c of Figure 3. Accordingly, reference numerals of the various elements of the attenuation block 102 are shown without subscripts.
• the local attenuation block 102 is in its attenuation mode, such that an RF signal received at the local input node (IN) is attenuated and provided at the local output node (OUT). Accordingly, the local bypass switching FET M1 of the local bypass path 105 is OFF, and each of the switching FETs M2 and M3 of the circuit 104 is ON.
• Figure 5 shows a circuit representation 120 of the example attenuation block 102 of Figure 4, in which the various switching FETs are represented as either off-capacitance(s) or on-resistance(s).
• the OFF state of M1 is represented as an off -capacitance Coff
• the ON state of each of M2 and M3 is represented as an on-resistance Ron.
• M2 can be similar to M3, such that Ron of M2 is approximately the same as Ron of M3; hence, Figure 5 depicts each of M2 and M3 as Ron.
• the circuit representation 120 is shown to have a source impedance Rs at the local input (IN), and a load impedance RL at the local output (OUT).
• Rs source impedance
• RL load impedance
• Such impedance values may or may not be the same.
• values of Rs and RL are assumed to be the same at a characteristic impedance Z0 (e.g., at 50 ⁇ ).
• Equations 1 and 2 the parameter K represents the attenuation value of the attenuation block 120. It is noted that as attenuation becomes larger, R1 generally increases, and R2 generally decreases.
• a portion of the attenuation block 120 can contribute to forward gain and phase shift (e.g., phase lead) of the attenuation block 120 as:
• a portion of the attenuation block 120 can contribute to forward gain and phase shift (e.g., phase lag) of the attenuation block 120 as: (j?2 +i?i)+Sj?2i?i c (5)
• the parameters ⁇ , R L , C off , R x and R 2 are typically set for a given frequency, characteristic impedance, switching FET configuration, and attenuation value.
• the value of the compensation capacitance Cc can be adjusted such that the phase lag of Equation 6 compensates for the phase lead of Equation 4.
• Such phase compensation can allow the phase associated with the attenuation block 102/120 of Figures 4 and 5 to be at or near a desired value.
• the compensated phase associated with the attenuation block 102/120 can have substantially the same phase variation as in a reference mode.
• the compensation capacitance Cc is arranged parallel to the corresponding shunt resistance R2.
• the impedance (l/ ' wQ)) of the compensation capacitance Cc will make an equivalent impedance of the shunt arm become less, resulting in more attenuation for the attenuation block.
• the compensation capacitance Cc can be selected to compensate for the impact of Coff on gain, and thereby achieve a desired gain profile (e.g., approximately flat profile) for the attenuation block over a wide frequency range.
• the compensation capacitance Cc can be selected to provide at least some phase compensation described herein, as well as to provide at least some gain compensation as described herein, for the attenuation block.
• Figure 6 shows an attenuation circuit similar to the example of Figure 3, but with the local attenuation blocks collectively indicated as 102 for simplicity.
• the bypass path 106 and the global phase compensation circuit 108 are substantially the same as in the example of Figure 3.
• the attenuation circuit can be in its attenuation mode, such that an RF signal received at the global input node (IN) is attenuated and provided at the global output node (OUT).
• the global bypass switching FET SBypass of the bypass path 106 can be OFF to provide a global off-capacitance of Coff.
• Figure 7 shows a circuit representation 130 of the global bypass path 106 and the global phase compensation circuit 108 of Figure 6.
• the resistances RGI and RG2 of the global phase compensation circuit 108 are substantially the same.
• the circuit representation 130 is shown to have a source impedance Rs at the global input (IN), and a load impedance RL at the global output (OUT).
• Such impedance values may or may not be the same.
• values of Rs and RL are assumed to be the same at a characteristic impedance Z0 (e.g., at 50 ⁇ ).
• the resistance RGI (and thus RG2 in the foregoing assumption) is also assumed to have a value of 50 ⁇ .
• a portion of the circuit 130 can contribute to forward gain and phase shift (e.g., phase lead) of the circuit 130 as:
• the global compensation capacitance CG is by itself as a shunt capacitance.
• the impedance (l/ ' wQ)) of the global compensation capacitance CG will make an equivalent impedance of the shunt arm become less, resulting in more attenuation for the global attenuation circuit.
• the global compensation capacitance CG can be selected to compensate for the impact of Coff on gain, and thereby achieve a desired gain profile (e.g., approximately flat profile) for the global attenuation circuit over a wide frequency range.
• the global compensation capacitance CG can be selected to provide at least some phase compensation described herein, as well as to provide at least some gain compensation as described herein, for the global attenuation circuit.
• a phase compensation circuit having one or more features as described herein can be configured to account for process variations.
• Figure 8 shows a circuit representation 120 that is similar to the circuit representation 120 of Figure 5 (which corresponds to the example attenuation block 102 of Figure 4).
• the off- capacitance (Coff) of the bypass capacitance results in a phase change that can be compensated by the compensation capacitances Cc.
• the off -capacitance (Coff) in the example of Figure 8 results from the OFF state of a bypass switch transistor which can suffer from process variation (e.g., among a number of such devices fabricated together on a wafer).
• process variation e.g., among a number of such devices fabricated together on a wafer.
• one or more electrical properties, including Coff, of the bypass switch transistor can vary due to such process variation.
• the phase change due to such Coff (e.g., as in Equations 4 or 8) can also vary.
• FIG. 8 shows that such process variation and related effects in Coff can be accounted for in the phase compensation circuit.
• the compensation capacitances Cc in the shunt arms can be configured to be affected by process variation similar to that of the bypass switch transistor (Coff).
• such compensation capacitances Cc can be configured as a transistor or transistor-like device, such that any process variation affecting the bypass switch transistor (Coff) also affects the compensation capacitances Cc.
• the bypass switch transistor having a Coff property is implemented as a MOSFET device
• each of the compensation capacitances Cc can be implemented as a MOSFET or MOSFET-like device.
• any process-related variation in the bypass switch MOSFET also affects the MOSFET devices of the compensation capacitances Cc, thereby substantially removing or reducing the dependence of the compensation capacitances Cc on process variation (e.g., on the process variation manifested in the bypass switch MOSFET).
• Figure 9 shows an example of how process variation can impact phase changes in an attenuator circuit, and how such phase changes can be compensated.
• phase-lead e.g., as in Equation 4
• RC values resulting from three different process corners FF, TT, SS.
• phase-lead typically depends on some combination of resistance and capacitance (e.g. , RC).
• RC capacitance
• removing or reducing process dependence of capacitances and resistances among a given bypass circuit and the corresponding phase compensation circuit can allow the resulting phase compensation to be more effective.
• the removal or reduction of process dependence can allow the resulting phase compensation in the form of phase lag (dashed lines) being more symmetric with the corresponding phase lead, relative to the frequency axis.
• a given phase lead due to the bypass path and the resulting phase lag due to the compensation circuit can be substantially symmetric, such that the net phase change is approximately zero for a range of frequency.
• the FF phase lead and the FF phase lag can be substantially symmetric about the frequency axis, such that the net phase change in a given attenuation block is approximately zero for a range of frequency.
• the TT phase lead (which is different than the FF phase lead due to process variation) can be compensated by the TT phase lag to provide a substantially zero phase change over a range of frequency.
• FIGs 10-12 show examples of different operating modes that can be implemented for the attenuation circuit 100 of Figure 3.
• the attenuation circuit 100 is shown to be in a global bypass mode, in which the global bypass switch SBypass is ON, and each of the switches S1 and S2 is OFF. Accordingly, an RF signal is shown to be routed as indicated by path 140. In such a mode, the RF signal is generally not subjected to a Coff capacitance; thus, undesirable phase shifting generally does not occur.
• the attenuation circuit 100 is shown to be in an attenuation mode in which A dB attenuation is being provided by the first attenuation block, and each of the second and third attenuation blocks is being bypassed. Accordingly, the global bypass switch FET SBypass is OFF, and each of the switches S1 and S2 is ON. Further, the first local bypass switch FET MIA is OFF, and each of the shunt arm switch FETs M2A, M3A is ON, while each of the second and third local bypass switch FETs MIB, MIC is ON.
• the global bypass switch FET SBypass presents a global Coff, and the resulting global phase shift can be compensated as described herein by the global phase compensation circuit 108.
• the first local bypass switch FET MIA presents a local Coff, and the resulting local phase shift can be compensated as described herein by the local phase compensation circuit generally indicated as 104a.
• the attenuation circuit 100 is shown to be in an attenuation mode in which B+C dB attenuation is being provided by the second and third attenuation blocks, and the first attenuation block is being bypassed. Accordingly, the global bypass switch FET SBypass is OFF, and each of the switches S1 and S2 is ON. Further, each of the second and third local bypass switch FETs MIB, MIC is OFF, and each of the shunt arm switch FETs M2B, M3B, IVhc, M3c is ON, while the first local bypass switch FET MIA is ON.
• the global bypass switch FET SBypass presents a global Coff, and the resulting global phase shift can be compensated as described herein by the global phase compensation circuit 108.
• each of the first and second local bypass switch FETs MIB, MIC presents a respective local Coff, and the resulting local phase shift can be compensated as described herein by the respective local phase compensation circuit generally indicated as 104b or 104c.
• Figures 13-16 show examples of how a global bypass switch FET (SBypass) as described herein (e.g., Figures 3 and 10-12) can be configured to provide desired performance when in the global bypass mode and when in the attenuation mode.
• the global bypass switch FET (SBypass) can have width (W) and length (L) dimensions, and for a given L, insertion loss at the global bypass switch FET (when ON) generally decreases when the quantity W/L increases (as shown by a plot 150).
• W width
• L length
• insertion loss at the global bypass switch FET when ON
• the global bypass switch FET can be relatively large.
• a width W of the global bypass switch FET can be as large as about 1 to 2 mm.
• the global bypass switch FET can be a relatively large device, and thus can provide a relatively large parasitic capacitance when in the OFF state (e.g., in the attenuation mode). Such a parasitic capacitance can cause some undesirable effects if not compensated.
• Figure 14 shows that a mismatch level of the attenuation circuit (e.g., 100 in Figure 3) can vary significantly from some uniform level when the size (e.g., W/L, for a given L) of the global bypass switch FET increases.
• a deviation from the uniform level is depicted by a curve 152.
• bypass compensation capacitance CG e.g., in Figure 3
• CG bypass compensation capacitance
• a bypass switch FET such as the global bypass switch FET can be implemented to be relatively large to reduce insertion loss.
• a phase compensation circuit such as the global phase compensation circuit.
• an attenuation circuit such as the example of Figure 3 can provide compensation for phase variation, as well as for gain variation.
• a gain variation can be at least in part due to a parasitic capacitance of the global bypass switch FET (SBypass).
• an attenuation level provided by the attenuation circuit (when in the attenuation mode) can vary from a desired level as the size (e.g., W/L, for a given L) varies.
• Figure 15 shows a plot 156 of an attenuation level that decreases from a desired level, as the FET size (W/L) increases.
• Such an effect typically occurs when an attenuation circuit is operating without global bypass compensation.
• an attenuation circuit includes a global bypass compensation circuit as described herein, attenuation provided by the attenuation circuit remains significantly more uniform (as depicted by a plot 158) as the FET size (W/L) increases.
• FIG. 16 shows that in some embodiments, an attenuation level can decrease from a desired level sooner as the FET size is increased, for a higher frequency.
• operating frequencies f1 , f2, f3 and f4 have values such that f1 ⁇ f2 ⁇ f3 ⁇ f4.
• the largest frequency (f4) signal will have its attenuation begin to deviate first as the FET size is increased.
• the next largest frequency (f3) will begin to deviate next as the FET size is increased.
• the third largest frequency (f2) followed by the smallest frequency (f 1 ) will begin to deviate similarly as the FET size is increased.
• an attenuation level can remain significantly more uniform for a wide range of operating frequencies, when an attenuation circuit operates with a global bypass compensation circuit as described herein.
• Such an approximately uniform attenuation level over a range of frequencies and a range of FET sizes is depicted as a plot 162.
• a local compensation circuit (e.g., 104a, 104b, 104c in Figure 3) can include a local compensation capacitance (e.g., C2A, C3A, C2B, C3B, C2C, C3C in Figure 3, and Cc in Figure 8).
• Figure 17A shows a local compensation path 170 that includes such a local compensation capacitance (indicated as C2).
• Such a local compensation path is also shown to have a resistance R2 in parallel with C2.
• FIG. 17B shows that in some embodiments, the capacitance C2 of Figure 17A can be implemented as a FET device 172 (e.g., as a MOSFET device) configured to provide a desired capacitance value of C2.
• FET device 172 e.g., as a MOSFET device
• source and drain of the FET device 172 can be connected to the two ends of the resistance R2, and a gate of the FET device 172 can be grounded without a gate bias, such that the FET device 172 acts as a capacitance similar to that of C2 of Figure 17A.
• the local compensation capacitance is implemented as in the example of Figure 17B, a number of desirable features can be achieved.
• the local compensation capacitance elements can be fabricated essentially together with the various FETs (e.g., local bypass FETs M1A, M1 B, M1 c in Figure 3).
• the FET devices 172 acting as capacitances are affected by essentially the same process variations that affect the other FETS (including the local bypass FETs M1 A, M1 B, M1 C). Accordingly, process independence can be achieved among, for example, the FET devices 172 and the other FETs.
• FIG 18 shows that in some embodiments, an attenuation circuit 100 (e.g., such as the attenuation circuit 100 of Figure 2) having one or more features as described herein can be controlled by a controller 180.
• a controller can provide various control signals to, for example, operate the various switches to achieve a bypass mode (e.g., as in Figure 10), or to provide various attenuation modes (e.g., as in Figures 1 1 and 12).
• the controller 180 can be configured to include MIPI (Mobile Industry Processor Interface) functionality.
• MIPI Mobile Industry Processor Interface
• Figure 19 shows that in some embodiments, some or all of an attenuation circuit 100 having one or more features as described herein can be implemented on a semiconductor die 200.
• a semiconductor die 200 can include a substrate 202, and at least some of a phase/gain compensation circuit 204 (e.g., either or both of global phase compensation circuit 108 and local phase compensation circuits 104a, 104b, 104c of Figure 3) can be implemented on the substrate 202.
• a phase/gain compensation circuit 204 e.g., either or both of global phase compensation circuit 108 and local phase compensation circuits 104a, 104b, 104c of Figure 3
• some or all of global compensation capacitance CG and local compensation capacitances C2A, C3A, C2B, C3B, C2C, C3C can be implemented as on-die capacitors.
• Figures 20 and 21 show that in some embodiments, some or all of an attenuation circuit 100 having one or more features as described herein can be implemented on a packaged module 300.
• a packaged module 300 can include a packaging substrate 302 configured to receive a plurality of components such as one or more die and one or more passive components.
• the packaged module 300 can include a semiconductor die 200 that is similar to the example of Figure 19. Accordingly, such a die can include some or all of the attenuation circuit 100, with at least some of a phase/gain compensation circuit 204 (e.g., either or both of global phase compensation circuit 108 and local phase compensation circuits 104a, 104b, 104c of Figure 3) being implemented on the die 200.
• a phase/gain compensation circuit 204 e.g., either or both of global phase compensation circuit 108 and local phase compensation circuits 104a, 104b, 104c of Figure 3
• the packaged module 300 can include a first semiconductor die 210 having some of the attenuation circuit 100, while the rest of the attenuation circuit 100 is implemented on another die 212, outside of a die (e.g., on the packaging substrate 302), or any combination thereof.
• some of a phase/gain compensation circuit 204 e.g., either or both of global phase compensation circuit 108 and local phase compensation circuits 104a, 104b, 104c of Figure 3
• the rest of the phase/gain compensation circuit 204 can be implemented on another die 212, outside of a die (e.g., on the packaging substrate 302), or any combination thereof.
• FIG 22 shows non-limiting examples of how an attenuator having one or more features as described herein can be implemented in an RF system 400.
• an RF system can include an antenna 402 configured to facilitate reception and/or transmission of RF signals.
• an RF signal received by the antenna 402 can be filtered (e.g., by a band-pass filter 410) and passed through an attenuator 100 before being amplified by a low- noise amplifier (LNA) 412.
• LNA low- noise amplifier
• Such an LNA-amplified RF signal can be filtered (e.g., by a band-pass filter 414), passed through an attenuator 100, and routed to a mixer 440.
• the mixer 440 can operate with an oscillator (not shown) to yield an intermediate-frequency (IF) signal.
• IF intermediate-frequency
• Such an IF signal can be filtered (e.g., by a band-pass filter 442) and passed through an attenuator 100 before being routed to an intermediate-frequency (IF) amplifier 416.
• IF intermediate-frequency
• Some or all of the foregoing attenuators 100 along the receive path can include one or more features as described herein.
• an IF signal can be provided to an IF amplifier 420.
• An output of the IF amplifier 420 can be filtered (e.g., by a band-pass filter 444) and passed through an attenuator 100 before being routed to a mixer 446.
• the mixer 446 can operate with an oscillator (not shown) to yield an RF signal.
• Such an RF signal can be filtered (e.g. , by a band-pass filter 422) and passed through an attenuator 100 before being routed to a power amplifier (PA) 424.
• the PA-amplified RF signal can be routed to the antenna 402 through an attenuator 100 and a filter (e.g., a band-pass filter 426) for transmission.
• various operations associated with the RF system 400 can be controlled and/or facilitated by a system controller 430.
• a system controller can include, for example, a processor 432 and a storage medium such as a non-transient computer-readable medium (CRM) 434.
• CCM computer-readable medium
• at least some control functionalities associated with the operation of one or more attenuators 100 in the RF system 400 can be performed by the system controller 430.
• an attenuation circuit having one or more features as described herein can be implemented along a receive (Rx) chain.
• a diversity receive (DRx) module can be implemented such that processing of a received signal can be achieved close to a diversity antenna.
• Figure 23 shows an example of such a DRx module.
• a diversity receiver module 300 can be an example of the modules 300 of Figures 20 and 21 .
• such a DRx module can be coupled to an off-module filter 513.
• the DRx module 300 can include a packaging substrate 501 configured to receive a plurality of components and a receiving system implemented on the packaging substrate 501 .
• the DRx module 300 can include one or more signal paths that are routed off the DRx module 300 and made available to a system integrator, designer, or manufacturer to support a filter for any desired band.
• the DRx module 300 of Figure 23 is shown to include a number of paths between the input and the output of the DRx module 300.
• the DRx module 300 is also shown to include a bypass path between the input and the output activated by a bypass switch 519 controlled by the DRx controller 502.
• Figure 23 depicts a single bypass switch 519, in some implementations, the bypass switch 519 may include multiple switches (e.g., a first switch disposed physically close to the input and a second switch disposed physically close to the output). As shown in Figure 23, the bypass path does not include a filter or an amplifier.
• the DRx module 300 is shown to include a number of multiplexer paths including a first multiplexer 51 1 and a second multiplexer 512.
• the multiplexer paths include a number of on-module paths that include the first multiplexer 51 1 , a bandpass filter 613a-613d implemented on the packaging substrate 501 , an amplifier 614a-614d implemented on the packaging substrate 501 , and the second multiplexer 512.
• the multiplexer paths include one or more off-module paths that include the first multiplexer 51 1 , a bandpass filter 513 implemented off the packaging substrate 501 , an amplifier 514, and the second multiplexer 512.
• the amplifier 514 may be a wide-band amplifier implemented on the packaging substrate 501 or may also be implemented off the packaging substrate 501.
• the amplifiers 614a-614d, 514 may be variable-gain amplifiers and/or variable-current amplifiers.
• a DRx controller 502 can be configured to selectively activate one or more of the plurality of paths between the input and the output. In some implementations, the DRx controller 502 can be configured to selectively activate one or more of the plurality of paths based on a band select signal received by the DRx controller 502 (e.g., from a communications controller). The DRx controller 502 may selectively activate the paths by, for example, opening or closing the bypass switch 519, enabling or disabling the amplifiers 614a-614d, 514, controlling the multiplexers 51 1 , 512, or through other mechanisms.
• the DRx controller 502 may open or close switches along the paths (e.g., between the filters 613a-613d, 513 and the amplifiers 614a-614d, 514) or by setting the gain of the amplifiers 614a-614d, 514 to substantially zero.
• some or all of the amplifiers 614a-614d, 514 can be provided with an attenuation circuit 100 having one or more features as described herein.
• each of such amplifiers is shown to have an attenuation circuit 100 implemented on its input side.
• a given amplifier can have an attenuation circuit on its input side and/or on its output side.
• an architecture, device and/or circuit having one or more features described herein can be included in an RF device such as a wireless device.
• a wireless device such as a wireless device.
• Such an architecture, device and/or circuit can be implemented directly in the wireless device, in one or more modular forms as described herein, or in some combination thereof.
• a wireless device can include, for example, a cellular phone, a smart-phone, a hand-held wireless device with or without phone functionality, a wireless tablet, a wireless router, a wireless access point, a wireless base station, etc.
• a wireless device can include, for example, a cellular phone, a smart-phone, a hand-held wireless device with or without phone functionality, a wireless tablet, a wireless router, a wireless access point, a wireless base station, etc.
• Figure 24 depicts an example wireless device 700 having one or more advantageous features described herein.
• one or more attenuators having one or more features as described herein can be implemented in a number of places in such a wireless device.
• a module such as a diversity receive (DRx) module 300 having one or more low-noise amplifiers (LNAs).
• DRx diversity receive
• LNAs low-noise amplifiers
• Such a DRx module can be configured as described herein in reference to Figures 20, 21 and 23.
• an attenuator having one or more features as described herein can be implemented along an RF signal path before and/or after an LNA.
• power amplifiers (PAs) in a PA module 712 can receive their respective RF signals from a transceiver 710 that can be configured and operated to generate RF signals to be amplified and transmitted, and to process received signals.
• the transceiver 710 is shown to interact with a baseband sub-system 708 that is configured to provide conversion between data and/or voice signals suitable for a user and RF signals suitable for the transceiver 710.
• the transceiver 710 is also shown to be connected to a power management component 706 that is configured to manage power for the operation of the wireless device 700. Such power management can also control operations of the baseband sub-system 708 and other components of the wireless device 700.
• the baseband sub-system 708 is shown to be connected to a user interface 702 to facilitate various input and output of voice and/or data provided to and received from the user.
• the baseband sub-system 708 can also be connected to a memory 704 that is configured to store data and/or instructions to facilitate the operation of the wireless device, and/or to provide storage of information for the user.
• the DRx module 300 can be implemented between one or more diversity antennas (e.g., diversity antenna 730) and the ASM 714.
• Such a configuration can allow an RF signal received through the diversity antenna 730 to be processed (in some embodiments, including amplification by an LNA) with little or no loss of and/or little or no addition of noise to the RF signal from the diversity antenna 730.
• Such processed signal from the DRx module 300 can then be routed to the ASM through one or more signal paths.
• a main antenna 720 can be configured to, for example, facilitate transmission of RF signals from the PA module 712. In some embodiments, receive operations can also be achieved through the main antenna.
• a number of other wireless device configurations can utilize one or more features described herein.
• a wireless device does not need to be a multi-band device.
• a wireless device can include additional antennas such as diversity antenna, and additional connectivity features such as Wi-Fi, Bluetooth, and GPS.

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• Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)

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