WO2018036513A1 - 氮化物半导体元件及其制造方法与所应用的封装结构 - Google Patents

氮化物半导体元件及其制造方法与所应用的封装结构 Download PDF

Info

Publication number
WO2018036513A1
WO2018036513A1 PCT/CN2017/098626 CN2017098626W WO2018036513A1 WO 2018036513 A1 WO2018036513 A1 WO 2018036513A1 CN 2017098626 W CN2017098626 W CN 2017098626W WO 2018036513 A1 WO2018036513 A1 WO 2018036513A1
Authority
WO
WIPO (PCT)
Prior art keywords
nitride semiconductor
layer
type
semiconductor device
barrier
Prior art date
Application number
PCT/CN2017/098626
Other languages
English (en)
French (fr)
Inventor
林宏诚
陈宗源
Original Assignee
亿光电子工业股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 亿光电子工业股份有限公司 filed Critical 亿光电子工业股份有限公司
Priority to CN201780045923.0A priority Critical patent/CN109863609A/zh
Publication of WO2018036513A1 publication Critical patent/WO2018036513A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof

Definitions

  • the present invention relates to a semiconductor device and a method of fabricating the same, and, in particular, to a nitride semiconductor device capable of improving luminous efficiency and improving process yield, and a method of fabricating the same.
  • LEDs Light emitting diodes
  • LEDs have advantages such as long life, small size, high shock resistance, low heat generation and low power consumption, and thus have been widely used as indicators or light sources in households and various devices.
  • LEDs have developed toward multiple colors and high brightness, so their applications have expanded to large outdoor billboards, traffic lights and related fields. At present, LEDs have become the main source of illumination for both power saving and environmental protection functions.
  • the present invention provides a plurality of nitride semiconductor elements which can improve luminous efficiency and improve process yield.
  • the present invention also provides a method of fabricating a plurality of nitride semiconductor devices for fabricating the above-described nitride semiconductor device.
  • the present invention also provides various package structures for use in the above-described nitride semiconductor device.
  • the present invention provides a nitride semiconductor device including a P-type nitride semiconductor, an N-type nitride semiconductor, a nitride semiconductor quantum well light-emitting structure, a substrate, and a buffer layer.
  • the nitride semiconductor quantum well light emitting structure is located between the P-type nitride semiconductor and the N-type nitride semiconductor.
  • the substrate includes opposing first and second faces.
  • the buffer layer is between the N-type nitride semiconductor and the first side of the substrate.
  • the nitride semiconductor quantum well light emitting structure has a plurality of well layers and a plurality of barrier layers.
  • the plurality of barrier layers include a first barrier layer disposed closest to the P-type nitride semiconductor, a second barrier layer disposed closest to the N-type nitride semiconductor site, and a plurality of third barrier layers.
  • a plurality of third barrier layers are sandwiched by a plurality of well layers.
  • the thickness of the first barrier layer is less than 100 angstroms (angstrom; ).
  • the thickness of the second barrier layer is greater than the thickness of the first barrier layer.
  • the thickness of the third barrier layer is greater than the thickness of the first barrier layer.
  • the thickness of the second barrier layer is greater than or equal to the above The thickness of the third barrier layer.
  • the thickness of the second barrier layer is less than or equal to the thickness of the third barrier layer.
  • the first barrier layer has a thickness of less than 50 angstroms .
  • the P-type nitride semiconductor includes a P-side stress releasing layer, a high-concentration hole layer, an electron blocking layer, and a P-type ohmic contact layer.
  • the first barrier layer disposed closest to the above is the P-side stress relief layer described above, and the P-type ohmic contact layer disposed at a distance from the first barrier layer, the high-concentration hole layer and the above-mentioned
  • the electron blocking layer is sequentially stacked over the P-side stress releasing layer described above, and the electron blocking layer is sandwiched by the high-concentration hole layer and the P-type ohmic contact layer.
  • the P-side stress relief layer may be a superlattice structure, the material comprising a superlattice structure composed of aluminum gallium nitride (AlGaN) and gallium nitride (GaN). Or a superlattice structure composed of aluminum gallium nitride (Al x GaN) and aluminum gallium nitride (Al y GaN), or aluminum gallium nitride (AlGaN) and aluminum indium gallium nitride (InAlGaN) The superlattice structure is composed of less than 20 pairs of superlattice structures.
  • the high concentration hole layer may be composed of gallium nitride (GaN) or aluminum gallium nitride (AlGaN), and the magnesium concentration of the high concentration hole layer is concentrated. It is higher than the magnesium doping concentration of the P-side stress releasing layer described above and the magnesium doping concentration of the above-described electron blocking layer.
  • the high concentration hole layer has a magnesium (Mg) doping concentration higher than 1 x 10 19 atoms/cm 3 (Atoms/cm 3 ).
  • the electron blocking layer may be composed of aluminum gallium nitride (AlGaN), and the percentage of the aluminum component of the electron blocking layer is higher than the percentage of the aluminum component of the P-side stress releasing layer and higher than The percentage of aluminum component of the above-mentioned high concentration hole layer.
  • AlGaN aluminum gallium nitride
  • the P-type ohmic contact layer may be composed of gallium nitride (GaN), and the magnesium doping concentration of the P-type ohmic contact layer is higher than the magnesium doping concentration of the electron blocking layer. .
  • the high concentration hole layer has a magnesium (Mg) doping concentration higher than 1 ⁇ 10 19 (Atoms/cm 3 ), and the high concentration hole layer has a lower aluminum component percentage than the above. The percentage of aluminum component of the electronic barrier layer.
  • the N-type nitride semiconductor includes an N-side first stress relief layer, an N-side second stress relief layer, a low-concentration electron layer, and an N-type ohmic contact layer, wherein the N-type ohmic contact layer is disposed closest to the above
  • the second barrier layer is the N-side first stress relief layer
  • the second barrier layer disposed farthest from the above is the N-type ohmic contact layer
  • the low-concentration electron layer and the second stress-relieving layer are Stacked above the N-type ohmic contact layer, the above-mentioned low-concentration electron layer It is sandwiched by the N-type ohmic contact layer and the second stress relief layer described above.
  • the N-side first stress relief layer may be a superlattice structure, and the material thereof comprises a superlattice structure composed of indium gallium nitride (InGaN) and gallium nitride (GaN). Or a superlattice structure composed of indium gallium nitride (In x GaN) and indium gallium nitride (In y GaN), the superlattice structure described above is less than 20 pairs.
  • the N-side second stress relief layer may be a superlattice structure, and the material thereof comprises a superlattice structure composed of indium gallium nitride (InGaN) and gallium nitride (GaN). Or a superlattice structure composed of indium gallium nitride (In x GaN) and indium gallium nitride (In y GaN), the superlattice structure described above is less than 20 pairs.
  • the indium component percentage of the N-side first stress-relieving layer is higher than the percentage of the indium component of the N-side second stress-relieving layer.
  • the low-concentration electron layer may be composed of gallium nitride (GaN), indium gallium nitride (InGaN) or aluminum gallium nitride (AlGaN), and the silicon of the low concentration electron layer is as described above.
  • the doping concentration is lower than the silicon doping concentration of the N-type ohmic contact layer described above.
  • the low concentration electron layer has a silicon doping concentration of less than 1 x 10 18 (Atoms/cm 3 ).
  • the N-type ohmic contact layer may be formed of gallium nitride (GaN), indium gallium nitride (InGaN) or aluminum gallium nitride (AlGaN), and the above-mentioned N-type ohmic contact layer
  • the silicon doping concentration is higher than the silicon doping concentration of the N-side first stress relief layer, the N-side second stress-relieving layer, and the low-concentration electron layer described above.
  • the super-lattice structure of the P-side stress relief layer is less than 10 pairs.
  • the above-described superlattice structure of the N-side first stress relief layer is less than 10 pairs.
  • the above-mentioned N-side second stress relief layer has a super-lattice structure of less than 10 pairs.
  • the substrate is selected from the group consisting of elements and alloys including group III-V, group IV, group II-VI, zinc oxide (ZnO), spinel, gallium nitride ( GaN), sapphire or silicon (Si).
  • the buffer layer includes a first buffer layer and a second buffer layer.
  • the first buffer layer is sandwiched by the first surface of the substrate and the second buffer layer, and the first buffer layer has a higher defect density than the second buffer layer, and the second buffer layer
  • the upper portion of the layer is a flat and defect density lower than the first buffer layer described above.
  • the material of the first buffer layer may be single crystal gallium nitride (GaN), single crystal aluminum nitride (AlN) or single crystal aluminum gallium nitride (AlGaN).
  • the material of the first buffer layer may be non-single-crystal gallium nitride (GaN), non-single-crystal aluminum nitride (AlN) or non-single-crystal aluminum gallium nitride (AlGaN).
  • the material of the buffer layer comprises gallium nitride (GaN), aluminum nitride (AlN) or aluminum gallium nitride (AlGaN).
  • the first surface of the substrate includes a growth surface and a plurality of microstructures on the growth surface, and the plurality of microstructures have non-smooth etched sides.
  • the surface roughness of the growth surface is less than 10 angstroms .
  • the microstructure of the microstructure has a surface roughness of less than 10 angstroms. .
  • the microstructure is a periodic protruding structure
  • the periodic protruding structure includes a height, a width, and a bottom surface spacing.
  • the height is between 1 micrometer ( ⁇ m) and 3 micrometers.
  • the width is between 1 micrometer and 3 micrometers.
  • the bottom surface spacing is between 0.1 microns and 3 microns.
  • the second surface roughness of the substrate is greater than the growth surface and the surface of the plurality of microstructures.
  • the microstructure of the microstructure is a hemisphere.
  • the microstructure of the microstructure is a cone.
  • the microstructure of the microstructure is a truncated-cone.
  • the microstructure of the above microstructure is a pyramid.
  • the microstructure of the above structure is a truncated-pyramid.
  • the microstructure of the microstructure is a square pillar.
  • the microstructure of the above structure is a cylinder.
  • the nitride semiconductor device further includes a platform structure, an N-type electrode, a current blocking layer, a transparent conductive layer, a P-type electrode, an insulating layer, and a highly reflective insulating layer.
  • the platform structure exposes a portion of the N-type ohmic contact layer described above.
  • the N-type electrode is electrically connected to the N-type ohmic contact layer described above.
  • the current blocking layer is in direct contact with the P-type ohmic contact layer described above.
  • the transparent conductive layer covers the current blocking layer described above and is in direct contact with the P-type ohmic contact layer described above.
  • P-type electrode is located above Above the conductive layer, and electrically connected to the P-type ohmic contact layer described above through the transparent conductive layer.
  • the insulating layer covers the N-type electrode and the P-type electrode described above and the sidewall of the above-described platform structure.
  • a highly reflective insulating layer is located on the second side of the substrate.
  • the high reflective insulating layer is composed of a plurality of pairs of dielectric materials.
  • the plurality of dielectric material pairs described above include a plurality of first dielectric pairs and a plurality of second dielectric pairs.
  • the first dielectric pair includes a first material layer and a second material layer, wherein the first material layer has a refractive index greater than the second material layer.
  • the first material layer and the second material layer have an optical thickness less than a quarter wavelength (wavelength / 4), and the wavelength is the above-mentioned nitride semiconductor quantum well illumination The wavelength emitted by the structure.
  • the second dielectric pair includes a first material layer and a second material layer, wherein the first material layer has a refractive index greater than the second material layer.
  • the optical thickness of the first material layer is less than (wavelength / 4), the optical thickness of the second material layer is greater than (wavelength / 4), and the wavelength is the nitride semiconductor.
  • the wavelength emitted by the quantum well luminescent structure is less than (wavelength / 4)
  • the optical thickness of the second material layer is greater than (wavelength / 4)
  • the wavelength is the nitride semiconductor. The wavelength emitted by the quantum well luminescent structure.
  • the high reflective insulating layer is composed of a plurality of pairs of dielectric materials.
  • the plurality of dielectric material pairs described above includes a plurality of third dielectric pairs and a plurality of second dielectric pairs.
  • the third dielectric pair includes a first material layer and a second material layer, wherein the first material layer has a refractive index greater than the second material layer.
  • the first material layer and the second material layer have an optical thickness greater than a quarter wavelength (wavelength / 4), and the wavelength is the above-described nitride semiconductor quantum well illumination The wavelength emitted by the structure.
  • the second dielectric pair includes a first material layer and a second material layer, wherein the first material layer has a refractive index greater than the second material layer.
  • the optical thickness of the first material layer is less than (wavelength / 4), the optical thickness of the second material layer is greater than (wavelength / 4), and the wavelength is the nitride semiconductor.
  • the wavelength emitted by the quantum well luminescent structure is less than (wavelength / 4)
  • the optical thickness of the second material layer is greater than (wavelength / 4)
  • the wavelength is the nitride semiconductor. The wavelength emitted by the quantum well luminescent structure.
  • the high reflective insulating layer is composed of a plurality of pairs of dielectric materials.
  • the plurality of dielectric material pairs described above includes a plurality of first dielectric pairs and a plurality of third dielectric pairs.
  • the first dielectric pair includes a first material layer and a second material layer, wherein the first material layer has a refractive index greater than the second material layer.
  • the first material layer and the second material layer have an optical thickness of less than a quarter wavelength (wavelength / 4), and the wavelength is the amount of the nitride semiconductor.
  • the wavelength emitted by the subwell luminescent structure is not limited to a quarter wavelength (wavelength / 4).
  • the third dielectric pair includes a first material layer and a second material layer, wherein the first material layer has a refractive index greater than the second material layer.
  • the first material layer and the second material layer have an optical thickness greater than a quarter wavelength (wavelength / 4), and the wavelength is the above-described nitride semiconductor quantum well illumination The wavelength emitted by the structure.
  • the high reflective insulating layer is composed of a plurality of pairs of dielectric materials.
  • the plurality of dielectric material pairs described above includes at least one first dielectric pair and at least one second dielectric pair, and at least one third dielectric pair.
  • the first dielectric pair includes a first material layer and a second material layer, wherein the first material layer has a refractive index greater than the second material layer.
  • the first material layer and the second material layer have an optical thickness of less than a quarter of a wavelength (wavelength / 4), and the wavelength is a visible light center wavelength of 550 nm.
  • the second dielectric pair includes a first material layer and a second material layer, wherein the first material layer has a refractive index greater than the second material layer.
  • the first material layer has an optical thickness less than (wavelength / 4)
  • the second material layer has an optical thickness greater than (wavelength / 4)
  • the wavelength is a visible light center wavelength of 550 nm.
  • the third dielectric pair includes a first material layer and a second material layer, wherein the first material layer has a refractive index greater than the second material layer.
  • the first material layer and the second material layer have an optical thickness greater than a quarter wavelength (wavelength / 4), and the wavelength is a visible light center wavelength of 550 nm.
  • the first dielectric pair may be adjacent to or far from the substrate.
  • the second dielectric pair may be adjacent to or far from the substrate.
  • the third dielectric pair may be adjacent to or far from the substrate.
  • the second dielectric pair may be located between the first dielectric pair and the third dielectric pair.
  • the first dielectric pair may be located between the second dielectric pair and the third dielectric pair.
  • the third dielectric pair may be located between the first dielectric pair and the second dielectric pair.
  • the high reflective insulating layer may have a metal reflective layer underneath, and the metal reflective layer material may be aluminum or silver or other high reflectivity metal.
  • the upper reflective insulating layer may have an interface layer thereon, and the interface layer material may be the same as the high reflective insulating layer material.
  • the transparent conductive layer may be Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Zinc Oxide (ZnO) or Oxidation.
  • ITO Indium Tin Oxide
  • IZO Indium Zinc Oxide
  • ZnO Zinc Oxide
  • Oxidation Aluminum Zinc Oxide (AZO).
  • the above-described insulating layer include silicon oxide (SiO X), silicon nitride (SiN X), polyimide (Polyimide) or other polymeric materials.
  • the material of the high reflective insulating layer comprises an oxide, a nitride, and at least silicon (Si), titanium (Ti), zirconium (Zr), niobium (Nb), tantalum (Ta). Or an oxide or nitride composed of an aluminum (Al) element.
  • the material of the N-type electrode includes silver (Ag), aluminum (Al), nickel (Ni), rhenium (Rh), gold (Au), copper (Cu), and titanium (Ti). ), platinum (Pt), palladium (Pd), molybdenum (Mo), chromium (Cr), tungsten (W) or an alloy of the above metals.
  • the material of the P-type electrode includes Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W or an alloy of the above metals.
  • the nitride semiconductor device is disposed on a package carrier and a package substrate, wherein the package substrate comprises a circuit board and two pads.
  • the above two pads are disposed on the above circuit board.
  • the package carrier described above comprises a bracket, two conductive pins, a resin, two conductive materials, a transparent glue, and a phosphor powder.
  • the conductive pin is disposed on the bracket for electrically connecting to the two solder pads, wherein the nitride semiconductor component is disposed on the two conductive pins and electrically conductive with the two The pins are electrically connected.
  • the above resin is disposed on the above-mentioned bracket and is used to accommodate the above-described nitride semiconductor device and the above two conductive pins.
  • the two conductive materials are electrically connected to the nitride semiconductor device and the two conductive pins.
  • the transparent adhesive is used to cover the nitride semiconductor device and the two conductive pins described above.
  • the above phosphor powder is used to fill in the above transparent glue.
  • the above-mentioned phosphor powder is made of a material having high stable light-emitting characteristics, such as Garnet, Sulfate, Nitrate, and Silicic Acid. Silicate, aluminate or any combination of the above materials, but not limited thereto, has an emission wavelength of about 300 nm to 700 nm.
  • the above-mentioned phosphor powder has a particle diameter of 1 to 25 ⁇ m.
  • the conductive material comprises a bonding wire, gold, silver, copper, aluminum or a mixed material.
  • the transparent adhesive material comprises an epoxy resin.
  • the conductive pin may be a pure metal material, gold, silver, copper, Aluminum, low melting point metal alloys, gold tin alloys, tin, antimony or tin antimony alloys.
  • the nitride semiconductor device further includes a platform structure, an N-type electrode, a current blocking layer, a transparent conductive layer, a P-type electrode, an insulating layer, a highly reflective insulating layer, a first pad layer, a second pad layer, a first connection electrode, and a second connection electrode.
  • the above-described platform structure exposes some of the above-described N-type ohmic contact layers.
  • the N-type electrode described above is electrically connected to the N-type ohmic contact layer described above.
  • the current blocking layer is in direct contact with the P-type ohmic contact layer described above.
  • the transparent conductive layer covers the current blocking layer and is in direct contact with the P-type ohmic contact layer described above.
  • the P-type electrode is located above the transparent conductive layer, and is electrically connected to the P-type ohmic contact layer through the transparent conductive layer.
  • the insulating layer covers the N-type electrode and the P-type electrode and the sidewall of the above-described terrace structure.
  • the above-mentioned highly reflective insulating layer is located on the above-mentioned insulating portion of the covering portion.
  • the first pad layer is electrically connected to the N-type electrode.
  • the second pad layer is electrically connected to the P-type electrode.
  • the first connection electrode is electrically connected to the first pad layer.
  • the second connection electrode is electrically connected to the second pad layer.
  • the high reflective insulating layer is composed of a plurality of pairs of dielectric materials, and the plurality of dielectric material pairs include a plurality of first dielectric pairs and a plurality of second dielectrics. Correct.
  • the first dielectric pair includes a first material layer and a second material layer, wherein the first material layer has a refractive index greater than the second material layer.
  • the first material layer and the second material layer have an optical thickness of less than a quarter of a wavelength, and the wavelength is a wavelength emitted by the nitride semiconductor quantum well emitting structure.
  • the second dielectric pair includes a first material layer and a second material layer, wherein the first material layer has a refractive index greater than the second material layer.
  • the first material layer has an optical thickness of less than a quarter of a wavelength
  • the second material layer has an optical thickness greater than a quarter of a wavelength, wherein the wavelength is the nitrogen The wavelength emitted by the quantum structure of a quantum well.
  • the transparent conductive layer may be Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Zinc Oxide (ZnO) or Oxidation.
  • ITO Indium Tin Oxide
  • IZO Indium Zinc Oxide
  • ZnO Zinc Oxide
  • Oxidation Aluminum Zinc Oxide (AZO).
  • the above-described insulating layer include silicon oxide (SiO X), silicon nitride (SiN X), polyimide (Polyimide) or other polymeric materials.
  • the material of the high reflective insulating layer comprises oxides and nitrides. Or an oxide or nitride consisting of at least Si, Ti, Zr, Nb, Ta or Al elements.
  • the material of the N-type electrode includes Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W or an alloy of the above metals.
  • the material of the P-type electrode includes Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W or an alloy of the above metals.
  • the material of the first conductive pin comprises Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W, tin (Sn) or the above metal. Alloy.
  • the material of the second conductive pin comprises Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W, Sn or an alloy of the above metals.
  • the nitride semiconductor device is disposed on a package carrier and a package substrate, wherein the package substrate comprises a circuit board and two pads.
  • the above two pads are disposed on the above circuit board.
  • the package carrier described above comprises a bracket, two conductive pins, a resin, two conductive materials, a transparent glue and a phosphor powder.
  • the two conductive pins are disposed on the bracket for electrically connecting to the two solder pads, wherein the nitride semiconductor component is disposed on the two conductive pins, and the two The conductive pins are electrically connected.
  • the above resin is disposed on the above-mentioned bracket and is used to accommodate the above-described nitride semiconductor device and the above two conductive pins.
  • the two conductive materials are electrically connected to the above-mentioned nitride semiconductor device and the two conductive pins.
  • the above transparent adhesive is used to coat the above-described nitride semiconductor device and the above two conductive pins.
  • the above phosphor powder is used to fill in the above transparent glue.
  • the above-mentioned phosphor powder is made of a material having high stable light-emitting characteristics, such as Garnet, Sulfate, Nitrate, and Silicic Acid. Silicate, aluminate or any combination of the above materials, but not limited thereto, has an emission wavelength of about 300 nm to 700 nm.
  • the above-mentioned phosphor powder has a particle diameter of 1 to 25 ⁇ m.
  • the transparent adhesive material comprises an epoxy resin.
  • the conductive pins may be pure metal materials, gold, silver, copper, aluminum, or low melting point metal alloys, gold tin alloys, tin, antimony or tin antimony alloys.
  • the nitride semiconductor device described above can be applied to the field of automotive lighting.
  • the nitride semiconductor device described above can be applied to the field of general illumination.
  • the nitride semiconductor device described above can be applied to the field of flash lamps.
  • the nitride semiconductor device described above can be applied to the field of backlights.
  • the nitride semiconductor device described above can be applied to the field of outdoor signage.
  • the nitride semiconductor device has a luminous efficiency higher than 220 lumens per watt (lm/W).
  • the display index (R9) for red in the color rendering index of the nitride semiconductor device is greater than 90.
  • the nitride semiconductor element has a Color Rendering Index (CRI) greater than 90.
  • the nitride semiconductor device has an average color rendering index (Ra) of more than 90.
  • the nitride semiconductor device may be a horizontal light-emitting wafer.
  • the nitride semiconductor device may be a vertical light-emitting chip.
  • the nitride semiconductor device may be a flip-chip light-emitting chip.
  • the present invention provides a nitride semiconductor device including a P-type nitride semiconductor, an N-type nitride semiconductor, a buffer layer, a nitride semiconductor quantum well light-emitting structure, a highly reflective insulating layer, a P-type high-reflection ohmic electrode, and an N-type electrode a first solder metal layer, a second solder metal layer, a bonding substrate, and a substrate electrode.
  • the above-described nitride semiconductor quantum well light-emitting structure is located between the above-described P-type nitride semiconductor and the above-described N-type nitride semiconductor.
  • the above-described highly reflective insulating layer covers the above-described P-type nitride semiconductor.
  • the P-type high-reflection ohmic electrode described above covers the above-described high-reflection insulating layer and the above-described P-type nitride semiconductor, and is electrically connected to the above-described P-type nitride semiconductor.
  • the N-type electrode described above covers the buffer layer and is electrically connected to the N-type nitride semiconductor described above.
  • the first solder metal layer is covered on the P-type high-reflection ohmic electrode and electrically connected to the P-type nitride semiconductor.
  • the second solder metal layer covers the first solder metal layer and is electrically connected to the P-type nitride semiconductor.
  • the bonding substrate described above covers the second solder metal layer and is electrically connected to the P-type nitride semiconductor described above.
  • the substrate electrode described above covers the bonded substrate and is electrically connected to the P-type nitride semiconductor described above.
  • the nitride semiconductor quantum well light-emitting structure has a plurality of well layers and a plurality of barrier layers, and the plurality of barrier layers include a first barrier layer disposed at a position closest to the P-type nitride semiconductor, and a first barrier layer disposed at the most a second barrier layer adjacent to the position of the N-type nitride semiconductor and a plurality of third barrier layers, wherein the plurality of third barrier layers are sandwiched by the plurality of well layers, wherein the thickness of the first barrier layer is Less than 100 angstroms.
  • the thickness of the second barrier layer is greater than the thickness of the first barrier layer.
  • the thickness of the third barrier layer is greater than the thickness of the first barrier layer.
  • the thickness of the second barrier layer is greater than or equal to the thickness of the third barrier layer.
  • the thickness of the second barrier layer is less than or equal to the thickness of the third barrier layer.
  • the first barrier layer has a thickness of less than 50 angstroms.
  • the P-type nitride semiconductor includes a P-side stress releasing layer, a high-concentration hole layer, an electron blocking layer, and a P-type ohmic contact layer.
  • the first barrier layer disposed closest to the above is the P-side stress-relieving layer, and is disposed at a distance from the first barrier layer as described above to the P-type ohmic contact layer, the high-concentration hole layer and the electrons.
  • the barrier layer is sequentially stacked over the P-side stress relief layer described above, and the electron blocking layer is sandwiched by the high-concentration hole layer and the P-type ohmic contact layer.
  • the P-side stress relief layer may be a superlattice structure, the material of which comprises a superlattice structure composed of aluminum gallium nitride (AlGaN) and gallium nitride (GaN), or a superlattice structure composed of aluminum gallium nitride (Al x GaN) and aluminum gallium nitride (Al y GaN), or composed of aluminum gallium nitride (AlGaN) and aluminum indium gallium nitride (InAlGaN) Superlattice structure, the above superlattice structure is less than 20 pairs.
  • the high concentration hole layer may be composed of gallium nitride (GaN) or aluminum gallium nitride (AlGaN), and the magnesium concentration of the high concentration hole layer is concentrated. It is higher than the magnesium doping concentration of the P-side stress releasing layer described above and the magnesium doping concentration of the above-described electron blocking layer.
  • the high concentration hole layer has a magnesium (Mg) doping concentration higher than 1 x 10 19 (Atoms/cm 3 ).
  • the electron blocking layer may be composed of aluminum gallium nitride (AlGaN), and the percentage of the aluminum component of the electron blocking layer is higher than the percentage of the aluminum component of the P-side stress releasing layer and higher than The percentage of aluminum component of the above-mentioned high concentration hole layer.
  • AlGaN aluminum gallium nitride
  • the P-type ohmic contact layer may be composed of gallium nitride (GaN), and the magnesium doping concentration of the P-type ohmic contact layer is higher than the magnesium doping concentration of the electron blocking layer. .
  • the high concentration hole layer has a magnesium (Mg) doping concentration higher than 1 ⁇ 10 19 (Atoms/cm 3 ) and the high concentration hole layer has a lower aluminum component percentage than the above. The percentage of aluminum component of the electron blocking layer.
  • the N-type nitride semiconductor includes an N-side first stress relief layer, an N-side second stress relief layer, a low concentration electron layer, and an N-type ohmic contact layer.
  • the second barrier layer disposed closest to the above is the N-side first stress relief layer, and the second barrier layer farthest from the above is the N-type ohmic contact layer, the low-concentration electron layer, and
  • the second stress relief layer is sequentially stacked over the N-type ohmic contact layer, and the low-concentration electron layer is sandwiched by the N-type ohmic contact layer and the second stress relief layer.
  • the N-side first stress relief layer may be a superlattice structure, and the material thereof comprises a superlattice structure composed of indium gallium nitride (InGaN) and gallium nitride (GaN). Or a superlattice structure composed of indium gallium nitride (In x GaN) and indium gallium nitride (In y GaN), or the above superlattice structure is less than 20 pairs.
  • the N-side second stress relief layer may be a superlattice structure, and the material thereof comprises a superlattice structure composed of indium gallium nitride (InGaN) and gallium nitride (GaN). Or a superlattice structure composed of indium gallium nitride (In x GaN) and indium gallium nitride (In y GaN), or the above superlattice structure is less than 20 pairs.
  • the percentage of indium component of the N-side first stress-relieving layer is higher than the percentage of the indium component of the N-side second stress-relieving layer.
  • the N-type nitride semiconductor, the low-concentration electron layer may be formed of gallium nitride (GaN) or indium gallium nitride (InGaN) or aluminum gallium nitride (AlGaN).
  • the silicon doping concentration of the low-concentration electron layer described above is lower than the silicon doping concentration of the N-type ohmic contact layer described above.
  • the low concentration electron layer has a silicon doping concentration of less than 1 x 10 18 (Atoms/cm 3 ).
  • the N-type ohmic contact layer may be formed of gallium nitride (GaN) or indium gallium nitride (InGaN) or aluminum gallium nitride (AlGaN), and the above-mentioned N-type
  • the concentration of silicon doping of the ohmic contact layer is higher than the N-side first stress-relieving layer and the N-side second stress-relieving layer and the low-concentration electron layer described above.
  • the super-lattice structure of the P-side stress relief layer is less than 10 pairs.
  • the above-described superlattice structure of the N-side first stress relief layer is less than 10 pairs.
  • the above-mentioned N-side second stress relief layer has a super-lattice structure of less than 10 pairs.
  • the material of the N-type electrode includes Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W or an alloy of the above metals.
  • the P-type high reflection ohmic electrode includes Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W or an alloy of the above metals.
  • the substrate electrode comprises Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W or an alloy of the above metals.
  • the first solder metal layer material comprises Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W, Sn or an alloy of the above metals.
  • the second solder metal layer material comprises Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W, Sn or an alloy of the above metals.
  • the bonding substrate includes a pure metal substrate, a copper substrate, a tungsten substrate, an aluminum substrate, an alloy substrate, a copper tungsten substrate, a ceramic substrate, an alumina substrate, a silicon substrate, or a silicon carbide substrate.
  • the bonded substrate has a thermal expansion coefficient higher than or equal to a thermal expansion coefficient of the buffer layer.
  • the bonded substrate has a thermal expansion coefficient lower than or equal to a thermal expansion coefficient of the buffer layer.
  • the buffer layer has a surface roughening structure to increase light extraction efficiency.
  • the high reflective insulating layer is composed of a plurality of pairs of dielectric materials, and the plurality of dielectric material pairs include a plurality of first dielectric pairs and a plurality of second dielectrics. Correct.
  • the first dielectric pair includes a first material layer and a second material layer. Wherein the first material layer has a refractive index greater than the second material layer.
  • the first material layer and the second material layer have an optical thickness of less than a quarter of a wavelength, and the wavelength is a wavelength emitted by the nitride semiconductor quantum well emitting structure.
  • the second dielectric pair includes a first material layer and a second material layer.
  • the first material layer has a refractive index greater than the second material layer.
  • the first material layer has an optical thickness of less than a quarter of a wavelength
  • the second material layer has an optical thickness greater than a quarter of a wavelength, wherein the wavelength is the nitrogen The wavelength emitted by the quantum structure of a quantum well.
  • the nitride semiconductor device is disposed on a package carrier and a package substrate, wherein the package substrate comprises a circuit board and two pads.
  • the above two welding The pad is disposed on the above circuit board.
  • the package carrier described above comprises a bracket, two conductive pins, a resin, two conductive materials, a transparent glue and a phosphor powder.
  • the two conductive pins are disposed on the bracket for electrically connecting to the two solder pads, wherein the nitride semiconductor component is disposed on the two conductive pins, and the two The conductive pins are electrically connected.
  • the above resin is disposed on the above-mentioned bracket and is used to accommodate the above-described nitride semiconductor device and the above two conductive pins.
  • the two conductive materials are electrically connected to the nitride semiconductor device and the two conductive pins.
  • the above transparent adhesive is used to coat the above-described nitride semiconductor device and the above two conductive pins.
  • the above phosphor powder is used to fill in the above transparent glue.
  • the above-mentioned phosphor powder is made of a material having high stable light-emitting characteristics, such as Garnet, Sulfate, Nitrate, and Silicic Acid. Silicate, aluminate or any combination of the above materials, but not limited thereto, has an emission wavelength of about 300 nm to 700 nm.
  • the above-mentioned phosphor powder has a particle diameter of 1 to 25 ⁇ m.
  • the conductive material comprises a bonding wire or gold, silver, copper, aluminum, or a mixed material.
  • the transparent adhesive material comprises an epoxy resin.
  • the conductive pins may be pure metal materials, gold, silver, copper, aluminum, or low melting point metal alloys, gold tin alloys, tin, antimony or tin antimony alloys.
  • the nitride semiconductor device described above can be applied to the field of automotive lighting.
  • the nitride semiconductor device described above can be applied to the field of general illumination.
  • the nitride semiconductor device described above can be applied to the field of flash lamps.
  • the nitride semiconductor device described above can be applied to the field of backlights.
  • the nitride semiconductor device described above can be applied to the field of outdoor signage.
  • the nitride semiconductor device has a luminous efficiency higher than 220 lumens per watt (lm/W).
  • the display index (R9) for red in the color rendering index of the nitride semiconductor device is greater than 90.
  • the nitride semiconductor element has a Color Rendering Index (CRI) greater than 90.
  • the nitride semiconductor device has an average color rendering index (Ra) of more than 90.
  • the microstructure is a periodic protruding structure
  • the periodic protruding structure includes a height, a width, and a bottom surface spacing.
  • the height is between 1 micrometer and 3 micrometers.
  • the width is between 1 micrometer and 3 micrometers.
  • the bottom surface spacing is between 0.1 microns and 3 microns.
  • the roughness of the second surface of the substrate is greater than the growth surface and the surface of the plurality of microstructures.
  • the microstructure of the microstructure is a hemisphere.
  • the microstructure of the microstructure is a cone.
  • the microstructure of the microstructure is a truncated-cone.
  • the microstructure of the above microstructure is a pyramid.
  • the microstructure of the above structure is a truncated-pyramid.
  • the microstructure of the microstructure is a square pillar.
  • the microstructure of the above structure is a cylinder.
  • the present invention provides a nitride semiconductor device including a P-type nitride semiconductor, an N-type nitride semiconductor, a nitride semiconductor quantum well light-emitting structure, a substrate, and a buffer layer.
  • the above-described nitride semiconductor quantum well light-emitting structure is located between the above-described P-type nitride semiconductor and the above-described N-type nitride semiconductor.
  • the substrate described above includes opposing first and second faces.
  • the buffer layer is located between the N-type nitride semiconductor and the first surface of the substrate.
  • the nitride semiconductor quantum well light-emitting structure has a plurality of well layers and a plurality of barrier layers
  • the plurality of barrier layers include a first barrier layer disposed at a position closest to the P-type nitride semiconductor, and disposed closest to a second barrier layer of the N-type nitride semiconductor position and a plurality of third barrier layers, wherein the plurality of third barrier layers are sandwiched by the plurality of well layers, wherein the thickness of the first barrier layer is less than The thickness of the second barrier layer described above.
  • the thickness of the second barrier layer is the same as the thickness of the third barrier layer.
  • the thickness of the second barrier layer is different from the thickness of the third barrier layer.
  • the nitride semiconductor device of the present invention includes a P-type nitride semiconductor, an N-type nitride semiconductor, a nitride semiconductor quantum well light-emitting structure, a substrate, and a buffer layer.
  • the above-described nitride semiconductor quantum well light-emitting structure is located between the above-described P-type nitride semiconductor and the above-described N-type nitride semiconductor.
  • the substrate described above includes opposing first and second faces.
  • the buffer layer is located between the N-type nitride semiconductor and the first surface of the substrate.
  • the nitride semiconductor quantum well light-emitting structure has a plurality of well layers and a plurality of barrier layers, and the plurality of barrier layers include a first barrier layer disposed at a position closest to the P-type nitride semiconductor, and a first barrier layer disposed at the most a second barrier layer adjacent to the position of the N-type nitride semiconductor and a plurality of third barrier layers, wherein the plurality of third barrier layers are sandwiched by the plurality of well layers, wherein the thickness of the first barrier layer is less than The thickness of the third barrier layer described above.
  • the thickness of the second barrier layer is the same as the thickness of the third barrier layer.
  • the thickness of the second barrier layer is different from the thickness of the third barrier layer.
  • the present invention provides a nitride semiconductor device including a P-type nitride semiconductor, an N-type nitride semiconductor, a buffer layer, a nitride semiconductor quantum well light-emitting structure, a highly reflective insulating layer, a P-type high-reflection ohmic electrode, and an N-type electrode a first solder metal layer, a second solder metal layer, a bonding substrate, and a substrate electrode.
  • the above-described nitride semiconductor quantum well light-emitting structure is located between the above-described P-type nitride semiconductor and the above-described N-type nitride semiconductor.
  • the above-described highly reflective insulating layer covers the above-described P-type nitride semiconductor.
  • the P-type high-reflection ohmic electrode described above covers the above-described high-reflection insulating layer and the above-described P-type nitride semiconductor, and is electrically connected to the above-described P-type nitride semiconductor.
  • the N-type electrode described above covers the buffer layer and is electrically connected to the N-type nitride semiconductor described above.
  • the first solder metal layer is covered on the P-type high-reflection ohmic electrode and electrically connected to the P-type nitride semiconductor.
  • the second solder metal layer covers the first solder metal layer and is electrically connected to the P-type nitride semiconductor.
  • the bonding substrate described above covers the second solder metal layer and is electrically connected to the P-type nitride semiconductor described above.
  • the substrate electrode described above covers the bonded substrate and is electrically connected to the P-type nitride semiconductor described above.
  • the nitride semiconductor quantum well light-emitting structure has a plurality of well layers and a plurality of barrier layers, and the plurality of barrier layers include a first barrier layer disposed at a position closest to the P-type nitride semiconductor, and a first barrier layer disposed at a closest position a second barrier layer of the N-type nitride semiconductor position and a plurality of third barrier layers, wherein the plurality of third barrier layers are sandwiched by the plurality of well layers, wherein the thickness of the first barrier layer is less than the above The thickness of the second barrier layer.
  • the thickness of the second barrier layer is the same as the thickness of the third barrier layer.
  • the thickness of the second barrier layer is different from the thickness of the third barrier layer.
  • the present invention provides a nitride semiconductor device including a P-type nitride semiconductor, an N-type nitride semiconductor, a buffer layer, a nitride semiconductor quantum well light-emitting structure, a highly reflective insulating layer, a P-type high-reflection ohmic electrode, and an N-type electrode a first solder metal layer, a second solder metal layer, a bonding substrate, and a substrate electrode.
  • the above-described nitride semiconductor quantum well light-emitting structure is located between the above-described P-type nitride semiconductor and the above-described N-type nitride semiconductor.
  • the above-described highly reflective insulating layer covers the above-described P-type nitride semiconductor.
  • the P-type high-reflection ohmic electrode described above covers the above-described high-reflection insulating layer and the above-described P-type nitride semiconductor, and is electrically connected to the above-described P-type nitride semiconductor.
  • the N-type electrode described above covers the buffer layer and is electrically connected to the N-type nitride semiconductor described above.
  • the first solder metal layer is covered on the P-type high-reflection ohmic electrode and electrically connected to the P-type nitride semiconductor.
  • the second solder metal layer covers the first solder metal layer and is electrically connected to the P-type nitride semiconductor.
  • the bonding substrate described above covers the second solder metal layer and is electrically connected to the P-type nitride semiconductor described above.
  • the substrate electrode described above covers the bonded substrate and is electrically connected to the P-type nitride semiconductor described above.
  • the nitride semiconductor quantum well light-emitting structure has a plurality of well layers and a plurality of barrier layers, and the plurality of barrier layers include a first barrier layer disposed at a position closest to the P-type nitride semiconductor, and a first barrier layer disposed at a closest position a second barrier layer of the N-type nitride semiconductor position and a plurality of third barrier layers, wherein the plurality of third barrier layers are sandwiched by the plurality of well layers, wherein the thickness of the first barrier layer is less than the above The thickness of the third barrier layer.
  • the thickness of the second barrier layer is the same as the thickness of the third barrier layer.
  • the thickness of the second barrier layer is different from the thickness of the third barrier layer.
  • the present invention provides a method of fabricating a nitride semiconductor device comprising the following steps. Forming a semiconductor wafer. The semiconductor wafer is cut by a stealth laser to form a nitride semiconductor device according to any of the above embodiments.
  • the present invention provides a package structure including a circuit board, a holder, and a nitride semiconductor element as in any of the above embodiments.
  • the above bracket is provided on the above circuit board.
  • the nitride semiconductor device described above is provided on the above-described holder.
  • the package structure further includes a transparent adhesive covering the nitride semiconductor device.
  • the package structure further includes a phosphor powder filled in the transparent glue.
  • the concentration of the phosphor powder is uniformly distributed in the above transparent Inside the glue.
  • the concentration of the phosphor powder is unevenly distributed in the transparent paste.
  • the concentration of the phosphor powder is gradually increased from the surface of the nitride semiconductor device to the surface of the transparent paste.
  • the concentration of the phosphor powder is gradually decreased from the surface of the nitride semiconductor element to the surface of the transparent paste.
  • the above-mentioned phosphor powder is made of a material having high stable light-emitting characteristics, such as Garnet, Sulfate, Nitrate, and Silicic Acid. Silicate, aluminate or any combination of the above materials, but not limited thereto, has an emission wavelength of about 300 nm to 700 nm.
  • the above-mentioned phosphor powder has a particle diameter of 1 to 25 ⁇ m.
  • the present invention provides a nitride semiconductor device including a substrate, a buffer layer, a first N-type nitride semiconductor, a nitride semiconductor quantum well light-emitting structure, a P-type nitride semiconductor, a tunnel junction, and a second N-type nitride semiconductor.
  • the substrate has opposite first and second faces.
  • the buffer layer is provided on the first surface of the substrate described above.
  • the first N-type nitride semiconductor described above is provided on the buffer layer described above.
  • the nitride semiconductor quantum well light-emitting structure described above is provided on the first N-type nitride semiconductor described above.
  • the above-described P-type nitride semiconductor is provided on the above-described nitride semiconductor quantum well light-emitting structure.
  • the tunneling junction surface described above is disposed on the nitride semiconductor quantum well light emitting structure.
  • the tunneling junction described above includes a heavily doped P-type (P+) nitride semiconductor and a heavily doped N-type (N+) nitride semiconductor.
  • the above heavily doped P-type (P+) nitride semiconductor is provided on the above-described nitride semiconductor quantum well light-emitting structure.
  • the above heavily doped N-type (N+) nitride semiconductor is provided on the above-described heavily doped P-type nitride semiconductor.
  • the second N-type nitride semiconductor is provided on the above-described heavily doped N-type nitride semiconductor on the tunnel junction surface.
  • the nitride semiconductor quantum well light-emitting structure has a plurality of well layers and a plurality of barrier layers, and the plurality of barrier layers include a first barrier layer disposed at a position closest to the P-type nitride semiconductor, and disposed closest to a second barrier layer of the first N-type nitride semiconductor position and a plurality of third barrier layers, wherein the plurality of third barrier layers are sandwiched by the plurality of well layers, wherein the first barrier layer Thickness less than 100 angstroms .
  • the energy bandgap of the heavily doped P-type semiconductor layer is higher as the P-type nitride semiconductor is higher, and the energy of the heavily doped N-type nitride semiconductor layer is higher. The closer the gap is to the second N-type nitride semiconductor described above.
  • the heavily doped P-type semiconductor layer has a thickness of about 1 nm to 100 nm
  • the heavily doped N-type nitride semiconductor layer has a thickness of about 1 nm (nanometer; Nm) ⁇ 100nm.
  • the thickness of the second barrier layer is greater than the thickness of the first barrier layer
  • the thickness of the third barrier layer is greater than the thickness of the first barrier layer
  • the thickness of the second barrier layer is greater than Or equal to the thickness of the third barrier layer described above.
  • the thickness of the second barrier layer is greater than the thickness of the first barrier layer
  • the thickness of the third barrier layer is greater than the thickness of the first barrier layer
  • the second barrier layer is The thickness is less than or equal to the thickness of the third barrier layer described above.
  • At least one of the first N-type nitride semiconductor and the second N-type nitride semiconductor has a rough surface for increasing the light-emitting effect of the nitride semiconductor device.
  • the P-type nitride semiconductor includes a P-side stress releasing layer, a high-concentration hole layer, and an electron blocking layer.
  • the first barrier layer disposed closest to the above is the P-side stress releasing layer, and the first barrier layer disposed farthest from the above is the electron blocking layer, and the high-concentration hole layer is subjected to the P-side stress.
  • the release layer and the above-described electron blocking layer are sandwiched.
  • the P-side stress relief layer may be a superlattice structure, the material of which comprises a superlattice structure composed of aluminum gallium nitride (AlGaN) and gallium nitride (GaN), or a superlattice structure composed of aluminum gallium nitride (Al x GaN) and aluminum gallium nitride (Al y GaN), or composed of aluminum gallium nitride (AlGaN) and aluminum indium gallium nitride (InAlGaN)
  • a superlattice structure in which x is not equal to y and the superlattice structure described above is less than 20 pairs.
  • the high concentration hole layer may be composed of gallium nitride (GaN) or aluminum gallium nitride (AlGaN), and the magnesium concentration of the high concentration hole layer is concentrated. It is higher than the magnesium doping concentration of the P-side stress releasing layer described above and the magnesium doping concentration of the above-described electron blocking layer.
  • the high concentration hole layer has a magnesium (Mg) doping concentration higher than 1 x 10 19 (Atoms/cm 3 ).
  • the electron blocking layer may be composed of aluminum gallium nitride (AlGaN), and the percentage of the aluminum component of the electron blocking layer is higher than the percentage of the aluminum component of the P-side stress releasing layer and higher than The percentage of aluminum component of the above-mentioned high concentration hole layer.
  • AlGaN aluminum gallium nitride
  • the tunneling junction further includes an intermediate semiconductor disposed on the heavily doped P-type (P+) nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor between.
  • the high concentration hole layer has a magnesium (Mg) doping concentration higher than 1 ⁇ 10 19 (Atoms/cm 3 ), and the high concentration hole layer has a lower aluminum component percentage than the above. The percentage of aluminum component of the electronic barrier layer.
  • the first N-type nitride semiconductor includes an N-side first stress relief layer, an N-side second stress relief layer, a low concentration electron layer, and an N-type ohmic contact layer.
  • the second barrier layer disposed closest to the above is the N-side first stress relief layer, and the second barrier layer farthest from the above is the N-type ohmic contact layer, the low-concentration electron layer and the above.
  • the second stress relief layer is sequentially stacked over the N-type ohmic contact layer, and the low-concentration electron layer is sandwiched by the N-type ohmic contact layer and the N-side second stress relief layer.
  • the N-side first stress relief layer may be a superlattice structure, and the material thereof comprises a superlattice structure composed of indium gallium nitride (InGaN) and gallium nitride (GaN). Or a superlattice structure composed of indium gallium nitride (In x GaN) and indium gallium nitride (In y GaN), wherein x is not equal to y, and the superlattice structure described above is less than 20 pairs.
  • the N-side second stress relief layer may be a superlattice structure, and the material thereof comprises a superlattice structure composed of indium gallium nitride (InGaN) and gallium nitride (GaN). Or a superlattice structure composed of indium gallium nitride (In x GaN) and indium gallium nitride (In y GaN), wherein x is not equal to y, and the superlattice structure described above is less than 20 pairs.
  • the percentage of indium component of the N-side first stress-relieving layer is higher than the percentage of the indium component of the N-side second stress-relieving layer.
  • the low-concentration electron layer may be formed of gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), or indium aluminum gallium nitride (InAlGaN).
  • GaN gallium nitride
  • InGaN indium gallium nitride
  • AlGaN aluminum gallium nitride
  • InAlGaN indium aluminum gallium nitride
  • the low concentration electron layer has a silicon doping concentration of less than 1 x 10 18 (Atoms/cm 3 ).
  • the N-type ohmic contact layer may be formed of gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN) or indium aluminum gallium nitride (InAlGaN).
  • the silicon doping concentration of the N-type ohmic contact layer is higher than the silicon doping concentration of the N-side first stress releasing layer, the silicon doping concentration of the N-side second stress releasing layer, and the low-concentration electron described above. The silicon doping concentration of the layer.
  • the super-lattice structure of the P-side stress relief layer is less than 10 pairs.
  • the above-described superlattice structure of the N-side first stress relief layer is less than 10 pairs.
  • the above-mentioned N-side second stress relief layer has a super-lattice structure of less than 10 pairs.
  • the substrate is selected from the group consisting of elements and alloys including Group III-V, Group IV, Group II-VI, zinc oxide (ZnO), spinel, and gallium nitride ( GaN), sapphire At least one of a group consisting of (sapphire) and silicon (Si).
  • the buffer layer includes a first buffer layer and a second buffer layer.
  • the first buffer layer is sandwiched by the first surface of the substrate and the second buffer layer, and the defect density of the first buffer layer is higher than the defect density of the second buffer layer.
  • the upper portion of the second buffer layer is flat, and the defect density of the second buffer layer is lower than the defect density of the first buffer layer.
  • the material of the first buffer layer may be single crystal gallium nitride (GaN), single crystal aluminum nitride (AlN), single crystal aluminum gallium nitride (AlGaN) or single crystal nitrogen.
  • the material of the first buffer layer may be non-single crystal gallium nitride (GaN), non-single-crystal aluminum nitride (AlN), non-single-crystal aluminum gallium nitride (AlGaN) or Non-single crystal indium aluminum gallium nitride (InAlGaN).
  • the material of the buffer layer comprises gallium nitride (GaN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN) or indium aluminum gallium nitride (InAlGaN).
  • the first surface of the substrate includes a growth surface and a plurality of microstructures on the growth surface, and the plurality of microstructures have non-smooth etched sides.
  • the surface roughness of the growth surface is less than 10 angstroms .
  • the microstructure of the microstructure has a surface roughness of less than 10 angstroms. .
  • the microstructure is a periodic protruding structure
  • the periodic protruding structure includes a height, a width, and a bottom surface spacing.
  • the height is between 1 micrometer and 3 micrometers.
  • the width is between 1 micrometer and 3 micrometers.
  • the bottom surface spacing is between 0.1 microns and 3 microns.
  • the roughness of the second surface of the substrate is greater than the roughness of the growth surface and the roughness of the surface of the plurality of microstructures.
  • the microstructure of the above microstructure is a hemisphere, a cone, a truncated-cone, a pyramid, and a truncated pyramid. Pyramid), square pillar or cylinder.
  • the tunneling junction further includes an intermediate semiconductor disposed on the heavily doped P-type (P+) nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor.
  • the intermediate semiconductor described above forms a heterojunction with respect to the above-mentioned heavily doped P-type (P+) nitride semiconductor and the above-mentioned heavily doped N-type (N+) nitride semiconductor to establish a polarization field, so that the above Heavy The valence band of the doped P-type (P+) nitride semiconductor and the conduction band of the above-described heavily doped N-type (N+) nitride semiconductor correspond to each other.
  • At least one of the heavily doped P-type (P+) nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor has a larger energy gap than the nitride semiconductor quantum The energy gap of the well-emitting structure.
  • the intermediate semiconductor comprises aluminum gallium nitride (AlGaN), gallium nitride (GaN), indium gallium nitride (InGaN) or indium aluminum gallium nitride (InAlGaN).
  • AlGaN aluminum gallium nitride
  • GaN gallium nitride
  • InGaN indium gallium nitride
  • InAlGaN indium aluminum gallium nitride
  • the intermediate semiconductor has an internal band gap barrier
  • the heavily doped P-type (P+) nitride semiconductor has a P-type depletion barrier (P-depletion). Barrier
  • the above heavily doped N-type (N+) nitride semiconductor has an N-depletion barrier.
  • the intermediate semiconductor has a thickness of about 0.5 nm to 10 nm.
  • the intermediate semiconductor has lateral material energy bandgaps, which includes a plurality of low and high band gap regions.
  • the nitride semiconductor device further includes a platform structure, a first N-type electrode, a current blocking layer, a transparent conductive layer, a second N-type electrode, an insulating layer, and a highly reflective insulating layer.
  • the above-described platform structure exposes some of the above-described N-type ohmic contact layers.
  • the first N-type electrode is electrically connected to the N-type ohmic contact layer described above.
  • the current blocking layer is in direct contact with the second N-type nitride semiconductor described above.
  • the transparent conductive layer covers the current blocking layer and is in direct contact with the second N-type nitride semiconductor.
  • the second N-type electrode is located above the transparent conductive layer, and is electrically connected to the second N-type nitride semiconductor through the transparent conductive layer.
  • the insulating layer covers the first N-type electrode and the second N-type electrode and the sidewall of the above-mentioned platform structure.
  • the high-reflection insulating layer described above is located on the second surface of the substrate described above.
  • the high reflective insulating layer is composed of a plurality of pairs of dielectric materials, and the plurality of dielectric material pairs include a plurality of first dielectric pairs and a plurality of second dielectric layers. Electric pair.
  • the first dielectric pair includes a first material layer and a second material layer, wherein the first material layer has a dielectric constant greater than a dielectric constant of the second material layer.
  • the first material layer and the second material layer have an optical thickness of less than a quarter of a wavelength, and the wavelength is a wavelength emitted by the nitride semiconductor quantum well emitting structure.
  • the second dielectric pair includes a first material layer and a second material layer, wherein the first material layer has a dielectric constant greater than a dielectric constant of the second material layer.
  • the first material layer has an optical thickness of less than a quarter of a wavelength
  • the second material layer has an optical thickness greater than a quarter of a wavelength, wherein the wavelength is the nitrogen The wavelength emitted by the quantum structure of a quantum well.
  • the transparent conductive layer may be Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Zinc Oxide (ZnO) or Oxidation.
  • ITO Indium Tin Oxide
  • IZO Indium Zinc Oxide
  • ZnO Zinc Oxide
  • Oxidation Aluminum Zinc Oxide (AZO).
  • the above-described insulating layer include silicon oxide (SiO X), silicon nitride (SiN X), polyimide (Polyimide) or other polymeric materials.
  • the material of the high-reflection insulating layer includes an oxide, a nitride, or an oxide or a nitride composed of at least Si, Ti, Zr, Nb, Ta, and Al elements.
  • the material of the first N-type electrode includes Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W or an alloy of the above metals.
  • the material of the second N-type electrode includes Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W or an alloy of the above metals.
  • the nitride semiconductor device is disposed on the package carrier and the package substrate.
  • the above package substrate comprises a circuit board and two solder pads.
  • the above two pads are disposed on the above circuit board.
  • the package carrier described above comprises a bracket or a carrier, two conductive pins, a resin, two conductive materials, a transparent glue and a phosphor powder.
  • the above bracket or the above carrier is provided on the above circuit board.
  • the two conductive pins are disposed on the bracket or the carrier board for electrically connecting to the two solder pads, wherein the nitride semiconductor component is disposed on the two conductive pins.
  • the first N-type electrode and the second N-type electrode are electrically connected to the two conductive pins.
  • the above resin is disposed on the above-mentioned bracket or the above-mentioned carrier, and is for accommodating the above-described nitride semiconductor device and the above two conductive pins.
  • the two conductive materials are used to electrically connect the first N-type electrode and the second N-type electrode of the nitride semiconductor device described above and the two conductive leads.
  • the above transparent adhesive is used to coat the above-described nitride semiconductor device and the above two conductive pins.
  • the above phosphor powder is used to fill in the above transparent glue.
  • the phosphor powder is made of a material having high stable luminescent properties, and includes Garnet, Sulfate, Nitrate, and silicate. (Silicate), aluminate (Aluminate) or any combination of the above materials, but not limited thereto, the emission wavelength is about 300 nm to 700 nm, wherein the above-mentioned phosphor powder has a particle diameter of 1 to 25 ⁇ m, wherein the above A part of the light generated by the nitride semiconductor element can excite the above-mentioned phosphor powder, so that the above-mentioned phosphor powder generates light of a longer wavelength, and the remaining part of the above-mentioned nitride semiconductor element
  • the light converted by the above-mentioned phosphor powder and the light generated by the above-mentioned phosphor powder may be mixed into white light.
  • the conductive material comprises a bonding wire, gold, silver, copper, aluminum or a mixed material.
  • the transparent adhesive material comprises an epoxy resin.
  • the conductive pins may be pure metal materials, gold, silver, copper, aluminum, low melting point metal alloys, gold tin alloys, tin, antimony or tin antimony alloys.
  • the nitride semiconductor device further includes a platform structure, a first N-type electrode, a current blocking layer, a transparent conductive layer, a second N-type electrode, an insulating layer, a highly reflective insulating layer, and a first a pad layer, a second pad layer, a first connection electrode, and a second connection electrode.
  • the above-described platform structure exposes some of the N-type ohmic contact layers described above.
  • the first N-type electrode described above is electrically connected to the N-type ohmic contact layer described above.
  • the current blocking layer is in direct contact with the second N-type nitride semiconductor described above.
  • the transparent conductive layer covers the current blocking layer and is in direct contact with the second N-type nitride semiconductor.
  • the second N-type electrode is located above the transparent conductive layer, and is electrically connected to the second N-type nitride semiconductor through the transparent conductive layer.
  • the insulating layer covers the first N-type electrode and the second N-type electrode and the sidewall of the platform structure.
  • the above-mentioned highly reflective insulating layer is located on the above-mentioned insulating layer of the covering portion.
  • the first pad layer is electrically connected to the first N-type electrode.
  • the second pad layer is electrically connected to the second N-type electrode.
  • the first connection electrode is electrically connected to the first pad layer.
  • the second connection electrode is electrically connected to the second pad layer.
  • the high reflective insulating layer is composed of a plurality of pairs of dielectric materials, and the plurality of dielectric material pairs include a plurality of first dielectric pairs and a plurality of second dielectrics. Correct.
  • the first dielectric pair includes a first material layer and a second material layer, wherein the first material layer has a dielectric constant greater than a dielectric constant of the second material layer.
  • the first material layer and the second material layer have an optical thickness of less than a quarter of a wavelength, and the wavelength is a wavelength emitted by the nitride semiconductor quantum well emitting structure.
  • the second dielectric pair includes a first material layer and a second material layer, wherein the first material layer has a dielectric constant greater than a dielectric constant of the second material layer.
  • the first material layer has an optical thickness of less than a quarter of a wavelength
  • the second material layer has an optical thickness greater than a quarter of a wavelength, wherein the wavelength is the nitrogen The wavelength emitted by the quantum structure of a quantum well.
  • the transparent conductive layer may be indium tin oxide (Indium) Tin Oxide; ITO), indium zinc oxide (IZO), zinc oxide (Zinc Oxide; ZnO) or aluminum zinc oxide (Aluminium Zinc Oxide; AZO).
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • ZnO zinc oxide
  • Al zinc oxide Al zinc oxide
  • the above-described insulating layer include silicon oxide (SiO X), silicon nitride (SiN X), polyimide (Polyimide) or other polymeric materials.
  • the material of the high-reflection insulating layer includes an oxide, a nitride, and an oxide or nitride composed of at least Si, Ti, Zr, Nb, Ta, and Al elements.
  • the material of the first N-type electrode includes Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W or an alloy of the above metals.
  • the material of the second N-type electrode includes Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W or an alloy of the above metals.
  • the material of the first conductive pin comprises Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W, Sn, In or the above metal. alloy.
  • the material of the second conductive pin comprises Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W, Sn, In or the above metal. alloy.
  • the nitride semiconductor device is disposed on a package carrier and a package substrate, wherein the package substrate comprises a circuit board and two pads.
  • the above two pads are disposed on the above circuit board.
  • the package carrier described above comprises a bracket or a carrier, two conductive pins, a resin, two conductive materials, a transparent glue and a phosphor powder.
  • the above bracket or the above carrier is provided on the above circuit board.
  • the two conductive pins are disposed on the bracket or the carrier board for electrically connecting to the two solder pads, wherein the nitride semiconductor component is disposed on the two conductive pins.
  • the first N-type electrode and the second N-type electrode are electrically connected to the two conductive pins.
  • the above resin is disposed on the above-mentioned bracket or the above-mentioned carrier, and is for accommodating the above-described nitride semiconductor device and the above two conductive pins.
  • the two conductive materials are used to electrically connect the first N-type electrode and the second N-type electrode of the nitride semiconductor device described above and the two conductive leads.
  • the above transparent adhesive is used to coat the above-described nitride semiconductor device and the above two conductive pins.
  • the above phosphor powder is used to fill in the above transparent glue.
  • the phosphor powder is made of a material having high stable luminescent properties, and includes Garnet, Sulfate, Nitrate, and silicate. (Silicate), aluminate (Aluminate) or any combination of the above materials, having an emission wavelength of about 300 nm to 700 nm, wherein the above-mentioned phosphor powder has a particle diameter of 1 to 25 ⁇ m, wherein the nitride semiconductor element is produced by the above-mentioned A part of the light can excite the above-mentioned phosphor powder, so that the above-mentioned phosphor powder generates light of a longer wavelength, and the remaining part of the above-mentioned nitride semiconductor element is not the above-mentioned phosphor
  • the light converted by the light powder and the light generated by the above-mentioned fluorescent powder can be mixed into white light.
  • the transparent adhesive material comprises an epoxy resin.
  • the conductive pins may be pure metal materials, gold, silver, copper, aluminum, low melting point metal alloys, gold tin alloys, tin, antimony or tin antimony alloys.
  • the nitride semiconductor device described above can be applied to the field of automotive lighting.
  • the nitride semiconductor device described above can be applied to the field of general illumination.
  • the nitride semiconductor device described above can be applied to the field of flash lamps.
  • the nitride semiconductor device described above can be applied to the field of backlights.
  • the nitride semiconductor device described above can be applied to the field of outdoor signage.
  • the nitride semiconductor device has a luminous efficiency higher than 220 lumens per watt (lm/W).
  • the display index (R9) for red in the color rendering index of the nitride semiconductor device is greater than 90.
  • the nitride semiconductor element has a Color Rendering Index (CRI) greater than 90.
  • the nitride semiconductor device has an average color rendering index (Ra) of more than 90.
  • the nitride semiconductor device may be a horizontal light-emitting wafer.
  • the nitride semiconductor device may be a vertical light-emitting chip.
  • the nitride semiconductor device may be a flip-chip light-emitting chip.
  • the microstructure is a periodic protruding structure
  • the periodic protruding structure includes a height, a width, and a bottom surface spacing.
  • the height is between 1 micrometer and 3 micrometers.
  • the width is between 1 micrometer and 3 micrometers.
  • the bottom surface spacing is between 0.1 microns and 3 microns.
  • the roughness of the second surface of the substrate is greater than the roughness of the growth surface and the roughness of the surface of the plurality of microstructures.
  • the microstructure of the above microstructure is a hemisphere, a cone, a truncated-cone, a pyramid, and a truncated pyramid. Pyramid), square pillar or cylinder.
  • the tunneling junction further includes an intermediate semiconductor disposed on the heavily doped P-type (P+) nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor.
  • the intermediate semiconductor described above forms a heterojunction with respect to the above-mentioned heavily doped P-type (P+) nitride semiconductor and the above-mentioned heavily doped N-type (N+) nitride semiconductor to establish a polarization field, so that the above The valence band of the heavily doped P-type (P+) nitride semiconductor and the conduction band of the above-described heavily doped N-type (N+) nitride semiconductor correspond to each other.
  • At least one of the heavily doped P-type (P+) nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor has a larger energy gap than the nitride semiconductor quantum The energy gap of the well-emitting structure.
  • the intermediate semiconductor comprises aluminum gallium nitride (AlGaN), gallium nitride (GaN), indium gallium nitride (InGaN) or indium aluminum gallium nitride (InAlGaN).
  • AlGaN aluminum gallium nitride
  • GaN gallium nitride
  • InGaN indium gallium nitride
  • InAlGaN indium aluminum gallium nitride
  • the intermediate semiconductor has an internal band gap barrier
  • the heavily doped P-type (P+) nitride semiconductor has a P-type depletion barrier (P-depletion). Barrier
  • the above heavily doped N-type (N+) nitride semiconductor has an N-depletion barrier.
  • the intermediate semiconductor has a thickness of about 0.5 nm to 10 nm.
  • the intermediate semiconductor has lateral material energy bandgaps, which includes a plurality of low and high band gap regions.
  • the second N-type nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor do not absorb light emitted by the nitride semiconductor quantum well light-emitting structure.
  • the energy gap of the second N-type nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor is larger than the energy gap of the nitride semiconductor quantum well light-emitting structure.
  • the plurality of nitride semiconductor elements are electrically connected in series to form a nitride semiconductor high voltage element.
  • the nitride semiconductor device may emit UV light, blue light or green light.
  • the nitride semiconductor device described above can be applied to a filament (Filament) products.
  • the nitride semiconductor device described above can be applied to a COB (Chip on Board) product.
  • COB Chip on Board
  • the nitride semiconductor device described above can be applied to a laser diode product.
  • the nitride semiconductor device described above can be applied to a light emitting diode (Light Emitting Diode) product.
  • a light emitting diode Light Emitting Diode
  • the present invention provides a nitride semiconductor device including a first N-type electrode, a first N-type nitride semiconductor, a nitride semiconductor quantum well light-emitting structure, a P-type nitride semiconductor, a tunnel junction, and a tunnel junction a N-type nitride semiconductor, a highly reflective insulating layer, an N-type highly reflective ohmic electrode, a first solder metal layer, a second solder metal layer, a bonding substrate, and a second N-type electrode.
  • the first N-type nitride semiconductor described above is provided on the first N-type electrode described above.
  • the nitride semiconductor quantum well light-emitting structure described above is provided on the first N-type nitride semiconductor described above.
  • the above-described P-type nitride semiconductor is provided on the above-described nitride semiconductor quantum well light-emitting structure.
  • the above tunnel junction is disposed on the nitride semiconductor quantum well light-emitting structure described above.
  • the tunneling junction described above includes a heavily doped P-type (P+) nitride semiconductor and a heavily doped N-type (N+) nitride semiconductor.
  • the above heavily doped P-type (P+) nitride semiconductor is provided on the above-described nitride semiconductor quantum well light-emitting structure.
  • the above heavily doped N-type (N+) nitride semiconductor is provided on the above-described heavily doped P-type nitride semiconductor.
  • the second N-type nitride semiconductor is provided on the above-described heavily doped N-type nitride semiconductor on the tunnel junction surface.
  • the high-reflection insulating layer is disposed on the second N-type nitride semiconductor and exposes a portion of the second N-type nitride semiconductor.
  • the N-type high-reflection ohmic electrode is provided on the second N-type nitride semiconductor and covers the high-reflection insulating layer and the second N-type nitride semiconductor.
  • the first solder metal layer described above is disposed on the N-type high reflection ohmic electrode described above.
  • the second solder metal layer is disposed on the first solder metal layer.
  • the bonding substrate is provided on the second solder metal layer and electrically connected to the first solder metal layer.
  • the second N-type electrode is provided on the above-described bonding substrate, and is electrically connected to the bonding substrate described above.
  • the nitride semiconductor quantum well light-emitting structure has a plurality of well layers and a plurality of barrier layers
  • the plurality of barrier layers include a first barrier layer disposed at a position closest to the P-type nitride semiconductor, and disposed closest to a second barrier layer of the first N-type nitride semiconductor position and a plurality of third barrier layers, wherein the plurality of third barrier layers are sandwiched by the plurality of well layers, wherein the first barrier layer
  • the thickness is less than 100 angstroms.
  • the second N-type nitride semiconductor described above is higher.
  • the heavily doped P-type semiconductor layer has a thickness of about 1 nm to 100 nm
  • the heavily doped N-type nitride semiconductor layer has a thickness of about 1 nm to 100 nm.
  • the thickness of the second barrier layer is greater than the thickness of the first barrier layer
  • the thickness of the third barrier layer is greater than the thickness of the first barrier layer
  • the thickness of the second barrier layer is greater than Or equal to the thickness of the third barrier layer described above.
  • the thickness of the second barrier layer is greater than the thickness of the first barrier layer
  • the thickness of the third barrier layer is greater than the thickness of the first barrier layer
  • the second barrier layer is The thickness is less than or equal to the thickness of the third barrier layer described above.
  • At least one of the first N-type nitride semiconductor and the second N-type nitride semiconductor has a rough surface for increasing the light-emitting effect of the nitride semiconductor device.
  • the P-type nitride semiconductor includes a P-side stress releasing layer, a high-concentration hole layer, and an electron blocking layer.
  • the first barrier layer disposed closest to the above is the P-side stress-relieving layer described above, and the first barrier layer disposed farthest from the above is the above-described electron blocking layer, and the high-concentration hole layer is high-concentrated as described above.
  • the hole layer and the above-mentioned electron blocking layer are sandwiched.
  • the P-side stress relief layer may be a superlattice structure, the material of which comprises a superlattice structure composed of aluminum gallium nitride (AlGaN) and gallium nitride (GaN), or Superlattice structure composed of aluminum gallium nitride (AlxGaN) and aluminum gallium nitride (AlyGaN), or superlattice structure composed of aluminum gallium nitride (AlGaN) and aluminum indium gallium nitride (InAlGaN) Where x is not equal to y and the superlattice structure described above is less than 20 pairs.
  • the high concentration hole layer may be composed of gallium nitride (GaN) or aluminum gallium nitride (AlGaN), and the magnesium concentration of the high concentration hole layer is concentrated. It is higher than the magnesium doping concentration of the P-side stress releasing layer described above and the magnesium doping concentration of the above-described electron blocking layer.
  • the high concentration hole layer has a magnesium (Mg) doping concentration higher than 1 x 10 19 (Atoms/cm 3 ).
  • the electron blocking layer may be composed of aluminum gallium nitride (AlGaN), and the percentage of the aluminum component of the electron blocking layer is higher than the percentage of the aluminum component of the P-side stress releasing layer and higher than The percentage of aluminum component of the above-mentioned high concentration hole layer.
  • AlGaN aluminum gallium nitride
  • the tunneling junction further includes an intermediate semiconductor disposed on the heavily doped P-type (P+) nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor between.
  • the high concentration hole layer has a magnesium (Mg) doping concentration higher than 1 ⁇ 10 19 (Atoms/cm 3 ) and the high concentration hole layer has a lower aluminum component percentage than the above. The percentage of aluminum component of the electron blocking layer.
  • the first N-type nitride semiconductor includes an N-side first stress relief layer, an N-side second stress relief layer, a low concentration electron layer, and an N-type ohmic contact layer.
  • the second barrier layer disposed closest to the above is the N-side first stress relief layer, and the second barrier layer farthest from the above is the N-type ohmic contact layer, the low-concentration electron layer and the above.
  • the second stress relief layer is sequentially stacked over the N-type ohmic contact layer, and the low-concentration electron layer is sandwiched by the N-type ohmic contact layer and the N-side second stress relief layer.
  • the N-side first stress relief layer may be a superlattice structure, and the material thereof comprises a superlattice structure composed of indium gallium nitride (InGaN) and gallium nitride (GaN). Or a superlattice structure composed of indium gallium nitride (In x GaN) and indium gallium nitride (In y GaN), wherein x is not equal to y, and the superlattice structure described above is less than 20 pairs.
  • the N-side second stress relief layer may be a superlattice structure, and the material thereof comprises a superlattice structure composed of indium gallium nitride (InGaN) and gallium nitride (GaN). Or a superlattice structure composed of indium gallium nitride (In x GaN) and indium gallium nitride (In y GaN), wherein x is not equal to y, and the superlattice structure described above is less than 20 pairs.
  • the percentage of indium component of the N-side first stress-relieving layer is higher than the percentage of the indium component of the N-side second stress-relieving layer.
  • the N-type nitride semiconductor, the low-concentration electron layer may be gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN) or indium nitride.
  • GaN gallium nitride
  • InGaN indium gallium nitride
  • AlGaN aluminum gallium nitride
  • Aluminum gallium (InAlGaN) is formed, and the silicon concentration of the low-concentration electron layer is lower than the silicon doping concentration of the N-type ohmic contact layer.
  • the low concentration electron layer has a silicon doping concentration of less than 1 x 10 18 (Atoms/cm 3 ).
  • the N-type ohmic contact layer may be formed of gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN) or indium aluminum gallium nitride (InAlGaN).
  • the silicon doping concentration of the N-type ohmic contact layer is higher than the silicon doping concentration of the N-side first stress releasing layer, the silicon doping concentration of the N-side second stress releasing layer, and the low-concentration electron described above. The silicon doping concentration of the layer.
  • the super-lattice structure of the P-side stress relief layer is less than 10 pairs.
  • the above-described superlattice structure of the N-side first stress relief layer is less than 10 pairs.
  • the above-mentioned super-crystal of the first N-side second stress relief layer is less than 10 pairs.
  • the material of the first N-type electrode includes Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W or an alloy of the above metals.
  • the N-type high reflection ohmic electrode includes Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W or an alloy of the above metals.
  • the second N-type electrode includes Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W or an alloy of the above metals.
  • the first solder metal layer material comprises Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W, Sn, indium (In) or the above An alloy of metals.
  • the second solder metal layer material comprises Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W, Sn, In or an alloy of the above metals. .
  • the bonding substrate includes a pure metal substrate, a copper substrate, a tungsten substrate, an aluminum substrate, an alloy substrate, a copper tungsten substrate, a ceramic substrate, an alumina substrate, a silicon substrate, or a silicon carbide substrate.
  • the bonding substrate has a thermal expansion coefficient higher than or equal to a thermal expansion coefficient of the first N-type nitride semiconductor.
  • the bonded substrate has a thermal expansion coefficient lower than or equal to a thermal expansion coefficient of the first N-type nitride semiconductor.
  • the first N-type nitride semiconductor has a surface roughening structure to increase light extraction efficiency.
  • the high reflective insulating layer is composed of a plurality of pairs of dielectric materials, and the plurality of dielectric material pairs include a plurality of first dielectric pairs and a plurality of second dielectrics. Correct.
  • the first dielectric pair includes a first material layer and a second material layer. Wherein the dielectric constant of the first material layer is greater than the dielectric constant of the second material layer.
  • the first material layer and the second material layer have an optical thickness of less than a quarter of a wavelength, and the wavelength is a wavelength emitted by the nitride semiconductor quantum well emitting structure.
  • the second dielectric pair includes a first material layer and a second material layer, wherein the first material layer has a dielectric constant greater than a dielectric constant of the second material layer.
  • the first material layer has an optical thickness of less than a quarter of a wavelength
  • the second material layer has an optical thickness greater than a quarter of a wavelength, wherein the wavelength is the nitrogen The wavelength emitted by the quantum structure of a quantum well.
  • the nitride semiconductor device is disposed on a package carrier and On the package substrate, the package substrate includes a circuit board and two pads.
  • the above two pads are disposed on the above circuit board.
  • the package carrier described above comprises a bracket or a carrier, two conductive pins, a resin, two conductive materials, a transparent glue and a phosphor powder.
  • the above bracket or the above carrier is provided on the above circuit board.
  • the two conductive pins are disposed on the bracket or the carrier board for electrically connecting to the two solder pads, wherein the nitride semiconductor component is disposed on the two conductive pins.
  • the first N-type electrode and the second N-type electrode are electrically connected to the two conductive pins.
  • the above resin is disposed on the above-mentioned bracket or the above-mentioned carrier, and is for accommodating the above-described nitride semiconductor device and the above two conductive pins.
  • the two conductive materials are used to electrically connect the first N-type electrode and the second N-type electrode of the nitride semiconductor device described above and the two conductive leads.
  • the above transparent adhesive is used to coat the above-described nitride semiconductor device and the above two conductive pins.
  • the above phosphor powder is used to fill in the above transparent glue.
  • the phosphor powder is made of a material having high stable luminescent properties, and includes Garnet, Sulfate, Nitrate, and silicate. (Silicate), aluminate (Aluminate) or any combination of the above materials, having an emission wavelength of about 300 nm to 700 nm, wherein the above-mentioned phosphor powder has a particle diameter of 1 to 25 ⁇ m, wherein the nitride semiconductor element is produced by the above-mentioned A part of the light can excite the phosphor powder, so that the phosphor powder generates a longer wavelength of light, and the remaining portion of the nitride semiconductor element is not generated by the phosphor converted by the phosphor and the phosphor powder.
  • the light can be mixed into white light.
  • the conductive material comprises a bonding wire, gold, silver, copper, aluminum, or a mixed material.
  • the transparent adhesive material comprises an epoxy resin.
  • the conductive pins may be pure metal materials, gold, silver, copper, aluminum, or low melting point metal alloys, gold tin alloys, tin, antimony or tin antimony alloys.
  • the second N-type nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor do not absorb light emitted by the nitride semiconductor quantum well light-emitting structure.
  • the energy gap of the second N-type nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor is larger than the energy gap of the nitride semiconductor quantum well light-emitting structure.
  • the plurality of nitride semiconductor elements are electrically connected in series to form a nitride semiconductor high voltage element.
  • the nitride semiconductor device can emit UV light, blue Color light or green light.
  • the nitride semiconductor device described above can be applied to a filament product.
  • the nitride semiconductor device described above can be applied to a COB (Chip on Board) product.
  • COB Chip on Board
  • the nitride semiconductor device described above can be applied to a laser diode product.
  • the nitride semiconductor device described above can be applied to a light emitting diode (Light Emitting Diode) product.
  • a light emitting diode Light Emitting Diode
  • the present invention provides a nitride semiconductor device including a substrate, a buffer layer, a first N-type nitride semiconductor, a nitride semiconductor quantum well light emitting structure, a P-type nitride semiconductor, a tunnel junction, and a second N-type nitride. semiconductor.
  • the substrate has opposite first and second faces.
  • the buffer layer is provided on the first surface of the substrate described above.
  • the first N-type nitride semiconductor described above is provided on the buffer layer described above.
  • the nitride semiconductor quantum well light-emitting structure described above is provided on the first N-type nitride semiconductor described above.
  • the above-described P-type nitride semiconductor is provided on the above-described nitride semiconductor quantum well light-emitting structure.
  • the above tunnel junction is disposed on the nitride semiconductor quantum well light-emitting structure described above.
  • the tunneling junction described above includes a heavily doped P-type (P+) nitride semiconductor and a heavily doped N-type (N+) nitride semiconductor.
  • the above heavily doped P-type (P+) nitride semiconductor is provided on the above-described nitride semiconductor quantum well light-emitting structure.
  • the above heavily doped N-type (N+) nitride semiconductor is provided on the above-described heavily doped P-type nitride semiconductor.
  • the second N-type nitride semiconductor described above is provided on the above-described heavily doped N-type nitride semiconductor on the tunnel junction surface.
  • the nitride semiconductor quantum well light-emitting structure has a plurality of well layers and a plurality of barrier layers, and the plurality of barrier layers include a first barrier layer disposed at a position closest to the P-type nitride semiconductor, and disposed closest to a second barrier layer of the first N-type nitride semiconductor position and a plurality of third barrier layers, wherein the plurality of third barrier layers are sandwiched by the plurality of well layers, wherein the first barrier layer The thickness is smaller than the thickness of the second barrier layer described above.
  • the heavily doped P-type semiconductor layer has a thickness of about 1 nm to 100 nm
  • the heavily doped N-type nitride semiconductor layer has a thickness of about 1 nm to 100 nm.
  • the second N-type nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor do not absorb light emitted by the nitride semiconductor quantum well emitting structure. line.
  • the energy gap of the second N-type nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor is larger than the energy gap of the nitride semiconductor quantum well light-emitting structure.
  • the plurality of nitride semiconductor elements are electrically connected in series to form a nitride semiconductor high voltage element.
  • the nitride semiconductor device may emit UV light, blue light or green light.
  • the nitride semiconductor device described above can be applied to a filament product.
  • the nitride semiconductor device described above can be applied to a COB (Chip on Board) product.
  • COB Chip on Board
  • the nitride semiconductor device described above can be applied to a laser diode product.
  • the nitride semiconductor device described above can be applied to a light emitting diode (Light Emitting Diode) product.
  • a light emitting diode Light Emitting Diode
  • the present invention provides a nitride semiconductor device including a substrate, a buffer layer, a first N-type nitride semiconductor, a nitride semiconductor quantum well light-emitting structure, a P-type nitride semiconductor, a tunnel junction, and a second N-type nitride semiconductor.
  • the substrate has opposite first and second faces.
  • the buffer layer is provided on the first surface of the substrate described above.
  • the first N-type nitride semiconductor described above is provided on the buffer layer described above.
  • the nitride semiconductor quantum well light-emitting structure described above is provided on the first N-type nitride semiconductor described above.
  • the above-described P-type nitride semiconductor is provided on the above-described nitride semiconductor quantum well light-emitting structure.
  • the above tunnel junction is disposed on the nitride semiconductor quantum well light-emitting structure described above.
  • the tunneling junction described above includes a heavily doped P-type (P+) nitride semiconductor and a heavily doped N-type (N+) nitride semiconductor.
  • the above heavily doped P-type (P+) nitride semiconductor is provided on the above-described nitride semiconductor quantum well light-emitting structure.
  • the above heavily doped N-type (N+) nitride semiconductor is provided on the above-described heavily doped P-type nitride semiconductor.
  • the second N-type nitride semiconductor is provided on the above-described heavily doped N-type nitride semiconductor on the tunnel junction surface.
  • the nitride semiconductor quantum well light-emitting structure has a plurality of well layers and a plurality of barrier layers, and the plurality of barrier layers include a first barrier layer disposed at a position closest to the P-type nitride semiconductor, and disposed closest to a second barrier layer of the first N-type nitride semiconductor position and a plurality of third barrier layers, wherein the plurality of third barrier layers are sandwiched by the plurality of well layers, wherein the first barrier layer The thickness is less than the thickness of the third barrier layer described above.
  • the heavily doped P-type semiconductor layer has a thickness of about 1 nm to 100 nm
  • the heavily doped N-type nitride semiconductor layer has a thickness of about 1 nm to 100 nm.
  • the second N-type nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor do not absorb light emitted by the nitride semiconductor quantum well light-emitting structure.
  • the energy gap of the second N-type nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor is larger than the energy gap of the nitride semiconductor quantum well light-emitting structure.
  • the plurality of nitride semiconductor elements are electrically connected in series to form a nitride semiconductor high voltage element.
  • the nitride semiconductor device may emit UV light, blue light or green light.
  • the nitride semiconductor device described above can be applied to a filament product.
  • the nitride semiconductor device described above can be applied to a COB (Chip on Board) product.
  • COB Chip on Board
  • the nitride semiconductor device described above can be applied to a laser diode product.
  • the nitride semiconductor device described above can be applied to a light emitting diode (Light Emitting Diode) product.
  • a light emitting diode Light Emitting Diode
  • the present invention provides a nitride semiconductor device including a first N-type electrode, a first N-type nitride semiconductor, a nitride semiconductor quantum well light-emitting structure, a P-type nitride semiconductor, a tunnel junction, and a tunnel junction a N-type nitride semiconductor, a highly reflective insulating layer, an N-type highly reflective ohmic electrode, a first solder metal layer, a second solder metal layer, a bonding substrate, and a second N-type electrode.
  • the first N-type nitride semiconductor described above is provided on the first N-type electrode described above.
  • the nitride semiconductor quantum well light-emitting structure described above is provided on the first N-type nitride semiconductor described above.
  • the above-described P-type nitride semiconductor is provided on the above-described nitride semiconductor quantum well light-emitting structure.
  • the above tunnel junction is disposed on the nitride semiconductor quantum well light-emitting structure described above.
  • the tunneling junction described above includes a heavily doped P-type (P+) nitride semiconductor and a heavily doped N-type (N+) nitride semiconductor.
  • the above heavily doped P-type (P+) nitride semiconductor is disposed in the above-described nitride semiconductor quantum well Light-emitting structure.
  • the above heavily doped N-type (N+) nitride semiconductor is provided on the above-described heavily doped P-type nitride semiconductor.
  • the second N-type nitride semiconductor is provided on the above-described heavily doped N-type nitride semiconductor on the tunnel junction surface.
  • the high-reflection insulating layer is disposed on the second N-type nitride semiconductor and exposes a portion of the second N-type nitride semiconductor.
  • the N-type high-reflection ohmic electrode is provided on the second N-type nitride semiconductor and covers the high-reflection insulating layer and the second N-type nitride semiconductor.
  • the first solder metal layer described above is disposed on the N-type high reflection ohmic electrode described above.
  • the second solder metal layer is disposed on the first solder metal layer.
  • the bonding substrate is provided on the second solder metal layer and electrically connected to the first solder metal layer.
  • the second N-type electrode is provided on the bonding substrate and electrically connected to the bonding substrate.
  • the nitride semiconductor quantum well light-emitting structure has a plurality of well layers and a plurality of barrier layers
  • the plurality of barrier layers include a first barrier layer disposed at a position closest to the P-type nitride semiconductor, and disposed closest to a second barrier layer of the first N-type nitride semiconductor position and a plurality of third barrier layers, wherein the plurality of third barrier layers are sandwiched by the plurality of well layers, wherein the first barrier layer The thickness is smaller than the thickness of the second barrier layer described above.
  • the heavily doped P-type semiconductor layer has a thickness of about 1 nm to 100 nm
  • the heavily doped N-type nitride semiconductor layer has a thickness of about 1 nm to 100 nm.
  • the second N-type nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor do not absorb light emitted by the nitride semiconductor quantum well light-emitting structure.
  • the energy gap of the second N-type nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor is larger than the energy gap of the nitride semiconductor quantum well light-emitting structure.
  • the plurality of nitride semiconductor elements are electrically connected in series to form a nitride semiconductor high voltage element.
  • the nitride semiconductor device may emit UV light, blue light or green light.
  • the nitride semiconductor device described above can be applied to a filament product.
  • the nitride semiconductor device described above can be applied to a COB (Chip) On Board) products.
  • the nitride semiconductor device described above can be applied to a laser diode product.
  • the nitride semiconductor device described above can be applied to a light emitting diode (Light Emitting Diode) product.
  • a light emitting diode Light Emitting Diode
  • the present invention provides a nitride semiconductor device including a first N-type electrode, a first N-type nitride semiconductor, a nitride semiconductor quantum well light-emitting structure, a P-type nitride semiconductor, a tunnel junction, and a tunnel junction a N-type nitride semiconductor, a highly reflective insulating layer, an N-type highly reflective ohmic electrode, a first solder metal layer, a second solder metal layer, a bonding substrate, and a second N-type electrode.
  • the first N-type nitride semiconductor described above is provided on the first N-type electrode described above.
  • the nitride semiconductor quantum well light-emitting structure described above is provided on the first N-type nitride semiconductor described above.
  • the above-described P-type nitride semiconductor is provided on the above-described nitride semiconductor quantum well light-emitting structure.
  • the above tunnel junction is disposed on the nitride semiconductor quantum well light-emitting structure described above.
  • the tunneling junction described above includes a heavily doped P-type (P+) nitride semiconductor and a heavily doped N-type (N+) nitride semiconductor.
  • the above heavily doped P-type (P+) nitride semiconductor is provided on the above-described nitride semiconductor quantum well light-emitting structure.
  • the above heavily doped N-type (N+) nitride semiconductor is provided on the above-described heavily doped P-type nitride semiconductor.
  • the second N-type nitride semiconductor is provided on the above-described heavily doped N-type nitride semiconductor on the tunnel junction surface.
  • the high-reflection insulating layer is disposed on the second N-type nitride semiconductor and exposes a portion of the second N-type nitride semiconductor.
  • the N-type high-reflection ohmic electrode is provided on the second N-type nitride semiconductor and covers the high-reflection insulating layer and the second N-type nitride semiconductor.
  • the first solder metal layer described above is disposed on the N-type high reflection ohmic electrode described above.
  • the second solder metal layer is disposed on the first solder metal layer.
  • the bonding substrate is provided on the second solder metal layer and electrically connected to the first solder metal layer.
  • the second N-type electrode is provided on the above-described bonding substrate, and is electrically connected to the bonding substrate described above.
  • the nitride semiconductor quantum well light-emitting structure has a plurality of well layers and a plurality of barrier layers
  • the plurality of barrier layers include a first barrier layer disposed at a position closest to the P-type nitride semiconductor, and disposed closest to a second barrier layer of the first N-type nitride semiconductor position and a plurality of third barrier layers, wherein the plurality of third barrier layers are sandwiched by the plurality of well layers, wherein the first barrier layer The thickness is less than the thickness of the third barrier layer described above.
  • the heavily doped P-type semiconductor layer has a thickness of about 1 nm to 100 nm
  • the heavily doped N-type nitride semiconductor layer has a thickness of about 1 nm to 100 nm.
  • the second N-type nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor do not absorb light emitted by the nitride semiconductor quantum well light-emitting structure.
  • the energy gap of the second N-type nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor is larger than the energy gap of the nitride semiconductor quantum well light-emitting structure.
  • the plurality of nitride semiconductor elements are electrically connected in series to form a nitride semiconductor high voltage element.
  • the nitride semiconductor device may emit UV light, blue light or green light.
  • the nitride semiconductor device described above can be applied to a filament product.
  • the nitride semiconductor device described above can be applied to a COB (Chip on Board) product.
  • COB Chip on Board
  • the nitride semiconductor device described above can be applied to a laser diode product.
  • the nitride semiconductor device described above can be applied to a light emitting diode (Light Emitting Diode) product.
  • a light emitting diode Light Emitting Diode
  • the present invention provides a method of fabricating a nitride semiconductor device comprising the following steps. Forming a semiconductor wafer. The semiconductor wafer is cut by a stealth laser to form a nitride semiconductor device according to any of the above embodiments.
  • the present invention provides a package structure comprising a circuit board, a bracket or a carrier and a nitride semiconductor component as in any of the above embodiments.
  • the above bracket or the above carrier is provided on the above circuit board.
  • the nitride semiconductor device described above is provided on the above-described holder or the above-described carrier.
  • the package structure further includes a transparent adhesive covering the nitride semiconductor device of any of the above embodiments.
  • the package structure further includes a phosphor powder filled in the transparent glue.
  • the concentration of the phosphor powder is uniformly distributed in the transparent paste.
  • the concentration of the phosphor powder is unevenly distributed in the above-mentioned In gelatin.
  • the concentration of the phosphor powder is gradually increased from the surface of the nitride semiconductor element in any of the above embodiments to the surface of the transparent paste.
  • the concentration of the phosphor powder is gradually reduced from the surface of the nitride semiconductor element in any of the above embodiments to the surface of the transparent paste.
  • the phosphor powder is made of a material having high stable luminescent properties, and includes Garnet, Sulfate, Nitrate, and silicate. (Silicate), aluminate (Aluminate) or any combination of the above materials, having an emission wavelength of about 300 nm to 700 nm, wherein the above-mentioned phosphor powder has a particle diameter of 1 to 25 ⁇ m, wherein the nitride semiconductor element is produced by the above-mentioned A part of the light can excite the phosphor powder, so that the phosphor powder generates a longer wavelength of light, and the remaining portion of the nitride semiconductor element is not generated by the phosphor converted by the phosphor and the phosphor powder.
  • the light can be mixed into white light.
  • the present invention provides a nitride semiconductor high voltage device including a circuit board and a plurality of nitride semiconductor elements.
  • the plurality of nitride semiconductor elements described above are provided on the above-described circuit board and electrically connected in series.
  • Each of the plurality of nitride semiconductor elements described above includes a first N-type nitride semiconductor, a nitride semiconductor quantum well light-emitting structure, a P-type nitride semiconductor, a tunnel junction, a second N-type nitride semiconductor, A first N-type electrode and a second N-type electrode.
  • the first N-type nitride semiconductor described above is provided on the above-described circuit board.
  • the nitride semiconductor quantum well light-emitting structure described above is provided on the first N-type nitride semiconductor described above.
  • the above-described P-type nitride semiconductor is provided on the above-described nitride semiconductor quantum well light-emitting structure.
  • the above tunnel junction is disposed on the nitride semiconductor quantum well light-emitting structure described above.
  • the tunneling junction described above includes a heavily doped P-type (P+) nitride semiconductor and a heavily doped N-type (N+) nitride semiconductor.
  • the above heavily doped P-type (P+) nitride semiconductor is provided on the above-described nitride semiconductor quantum well light-emitting structure.
  • the above heavily doped N-type (N+) nitride semiconductor is provided on the above-described heavily doped P-type nitride semiconductor.
  • the second N-type nitride semiconductor is provided on the above-described heavily doped N-type nitride semiconductor on the tunnel junction surface.
  • the first N-type electrode is provided on one side of the first N-type nitride semiconductor.
  • the second N-type electrode is provided on the second N-type nitride semiconductor.
  • the first N-type electrode of one of the plurality of nitride semiconductor elements described above is electrically connected to the P-type nitride semiconductor of one of the other plurality of nitride semiconductor elements described above.
  • the heavily doped P-type semiconductor layer has a thickness of about 1 nm to 100 nm
  • the heavily doped N-type nitride semiconductor layer has a thickness of about 1 nm to 100 nm.
  • the tunneling junction further includes an intermediate semiconductor disposed on the heavily doped P-type (P+) nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor.
  • the intermediate semiconductor described above forms a heterojunction with respect to the above-mentioned heavily doped P-type (P+) nitride semiconductor and the above-mentioned heavily doped N-type (N+) nitride semiconductor to establish a polarization field, so that the above The valence band of the heavily doped P-type (P+) nitride semiconductor and the conduction band of the above-described heavily doped N-type (N+) nitride semiconductor correspond to each other.
  • At least one of the heavily doped P-type (P+) nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor has a larger energy gap than the nitride semiconductor quantum The energy gap of the well-emitting structure.
  • the intermediate semiconductor comprises aluminum gallium nitride (AlGaN), gallium nitride (GaN), indium gallium nitride (InGaN) or indium aluminum gallium nitride (InAlGaN).
  • AlGaN aluminum gallium nitride
  • GaN gallium nitride
  • InGaN indium gallium nitride
  • InAlGaN indium aluminum gallium nitride
  • the intermediate semiconductor has an internal band gap barrier
  • the heavily doped P-type (P+) nitride semiconductor has a P-type depletion barrier (P-depletion). Barrier
  • the above heavily doped N-type (N+) nitride semiconductor has an N-depletion barrier.
  • the intermediate semiconductor has a thickness of about 0.5 nm to 10 nm.
  • the intermediate semiconductor has lateral material energy bandgaps, which includes a plurality of low and high band gap regions.
  • the plurality of nitride semiconductor units are covered by a transparent adhesive, and the transparent adhesive comprises a phosphor.
  • the concentration of the phosphor powder is uniformly distributed in the transparent paste.
  • the concentration of the phosphor powder is unevenly distributed in the transparent paste.
  • the concentration of the phosphor powder is gradually increased from the surface of the nitride semiconductor unit to the surface of the transparent paste.
  • the concentration of the phosphor powder is gradually reduced from the surface of the nitride semiconductor unit to the surface of the transparent paste.
  • the phosphor powder is made of a material having high stable luminescent properties, and includes Garnet, Sulfate, Nitrate, and Silicic Acid. a salt (Silicate), an aluminate (Aluminate) or any combination of the above materials, having an emission wavelength of about 300 nm to 700 nm, wherein the above-mentioned phosphor powder has a particle diameter of 1 to 25 ⁇ m, wherein the above-described nitride semiconductor device is produced.
  • a salt Silicate
  • Alluminate aluminate
  • a part of the light can excite the above-mentioned phosphor powder, so that the above-mentioned phosphor powder generates light of a longer wavelength, and the remaining part of the nitride semiconductor element is not converted by the above-mentioned phosphor powder and the above-mentioned phosphor powder
  • the resulting light can be mixed into white light.
  • the nitride semiconductor quantum well light-emitting structure has a plurality of well layers and a plurality of barrier layers, and the plurality of barrier layers include a portion disposed closest to the position of the P-type nitride semiconductor. a barrier layer, a second barrier layer disposed at a position closest to the first N-type nitride semiconductor region, and a plurality of third barrier layers, wherein the plurality of third barrier layers are sandwiched by the plurality of well layers Wherein the thickness of the second barrier layer is greater than the thickness of the first barrier layer, the thickness of the third barrier layer is greater than the thickness of the first barrier layer, and the thickness of the second barrier layer is greater than or equal to the third barrier The thickness of the layer.
  • the nitride semiconductor quantum well light-emitting structure has a plurality of well layers and a plurality of barrier layers, and the plurality of barrier layers include a portion disposed closest to the position of the P-type nitride semiconductor. a barrier layer, a second barrier layer disposed at a position closest to the first N-type nitride semiconductor region, and a plurality of third barrier layers, wherein the plurality of third barrier layers are sandwiched by the plurality of well layers Wherein the thickness of the second barrier layer is greater than the thickness of the first barrier layer, the thickness of the third barrier layer is greater than the thickness of the first barrier layer, and the thickness of the second barrier layer is less than or equal to the above The thickness of the three barrier layers.
  • At least one of the first N-type nitride semiconductor and the second N-type nitride semiconductor has a rough surface for increasing the light-emitting effect of the nitride semiconductor device.
  • the present invention provides a nitride semiconductor high voltage device including a circuit board and a plurality of nitride semiconductor elements.
  • the plurality of nitride semiconductor elements described above are provided on the above-described circuit board and electrically connected in series.
  • Each of the plurality of nitride semiconductor elements includes a first N-type electrode, a first N-type nitride semiconductor, a nitride semiconductor quantum well light-emitting structure, a P-type nitride semiconductor, a tunnel junction, and a second An N-type nitride semiconductor, a highly reflective insulating layer, an N-type highly reflective ohmic electrode, a first solder metal layer, a second solder metal layer, a bonding substrate, and a second N-type electrode.
  • the first N-type nitride semiconductor described above is provided on the first N-type electrode described above.
  • the nitride semiconductor quantum well light-emitting structure described above is provided on the first N-type nitride semiconductor described above.
  • the above-described P-type nitride semiconductor is provided on the above-described nitride semiconductor quantum well light-emitting structure.
  • the above tunnel junction is disposed on the nitride semiconductor quantum well light-emitting structure described above.
  • the tunneling junction described above includes a heavily doped P-type (P+) nitride semiconductor and a heavily doped N-type (N+) nitride semiconductor body.
  • the above heavily doped P-type (P+) nitride semiconductor is provided on the above-described nitride semiconductor quantum well light-emitting structure.
  • the above heavily doped N-type (N+) nitride semiconductor is provided on the above-described heavily doped P-type nitride semiconductor.
  • the second N-type nitride semiconductor is provided on the above-described heavily doped N-type nitride semiconductor on the tunnel junction surface.
  • the high-reflection insulating layer is disposed on the second N-type nitride semiconductor and exposes a portion of the second N-type nitride semiconductor.
  • the N-type high-reflection ohmic electrode is provided on the second N-type nitride semiconductor and covers the high-reflection insulating layer and the second N-type nitride semiconductor.
  • the first solder metal layer described above is disposed on the N-type high reflection ohmic electrode described above.
  • the second solder metal layer is disposed on the first solder metal layer.
  • the bonding substrate is provided on the second solder metal layer and electrically connected to the first solder metal layer.
  • the second N-type electrode is provided on the above-described bonding substrate, and is electrically connected to the bonding substrate described above.
  • the first N-type electrode of one of the plurality of nitride semiconductor elements described above is electrically connected to the P-type nitride semiconductor of one of the other plurality of nitride semiconductor elements described above.
  • the heavily doped P-type semiconductor layer has a thickness of about 1 nm to 100 nm
  • the heavily doped N-type nitride semiconductor layer has a thickness of about 1 nm to 100 nm.
  • the tunneling junction further includes an intermediate semiconductor disposed on the heavily doped P-type (P+) nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor.
  • the intermediate semiconductor described above forms a heterojunction with respect to the above-mentioned heavily doped P-type (P+) nitride semiconductor and the above-mentioned heavily doped N-type (N+) nitride semiconductor to establish a polarization field, so that the above The valence band of the heavily doped P-type (P+) nitride semiconductor and the conduction band of the above-described heavily doped N-type (N+) nitride semiconductor correspond to each other.
  • At least one of the heavily doped P-type (P+) nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor has a larger energy gap than the nitride semiconductor quantum The energy gap of the well-emitting structure.
  • the intermediate semiconductor comprises aluminum gallium nitride (AlGaN), gallium nitride (GaN), indium gallium nitride (InGaN) or indium aluminum gallium nitride (InAlGaN).
  • AlGaN aluminum gallium nitride
  • GaN gallium nitride
  • InGaN indium gallium nitride
  • InAlGaN indium aluminum gallium nitride
  • the intermediate semiconductor has an internal band gap barrier
  • the heavily doped P-type (P+) nitride semiconductor has a P-type depletion barrier (P-depletion). Barrier
  • the above heavily doped N-type (N+) nitride semiconductor has an N-depletion barrier.
  • the intermediate semiconductor has a thickness of about 0.5 nm to 10 nm.
  • the intermediate semiconductor has lateral material energy bandgaps, which includes a plurality of low and high band gap regions.
  • the plurality of nitride semiconductor units are covered by a transparent adhesive, and the transparent adhesive comprises a phosphor.
  • the concentration of the phosphor powder is uniformly distributed in the transparent paste.
  • the concentration of the phosphor powder is unevenly distributed in the transparent paste.
  • the concentration of the phosphor powder is gradually increased from the surface of the nitride semiconductor unit to the surface of the transparent paste.
  • the concentration of the phosphor powder is gradually reduced from the surface of the nitride semiconductor unit to the surface of the transparent paste.
  • the phosphor powder is made of a material having high stable luminescent properties, and includes Garnet, Sulfate, Nitrate, and silicate. (Silicate), aluminate (Aluminate) or any combination of the above materials, having an emission wavelength of about 300 nm to 700 nm, wherein the above-mentioned phosphor powder has a particle diameter of 1 to 25 ⁇ m, wherein the nitride semiconductor element is produced by the above-mentioned A part of the light can excite the phosphor powder, so that the phosphor powder generates a longer wavelength of light, and the remaining portion of the nitride semiconductor element is not generated by the phosphor converted by the phosphor and the phosphor powder.
  • the light can be mixed into white light.
  • the nitride semiconductor quantum well light-emitting structure has a plurality of well layers and a plurality of barrier layers, and the plurality of barrier layers include a portion disposed closest to the position of the P-type nitride semiconductor. a barrier layer, a second barrier layer disposed at a position closest to the first N-type nitride semiconductor region, and a plurality of third barrier layers, wherein the plurality of third barrier layers are sandwiched by the plurality of well layers Wherein the thickness of the second barrier layer is greater than the thickness of the first barrier layer, the thickness of the third barrier layer is greater than the thickness of the first barrier layer, and the thickness of the second barrier layer is greater than or equal to the third barrier The thickness of the layer.
  • the nitride semiconductor quantum well light-emitting structure has a plurality of well layers and a plurality of barrier layers, and the plurality of barrier layers include a portion disposed closest to the position of the P-type nitride semiconductor. a barrier layer, a second barrier layer disposed at a position closest to the first N-type nitride semiconductor region, and a plurality of third barrier layers, wherein the plurality of third barrier layers are sandwiched by the plurality of well layers Wherein the thickness of the second barrier layer is greater than the thickness of the first barrier layer, The thickness of the third barrier layer is greater than the thickness of the first barrier layer, and the thickness of the second barrier layer is less than or equal to the thickness of the third barrier layer.
  • At least one of the first N-type nitride semiconductor and the second N-type nitride semiconductor has a rough surface for increasing the light-emitting effect of the nitride semiconductor device.
  • the present invention provides a nitride semiconductor device including a substrate, a buffer layer, a first N-type nitride semiconductor, a nitride semiconductor quantum well light-emitting structure, a P-type nitride semiconductor, a tunnel junction, and a second N-type nitride semiconductor.
  • the substrate has opposite first and second faces.
  • the buffer layer is provided on the first surface of the substrate described above.
  • the first N-type nitride semiconductor described above is provided on the buffer layer described above.
  • the nitride semiconductor quantum well light-emitting structure described above is provided on the first N-type nitride semiconductor described above.
  • the above-described P-type nitride semiconductor is provided on the above-described nitride semiconductor quantum well light-emitting structure.
  • the P-type nitride semiconductor described above includes a P-side stress releasing layer, a high-concentration hole layer, and an electron blocking layer.
  • the above tunnel junction is disposed on the nitride semiconductor quantum well light-emitting structure described above.
  • the tunneling junction described above includes a heavily doped P-type (P+) nitride semiconductor and a heavily doped N-type (N+) nitride semiconductor.
  • the above heavily doped P-type (P+) nitride semiconductor is provided on the above-described nitride semiconductor quantum well light-emitting structure.
  • the above heavily doped N-type (N+) nitride semiconductor is provided on the above-described heavily doped P-type nitride semiconductor.
  • the second N-type nitride semiconductor is provided on the above-described heavily doped N-type nitride semiconductor on the tunnel junction surface.
  • the nitride semiconductor quantum well light-emitting structure has a plurality of well layers and a plurality of barrier layers
  • the plurality of barrier layers include a first barrier layer disposed at a position closest to the P-type nitride semiconductor, and disposed closest to a second barrier layer of the first N-type nitride semiconductor position and a plurality of third barrier layers, wherein the plurality of third barrier layers are sandwiched by the plurality of well layers, wherein the first layer is disposed closest to the first a barrier layer is the P-side stress relieving layer, and the first barrier layer farthest from the above is the above-mentioned electron blocking layer, and the high-concentration hole layer is the P-side stress releasing layer and the electron blocking layer. Caught.
  • the P-side stress relief layer may be a superlattice structure, the material of which comprises a superlattice structure composed of aluminum gallium nitride (AlGaN) and gallium nitride (GaN), or a superlattice structure composed of aluminum gallium nitride (Al x GaN) and aluminum gallium nitride (Al y GaN), or composed of aluminum gallium nitride (AlGaN) and aluminum indium gallium nitride (InAlGaN)
  • a superlattice structure in which x is not equal to y and the superlattice structure described above is less than 20 pairs.
  • the high concentration hole layer may be composed of gallium nitride (GaN) or aluminum gallium nitride (AlGaN), and the magnesium concentration of the high concentration hole layer is concentrated. It is higher than the magnesium doping concentration of the P-side stress releasing layer described above and the magnesium doping concentration of the above-described electron blocking layer.
  • the high concentration hole layer has a magnesium (Mg) doping concentration higher than 1 x 10 19 (Atoms/cm 3 ).
  • the electron blocking layer may be composed of aluminum gallium nitride (AlGaN), and the percentage of the aluminum component of the electron blocking layer is higher than the percentage of the aluminum component of the P-side stress releasing layer and higher than The percentage of aluminum component of the above-mentioned high concentration hole layer.
  • AlGaN aluminum gallium nitride
  • the tunneling junction further includes an intermediate semiconductor disposed on the heavily doped P-type (P+) nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor between.
  • the high concentration hole layer has a magnesium (Mg) doping concentration higher than 1 ⁇ 10 19 (Atoms/cm 3 ), and the high concentration hole layer has a lower aluminum component percentage than the above. The percentage of aluminum component of the electronic barrier layer.
  • the second N-type nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor do not absorb light emitted by the nitride semiconductor quantum well light-emitting structure.
  • the energy gap of the second N-type nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor is larger than the energy gap of the nitride semiconductor quantum well light-emitting structure.
  • the plurality of nitride semiconductor elements are electrically connected in series to form a nitride semiconductor high voltage element.
  • the nitride semiconductor device may emit UV light, blue light or green light.
  • the nitride semiconductor device described above can be applied to a filament product.
  • the nitride semiconductor device described above can be applied to a COB (Chip on Board) product.
  • COB Chip on Board
  • the nitride semiconductor device described above can be applied to a laser diode product.
  • the nitride semiconductor device described above can be applied to a light emitting diode (Light Emitting Diode) product.
  • a light emitting diode Light Emitting Diode
  • the present invention provides a nitride semiconductor device including a substrate, a buffer layer, a first N-type nitride semiconductor, a nitride semiconductor quantum well light-emitting structure, a P-type nitride semiconductor, a tunnel junction, and a second N-type nitride semiconductor.
  • the substrate has opposite first and second faces.
  • the buffer layer is provided on the first surface of the substrate described above. Above An N-type nitride semiconductor is provided on the above buffer layer.
  • the first N-type nitride semiconductor described above includes an N-side first stress releasing layer, an N-side second stress releasing layer, a low-concentration electron layer, and an N-type ohmic contact layer.
  • the nitride semiconductor quantum well light-emitting structure described above is provided on the first N-type nitride semiconductor described above.
  • the above-described P-type nitride semiconductor is provided on the above-described nitride semiconductor quantum well light-emitting structure.
  • the above tunnel junction is disposed on the nitride semiconductor quantum well light-emitting structure described above.
  • the tunneling junction described above includes a heavily doped P-type (P+) nitride semiconductor and a heavily doped N-type (N+) nitride semiconductor.
  • the above heavily doped P-type (P+) nitride semiconductor is provided on the above-described nitride semiconductor quantum well light-emitting structure.
  • the above heavily doped N-type (N+) nitride semiconductor is provided on the above-described heavily doped P-type nitride semiconductor.
  • the second N-type nitride semiconductor described above is provided on the above-described heavily doped N-type nitride semiconductor on the tunnel junction surface.
  • the nitride semiconductor quantum well light-emitting structure has a plurality of well layers and a plurality of barrier layers
  • the plurality of barrier layers include a first barrier layer disposed at a position closest to the P-type nitride semiconductor, and disposed closest to a second barrier layer of the first N-type nitride semiconductor position and a plurality of third barrier layers, wherein the plurality of third barrier layers are sandwiched by the plurality of well layers, wherein the first layer is disposed closest to the first
  • the second barrier layer is the N-side first stress relief layer, and the second barrier layer farthest from the above is the N-type ohmic contact layer, and the low-concentration electron layer and the second stress-relieving layer are sequentially arranged. Stacked above the N-type ohmic contact layer, the low-concentration electron layer is sandwiched by the N-type ohmic contact layer and the N-side second stress-relieving layer.
  • the N-side first stress relief layer may be a superlattice structure, and the material thereof comprises a superlattice structure composed of indium gallium nitride (InGaN) and gallium nitride (GaN). Or a superlattice structure composed of indium gallium nitride (In x GaN) and indium gallium nitride (In y GaN), wherein x is not equal to y, and the superlattice structure described above is less than 20 pairs.
  • the N-side second stress relief layer may be a superlattice structure, and the material thereof comprises a superlattice structure composed of indium gallium nitride (InGaN) and gallium nitride (GaN). Or a superlattice structure composed of indium gallium nitride (In x GaN) and indium gallium nitride (In y GaN), wherein x is not equal to y, and the superlattice structure described above is less than 20 pairs.
  • the percentage of indium component of the N-side first stress-relieving layer is higher than the percentage of the indium component of the N-side second stress-relieving layer.
  • the low-concentration electron layer may be formed of gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), or indium aluminum gallium nitride (InAlGaN).
  • GaN gallium nitride
  • InGaN indium gallium nitride
  • AlGaN aluminum gallium nitride
  • InAlGaN indium aluminum gallium nitride
  • the low concentration electron layer has a silicon doping concentration of less than 1 x 10 18 (Atoms/cm 3 ).
  • the N-type ohmic contact layer may be formed of gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN) or indium aluminum gallium nitride (InAlGaN).
  • the silicon doping concentration of the N-type ohmic contact layer is higher than the silicon doping concentration of the N-side first stress releasing layer, the silicon doping concentration of the N-side second stress releasing layer, and the low-concentration electron described above. The silicon doping concentration of the layer.
  • the second N-type nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor do not absorb light emitted by the nitride semiconductor quantum well light-emitting structure.
  • the energy gap of the second N-type nitride semiconductor and the heavily doped N-type (N+) nitride semiconductor is larger than the energy gap of the nitride semiconductor quantum well light-emitting structure.
  • the plurality of nitride semiconductor elements are electrically connected in series to form a nitride semiconductor high voltage element.
  • the nitride semiconductor device may emit UV light, blue light or green light.
  • the nitride semiconductor device described above can be applied to a filament product.
  • the nitride semiconductor device described above can be applied to a COB (Chip on Board) product.
  • COB Chip on Board
  • the nitride semiconductor device described above can be applied to a laser diode product.
  • the nitride semiconductor device described above can be applied to a light emitting diode (Light Emitting Diode) product.
  • a light emitting diode Light Emitting Diode
  • the structure and process of the Current Blocking Layer (CBL) and the Transparent Conductive Layer (TCL) may be omitted based on the tunnel junction structure.
  • CBL Current Blocking Layer
  • TTL Transparent Conductive Layer
  • the nitride semiconductor device of the present invention can improve luminous efficiency and improve process yield.
  • the method for producing a nitride semiconductor device of the present invention can be used to fabricate the above-described nitride semiconductor device.
  • the package structure of the present invention can be applied to the above-described nitride semiconductor device.
  • Figure 1 is a cross-sectional view showing a nitride semiconductor device in accordance with a first embodiment of the present invention. Figure.
  • FIG. 2 is a schematic cross-sectional view showing a nitride semiconductor device in accordance with a second embodiment of the present invention.
  • Figure 3 is a cross-sectional view showing a nitride semiconductor device in accordance with a third embodiment of the present invention.
  • Figure 4 is a cross-sectional view showing a nitride semiconductor device in accordance with a fourth embodiment of the present invention.
  • Figure 5 is a cross-sectional view showing a nitride semiconductor device in accordance with a fifth embodiment of the present invention.
  • Figure 6 is a cross-sectional view showing a nitride semiconductor device in accordance with a sixth embodiment of the present invention.
  • Figure 7 is a cross-sectional view showing a nitride semiconductor high voltage device in accordance with a seventh embodiment of the present invention.
  • Figure 8 is a cross-sectional view showing a nitride semiconductor high voltage device in accordance with an eighth embodiment of the present invention.
  • Figure 9 is a cross-sectional view showing a nitride semiconductor high voltage device in accordance with a ninth embodiment of the present invention.
  • Figure 10 is a cross-sectional view showing a nitride semiconductor high voltage device in accordance with a tenth embodiment of the present invention.
  • Figure 11 is a cross-sectional view showing a package structure of a nitride semiconductor device in accordance with an eleventh embodiment of the present invention.
  • Figure 12 is a cross-sectional view showing a package structure of a nitride semiconductor device in accordance with a twelfth embodiment of the present invention.
  • Figure 13 is a cross-sectional view showing a package structure of a nitride semiconductor device in accordance with a thirteenth embodiment of the present invention.
  • Figure 14 is a flow chart showing the manufacture of a nitride semiconductor device in accordance with the present invention.
  • nitride semiconductor components 100, 200, 300, 400, 500, 600, 1100a, 1200a, 1300a: nitride semiconductor components
  • 700a, 800a, 900a, 1000a first nitride semiconductor component
  • 700b, 800b, 900b, 1000b second nitride semiconductor component
  • FIG. 1 is a schematic cross-sectional view showing a nitride semiconductor device in accordance with a first embodiment of the present invention.
  • the nitride semiconductor device 100 of the present embodiment includes a P-type nitride semiconductor 101, an N-type nitride semiconductor 102, a nitride semiconductor quantum well light-emitting structure 103, a substrate 104, and a buffer layer 105.
  • the nitride semiconductor quantum well light emitting structure 103 is located between the P-type nitride semiconductor 101 and the N-type nitride semiconductor 102.
  • the substrate 104 has opposing first and second faces 104A, 104B.
  • the buffer layer 105 is located between the N-type nitride semiconductor 102 and the first surface 104A of the substrate 104.
  • the nitride semiconductor quantum well light emitting structure 103 has a plurality of well layers 103A and a plurality of barrier layers 103B.
  • the plurality of barrier layers 103B include a first barrier layer 103B1 disposed at a position closest to the P-type nitride semiconductor 101, a second barrier layer 103B2 disposed at a position closest to the N-type nitride semiconductor 102, and at least one third barrier layer 103B3. In the embodiment illustrated in FIG.
  • the number of the third barrier layers 103B3 is exemplified by one, but the present invention does not limit the number of the third barrier layers 103B3.
  • the opposite ends of the third barrier layer 103B3 are respectively sandwiched by the corresponding two well layers 103A.
  • the plurality of well layers 103A and the respective plurality of barrier layers 103B are alternately arranged with each other.
  • the thickness of the first barrier layer 103B1 is less than 100 angstroms .
  • the nitride semiconductor device 100 of the present embodiment may be a light emitting diode (LED) having a horizontal structure.
  • the thickness of the second barrier layer 103B2 may be greater than the thickness of the first barrier layer 103B1, but the invention is not limited thereto.
  • the thickness of the third barrier layer 103B3 may be greater than the thickness of the first barrier layer 103B1, but the invention is not limited thereto.
  • the first barrier layer 103B1 may have a thickness of less than 50 angstroms. However, the invention is not limited thereto.
  • the nitride semiconductor may include gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN) or gallium nitride as the compound crystal (In x Al y Ga 1-xy N, 0) ⁇ x,0 ⁇ y,x+y ⁇ 1).
  • a group IIIA element for example, boron (B)
  • a group VA element for example, phosphorus (P), arsenic (As)
  • a group IIIA element for example, boron (B)
  • a group VA element for example, phosphorus (P), arsenic (As)
  • P phosphorus
  • As arsenic
  • the nitride semiconductor quantum well light-emitting structure 103 may have a multiple quantum well (MQW) structure or a single quantum well (SQW) structure, which is not limited in the present invention.
  • multiple quantum well configurations may be formed to increase the output or reduce the oscillation threshold.
  • a plurality of well layers 103A and a plurality of barrier layers 103B may be alternately staggered to form a quantum well structure having a stacked structure.
  • the barrier layer 103B may be sandwiched into the corresponding two well layers 103A to form a laminated structure.
  • At least one barrier layer 103B may be provided on one side of the P-type nitride semiconductor 101 layer and one side of the N-type nitride semiconductor 102 layer to sandwich the well layer 103A.
  • the quantum well configuration may have other configurations, which are not limited in the present invention.
  • the foregoing multiple quantum well configuration may have at least one barrier layer 103B (ie, first barrier layer 103B1) on one side of the P-type nitride semiconductor 101 layer, and an N-type nitride semiconductor 102 layer.
  • Each of the first barrier layer 103B1 and the second barrier layer 103B2 has at least one barrier layer 103B (ie, the third barrier layer 103B3), To sandwich a plurality of well layers 103A.
  • the first barrier layer 103B1, the second barrier layer 103B2, and the third barrier layer 103B3 are respectively different film layers.
  • the opposite outermost sides of the nitride semiconductor quantum well light emitting structure 103 may be the first barrier layer 103B1 and the second barrier layer 103B2, respectively.
  • the barrier layer 103B sandwiched by the different well layers 103A is not limited to one layer (for example, the first well layer 103A/barrier layer 103B/second well layer 103A) .
  • two or more layers of the plurality of barrier layers 103B may also be sandwiched between different well layers 103A (eg, first well layer 103A/first barrier layer 103B1/second barrier)
  • the layer 103B2 / the second well layer 103A), and the composition or impurity doping amount between the foregoing plurality of barrier layers 103B may be different from each other.
  • the well layer 103A may be a nitride semiconductor layer containing indium.
  • the composition of the well layer 103A may be In ⁇ Ga 1- ⁇ N (0 ⁇ 1) or InAlGaN.
  • the well layer 103A having good luminescence or oscillation can be formed.
  • the mixed crystal ratio of indium in the well layer 103A may also cause the nitride semiconductor quantum well light-emitting structure 103 to have a corresponding light-emitting wavelength.
  • the composition of the well layer 103A may also be a nitride semiconductor containing no indium, such as AlGaN, GaN, etc., and the invention is not limited thereto.
  • the present invention does not limit the film thickness and number of the well layer 103A.
  • the film thickness of the well layer 103A may be in the range of 10 angstroms or more and 300 angstroms or less.
  • the film thickness of the well layer 103A is in the range of 20 angstroms or more and 200 angstroms or less, and the forward voltage (Vf) and/or the critical current density of the nitride semiconductor device 100 can be lowered. .
  • the film thickness of the well layer 103A above 20 angstroms can increase the uniformity of the film layer, and the film thickness of the well layer 103A is 200 angstroms. Lower crystal defects can be reduced.
  • the number of well layers 103A may be 1 or more. In general, when the number of the well layers 103A is 4 or more, the film thickness of each layer of the nitride semiconductor quantum well light-emitting structure 103 is thickened correspondingly, and the overall thickness of the nitride semiconductor quantum well light-emitting structure 103 is further increased. , thus causing the forward voltage to rise.
  • the film thickness of the well layer 103A may be made to be in the range of 100 angstroms or less, and thus the overall thickness of the nitride semiconductor quantum well light-emitting structure 103 may be further reduced.
  • the doping of the well layer 103A is not limited in the present invention.
  • the well layer 103A is a nitride semiconductor containing indium
  • the doping concentration of the N-type impurity is increased, the crystallinity of the well layer 103A may be lowered. Therefore, the doping concentration of the N-type impurity of the well layer 103A can be lowered to enhance the crystallinity of the well layer 103A, and the quality of the nitride semiconductor device 100 can be further improved.
  • the doping concentration of the N-type impurity is 5 ⁇ 10 16 atoms/cm 3 or less, it can be considered that there is no N-type impurity.
  • the doping concentration of the N-type impurity is in the range of 1 ⁇ 10 18 atoms/cm 3 or less and 5 ⁇ 10 16 atoms/cm 3 or more, the crystallinity can be improved and the carrier can be lifted.
  • the carrier concentration reduces the forward voltage and/or the critical current density of the nitride semiconductor device 100.
  • the doping concentration of the N-type impurity of the well layer 103A may be substantially less than or equal to the doping concentration of the N-type impurity of the barrier layer 103B. In terms of the process, less N-type impurities may be incorporated in the step of forming the well layer 103A than the step of forming the barrier layer 103B. Alternatively, the N-type impurity is doped in the step of forming the barrier layer 103B, and the N-type impurity is not incorporated in the step of forming the well layer 103A. In this way, the light recombination of the well layer 103A can be improved, and the luminous efficiency of the nitride semiconductor device 100 can be further improved.
  • the above-described impurity-type light-emitting element can have a good quality by reducing the density of its forward voltage and/or critical current.
  • the well layer 103A and the barrier layer 103B may be formed as part of the nitride semiconductor quantum well light-emitting structure 103 without doping growth.
  • the well layer 103A may be substantially free of N-type impurities, and may facilitate carrier recombination within the well layer 103A to enhance luminescence recombination of the well layer 103A, thereby further enhancing nitrogen.
  • the luminous efficiency of the semiconductor device 100 if the well layer 103A has an N-type impurity, since the carrier concentration of the well layer 103A is high, the probability of recombination of the well layer 103A may be lowered, so that a driving circuit rises at a certain output. It is possible to reduce the reliability or life time of the nitride semiconductor device 100.
  • the N-type impurity concentration of the well layer 103A can be 1 ⁇ 10 18 atoms/cm 3 or less, and the nitride semiconductor device 100 which can be driven with high output and stably driven can be obtained.
  • the N-type impurity concentration of the well layer 103A may be undoped or substantially free of N-type impurities.
  • the nitride semiconductor device 100 As a laser device, if the well layer 103A has an N-type impurity, the spectral width of the peak wavelength of the laser light may be broadened, or the crystallinity in the well layer 103A may be lowered. The component life of the laser component. Therefore, the above impurity method can make the N-type impurity concentration of the well layer 103A 1 ⁇ 10 17 atoms/cm 3 to improve the reliability or the life time of the nitride semiconductor device 100.
  • the barrier layer 103B may have a lower indium mixed crystal indium-containing nitride semiconductor than the indium mixed crystal ratio of the well layer 103A, but the present invention is not limited thereto.
  • the barrier layer 103B may also be a semiconductor containing a nitride of gallium nitride, aluminum, or the like.
  • the material of the barrier layer 103B may be In ⁇ Al ⁇ Ga 1- ⁇ N(0 ⁇ 1, 0 ⁇ 1), In ⁇ Ga 1- ⁇ N (0 ⁇ 1, ⁇ > ⁇ ), GaN or Al ⁇ Ga 1- ⁇ N (0 ⁇ 1).
  • a nitride semiconductor containing no aluminum can be generally used.
  • the material of the bottommost barrier layer 103B e.g., the lower barrier layer 103B or the second barrier layer 103B2
  • the well layer 103A formed thereon and containing the In nitride can be prevented from being directly formed on the nitride semiconductor containing aluminum (eg, In ⁇ Al ⁇ Ga 1- ⁇ N or Al ⁇ Ga 1- ⁇ N).
  • the crystallinity of the well layer 103A is lowered.
  • the band gap of the barrier layer 103B may be made larger than the band gap of the well layer 103A, and the composition of the barrier layer 103B and/or the well layer 103A may be appropriately adjusted.
  • the present invention is for the remaining barrier layer 103B (eg, the second barrier layer 103B2 except for the upper barrier layer 103B (ie, the barrier layer 103B closer to the P-type nitride semiconductor 101, such as the first barrier layer 103B1).
  • the doping concentration of the N-type impurity of the third barrier layer 103B3) is not limited.
  • the barrier layer 103B having an N-type impurity may have a doping concentration of the N-type impurity of 5 ⁇ 10 16 atoms / cm 3 to 1 ⁇ 10 20 atoms / cm 3 .
  • the aforementioned N-type impurity may have a doping concentration of 5 ⁇ 10 16 atoms / cm 3 to 2 ⁇ 10 18 atoms / cm 3 .
  • the doping concentration of the aforementioned N-type impurity may be 5 ⁇ 10 17 atoms / cm 3 to 1 ⁇ 10 20 atoms / cm 3 , and may further 1 ⁇ 10 18 atoms / cm 3 to 5 ⁇ 10 19 atoms / cm 3 .
  • the well layer 103A can be made substantially doped without an N-type impurity.
  • the nitride semiconductor device 100 for different light emitting diodes a high output can be obtained in order to increase the driving current, and the N-type impurity is doped.
  • the impurity concentration is increased to further increase the carrier concentration. Therefore, in the nitride semiconductor device 100 used for the foregoing general light emitting diode, the N-type impurity may be doped in a portion of the second barrier layer 103B2 and/or the third barrier layer 103B3, or may be doped without N.
  • the type of impurities is not limited in the present invention.
  • the film thickness of the barrier layer 103B may be less than or equal to 500 angstroms, but the invention is not limited thereto. In some embodiments, the film thickness of the barrier layer 103B may be substantially the same as the film thickness of the well layer 103A, that is, the film thickness of the barrier layer 103B may range from 10 angstroms to 300 angstroms.
  • the barrier layer 103B can also have a P-type doping.
  • the doping concentration of the P-type impurity may be 5 ⁇ 10 16 atoms / cm 3 to 1 ⁇ 10 20 atoms / cm 3 .
  • the aforementioned P-type impurity may have a doping concentration of 5 ⁇ 10 16 atoms/cm 3 to 1 ⁇ 10 18 atoms/cm 3 .
  • the doping concentration of the P-type impurity exceeds 1 ⁇ 10 20 atoms/cm 3 , even if the doping concentration of the p-type impurity is increased, the carrier concentration hardly changes, but crystals due to excessive impurities are caused. The deterioration of the property causes an increase in the scattering effect of light, and further reduces the luminous efficiency of the nitride semiconductor quantum well light-emitting structure 103.
  • the doping concentration of the P-type impurity is less than 1 ⁇ 10 18 atoms/cm 3 , the above-described factor of deterioration in luminous efficiency due to an increase in impurities can be suppressed, and the nitride semiconductor quantum well light-emitting structure 103 can be made.
  • the concentration of the carrier inside is stable. Further, in terms of the doping amount of the P-type impurity, generally, there is at least a slight amount of P-type impurity doping.
  • the barrier layer 103B at the position of the P-type nitride semiconductor 101 may be undoped with N-type impurities and substantially undoped (ie, the impurity concentration is less than 5 ⁇ 10 16 atoms). /cm 3 ) N-type impurity or doped P-type impurity, and the thickness of the first barrier layer 103B1 is less than 100 angstroms.
  • the P-type nitride semiconductor 101 may include a P-side stress releasing layer 101A, a high-concentration hole layer 101B, an electron blocking layer 101C, and a P-type ohmic contact layer 101D, and is away from the first barrier layer 103B1.
  • the direction of the first barrier layer 103B1 is, in order, the P-side stress releasing layer 101A, the high-concentration hole layer 101B, the electron blocking layer 101C, and the P-type ohmic contact layer 101D.
  • the P-side stress relief layer 101A may be a super lattice structure.
  • the superlattice structure material may include a superlattice structure composed of aluminum gallium nitride (AlGaN) and gallium nitride (GaN), or aluminum gallium nitride (Al x GaN) and aluminum gallium nitride (Al y)
  • AlGaN aluminum gallium nitride
  • Al x GaN aluminum gallium nitride
  • Al y aluminum gallium nitride
  • the superlattice structure composed of GaN) or a superlattice structure composed of aluminum gallium nitride (AlGaN) and aluminum indium gallium nitride (InAlGaN) is not limited in the present invention.
  • the logarithm of the aforementioned superlattice structure may be less than 20 pairs, but the invention is not limited thereto. In some embodiments, the aforementioned superlattice structure may also have a logarithm of less than 10 pairs.
  • the high concentration hole layer 101B may be composed of gallium nitride (GaN) or aluminum gallium nitride (AlGaN), and the magnesium concentration of the high concentration hole layer 101B is higher than that of the P side stress release layer 101A.
  • the high concentration hole layer 101B may have a magnesium (Mg) doping concentration higher than 1 ⁇ 10 19 (Atoms/cm 3 ).
  • the electron blocking layer 101C may be composed of aluminum gallium nitride (AlGaN), and the percentage of the aluminum component of the electron blocking layer 101C is higher than the percentage of the aluminum component of the P-side stress releasing layer 101A and the percentage of the aluminum component higher than the high-concentration hole layer 101B. In some embodiments, the aluminum component percentage of the high concentration hole layer 101B is lower than the aluminum component percentage of the electron blocking layer 101C, but the invention is not limited thereto.
  • AlGaN aluminum gallium nitride
  • the P-type ohmic contact layer 101D may be composed of gallium nitride (GaN), and the magnesium doping concentration of the P-type ohmic contact layer 101D is higher than the magnesium doping concentration of the electron blocking layer 101C.
  • the N-type nitride semiconductor 102 may include an N-side first stress relief layer 102A, an N-side second stress relief layer 102B, a low concentration electron layer 102C, and an N-type ohmic contact layer 102D. And from the second barrier layer 103B2 in a direction away from the second barrier layer 103B2, the N-side first stress relief layer 102A, the N-side second stress release layer 102B, the low-concentration electron layer 102C, and the N-type ohmic contact layer. 102D.
  • the N-side first stress relief layer 102A and/or the N-side second stress relief layer 102B may be a superlattice structure which may be a super lattice structure.
  • the superlattice structure material may include a superlattice structure composed of aluminum gallium nitride (AlGaN) and gallium nitride (GaN), or aluminum gallium nitride (Al x GaN) and aluminum gallium nitride (Al y)
  • AlGaN aluminum gallium nitride
  • Al y aluminum gallium nitride
  • the superlattice structure composed of GaN) or a superlattice structure composed of aluminum gallium nitride (AlGaN) and aluminum indium gallium nitride (InAlGaN) is not limited in the present invention.
  • the logarithm of the aforementioned superlattice structure may be less than 20 pairs, but the invention is not limited thereto. In some embodiments, the aforementioned superlattice structure may also have a logarithm of less than 10 pairs.
  • the percentage of the indium component of the N-side first stress-relieving layer 102A is higher than the percentage of the indium component of the N-side second stress-relieving layer 102B.
  • the low concentration electron layer 102C may be composed of gallium nitride (GaN), indium gallium nitride (InGaN), or aluminum gallium nitride (AlGaN).
  • the silicon doping concentration of the low concentration electron layer 102C is lower than the silicon doping concentration of the N type ohmic contact layer 102D, but the invention is not limited thereto.
  • the low concentration electron layer 102C may have a silicon (Si) doping concentration of less than 1 x 10 18 (Atoms/cm 3 ).
  • the N-type ohmic contact layer 102D may be composed of gallium nitride (GaN), indium gallium nitride (InGaN), or aluminum gallium nitride (AlGaN).
  • the silicon doping concentration of the N-type ohmic contact layer 102D is higher than the N-side first stress-relieving layer 102A, the N-side second stress-relieving layer 102B, and the low-concentration electron layer 102C, but the invention is not limited thereto.
  • the material of the substrate 104 may include a group III-V (for example, GaN), a group IV (for example, Si), and II-VI.
  • Elements and alloys of the family eg CdS, CdTe, ZnS), zinc oxide (ZnO), spinel, gallium nitride (GaN), sapphire or silicon (Si).
  • the first side 104A of the substrate 104 includes a growth surface 104A1 and a plurality of microstructures 104A2 located on the growth surface 104A1.
  • the microstructures 104A2 have non-smooth etched sides.
  • the surface roughness of the growth surface 104A1 can be less than 10 angstroms.
  • the surface roughness of the microstructure 104A2 is less than 10 angstroms .
  • the roughness of the second face 104B of the substrate 104 is greater than the roughness of the growth surface 104A1 and the surface roughness of the microstructure 104A2.
  • the microstructures 104A2 can be periodic protruding structures, and the pre-periodic protruding structures can have corresponding heights 104D, widths 104E, and bottom surface spacings 104F.
  • Height 104D can be between 1 micron and 3 microns.
  • the width 104E is between 1 micron and 3 microns.
  • the bottom surface spacing 104F is between 0.1 microns and 3 microns.
  • the microstructure of the microstructure 104A2 may be a hemisphere, a cone, a truncated-cone, a pyramid, a truncated-pyramid, a square pillar. (square pillar), cylinder or other suitable periodic protruding structure 104C, which is not limited in the present invention.
  • the buffer layer 105 can include a first buffer layer 105A and a second buffer layer 105B.
  • the first buffer layer 105A can be conformally formed with the microstructures 104A2.
  • the second buffer layer 105B is located on the first buffer layer 105A, and the second buffer layer 105B may be a flat surface with respect to one surface of the first buffer layer 105A, so as to form a subsequently formed film layer (eg, an N-type ohmic contact layer 102D). ) may be located on a flat surface of the second buffer layer 105B.
  • the nitride semiconductor device 100 may further include a land structure 106, an N-type electrode 107, a current blocking layer 108, a transparent conductive layer 109, a P-type electrode 110, an insulating layer 111, and a highly reflective insulating layer 112.
  • the platform structure 106 exposes a portion of the N-type ohmic contact layer 102D.
  • the N-type electrode 107 is electrically connected to the N-type ohmic contact layer 102D.
  • the current blocking layer 108 is in direct contact with the P-type ohmic contact layer 101D.
  • the transparent conductive layer 109 covers the current blocking layer 108 and is in direct contact with the P-type ohmic contact layer 101D.
  • the P-type electrode 110 is located above the transparent conductive layer 109 and is electrically connected to the P-type ohmic contact layer 101D through the transparent conductive layer 109.
  • the insulating layer 111 covers the N-type electrode 107, the P-type electrode 110, and the sidewall of the land structure 106.
  • the highly reflective insulating layer 112 is located on the second side 104B of the substrate 104.
  • the highly reflective insulating layer 112 can be comprised of a plurality of pairs of dielectric materials.
  • the plurality of dielectric material pairs described above may include a plurality of first dielectric pairs 112A and a plurality of second dielectric pairs 112B.
  • the first dielectric pair 112A and/or the second dielectric pair 112B may include a first material layer 112C and a second material layer 112D, wherein the first material layer 112C has a higher dielectric constant than the second material layer 112D Dielectric coefficient.
  • the first material layer 112C and/or the second material layer 112D have an optical thickness less than a quarter wavelength (wavelength / 4), and the aforementioned wavelength is substantially a nitride semiconductor quantum well light emitting structure 103. The wavelength of the emitted light.
  • the material of the highly reflective insulating layer 112 may include an oxide, a nitride, and/or at least silicon (Si), titanium (Ti), zirconium (Zr), niobium (Nb), tantalum (Ta).
  • An oxide or a nitride composed of an aluminum (Al) element is not limited thereto.
  • the material of the transparent conductive layer 109 may include Indium Tin Oxide (ITO), indium zinc oxide (IZO), zinc oxide (Zinc Oxide; ZnO), or zinc aluminum oxide. (Aluminum Zinc Oxide; AZO), the invention is not limited thereto.
  • the material of the insulating layer 111 may include silicon oxide (SiO X ), silicon nitride (SiN X ), polyimide (Polyimide), or other high molecular materials, and the present invention is not limited thereto.
  • the material of the N-type electrode 107 and/or the P-type electrode 110 may include silver (Ag), aluminum (Al), nickel (Ni), rhenium (Rh), gold (Au), copper (Cu). Titanium (Ti), platinum (Pt), palladium (Pd), molybdenum (Mo), chromium (Cr), tungsten (W), other suitable metals, and/or alloys of the above metals are not limited thereto.
  • FIG. 2 is a schematic cross-sectional view of a nitride semiconductor device 200 in accordance with a second embodiment of the present invention.
  • the nitride semiconductor device 200 of the second embodiment is similar to the nitride semiconductor device 100 of FIG. 1, and the present embodiment is described with respect to the nitride semiconductor device 200 using FIG.
  • FIG. 2 the same or similar reference numerals denote the same or similar components, and thus the components described in FIG. 1 will not be described again.
  • the nitride semiconductor device 200 of the second embodiment is similar to the nitride semiconductor device 100 of FIG. 1, and the difference is that the nitride semiconductor device 200 of the present embodiment further includes a P-type high reflection ohmic electrode 225.
  • the composition of the highly reflective insulating layer 212 may be similar to the highly reflective insulating layer 112 of the foregoing embodiment (e.g., the first embodiment).
  • the P-type high reflection ohmic electrode 225 covers the high reflection insulating layer 212 and the P type nitride semiconductor 101, and is electrically connected to the P type nitride semiconductor 101.
  • the first solder metal layer 221 covers the P-type high reflection ohmic electrode 225 and is electrically connected to the P-type nitride semiconductor 101.
  • the second solder metal layer 222 covers the first solder metal layer 221 and is electrically connected to the P-type nitride semiconductor 101.
  • the bonding substrate 223 covers the second solder metal layer 222 and is electrically connected to the P-type nitride semiconductor 101.
  • the substrate electrode 224 is overlaid on the bonding substrate 223 and electrically connected to the P-type nitride semiconductor 101.
  • the nitride semiconductor device 100 of the present embodiment may have a vertical junction Light-emitting diode elements.
  • the material of the P-type highly reflective ohmic electrode 225 and the substrate electrode 224 may be similar to the material of the N-type electrode 107 and/or the P-type electrode 110 of the foregoing embodiment, and the invention is not limited thereto.
  • the material of the first solder metal layer 221 and/or the second solder metal layer 222 may include silver (Ag), aluminum (Al), nickel (Ni), rhenium (Rh), gold (Au), Copper (Cu), titanium (Ti), platinum (Pt), palladium (Pd), molybdenum (Mo), chromium (Cr), tungsten (W), tin (Sn) other suitable metals and / or alloys of the above metals The invention is not limited thereto.
  • FIG. 3 is a cross-sectional view of a nitride semiconductor device 300 in accordance with a third embodiment of the present invention.
  • the nitride semiconductor device 300 of the third embodiment is similar to the nitride semiconductor device 100 of FIG. 1, and the present embodiment is described with respect to the nitride semiconductor device 300 using FIG. It is to be noted that in FIG. 3, the same or similar reference numerals denote the same or similar components, and thus the components described in FIG. 1 will not be described again.
  • the nitride semiconductor device 300 of the third embodiment is similar to the nitride semiconductor device 100 of FIG. 1.
  • the nitride semiconductor device 100 of the present embodiment further includes a first pad layer 321, The second pad layer 322, the first connection electrode 323, and the second connection electrode 324.
  • the composition of the highly reflective insulating layer 312 may be similar to the highly reflective insulating layer 112 of the foregoing embodiment (e.g., the first embodiment).
  • the first pad layer 321 is electrically connected to the N-type electrode 107.
  • the second pad layer 322 is electrically connected to the P-type electrode 110.
  • the first connection electrode 323 is electrically connected to the first pad layer 321 .
  • the second connection electrode 324 is electrically connected to the second pad layer 322 .
  • the nitride semiconductor device 300 of the present embodiment may be a light emitting diode element having a flip chip structure.
  • first connection electrode 323 and the second connection electrode 324 can be electrically connected to different end points on the circuit board 319, respectively.
  • FIG. 4 is a cross-sectional view showing a nitride semiconductor device 400 in accordance with a fourth embodiment of the present invention.
  • the nitride semiconductor device 400 of the fourth embodiment is similar to the nitride semiconductor device 100 of FIG. 1, and the present embodiment is described with respect to the nitride semiconductor device 400 using FIG. It is noted that in FIG. 4, the same or similar reference numerals denote the same or similar components, and thus the components described in FIG. 1 will not be described again.
  • the nitride semiconductor device 400 of the fourth embodiment is similar to the nitride semiconductor device 100 of FIG. 1, and the difference is that the nitride semiconductor device 400 of the present embodiment further includes a tunnel junction (Tunnel Junction). And a second N-type nitride semiconductor 452.
  • Tunneling junction 470 includes heavily doped P-type (P+) nitride semiconductor 401D and heavily doped N-type (N+) nitride semiconductor
  • the body 451 is either a junction formed by heavily doped P-type (P+) nitride semiconductor 401D and heavily doped N-type (N+) nitride semiconductor 451.
  • the heavily doped P-type nitride semiconductor 401D is disposed on the nitride semiconductor quantum well light-emitting structure 103.
  • the heavily doped N-type nitride semiconductor 451 is disposed on the heavily doped P-type nitride semiconductor 401D.
  • the second N-type nitride semiconductor 452 is disposed on the heavily doped N-type nitride semiconductor 451 of the tunnel junction 470.
  • the energy bandgap of the heavily doped N-type nitride semiconductor 451 is greater than the energy gap of the nitride semiconductor quantum well emitting structure 103.
  • the heavily doped N-type nitride semiconductor 451 may substantially not absorb the light emitted by the nitride semiconductor quantum well light-emitting structure 103.
  • the composition or formation of the heavily doped P-type nitride semiconductor layer 401D may be similar to the P-type ohmic contact layer 101D. That is, the heavily doped P-type nitride semiconductor layer 401D may constitute the P-type nitride semiconductor 101 with the P-side stress releasing layer 101A, the high-concentration hole layer 101B, and the electron blocking layer 101C.
  • the energy bandgap of the heavily doped P-type nitride semiconductor layer 401D may be higher toward the P-type nitride semiconductor 101, and the thickness of the heavily doped P-type nitride semiconductor layer 401D may be It is between 1 nm (nm) and 100 nm, but the invention is not limited thereto.
  • the energy gap of the heavily doped N-type nitride semiconductor 451 may be higher toward the N-type nitride semiconductor 102, and the thickness of the heavily doped N-type nitride semiconductor 451 may be between 1 nm nm and Between 100 nm, but the invention is not limited thereto.
  • the first N-type nitride semiconductor 102 and/or the second N-type nitride semiconductor 452 may have a rough surface to enhance the light-emitting effect of the nitride semiconductor device 400.
  • the tunnel junction 470 can further include an intermediate semiconductor (not shown) disposed between the heavily doped P-type nitride semiconductor 401D and the heavily doped N-type nitride semiconductor 451.
  • the intermediate semiconductor may have an internal band gap barrier, and the heavily doped P-type nitride semiconductor 401D may have a P-depletion barrier, and the heavily doped N-type nitride semiconductor 451 may It has an N-depletion barrier.
  • the intermediate semiconductor forms a heterojunction with respect to the heavily doped P-type nitride semiconductor 401D and the heavily doped N-type nitride semiconductor 451, so as to heavily dope the P-type nitride semiconductor 401D and heavily doped.
  • a polarization field is formed between the hetero-N-type nitride semiconductors 451, and the valence band of the heavily doped P-type nitride semiconductor 401D and the conduction band of the heavily doped N-type nitride semiconductor 451 can correspond to each other .
  • the material of the intermediate semiconductor may comprise aluminum gallium nitride (AlGaN), gallium nitride (GaN), indium gallium nitride (InGaN) or indium aluminum gallium nitride (InAlGaN).
  • AlGaN aluminum gallium nitride
  • GaN gallium nitride
  • InGaN indium gallium nitride
  • InAlGaN indium aluminum gallium nitride
  • the thickness of the intermediate semiconductor is about 0.5 nm to 10 nm, but the invention is not limited thereto.
  • the intermediate semiconductor has a lateral material energy bandgap, which includes a plurality of low bandgap and high band gap regions.
  • the nitride semiconductor device 400 has a tunneling junction 470 structure
  • the structure and process of the Current Blocking Layer (CBL) and the Transparent Conductive Layer (TCL) may be omitted. In the same way, the uniform distribution of current and the improvement of luminous efficiency can be achieved.
  • Figure 5 is a cross-sectional view showing a nitride semiconductor device 500 in accordance with a fifth embodiment of the present invention.
  • the nitride semiconductor device 500 of the fifth embodiment is similar to the nitride semiconductor device 200 of FIG. 2, and the present embodiment will be described with respect to the nitride semiconductor device 500 using FIG. It is to be noted that in FIG. 5, the same or similar reference numerals denote the same or similar components, and thus the components described in FIG. 2 will not be described again.
  • the nitride semiconductor device 500 of the fifth embodiment is similar to the nitride semiconductor device 200 of FIG. 2, and the difference is that the nitride semiconductor device 500 of the present embodiment further includes a tunnel junction surface 470 and Two N-type nitride semiconductors 452.
  • the tunnel junction 470 and the second N-type nitride semiconductor 452 can be similar to the tunnel junction 470 of the foregoing embodiment (eg, the fourth embodiment) and the second N-type nitride semiconductor 452. I will not repeat them here.
  • Figure 6 is a cross-sectional view showing a nitride semiconductor device 600 in accordance with a sixth embodiment of the present invention.
  • the nitride semiconductor device 600 of the sixth embodiment is similar to the nitride semiconductor device 300 of FIG. 3, and the present embodiment will be described with respect to the nitride semiconductor device 600 using FIG. It is to be noted that in FIG. 6, the same or similar reference numerals denote the same or similar components, and the components described in FIG. 3 will not be described again.
  • the nitride semiconductor device 600 of the sixth embodiment is similar to the nitride semiconductor device 300 of FIG. 3, and the difference is that the nitride semiconductor device 600 of the present embodiment further includes a tunnel junction 470 and a Two N-type nitride semiconductors 452.
  • the tunnel junction 470 and the second N-type nitride semiconductor 452 can be similar to the tunnel junction 470 of the foregoing embodiment (eg, the fourth embodiment) and the second N-type nitride semiconductor 452. I will not repeat them here.
  • Figure 7 is a cross-sectional view showing a nitride semiconductor high voltage device in accordance with a seventh embodiment of the present invention.
  • the nitride semiconductor high voltage device 700 of the seventh embodiment is similar to the nitride semiconductor device 400 of FIG. 4, and the difference is that the nitride semiconductor high voltage device of the embodiment may be a plurality of nitride semiconductor devices as shown in FIG.
  • the nitride semiconductor high voltage element 700 is formed by connecting the nitride semiconductor elements 400 in series.
  • the first nitride semiconductor device 700a and/or the second nitride semiconductor device 700b may be similar to the nitride semiconductor device 400 of FIG. 4, and the N-type of the first nitride semiconductor device 700a
  • the nitride semiconductor 102 can be electrically connected to the P-type nitride semiconductor 101 of the second nitride semiconductor device 700b through the N-type electrode 107, the metal connection 760, and the P-type electrode 110.
  • the substrate 104 of the first nitride semiconductor element 700a and the substrate 104 of the second nitride semiconductor element 700b are connected to each other. That is, the first nitride semiconductor element 700a and the second nitride semiconductor element 700b may have a common substrate 104, but the invention is not limited thereto.
  • Figure 8 is a cross-sectional view showing a nitride semiconductor high voltage device in accordance with an eighth embodiment of the present invention.
  • the nitride semiconductor high voltage element 800 of the eighth embodiment is similar to the nitride semiconductor element 700 of FIG. 7, and the present embodiment is described with respect to the nitride semiconductor high voltage element 800 using FIG. It is noted that in FIG. 8, the same or similar reference numerals denote the same or similar components, and thus the components described in FIG. 7 will not be described again.
  • the nitride semiconductor high voltage device 800 of the eighth embodiment is similar to the nitride semiconductor device 700 of FIG. 7, and the difference is that the nitride semiconductor high voltage device of the present embodiment has the first nitride semiconductor device 800a.
  • the substrate 804a and the substrate 804b of the second nitride semiconductor element 800b are separated from each other.
  • Figure 9 is a cross-sectional view showing a nitride semiconductor high voltage device in accordance with a ninth embodiment of the present invention.
  • the nitride semiconductor high voltage element 900 of the ninth embodiment is similar to the nitride semiconductor element 500 of FIG. 5, and the present embodiment will be described with reference to FIG. 9 for the nitride semiconductor high voltage element 900. It is to be noted that, in FIG. 9, the same or similar reference numerals denote the same or similar components, and the components described in FIG. 5 will not be described again.
  • the nitride semiconductor high voltage device 900 of the ninth embodiment is similar to the nitride semiconductor device 500 of FIG. 5, and the difference is that the nitride semiconductor high voltage device of the embodiment may be a plurality of nitride semiconductor devices as shown in FIG.
  • the nitride semiconductor device 500 is connected in series to each other to form a high nitride semiconductor Pressing element 900.
  • the first nitride semiconductor device 900a and/or the second nitride semiconductor device 900b may be similar to the nitride semiconductor device 500 of FIG. 5, and the N-type of the first nitride semiconductor device 900a
  • the nitride semiconductor 102 can be electrically connected to the P-type nitride semiconductor 101 of the second nitride semiconductor device 900a through the N-type electrode 107, the metal connection 706, and the substrate electrode 224.
  • Figure 10 is a cross-sectional view showing a nitride semiconductor high voltage device in accordance with a tenth embodiment of the present invention.
  • the nitride semiconductor high voltage element 1000 of the tenth embodiment is similar to the nitride semiconductor element 600 of FIG. 6, and the present embodiment will be described with reference to FIG. 10 for the nitride semiconductor high voltage element 1000.
  • the same or similar reference numerals denote the same or similar members, and thus the components explained in FIG. 6 will not be described again.
  • the nitride semiconductor high voltage device 1000 of the tenth embodiment is similar to the nitride semiconductor device 600 of FIG. 6. The difference between the two is that the nitride semiconductor high voltage device of the present embodiment may be a plurality of nitride semiconductor devices as shown in FIG.
  • the nitride semiconductor high voltage element 1000 is formed by connecting the nitride semiconductor elements 600 in series.
  • the first nitride semiconductor device 1000a and/or the second nitride semiconductor device 1000b may be similar to the nitride semiconductor device 600 of FIG. 6, and the N-type of the first nitride semiconductor device 1000a
  • the nitride semiconductor 102 can be electrically connected to the P-type nitride semiconductor 101 of the second nitride semiconductor device 1000b through the N-type electrode 107, a metal connection (not shown) on the circuit board 319, and the second connection electrode 324.
  • Figure 11 is a cross-sectional view showing a package structure of a nitride semiconductor device in accordance with an eleventh embodiment of the present invention.
  • the nitride semiconductor device 1100a may be a horizontally structured light emitting diode element.
  • the nitride semiconductor device 1100a may be a nitride semiconductor device 100 similar to the first embodiment or a nitride semiconductor device 400 similar to the fourth embodiment, but the invention is not limited thereto.
  • the package structure 1100 includes a package carrier, a package substrate, and a nitride semiconductor device 1100a.
  • the nitride semiconductor device 1100a is disposed on the package carrier and the package substrate.
  • the package substrate includes a circuit board 1119 and two pads 1120A and 1120B.
  • the two pads 1120A, 1120B are respectively disposed on the circuit board 1119 and separated from each other.
  • the package carrier includes a bracket 1113, two conductive pins 1114A, 1114B, a resin 1115, a transparent glue 1117, and a phosphor powder 1118.
  • Two conductive pins 1114A and 1114B are respectively disposed on the bracket 1113 for electrically connecting the two pads 1120A and 1120B, respectively.
  • the nitride semiconductor device 1100a is disposed on the two conductive pins 1114A and 1114B and electrically connected to the two conductive pins 1114A and 1114B.
  • the resin 1115 is disposed on the bracket 1113 and is configured to receive The nitride semiconductor device 1100a and the two conductive pins 1114A and 1114B.
  • the transparent adhesive 1117 is used to coat the nitride semiconductor device 1100a and the two conductive pins 1114A and 1114B. Fluorescent powder 1118 is used to fill the transparent adhesive 1117.
  • the package carrier further includes two conductive materials 1116.
  • Two conductive materials 1116 are used to electrically connect the nitride semiconductor device 1100a and the two conductive pins 1114A, 1114B.
  • the phosphor powder 1118 is made of a material having highly stable luminescent properties, and the material thereof may include, for example, Garnet, Sulfate, Nitrate, silicate. (Silicate), aluminate (Aluminate) or any combination thereof, but the invention is not limited thereto.
  • the phosphor powder 1118 has an emission wavelength of about 300 nm to 700 nm.
  • the phosphor powder 1118 has a particle diameter of 1 to 25 ⁇ m.
  • the conductive material 1116 can be a wire bond, gold, silver, copper, aluminum, solder, or a hybrid material.
  • the conductive material 1116 is exemplified by a bonding wire, but the invention is not limited thereto.
  • the material of the transparent adhesive 1117 may include an epoxy resin, but the invention is not limited thereto.
  • the material of the conductive pins 1114A, 1114B may be a pure metal material, gold, silver, copper, aluminum, a low melting point metal alloy, a gold tin alloy, a tin, a tantalum or a tin tantalum alloy, but the present invention does not Limited to this.
  • Figure 12 is a cross-sectional view showing a package structure of a nitride semiconductor device in accordance with a twelfth embodiment of the present invention.
  • the package structure 1200 of the twelfth embodiment is similar to the package structure 1100 of FIG. 11, and the present embodiment is described with reference to FIG. 12 for the package structure 1200. It is to be noted that in FIG. 12, the same or similar reference numerals denote the same or similar components, and the components described in FIG. 11 will not be described again.
  • the package structure 1200 of the twelfth embodiment is similar to the package structure 1100 of FIG. 11, and the difference is that in the embodiment, the nitride semiconductor device 1200a may be a vertical structure light-emitting diode element.
  • the nitride semiconductor element 1200a may be a nitride semiconductor element 200 similar to the second embodiment or a nitride semiconductor element 500 similar to the fifth embodiment, but the invention is not limited thereto.
  • the package carrier includes a first conductive material 1116 and a second conductive material 1116.
  • the first conductive material 1116 and the second conductive material 1116 can be similar to the conductive material 1116 of the previous embodiment.
  • the first conductive material 1116 may be a bonding wire, and the second conductive material 1116 may be a solder ball, a bump, or the like, but the invention is not limited thereto.
  • Figure 13 is a diagram of a package of a nitride semiconductor device 100 in accordance with a thirteenth embodiment of the present invention. Schematic diagram of the structure.
  • the package structure 1300 of the thirteenth embodiment is similar to the package structure 1100 of FIG. 11, and the present embodiment is described with reference to FIG. 13 for the package structure 1300. It is to be noted that in FIG. 13, the same or similar reference numerals denote the same or similar components, and the components described in FIG. 11 will not be described again.
  • the package structure 1300 of the thirteenth embodiment is similar to the package structure 1100 of FIG. 11, and the difference is that in the embodiment, the nitride semiconductor device 1300a may be a flip-chip light-emitting diode element.
  • the nitride semiconductor element 1300a may be a nitride semiconductor element 100300 similar to the third embodiment or a nitride semiconductor element 600 similar to the sixth embodiment, but the invention is not limited thereto.
  • the package carrier further includes two conductive materials 1116.
  • Conductive material 1116 can be similar to conductive material 1116 of the previous embodiments.
  • the conductive material 1116 may be a solder ball, a bump or the like, but the invention is not limited thereto.
  • Figure 14 is a flow chart showing the manufacture of a nitride semiconductor device in accordance with the present invention.
  • step S1 a semiconductor wafer is formed.
  • step S2 the semiconductor wafer is diced in a stealth dicing process to form a nitride semiconductor device.
  • the nitride semiconductor device is, for example, the nitride semiconductor device in any of the above embodiments.
  • the method of fabricating the nitride semiconductor device of the present embodiment may be a method of fabricating the nitride semiconductor device 100, 200, 300, 400, 500, 600, or a nitride semiconductor high voltage device 700, 800, 900, 1000. Manufacturing method, but the invention is not limited thereto.
  • the nitride semiconductor component can emit UV light, blue light, or green light.
  • the nitride semiconductor component can be applied to a filament product, a COB (Chip on Board) product, a laser diode (Laser Diode) product, or a light emitting diode (Light Emitting Diode) product.
  • the nitride semiconductor device of the present invention can improve luminous efficiency and improve process yield.
  • the method for producing a nitride semiconductor device of the present invention can be used to fabricate the above-described nitride semiconductor device.
  • the package structure of the present invention can be applied to the above-described nitride semiconductor device.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)

Abstract

一种氮化物半导体元件（100），其包括P型氮化物半导体（101）、N型氮化物半导体（102）、氮化物半导体量子井发光结构（103）、基板（104）以及缓冲层（105）。氮化物半导体量子井发光结构（103）位于P型氮化物半导体（101）以及N型氮化物半导体（102）之间，且包括多个井层（103A）以及多个阻挡层（103B）。各个井层（103A）以及各个阻挡层（103B）彼此交错配置。多个阻挡层（103B）包括配置于最接近P型氮化物半导体位置（101）的第一阻挡层（103B1）、配置于最接近N型氮化物半导体（102）位置的第二阻挡层（103B2）以及多个第三阻挡层（103B3）。第一阻挡层（103B1）的厚度小于100埃。各个第三阻挡层（103B1）位于相邻的两个井层（103A）之间。缓冲层（105）位于N型氮化物半导体（102）以及基板（104）之间。

Description

氮化物半导体元件及其制造方法与所应用的封装结构 技术领域
本发明涉及一种半导体元件及其制造方法，且特别涉及一种可以提升发光效率及改善制程良率的氮化物半导体元件及其制造方法。
背景技术
发光二极管(light emitting diode；LED)具有诸如寿命长、体积小、高抗震性、低热产生及低功率消耗等优点，因此已被广泛应用于家用及各种设备中的指示器或光源。近年来，发光二极管已朝多色彩及高亮度发展，因此其应用领域已扩展至大型户外看板、交通号志灯及相关领域。在目前，发光二极管已经成为兼具省电及环保功能的主要照明光源。
因此，如何进一步提升发光二极管的发光效率，实已成目前亟欲解决的课题。
发明内容
本发明提供多种氮化物半导体元件，其可以提升发光效率及改善制程良率。
本发明还提供多种氮化物半导体元件的制造方法，其用以制作上述的氮化物半导体元件。
本发明还提供多种封装结构，其应用于上述的氮化物半导体元件。
本发明提供一种氮化物半导体元件，其包括P型氮化物半导体、N型氮化物半导体、氮化物半导体量子井发光结构、基板以及缓冲层。氮化物半导体量子井发光结构位于P型氮化物半导体以及N型氮化物半导体之间。基板包含相对的第一面以及第二面。缓冲层位于N型氮化物半导体以及基板的第一面之间。氮化物半导体量子井发光结构具有多个井层以及多个阻挡层。多个阻挡层包含配置于最接近P型氮化物半导体的第一阻挡层、配置于最接近N型氮化物半导体位置的第二阻挡层以及多个第三阻挡层。多个第三阻挡层被多个井层夹住。第一阻挡层的厚度小于100埃(angstrom；
Figure PCTCN2017098626-appb-000001
)。
在本发明的一实施例中，上述的第二阻挡层的厚度大于上述的第一阻挡层的厚度。
在本发明的一实施例中，上述的第三阻挡层的厚度大于上述的第一阻挡层的厚度。
在本发明的一实施例中，上述的第二阻挡层的厚度大于或是等于上述的 第三阻挡层的厚度。
在本发明的一实施例中，上述的第二阻挡层的厚度小于或是等于上述的第三阻挡层的厚度。
在本发明的一实施例中，上述的第一阻挡层的厚度小于50埃
Figure PCTCN2017098626-appb-000002
。
在本发明的一实施例中，上述的P型氮化物半导体包括P侧应力释放层、高浓度空穴层、电子阻挡层以及P型欧姆接触层。其中配置于最接近上述的第一阻挡层为上述的P侧应力释放层，配置于最远离上述的第一阻挡层的为上述的P型欧姆接触层，上述的高浓度空穴层以及上述的电子阻挡层依序堆迭于上述的P侧应力释放层上方，上述的电子阻挡层被上述的高浓度空穴层以及上述的P型欧姆接触层所夹住。
在本发明的一实施例中，上述的P侧应力释放层可为超晶格(superlattice)结构，其材料包含氮化铝镓(AlGaN)以及氮化镓(GaN)所构成的超晶格结构，或是由氮化铝镓(AlxGaN)以及氮化铝镓(AlyGaN)所构成的超晶格结构，或是由氮化铝镓(AlGaN)以及氮化铝铟镓(InAlGaN)所构成的超晶格结构，上述的超晶格结构小于20对。
在本发明的一实施例中，上述的高浓度空穴层可由氮化镓(GaN)或是氮化铝镓(AlGaN)所构成，上述的高浓度空穴层的镁掺杂浓度(concentration)高于上述的P侧应力释放层的镁掺杂浓度以及上述的电子阻挡层的镁掺杂浓度。
在本发明的一实施例中，上述的高浓度空穴层的镁(Mg)掺杂浓度高于1x1019原子数/立方公分(Atoms/cm3)。
在本发明的一实施例中，上述的电子阻挡层可由氮化铝镓(AlGaN)所构成，上述的电子阻挡层的铝成份百分比高于上述的P侧应力释放层的铝成份百分比以及高于上述的高浓度空穴层的铝成份百分比。
在本发明的一实施例中，上述的P型欧姆接触层可由氮化镓(GaN)所构成，上述的P型欧姆接触层的镁掺杂浓度高于上述的电子阻挡层的镁掺杂浓度。
在本发明的一实施例中，上述的高浓度空穴层的镁(Mg)掺杂浓度高于1x1019(Atoms/cm3)，且上述的高浓度空穴层的铝成份百分比低于上述的电子阻挡层的铝成份百分比。
在本发明的一实施例中，上述的N型氮化物半导体包括N侧第一应力释放层、N侧第二应力释放层、低浓度电子层以及N型欧姆接触层，其中配置于最接近上述的第二阻挡层为上述的N侧第一应力释放层，配置于最远离上述的第二阻挡层为上述的N型欧姆接触层，上述的低浓度电子层以及上述的第二应力释放层依序堆迭于上述的N型欧姆接触层上方，上述的低浓度电子层 被上述的N型欧姆接触层及上述的第二应力释放层所夹住。
在本发明的一实施例中，上述的N侧第一应力释放层可为超晶格结构，其材料包含氮化铟镓(InGaN)以及氮化镓(GaN)所构成的超晶格结构，或是由氮化铟镓(InxGaN))以及氮化铟镓(InyGaN)所构成的超晶格结构，上述的超晶格结构小于20对。
在本发明的一实施例中，上述的N侧第二应力释放层可为超晶格结构，其材料包含氮化铟镓(InGaN)以及氮化镓(GaN)所构成的超晶格结构，或是由氮化铟镓(InxGaN))以及氮化铟镓(InyGaN)所构成的超晶格结构，上述的超晶格结构小于20对。
在本发明的一实施例中，上述的N侧第一应力释放层的铟(Indium)成份百分比高于上述的N侧第二应力释放层的铟成份百分比。
在本发明的一实施例中，上述的低浓度电子层可由氮化镓(GaN)、氮化铟镓(InGaN)或是氮化铝镓(AlGaN)所构成，上述的低浓度电子层的硅掺杂浓度低于上述的N型欧姆接触层的硅掺杂浓度。
在本发明的一实施例中，上述的低浓度电子层的硅掺杂浓度低于1x1018(Atoms/cm3)。
在本发明的一实施例中，上述的N型欧姆接触层可由氮化镓(GaN)、氮化铟镓(InGaN)或是氮化铝镓(AlGaN)所构成，上述的N型欧姆接触层的硅掺杂浓度高于上述的N侧第一应力释放层、上述的N侧第二应力释放层以及上述的低浓度电子层的硅掺杂浓度。
在本发明的一实施例中，上述的P侧应力释放层的上述的超晶格结构小于10对。
在本发明的一实施例中，上述的N侧第一应力释放层的上述的超晶格结构小于10对。
在本发明的一实施例中，上述的N侧第二应力释放层的上述的超晶格结构小于10对。
在本发明的一实施例中，上述的基板是选自包含III-V族，IV族，II-VI族的元素与合金、氧化锌(ZnO)、尖晶石(spinel)、氮化镓(GaN)、蓝宝石(sapphire)或硅(Si)。
在本发明的一实施例中，上述的缓冲层包括第一缓冲层以及第二缓冲层。其中上述的第一缓冲层被上述的基板的上述的第一面以及上述的第二缓冲层所夹住，上述的第一缓冲层缺陷密度高于上述的第二缓冲层，上述的第二缓冲层上部为一平坦且缺陷密度低于上述的第一缓冲层。
在本发明的一实施例中，上述的第一缓冲层的材料可为单晶氮化镓(GaN)、单晶氮化铝(AlN)或是单晶氮化铝镓(AlGaN)。
在本发明的一实施例中，上述的第一缓冲层的材料可为非单晶氮化镓(GaN)、非单晶氮化铝(AlN)或是非单晶氮化铝镓(AlGaN)。
在本发明的一实施例中，上述的缓冲层的材料包含氮化镓(GaN)，氮化铝(AlN)或氮化铝镓(AlGaN)所构成。
在本发明的一实施例中，上述的基板的上述的第一面包括成长表面以及多个位于上述的成长表面上的微结构，上述的多个微结构具有非圆滑的蚀刻侧面。
在本发明的一实施例中，上述的成长表面的表面粗糙度低于10埃
Figure PCTCN2017098626-appb-000003
。
在本发明的一实施例中，上述的微结构的表面粗糙度低于10埃
Figure PCTCN2017098626-appb-000004
。
在本发明的一实施例中，上述的微结构为周期性突出结构，上述的周期性突出结构包括高度、宽度以及底面间距。
在本发明的一实施例中，上述的高度介于1微米(micrometer；μm)至3微米之间。
在本发明的一实施例中，上述的宽度介于1微米至3微米之间。
在本发明的一实施例中，上述的底面间距介于0.1微米至3微米之间。
在本发明的一实施例中，上述的基板的第二面粗糙度大于上述的成长表面以及上述的多个微结构的表面。
在本发明的一实施例中，上述的微结构的外型为半球体(hemisphere)。
在本发明的一实施例中，上述的微结构的外型为锥体(cone)。
在本发明的一实施例中，上述的微结构的外型为截头锥体(truncated-cone)。
在本发明的一实施例中，上述的微结构的外型为金字塔(pyramid)。
在本发明的一实施例中，上述的微结构的外型为截头金字塔(truncated-pyramid)。
在本发明的一实施例中，上述的微结构的外型为方柱(square pillar)。
在本发明的一实施例中，上述的微结构的外型为圆桶(cylinder)。
在本发明的一实施例中，上述的氮化物半导体元件还包括平台结构、N型电极、电流阻挡层、透明导电层、P型电极、绝缘层以及高反射绝缘层。平台结构露出部分上述的N型欧姆接触层。N型电极与上述的N型欧姆接触层电性连接。电流阻挡层与上述的P型欧姆接触层直接接触。透明导电层覆盖上述的电流阻挡层以及与上述的P型欧姆接触层直接接触。P型电极位于上述的透 明导电层的上方，且通过透明导电层与上述的P型欧姆接触层电性连接。绝缘层覆盖上述的N型电极以及上述的P型电极及上述的平台结构的侧壁。高反射绝缘层，位于上述的基板的第二面。
在本发明的一实施例中，上述的高反射绝缘层由多个介电材料对(pair)组成。上述的多个介电材料对包括多个第一介电对以及多个第二介电对。
在本发明的一实施例中，上述的第一介电对包括第一材料层以及第二材料层，其中上述的第一材料层折射系数(refractive index)大于第二材料层。
在本发明的一实施例中，上述的第一材料层以及上述的第二材料层的光学厚度小于四分之一的波长(波长/4)，上述的波长为上述的氮化物半导体量子井发光结构所发出的波长。
在本发明的一实施例中，上述的第二介电对包括第一材料层以及第二材料层，其中上述的第一材料层折射系数(refractive index)大于第二材料层。
在本发明的一实施例中，上述的第一材料层的光学厚度小于(波长/4)，上述的第二材料层的光学厚度大于(波长/4)，上述的波长为上述的氮化物半导体量子井发光结构所发出的波长。
在本发明的一实施例中，上述的高反射绝缘层由多个介电材料对(pair)组成。上述的多个介电材料对包括多个第三介电对以及多个第二介电对。
在本发明的一实施例中，上述的第三介电对包括第一材料层以及第二材料层，其中上述的第一材料层折射系数(refractive index)大于第二材料层。
在本发明的一实施例中，上述的第一材料层以及上述的第二材料层的光学厚度大于四分之一的波长(波长/4)，上述的波长为上述的氮化物半导体量子井发光结构所发出的波长。
在本发明的一实施例中，上述的第二介电对包括第一材料层以及第二材料层，其中上述的第一材料层折射系数(refractive index)大于第二材料层。
在本发明的一实施例中，上述的第一材料层的光学厚度小于(波长/4)，上述的第二材料层的光学厚度大于(波长/4)，上述的波长为上述的氮化物半导体量子井发光结构所发出的波长。
在本发明的一实施例中，上述的高反射绝缘层由多个介电材料对(pair)组成。上述的多个介电材料对包括多个第一介电对以及多个第三介电对。
在本发明的一实施例中，上述的第一介电对包括第一材料层以及第二材料层，其中上述的第一材料层折射系数(refractive index)大于第二材料层。
在本发明的一实施例中，上述的第一材料层以及上述的第二材料层的光学厚度小于四分之一的波长(波长/4)，上述的波长为上述的氮化物半导体量 子井发光结构所发出的波长。
在本发明的一实施例中，上述的第三介电对包括第一材料层以及第二材料层，其中上述的第一材料层折射系数(refractive index)大于第二材料层。
在本发明的一实施例中，上述的第一材料层以及上述的第二材料层的光学厚度大于四分之一的波长(波长/4)，上述的波长为上述的氮化物半导体量子井发光结构所发出的波长。
在本发明的一实施例中，上述的高反射绝缘层由多个介电材料对(pair)组成。上述的多个介电材料对包括至少一个第一介电对以及至少一个第二介电对，以及至少一个第三介电对。
在本发明的一实施例中，上述的第一介电对包括第一材料层以及第二材料层，其中上述的第一材料层折射系数(refractive index)大于第二材料层。
在本发明的一实施例中，上述的第一材料层以及上述的第二材料层的光学厚度小于四分之一的波长(波长/4)，上述的波长为可见光中心波长550nm。
在本发明的一实施例中，上述的第二介电对包括第一材料层以及第二材料层，其中上述的第一材料层折射系数(refractive index)大于第二材料层。
在本发明的一实施例中，上述的第一材料层的光学厚度小于(波长/4)，上述的第二材料层的光学厚度大于(波长/4)，上述的波长为可见光中心波长550nm。
在本发明的一实施例中，上述的第三介电对包括第一材料层以及第二材料层，其中上述的第一材料层折射系数(refractive index)大于第二材料层。
在本发明的一实施例中，上述的第一材料层以及上述的第二材料层的光学厚度大于四分之一的波长(波长/4)，上述的波长为可见光中心波长550nm。
在本发明的一实施例中，上述的第一介电对可以靠近或远基板。
在本发明的一实施例中，上述的第二介电对可以靠近或远基板。
在本发明的一实施例中，上述的第三介电对可以靠近或远基板。
在本发明的一实施例中，上述的第二介电对可以位于第一介电对及第三介电对之间。
在本发明的一实施例中，上述的第一介电对可以位于第二介电对及第三介电对之间。
在本发明的一实施例中，上述的第三介电对可以位于第一介电对及第二介电对之间。
在本发明的一实施例中，上述的高反射绝缘层下方可以有一金属反射层，该金属反射层材料可为铝或银或其他高反射率金属组成。
在本发明的一实施例中，上述的高反射绝缘层上方可以有一界面层，该界面层材料可与高反射绝缘层材料相同。
在本发明的一实施例中，上述的透明导电层可以是铟锡氧化物(Indium Tin Oxide；ITO)、铟锌氧化物(indium zinc oxide；IZO)、氧化锌(Zinc Oxide；ZnO)或氧化锌铝(Aluminum Zinc Oxide；AZO)。
在本发明的一实施例中，上述的绝缘层包括氧化硅(SiOX)、氮化硅(SiNX)、聚酰亚胺(Polyimide)或其他高分子材料。
在本发明的一实施例中，上述的高反射绝缘层的材料包括氧化物，氮化物，以及至少包含硅(Si)、钛(Ti)、锆(Zr)、铌(Nb)、钽(Ta)或铝(Al)元素所组成的氧化物或氮化物。
在本发明的一实施例中，上述的N型电极的材料包括银(Ag)、铝(Al)、镍(Ni)、铑(Rh)、金(Au)、铜(Cu)、钛(Ti)、铂(Pt)、钯(Pd)、钼(Mo)、铬(Cr)、钨(W)或上述金属的合金。
在本发明的一实施例中，上述的P型电极的材料包括Ag、Al、Ni、Rh、Au、Cu、Ti、Pt、Pd、Mo、Cr、W或上述金属的合金。
在本发明的一实施例中，上述的氮化物半导体元件设置于封装载体以及封装基板上，其中上述的封装基板包括电路板以及二个焊垫。上述的二个焊垫设置于上述的电路板上。上述的封装载体包括支架、二个导电引脚、树脂、二个导电材料、透明胶以及萤光粉。上述的导电引脚设置于上述的支架上，用以与上述的二个焊垫电性连接，其中上述的氮化物半导体元件设置于上述的二个导电引脚上，并与上述的二个导电引脚电性连接。上述的树脂设置于上述的支架上，并用以容纳上述的氮化物半导体元件及上述的二个导电引脚。上述的二个导电材料用以电性连接上述的上述的氮化物半导体元件及上述的二个导电引脚。上述的透明胶用以包覆上述的氮化物半导体元件及上述的二个导电引脚。上述的萤光粉用以填入于上述的透明胶中。
在本发明的一实施例中，上述的萤光粉其是由具高稳定发光特性的材料所制成，例如石榴石系(Garnet)、硫化物(Sulfate)、氮化物(Nitrate)、硅酸盐(Silicate)、铝酸盐(Aluminate)或上述材料的任意组合，但不以此为限，其发光波长约为300nm至700nm。其中上述的萤光粉的粒径为1～25μm。
在本发明的一实施例中，上述的导电材料包含焊线、金、银、铜、铝或混合材料。
在本发明的一实施例中，上述的透明胶材包括环氧树脂。
在本发明的一实施例中，上述的导电引脚可为纯金属材料、金、银、铜、 铝、低熔点金属合金、金锡合金、锡、铋或锡铋合金。
在本发明的一实施例中，上述的氮化物半导体元件还包括平台结构、N型电极、电流阻挡层、透明导电层、P型电极、绝缘层、高反射绝缘层、第一焊垫层、第二焊垫层、第一连接电极以及第二连接电极。上述的平台结构露出部分上述的N型欧姆接触层。上述的N型电极与上述的N型欧姆接触层电性连接。上述的电流阻挡层与上述的P型欧姆接触层直接接触。上述的透明导电层覆盖上述的电流阻挡层以及与上述的P型欧姆接触层直接接触。上述的P型电极位于上述的透明导电层的上方，通过透明导电层与上述的P型欧姆接触层电性连接。上述的绝缘层覆盖上述的N型电极以及上述的P型电极及上述的平台结构的侧壁。上述的高反射绝缘层位于上述的覆盖部分上述的绝缘层覆。上述的第一焊垫层与上述的N型电极电性连接。上述的第二焊垫层与上述的P型电极电性连接。上述的第一连接电极与上述的第一焊垫层电性连接。上述的第二连接电极与上述的第二焊垫层电性连接。
在本发明的一实施例中，上述的高反射绝缘层由多个介电材料对(pair)组成，上述的多个介电材料对包括多个第一介电对以及多个第二介电对。
在本发明的一实施例中，上述的第一介电对包括第一材料层以及第二材料层，其中上述的第一材料层折射系数(refractive index)大于上述的第二材料层。
在本发明的一实施例中，上述的第一材料层以及上述的第二材料层的光学厚度小于四分之一的波长，上述的波长为上述的氮化物半导体量子井发光结构所发出的波长。
在本发明的一实施例中，上述的第二介电对包括第一材料层以及第二材料层，其中上述的第一材料层折射系数(refractive index)大于上述的第二材料层。
在本发明的一实施例中，上述的第一材料层的光学厚度小于四分之一的波长，上述的第二材料层的光学厚度大于四分之一的波长，上述的波长为上述的氮化物半导体量子井发光结构所发出的波长。
在本发明的一实施例中，上述的透明导电层可以是铟锡氧化物(Indium Tin Oxide；ITO)、铟锌氧化物(indium zinc oxide；IZO)、氧化锌(Zinc Oxide；ZnO)或氧化锌铝(Aluminum Zinc Oxide；AZO)。
在本发明的一实施例中，上述的绝缘层包括氧化硅(SiOX)、氮化硅(SiNX)、聚酰亚胺(Polyimide)或其他高分子材料。
在本发明的一实施例中，上述的高反射绝缘层的材料包括氧化物、氮化 物或至少包含Si、Ti、Zr、Nb、Ta或Al元素所组成的氧化物或氮化物。
在本发明的一实施例中，上述的N型电极的材料包括Ag、Al、Ni、Rh、Au、Cu、Ti、Pt、Pd、Mo、Cr、W或上述金属的合金。
在本发明的一实施例中，上述的P型电极的材料包括Ag、Al、Ni、Rh、Au、Cu、Ti、Pt、Pd、Mo、Cr、W或上述金属的合金。
在本发明的一实施例中，上述的第一导电引脚的材料包括Ag、Al、Ni、Rh、Au、Cu、Ti、Pt、Pd、Mo、Cr、W、锡(Sn)或上述金属的合金。
在本发明的一实施例中，上述的第二导电引脚的材料包括Ag、Al、Ni、Rh、Au、Cu、Ti、Pt、Pd、Mo、Cr、W、Sn或上述金属的合金。
在本发明的一实施例中，上述的氮化物半导体元件设置于封装载体以及封装基板上，其中上述的封装基板包括电路板以及二个焊垫。上述的二个焊垫设置于上述的电路板上。其中上述的封装载体包括支架、二个导电引脚、树脂、二个导电材料、透明胶以及萤光粉。上述的二个导电引脚设置于上述的支架上，用以与上述的二个焊垫电性连接，其中上述的氮化物半导体元件设置于上述的二个导电引脚上，并与上述的二个导电引脚电性连接。上述的树脂设置于上述的支架上，并用以容纳上述的氮化物半导体元件及上述的二个导电引脚。上述的二个导电材料，用以电性连接上述的上述的氮化物半导体元件及上述的二个导电引脚。上述的透明胶用以包覆上述的上述的氮化物半导体元件及上述的二个导电引脚。上述的萤光粉用以填入于上述的透明胶中。
在本发明的一实施例中，上述的萤光粉其是由具高稳定发光特性的材料所制成，例如石榴石系(Garnet)、硫化物(Sulfate)、氮化物(Nitrate)、硅酸盐(Silicate)、铝酸盐(Aluminate)或上述材料的任意组合，但不以此为限，其发光波长约为300nm至700nm。其中上述的萤光粉的粒径为1～25μm。
在本发明的一实施例中，上述的透明胶材包括环氧树脂。
在本发明的一实施例中，上述的导电引脚可为纯金属材料、金、银、铜、铝、或低熔点金属合金、金锡合金、锡、铋或锡铋合金。
在本发明的一实施例中，上述的氮化物半导体元件可应用于车用照明领域。
在本发明的一实施例中，上述的氮化物半导体元件可应用于一般照明领域。
在本发明的一实施例中，上述的氮化物半导体元件可应用于闪光灯领域。
在本发明的一实施例中，上述的氮化物半导体元件可应用于背光领域。
在本发明的一实施例中，上述的氮化物半导体元件可应用于户外看板领域。
在本发明的一实施例中，上述的氮化物半导体元件的发光效率高于220流明每瓦(lm/W)。
在本发明的一实施例中，上述的氮化物半导体元件的显色指数中对红色的显示能力(R9)大于90。
在本发明的一实施例中，上述的氮化物半导体元件的演色性指数(Color Rendering Index；CRI)大于90。
在本发明的一实施例中，上述的氮化物半导体元件的平均演色评价指数(Ra)大于90。
在本发明的一实施例中，上述的氮化物半导体元件可以是水平式发光晶片。
在本发明的一实施例中，上述的氮化物半导体元件可以是垂直式发光晶片。
在本发明的一实施例中，上述的氮化物半导体元件可以是覆晶式发光晶片。
本发明提供一种氮化物半导体元件，其包括P型氮化物半导体、N型氮化物半导体、缓冲层、氮化物半导体量子井发光结构、高反射绝缘层、P型高反射欧姆电极、N型电极、第一焊接金属层、第二焊接金属层、接合基板以及基板电极。上述的氮化物半导体量子井发光结构位于上述的P型氮化物半导体及上述的N型氮化物半导体之间。上述的高反射绝缘层覆盖于上述的P型氮化物半导体。上述的P型高反射欧姆电极覆盖于上述的高反射绝缘层以及上述的P型氮化物半导体，并与上述的P型氮化物半导体电性连接。上述的N型电极覆盖于上述的缓冲层，并与上述的N型氮化物半导体电性连接。上述的第一焊接金属层覆盖于上述的P型高反射欧姆电极，并与上述的P型氮化物半导体电性连接。上述的第二焊接金属层覆盖于上述的第一焊接金属层，并与上述的P型氮化物半导体电性连接。上述的接合基板覆盖于上述的第二焊接金属层，并与上述的P型氮化物半导体电性连接。上述的基板电极覆盖于上述的接合基板，并与上述的P型氮化物半导体电性连接。其中上述的氮化物半导体量子井发光结构具有多个井层和多个阻挡层，上述的多个阻挡层包含一配置于最接近前述P型氮化物半导体位置的第一阻挡层、一配置于最接近前述N型氮化物半导体位置的第二阻挡层以及多个第三阻挡层，其中上述的多个第三阻挡层被上述的多个井层夹住，其中上述的第一阻挡层的厚度 小于100埃。
在本发明的一实施例中，上述的第二阻挡层的厚度大于上述的第一阻挡层的厚度。
在本发明的一实施例中，上述的第三阻挡层的厚度大于上述的第一阻挡层的厚度。
在本发明的一实施例中，上述的第二阻挡层的厚度大于或是等于上述的第三阻挡层的厚度。
在本发明的一实施例中，上述的第二阻挡层的厚度小于或是等于上述的第三阻挡层的厚度。
在本发明的一实施例中，上述的第一阻挡层的厚度小于50埃。
在本发明的一实施例中，上述的P型氮化物半导体包括P侧应力释放层、高浓度空穴层、电子阻挡层以及P型欧姆接触层。其中配置于最接近前述上述的第一阻挡层为上述的P侧应力释放层，配置于最远离前述上述的第一阻挡层为上述的P型欧姆接触层，上述的高浓度空穴层以及电子阻挡层依序堆迭于上述的P侧应力释放层上方，上述的电子阻挡层被上述的高浓度空穴层以及上述的P型欧姆接触层所夹住。
在本发明的一实施例中，上述的P侧应力释放层可为超晶格结构，其材料包含氮化铝镓(AlGaN)以及氮化镓(GaN)所构成的超晶格结构，或是由氮化铝镓(AlxGaN)以及氮化铝镓(AlyGaN)所构成的超晶格结构，或是由氮化铝镓(AlGaN)以及氮化铝铟镓(InAlGaN)所构成的超晶格结构，上述的超晶格结构小于20对。
在本发明的一实施例中，上述的高浓度空穴层可由氮化镓(GaN)或是氮化铝镓(AlGaN)所构成，上述的高浓度空穴层的镁掺杂浓度(concentration)高于上述的P侧应力释放层的镁掺杂浓度以及上述的电子阻挡层的镁掺杂浓度。
在本发明的一实施例中，上述的高浓度空穴层的镁(Mg)掺杂浓度高于1x1019(Atoms/cm3)。
在本发明的一实施例中，上述的电子阻挡层可由氮化铝镓(AlGaN)所构成，上述的电子阻挡层的铝成份百分比高于上述的P侧应力释放层的铝成份百分比以及高于上述的高浓度空穴层的铝成份百分比。
在本发明的一实施例中，上述的P型欧姆接触层可由氮化镓(GaN)所构成，上述的P型欧姆接触层的镁掺杂浓度高于上述的电子阻挡层的镁掺杂浓度。
在本发明的一实施例中，上述的高浓度空穴层的镁(Mg)掺杂浓度高于1x1019(Atoms/cm3)且上述的高浓度空穴层的铝成份百分比低于上述的电子阻 挡层的铝成份百分比。
在本发明的一实施例中，上述的N型氮化物半导体包括N侧第一应力释放层、N侧第二应力释放层、低浓度电子层以及N型欧姆接触层。其中配置于最接近前述上述的第二阻挡层为上述的N侧第一应力释放层，配置于最远离述上述的第二阻挡层为上述的N型欧姆接触层，上述的低浓度电子层以及上述的第二应力释放层依序堆迭于上述的N型欧姆接触层上方，上述的低浓度电子层被N型欧姆接触层及上述的第二应力释放层所夹住。
在本发明的一实施例中，上述的N侧第一应力释放层可为超晶格结构，其材料包含氮化铟镓(InGaN)以及氮化镓(GaN)所构成的超晶格结构，或是由氮化铟镓(InxGaN))以及氮化铟镓(InyGaN)所构成的超晶格结构，或是由，上述的超晶格结构小于20对。
在本发明的一实施例中，上述的N侧第二应力释放层可为超晶格结构，其材料包含氮化铟镓(InGaN)以及氮化镓(GaN)所构成的超晶格结构，或是由氮化铟镓(InxGaN))以及氮化铟镓(InyGaN)所构成的超晶格结构，或是由，上述的超晶格结构小于20对。
在本发明的一实施例中，上述的N侧第一应力释放层的铟成份百分比高于上述的N侧第二应力释放层的铟成份百分比。
在本发明的一实施例中，上述的N型氮化物半导体，上述的低浓度电子层可由氮化镓(GaN)所构成或是氮化铟镓(InGaN)或是氮化铝镓(AlGaN)所构成，上述的低浓度电子层的硅掺杂浓度低于上述的N型欧姆接触层的硅掺杂浓度。
在本发明的一实施例中，上述的低浓度电子层的硅掺杂浓度低于1x1018(Atoms/cm3)。
在本发明的一实施例中，上述的N型欧姆接触层可由氮化镓(GaN)所构成或是氮化铟镓(InGaN)或是氮化铝镓(AlGaN)所构成，上述的N型欧姆接触层的硅掺杂的浓度高于上述的N侧第一应力释放层及上述的N侧第二应力释放层及上述的低浓度电子层。
在本发明的一实施例中，上述的P侧应力释放层的上述的超晶格结构小于10对。
在本发明的一实施例中，上述的N侧第一应力释放层的上述的超晶格结构小于10对。
在本发明的一实施例中，上述的N侧第二应力释放层的上述的超晶格结构小于10对。
在本发明的一实施例中，上述的N型电极的材料包括Ag、Al、Ni、Rh、Au、Cu、Ti、Pt、Pd、Mo、Cr、W或上述金属的合金。
在本发明的一实施例中，上述的P型高反射欧姆电极包括Ag、Al、Ni、Rh、Au、Cu、Ti、Pt、Pd、Mo、Cr、W或上述金属的合金。
在本发明的一实施例中，上述的基板电极包括Ag、Al、Ni、Rh、Au、Cu、Ti、Pt、Pd、Mo、Cr、W或上述金属的合金。
在本发明的一实施例中，上述的第一焊接金属层材料包含Ag、Al、Ni、Rh、Au、Cu、Ti、Pt、Pd、Mo、Cr、W、Sn或上述金属的合金。
在本发明的一实施例中，上述的第二焊接金属层材料包含Ag、Al、Ni、Rh、Au、Cu、Ti、Pt、Pd、Mo、Cr、W、Sn或上述金属的合金。
在本发明的一实施例中，上述的接合基板包含纯金属基板、铜基板、钨基板、铝基板、合金基板、铜钨基板、陶瓷基板、氧化铝基板、硅基板或碳化硅基板。
在本发明的一实施例中，上述的接合基板的热膨胀系数高于或等于上述的缓冲层的热膨胀系数。
在本发明的一实施例中，上述的接合基板的热膨胀系数低于或等于上述的缓冲层的热膨胀系数。
在本发明的一实施例中，上述的缓冲层具有表面粗化结构，增加光取出效率。
在本发明的一实施例中，上述的高反射绝缘层由多个介电材料对(pair)组成，上述的多个介电材料对包括多个第一介电对以及多个第二介电对。
在本发明的一实施例中，上述的第一介电对包括第一材料层以及第二材料层。其中上述的第一材料层折射系数(refractive index)大于第二材料层。
在本发明的一实施例中，上述的第一材料层以及上述的第二材料层的光学厚度小于四分之一的波长，上述的波长为上述的氮化物半导体量子井发光结构所发出的波长。
在本发明的一实施例中，上述的第二介电对包括第一材料层以及第二材料层。其中上述的第一材料层折射系数(refractive index)大于第二材料层。
在本发明的一实施例中，上述的第一材料层的光学厚度小于四分之一的波长，上述的第二材料层的光学厚度大于四分之一的波长，上述的波长为上述的氮化物半导体量子井发光结构所发出的波长。
在本发明的一实施例中，上述的氮化物半导体元件设置于封装载体以及封装基板上，其中上述的封装基板包括电路板以及二个焊垫。上述的二个焊 垫设置于上述的电路板上。其中上述的封装载体包括支架、二个导电引脚、树脂、二个导电材料、透明胶以及萤光粉。上述的二个导电引脚设置于上述的支架上，用以与上述的二个焊垫电性连接，其中上述的氮化物半导体元件设置于上述的二个导电引脚上，并与上述的二个导电引脚电性连接。上述的树脂设置于上述的支架上，并用以容纳上述的氮化物半导体元件及上述的二个导电引脚。上述的二个导电材料用以电性连接上述的上述的氮化物半导体元件及上述的二个导电引脚。上述的透明胶用以包覆上述的上述的氮化物半导体元件及上述的二个导电引脚。上述的萤光粉用以填入于上述的透明胶中。
在本发明的一实施例中，上述的萤光粉其是由具高稳定发光特性的材料所制成，例如石榴石系(Garnet)、硫化物(Sulfate)、氮化物(Nitrate)、硅酸盐(Silicate)、铝酸盐(Aluminate)或上述材料的任意组合，但不以此为限，其发光波长约为300nm至700nm。其中上述的萤光粉的粒径为1～25μm。
在本发明的一实施例中，上述的导电材料包含焊线或金、银、铜、铝、或是混合材料。
在本发明的一实施例中，上述的透明胶材包括环氧树脂。
在本发明的一实施例中，上述的导电引脚可为纯金属材料、金、银、铜、铝、或低熔点金属合金、金锡合金、锡、铋或锡铋合金。
在本发明的一实施例中，上述的氮化物半导体元件可应用于车用照明领域。
在本发明的一实施例中，上述的氮化物半导体元件可应用于一般照明领域。
在本发明的一实施例中，上述的氮化物半导体元件可应用于闪光灯领域。
在本发明的一实施例中，上述的氮化物半导体元件可应用于背光领域。
在本发明的一实施例中，上述的氮化物半导体元件可应用于户外看板领域。
在本发明的一实施例中，上述的氮化物半导体元件的发光效率高于220流明每瓦(lm/W)。
在本发明的一实施例中，上述的氮化物半导体元件的显色指数中对红色的显示能力(R9)大于90。
在本发明的一实施例中，上述的氮化物半导体元件的演色性指数(Color Rendering Index；CRI)大于90。
在本发明的一实施例中，上述的氮化物半导体元件的平均演色评价指数(Ra)大于90。
在本发明的一实施例中，上述的微结构为周期性突出结构，上述的周期性突出结构包括高度、宽度以及底面间距。
在本发明的一实施例中，上述的高度介于1微米至3微米之间。
在本发明的一实施例中，上述的宽度介于1微米至3微米之间。
在本发明的一实施例中，上述的底面间距介于0.1微米至3微米之间。
在本发明的一实施例中，上述的基板上述的第二面的粗糙度大于上述的成长表面以及上述的多个微结构的表面。
在本发明的一实施例中，上述的微结构的外型为半球体(hemisphere)。
在本发明的一实施例中，上述的微结构的外型为锥体(cone)。
在本发明的一实施例中，上述的微结构的外型为截头锥体(truncated-cone)。
在本发明的一实施例中，上述的微结构的外型为金字塔(pyramid)。
在本发明的一实施例中，上述的微结构的外型为截头金字塔(truncated-pyramid)。
在本发明的一实施例中，上述的微结构的外型为方柱(square pillar)。
在本发明的一实施例中，上述的微结构的外型为圆桶(cylinder)。
本发明提供一种氮化物半导体元件，其包括P型氮化物半导体、N型氮化物半导体、氮化物半导体量子井发光结构、基板以及缓冲层。上述的氮化物半导体量子井发光结构位于上述的P型氮化物半导体及上述的N型氮化物半导体之间。上述的基板包含相对的第一面以及第二面。上述的缓冲层位于上述的N型氮化物半导体以及上述的基板的上述的第一面之间。其中上述的氮化物半导体量子井发光结构具有多个井层和多个阻挡层，上述的多个阻挡层包含配置于最接近上述的P型氮化物半导体位置的第一阻挡层、配置于最接近上述的N型氮化物半导体位置的第二阻挡层以及多个第三阻挡层，其中上述的多个第三阻挡层被上述的多个井层夹住，其中上述的第一阻挡层的厚度小于上述的第二阻挡层的厚度。
在本发明的一实施例中，上述的第二阻挡层的厚度与上述的第三阻挡层的厚度相同。
在本发明的一实施例中，上述的第二阻挡层的厚度与上述的第三阻挡层的厚度不同。
本发明的氮化物半导体元件包括P型氮化物半导体、N型氮化物半导体、氮化物半导体量子井发光结构、基板以及缓冲层。上述的氮化物半导体量子井发光结构位于上述的P型氮化物半导体及上述的N型氮化物半导体之间。 上述的基板包含相对的第一面以及第二面。上述的缓冲层位于上述的N型氮化物半导体以及上述的基板的上述的第一面之间。其中上述的氮化物半导体量子井发光结构具有多个井层和多个阻挡层，上述的多个阻挡层包含一配置于最接近前述P型氮化物半导体位置的第一阻挡层、一配置于最接近前述N型氮化物半导体位置的第二阻挡层以及多个第三阻挡层，其中上述的多个第三阻挡层被上述的多个井层夹住，其中上述的第一阻挡层的厚度小于上述的第三阻挡层的厚度。
在本发明的一实施例中，上述的第二阻挡层的厚度与上述的第三阻挡层的厚度相同。
在本发明的一实施例中，上述的第二阻挡层的厚度与上述的第三阻挡层的厚度不同。
本发明提供一种氮化物半导体元件，其包括P型氮化物半导体、N型氮化物半导体、缓冲层、氮化物半导体量子井发光结构、高反射绝缘层、P型高反射欧姆电极、N型电极、第一焊接金属层、第二焊接金属层、接合基板以及基板电极。上述的氮化物半导体量子井发光结构位于上述的P型氮化物半导体及上述的N型氮化物半导体之间。上述的高反射绝缘层覆盖于上述的P型氮化物半导体。上述的P型高反射欧姆电极覆盖于上述的高反射绝缘层以及上述的P型氮化物半导体，并与上述的P型氮化物半导体电性连接。上述的N型电极覆盖于上述的缓冲层，并与上述的N型氮化物半导体电性连接。上述的第一焊接金属层覆盖于上述的P型高反射欧姆电极，并与上述的P型氮化物半导体电性连接。上述的第二焊接金属层覆盖于上述的第一焊接金属层，并与上述的P型氮化物半导体电性连接。上述的接合基板覆盖于上述的第二焊接金属层，并与上述的P型氮化物半导体电性连接。上述的基板电极覆盖于上述的接合基板，并与上述的P型氮化物半导体电性连接。上述的氮化物半导体量子井发光结构具有多个井层和多个阻挡层，上述的多个阻挡层包含一配置于最接近前述P型氮化物半导体位置的第一阻挡层、一配置于最接近前述N型氮化物半导体位置的第二阻挡层以及多个第三阻挡层，其中上述的多个第三阻挡层被上述的多个井层夹住，其中上述的第一阻挡层的厚度小于上述的第二阻挡层的厚度。
在本发明的一实施例中，上述的第二阻挡层的厚度与上述的第三阻挡层的厚度相同。
在本发明的一实施例中，上述的第二阻挡层的厚度与上述的第三阻挡层的厚度不同。
本发明提供一种氮化物半导体元件，其包括P型氮化物半导体、N型氮化物半导体、缓冲层、氮化物半导体量子井发光结构、高反射绝缘层、P型高反射欧姆电极、N型电极、第一焊接金属层、第二焊接金属层、接合基板以及基板电极。上述的氮化物半导体量子井发光结构位于上述的P型氮化物半导体及上述的N型氮化物半导体之间。上述的高反射绝缘层覆盖于上述的P型氮化物半导体。上述的P型高反射欧姆电极覆盖于上述的高反射绝缘层以及上述的P型氮化物半导体，并与上述的P型氮化物半导体电性连接。上述的N型电极覆盖于上述的缓冲层，并与上述的N型氮化物半导体电性连接。上述的第一焊接金属层覆盖于上述的P型高反射欧姆电极，并与上述的P型氮化物半导体电性连接。上述的第二焊接金属层覆盖于上述的第一焊接金属层，并与上述的P型氮化物半导体电性连接。上述的接合基板覆盖于上述的第二焊接金属层，并与上述的P型氮化物半导体电性连接。上述的基板电极覆盖于上述的接合基板，并与上述的P型氮化物半导体电性连接。上述的氮化物半导体量子井发光结构具有多个井层和多个阻挡层，上述的多个阻挡层包含一配置于最接近前述P型氮化物半导体位置的第一阻挡层、一配置于最接近前述N型氮化物半导体位置的第二阻挡层以及多个第三阻挡层，其中上述的多个第三阻挡层被上述的多个井层夹住，其中上述的第一阻挡层的厚度小于上述的第三阻挡层的厚度。
在本发明的一实施例中，上述的第二阻挡层的厚度与上述的第三阻挡层的厚度相同。
在本发明的一实施例中，上述的第二阻挡层的厚度与上述的第三阻挡层的厚度不同。
本发明提供一种氮化物半导体元件的制造方法，其包括下列步骤。形成半导体晶圆。以隐形激光方式切割上述的半导体晶圆，形成如上述任一实施例中的氮化物半导体元件。
本发明提供一种封装结构，其包括电路板、支架、以及如上述任一实施例中的氮化物半导体元件。上述的支架设置于上述的电路板上。上述的氮化物半导体元件设置于上述的支架上。
在本发明的一实施例中，上述的封装结构还包括透明胶覆盖上述的氮化物半导体元件。
在本发明的一实施例中，上述的封装结构还包括萤光粉，填入于上述的透明胶内。
在本发明的一实施例中，上述的萤光粉的浓度是均匀分布于上述的透明 胶内。
在本发明的一实施例中，上述的萤光粉的浓度是不均匀分布于上述的透明胶内。
在本发明的一实施例中，上述的萤光粉的浓度是由上述的氮化物半导体元件的表面往上述的透明胶的表面逐渐增加。
在本发明的一实施例中，上述的萤光粉的浓度是由上述的氮化物半导体元件的表面往上述的透明胶的表面逐渐减少。
在本发明的一实施例中，上述的萤光粉其是由具高稳定发光特性的材料所制成，例如石榴石系(Garnet)、硫化物(Sulfate)、氮化物(Nitrate)、硅酸盐(Silicate)、铝酸盐(Aluminate)或上述材料的任意组合，但不以此为限，其发光波长约为300nm至700nm。其中上述的萤光粉的粒径为1～25μm。
本发明提供一种氮化物半导体元件，其包括基板、缓冲层、第一N型氮化物半导体、氮化物半导体量子井发光结构、P型氮化物半导体、穿隧接面(Tunnel Junction)以及第二N型氮化物半导体。上述的基板具有相对的第一面及第二面。上述的缓冲层设置于上述的基板的上述的第一面上。上述的第一N型氮化物半导体设置于上述的缓冲层上。上述的氮化物半导体量子井发光结构设置于上述的第一N型氮化物半导体上。上述的P型氮化物半导体设置于上述的氮化物半导体量子井发光结构上。上述的穿隧接面设置于上述的氮化物半导体量子井发光结构上。上述的穿隧接面包括重掺杂P型(P+)氮化物半导体以及重掺杂N型(N+)氮化物半导体。上述的重掺杂P型(P+)氮化物半导体设置于上述的氮化物半导体量子井发光结构上。上述的重掺杂N型(N+)氮化物半导体设置于上述的重掺杂P型氮化物半导体上。上述的第二N型氮化物半导体设置于上述的穿隧接面的上述的重掺杂N型氮化物半导体上。其中上述的氮化物半导体量子井发光结构具有多个井层和多个阻挡层，上述的多个阻挡层包含配置于最接近上述的P型氮化物半导体位置的第一阻挡层、配置于最接近上述的第一N型氮化物半导体位置的第二阻挡层以及多个第三阻挡层，其中上述的多个第三阻挡层被上述的多个井层夹住，其中上述的第一阻挡层的厚度小于100埃
Figure PCTCN2017098626-appb-000005
。
在本发明的一实施例中，上述的重掺杂P型半导体层的能隙(Energy Bandgap)越靠近上述的P型氮化物半导体越高，上述的重掺杂N型氮化物半导体层的能隙越靠近上述的第二N型氮化物半导体越高。
在本发明的一实施例中，上述的重掺杂P型半导体层的厚度约为1nm～100nm，上述的重掺杂N型氮化物半导体层的厚度约为1纳米(nanometer； nm)～100nm。
在本发明的一实施例中，上述的第二阻挡层的厚度大于上述的第一阻挡层的厚度，第三阻挡层的厚度大于上述的第一阻挡层的厚度，第二阻挡层的厚度大于或是等于上述的第三阻挡层的厚度。
在本发明的一实施例中，上述的第二阻挡层的厚度大于上述的第一阻挡层的厚度，第三阻挡层的厚度大于上述的第一阻挡层的厚度，上述的第二阻挡层的厚度小于或是等于上述的第三阻挡层的厚度。
在本发明的一实施例中，上述的第一N型氮化物半导体及上述的第二N型氮化物半导体的至少一者具有粗糙表面，用以增加上述的氮化物半导体元件的出光效果。
在本发明的一实施例中，上述的P型氮化物半导体包括P侧应力释放层、高浓度空穴层以及电子阻挡层。其中配置于最接近上述的第一阻挡层为上述的P侧应力释放层，配置于最远离上述的第一阻挡层为上述的电子阻挡层，上述的高浓度空穴层被上述的P侧应力释放层以及上述的电子阻挡层所夹住。
在本发明的一实施例中，上述的P侧应力释放层可为超晶格结构，其材料包含氮化铝镓(AlGaN)以及氮化镓(GaN)所构成的超晶格结构，或是由氮化铝镓(AlxGaN)以及氮化铝镓(AlyGaN)所构成的超晶格结构，或是由氮化铝镓(AlGaN)以及氮化铝铟镓(InAlGaN)所构成的超晶格结构，其中，x不等于y，上述的超晶格结构小于20对。
在本发明的一实施例中，上述的高浓度空穴层可由氮化镓(GaN)或是氮化铝镓(AlGaN)所构成，上述的高浓度空穴层的镁掺杂浓度(concentration)高于上述的P侧应力释放层的镁掺杂浓度以及上述的电子阻挡层的镁掺杂浓度。
在本发明的一实施例中，上述的高浓度空穴层的镁(Mg)掺杂浓度高于1x1019(Atoms/cm3)。
在本发明的一实施例中，上述的电子阻挡层可由氮化铝镓(AlGaN)所构成，上述的电子阻挡层的铝成份百分比高于上述的P侧应力释放层的铝成份百分比以及高于上述的高浓度空穴层的铝成份百分比。
在本发明的一实施例中，上述的穿隧接面还包括中间半导体，设置于上述的重掺杂P型(P+)氮化物半导体及上述的重掺杂N型(N+)氮化物半导体之间。
在本发明的一实施例中，上述的高浓度空穴层的镁(Mg)掺杂浓度高于1x1019(Atoms/cm3)，且上述的高浓度空穴层的铝成份百分比低于上述的电子阻挡层的铝成份百分比。
在本发明的一实施例中，上述的第一N型氮化物半导体包括N侧第一应力释放层、N侧第二应力释放层、低浓度电子层以及N型欧姆接触层。其中配置于最接近上述的第二阻挡层为上述的N侧第一应力释放层，配置于最远离述上述的第二阻挡层为上述的N型欧姆接触层，上述的低浓度电子层以及上述的第二应力释放层依序堆迭于上述的N型欧姆接触层上方，上述的低浓度电子层被上述的N型欧姆接触层及上述的N侧第二应力释放层所夹住。
在本发明的一实施例中，上述的N侧第一应力释放层可为超晶格结构，其材料包含氮化铟镓(InGaN)以及氮化镓(GaN)所构成的超晶格结构，或是由氮化铟镓(InxGaN)以及氮化铟镓(InyGaN)所构成的超晶格结构，其中x不等于y，上述的超晶格结构小于20对。
在本发明的一实施例中，上述的N侧第二应力释放层可为超晶格结构，其材料包含氮化铟镓(InGaN)以及氮化镓(GaN)所构成的超晶格结构，或是由氮化铟镓(InxGaN))以及氮化铟镓(InyGaN)所构成的超晶格结构，其中x不等于y，上述的超晶格结构小于20对。
在本发明的一实施例中，上述的N侧第一应力释放层的铟成份百分比高于上述的N侧第二应力释放层的铟成份百分比。
在本发明的一实施例中，上述的低浓度电子层可由氮化镓(GaN)、氮化铟镓(InGaN)、氮化铝镓(AlGaN)或氮化铟铝镓(InAlGaN)所构成，上述的低浓度电子层的硅掺杂浓度低于上述的N型欧姆接触层的硅掺杂浓度。
在本发明的一实施例中，上述的低浓度电子层的硅掺杂浓度低于1x1018(Atoms/cm3)。
在本发明的一实施例中，上述的N型欧姆接触层可由氮化镓(GaN)、氮化铟镓(InGaN)、氮化铝镓(AlGaN)或氮化铟铝镓(InAlGaN)所构成，上述的N型欧姆接触层的硅掺杂浓度高于上述的N侧第一应力释放层的硅掺杂浓度、上述的N侧第二应力释放层的硅掺杂浓度及上述的低浓度电子层的硅掺杂浓度。
在本发明的一实施例中，上述的P侧应力释放层的上述的超晶格结构小于10对。
在本发明的一实施例中，上述的N侧第一应力释放层的上述的超晶格结构小于10对。
在本发明的一实施例中，上述的N侧第二应力释放层的上述的超晶格结构小于10对。
在本发明的一实施例中，上述的基板是选自包含III-V族、IV族、II-VI族的元素与合金、氧化锌(ZnO)、尖晶石(spinel)、氮化镓(GaN)、蓝宝石 (sapphire)、硅(Si)所组成的群组中的至少一者。
在本发明的一实施例中，上述的缓冲层包括第一缓冲层以及第二缓冲层。其中上述的第一缓冲层被上述的基板的上述的第一面及上述的第二缓冲层所夹住，上述的第一缓冲层的缺陷密度高于上述的第二缓冲层的缺陷密度，上述的第二缓冲层上部为一平坦，且上述的第二缓冲层的缺陷密度低于上述的第一缓冲层的缺陷密度。
在本发明的一实施例中，上述的第一缓冲层的材料可为单晶氮化镓(GaN)、单晶氮化铝(AlN)、单晶氮化铝镓(AlGaN)或单晶氮化铟铝镓(InAlGaN)。
在本发明的一实施例中，上述的第一缓冲层的材料可为非单晶氮化镓(GaN)、非单晶氮化铝(AlN)、非单晶氮化铝镓(AlGaN)或非单晶氮化铟铝镓(InAlGaN)。
在本发明的一实施例中，上述的缓冲层的材料包含氮化镓(GaN)、氮化铝(AlN)、氮化铝镓(AlGaN)或氮化铟铝镓(InAlGaN)。
在本发明的一实施例中，上述的基板的上述的第一面包括成长表面以及多个位于上述的成长表面上的微结构，上述的多个微结构具有非圆滑的蚀刻侧面。
在本发明的一实施例中，上述的成长表面的表面粗糙度低于10埃
Figure PCTCN2017098626-appb-000006
。
在本发明的一实施例中，上述的微结构的表面粗糙度低于10埃
Figure PCTCN2017098626-appb-000007
。
在本发明的一实施例中，上述的微结构为周期性突出结构，上述的周期性突出结构包括高度、宽度以及底面间距。
在本发明的一实施例中，上述的高度介于1微米至3微米之间。
在本发明的一实施例中，上述的宽度介于1微米至3微米之间。
在本发明的一实施例中，上述的底面间距介于0.1微米至3微米之间。
在本发明的一实施例中，上述的基板的上述的第二面的粗糙度大于上述的成长表面的粗糙度以及上述的多个微结构的表面的粗糙度。
在本发明的一实施例中，上述的微结构的外型为半球体(hemisphere)、锥体(cone)、截头锥体(truncated-cone)、金字塔(pyramid)、截头金字塔(truncated-pyramid)、方柱(square pillar)或圆桶(cylinder)。
在本发明的一实施例中，上述的穿隧接面还包括中间半导体，设置于上述的重掺杂P型(P+)氮化物半导体及上述的重掺杂N型(N+)氮化物半导体之间，上述的中间半导体相对于上述的重掺杂P型(P+)氮化物半导体及上述的重掺杂N型(N+)氮化物半导体形成异质接面，以建立极化场，使得上述的重 掺杂P型(P+)氮化物半导体的价带及上述的重掺杂N型(N+)氮化物半导体的导带相互对应。
在本发明的一实施例中，上述的重掺杂P型(P+)氮化物半导体及上述的重掺杂N型(N+)氮化物半导体的至少一者的能隙大于上述的氮化物半导体量子井发光结构的能隙。
在本发明的一实施例中，上述的中间半导体包含氮化铝镓(AlGaN)、氮化镓(GaN)、氮化铟镓(InGaN)或氮化铟铝镓(InAlGaN)。
在本发明的一实施例中，上述的中间半导体具有内部带穿隧阻挡层(inter band tunnel barrier)，上述的重掺杂P型(P+)氮化物半导体具有P型空乏阻挡层(P-depletion barrier)，上述的重掺杂N型(N+)氮化物半导体具有N型空乏阻挡层(N-depletion barrier)。
在本发明的一实施例中，上述的中间半导体的厚度约为0.5nm～10nm。
在本发明的一实施例中，上述的中间半导体具有侧面材料能隙波动(lateral material energy bandgap fluctuations)，其包含多个低及高能隙区域(low and high bandgap regions)。
在本发明的一实施例中，上述的氮化物半导体元件还包括平台结构、第一N型电极、电流阻挡层、透明导电层、第二N型电极、绝缘层以及高反射绝缘层。上述的平台结构露出部分上述的N型欧姆接触层。上述的第一N型电极与上述的N型欧姆接触层电性连接。上述的电流阻挡层与上述的第二N型氮化物半导体直接接触。上述的透明导电层覆盖上述的电流阻挡层以及与上述的第二N型氮化物半导体直接接触。上述的第二N型电极位于上述的透明导电层的上方，通过透明导电层与上述的第二N型氮化物半导体电性连接。上述的绝缘层覆盖上述的第一N型电极以及上述的第二N型电极及上述的平台结构的侧壁。上述的高反射绝缘层位于上述的基板的上述的第二面。
在本发明的一实施例中，上述的高反射绝缘层由多个介电材料对(pair)所组成，上述的多个介电材料对包括多个第一介电对以及多个第二介电对。
在本发明的一实施例中，上述的第一介电对包括第一材料层以及第二材料层，其中上述的第一材料层的介电系数大于上述的第二材料层的介电系数。
在本发明的一实施例中，上述的第一材料层以及上述的第二材料层的光学厚度小于四分之一的波长，上述的波长为上述的氮化物半导体量子井发光结构所发出的波长。
在本发明的一实施例中，上述的第二介电对包括第一材料层以及第二材料层，其中上述的第一材料层的介电系数大于上述的第二材料层的介电系数。
在本发明的一实施例中，上述的第一材料层的光学厚度小于四分之一的波长，上述的第二材料层的光学厚度大于四分之一的波长，上述的波长为上述的氮化物半导体量子井发光结构所发出的波长。
在本发明的一实施例中，上述的透明导电层可以是铟锡氧化物(Indium Tin Oxide；ITO)、铟锌氧化物(indium zinc oxide；IZO)、氧化锌(Zinc Oxide；ZnO)或氧化锌铝(Aluminum Zinc Oxide；AZO)。
在本发明的一实施例中，上述的绝缘层包括氧化硅(SiOX)、氮化硅(SiNX)、聚酰亚胺(Polyimide)或其他高分子材料。
在本发明的一实施例中，上述的高反射绝缘层的材料包括氧化物、氮化物、或至少包含Si、Ti、Zr、Nb、Ta、Al元素所组成的氧化物或氮化物。
在本发明的一实施例中，上述的第一N型电极的材料包括Ag、Al、Ni、Rh、Au、Cu、Ti、Pt、Pd、Mo、Cr、W或上述金属的合金。
在本发明的一实施例中，上述的第二N型电极的材料包括Ag、Al、Ni、Rh、Au、Cu、Ti、Pt、Pd、Mo、Cr、W或上述金属的合金。
在本发明的一实施例中，上述的氮化物半导体元件设置于封装载体以及封装基板上。其中上述的封装基板包括电路板以及二个焊垫。上述的二个焊垫设置于上述的电路板上。其中上述的封装载体包括支架或载板、二个导电引脚、树脂、二个导电材料、透明胶以及萤光粉。上述的支架或上述的载板设置于上述的电路板上。上述的二个导电引脚设置于上述的支架或上述的载板上，用以与上述的二个焊垫电性连接，其中上述的氮化物半导体元件设置于上述的二个导电引脚上，其中上述的第一N型电极及上述的第二N型电极并与上述的二个导电引脚对应地电性连接。上述的树脂设置于上述的支架或上述的载板上，并用以容纳上述的氮化物半导体元件及上述的二个导电引脚。上述的二个导电材料用以电性连接上述的上述的氮化物半导体元件的上述的第一N型电极及上述的第二N型电极以及上述的二个导电引脚。上述的透明胶用以包覆上述的上述的氮化物半导体元件及上述的二个导电引脚。上述的萤光粉用以填入于上述的透明胶中。
在本发明的一实施例中，上述的萤光粉是由具高稳定发光特性的材料所制成，包含石榴石系(Garnet)、硫化物(Sulfate)、氮化物(Nitrate)、硅酸盐(Silicate)、铝酸盐(Aluminate)或上述材料的任意组合，但不以此为限，其发光波长约为300nm至700nm，其中上述的萤光粉的粒径为1～25μm，其中上述的氮化物半导体元件所产生的一部分的光线可以激发上述的萤光粉，使得上述的萤光粉产生较长波长的光线，上述的氮化物半导体元件的剩余一部 分未被上述的萤光粉转换的光线与上述的萤光粉产生的光线可以混合成白光。
在本发明的一实施例中，上述的导电材料包含焊线、金、银、铜、铝或是混合材料。
在本发明的一实施例中，上述的透明胶材包括环氧树脂。
在本发明的一实施例中，上述的导电引脚可为纯金属材料、金、银、铜、铝、低熔点金属合金、金锡合金、锡、铋或锡铋合金。
在本发明的一实施例中，上述的氮化物半导体元件还包括平台结构、第一N型电极、电流阻挡层、透明导电层、第二N型电极、绝缘层、高反射绝缘层、第一焊垫层、第二焊垫层、第一连接电极以及第二连接电极。上述的平台结构，露出部分上述的N型欧姆接触层。上述的第一N型电极，与上述的N型欧姆接触层电性连接。上述的电流阻挡层，与上述的第二N型氮化物半导体直接接触。上述的透明导电层，覆盖上述的电流阻挡层以及与上述的第二N型氮化物半导体直接接触。上述的第二N型电极，位于上述的透明导电层的上方，通过透明导电层与上述的第二N型氮化物半导体电性连接。上述的绝缘层，覆盖上述的第一N型电极以及上述的第二N型电极及上述的平台结构的侧壁。上述的高反射绝缘层位于上述的覆盖部分上述的绝缘层。上述的第一焊垫层与上述的第一N型电极电性连接。上述的第二焊垫层与上述的第二N型电极电性连接。上述的第一连接电极与上述的第一焊垫层电性连接。上述的第二连接电极与上述的第二焊垫层电性连接。
在本发明的一实施例中，上述的高反射绝缘层由多个介电材料对(pair)组成，上述的多个介电材料对包括多个第一介电对以及多个第二介电对。
在本发明的一实施例中，上述的第一介电对包括第一材料层以及第二材料层，其中上述的第一材料层的介电系数大于上述的第二材料层的介电系数。
在本发明的一实施例中，上述的第一材料层以及上述的第二材料层的光学厚度小于四分之一的波长，上述的波长为上述的氮化物半导体量子井发光结构所发出的波长。
在本发明的一实施例中，上述的第二介电对包括第一材料层以及第二材料层，其中上述的第一材料层的介电系数大于上述的第二材料层的介电系数。
在本发明的一实施例中，上述的第一材料层的光学厚度小于四分之一的波长，上述的第二材料层的光学厚度大于四分之一的波长，上述的波长为上述的氮化物半导体量子井发光结构所发出的波长。
在本发明的一实施例中，上述的透明导电层可以是铟锡氧化物(Indium  Tin Oxide；ITO)、铟锌氧化物(indium zinc oxide；IZO)、氧化锌(Zinc Oxide；ZnO)或氧化锌铝(Aluminum Zinc Oxide；AZO)。
在本发明的一实施例中，上述的绝缘层包括氧化硅(SiOX)、氮化硅(SiNX)、聚酰亚胺(Polyimide)或其他高分子材料。
在本发明的一实施例中，上述的高反射绝缘层的材料包括氧化物、氮化物、以及至少包含Si、Ti、Zr、Nb、Ta、Al元素所组成的氧化物或氮化物。
在本发明的一实施例中，上述的第一N型电极的材料包括Ag、Al、Ni、Rh、Au、Cu、Ti、Pt、Pd、Mo、Cr、W或上述金属的合金。
在本发明的一实施例中，上述的第二N型电极的材料包括Ag、Al、Ni、Rh、Au、Cu、Ti、Pt、Pd、Mo、Cr、W或上述金属的合金。
在本发明的一实施例中，上述的第一导电引脚的材料包括Ag、Al、Ni、Rh、Au、Cu、Ti、Pt、Pd、Mo、Cr、W、Sn、In或上述金属的合金。
在本发明的一实施例中，上述的第二导电引脚的材料包括Ag、Al、Ni、Rh、Au、Cu、Ti、Pt、Pd、Mo、Cr、W、Sn、In或上述金属的合金。
在本发明的一实施例中，上述的氮化物半导体元件设置于封装载体以及封装基板上，其中上述的封装基板包括电路板以及二个焊垫。上述的二个焊垫设置于上述的电路板上。其中上述的封装载体包括支架或载板、二个导电引脚、树脂、二个导电材料、透明胶以及萤光粉。上述的支架或上述的载板设置于上述的电路板上。上述的二个导电引脚设置于上述的支架或上述的载板上，用以与上述的二个焊垫电性连接，其中上述的氮化物半导体元件设置于上述的二个导电引脚上，其中上述的第一N型电极及上述的第二N型电极并与上述的二个导电引脚对应地电性连接。上述的树脂设置于上述的支架或上述的载板上，并用以容纳上述的氮化物半导体元件及上述的二个导电引脚。上述的二个导电材料用以电性连接上述的上述的氮化物半导体元件的上述的第一N型电极及上述的第二N型电极以及上述的二个导电引脚。上述的透明胶用以包覆上述的上述的氮化物半导体元件及上述的二个导电引脚。上述的萤光粉用以填入于上述的透明胶中。
在本发明的一实施例中，上述的萤光粉是由具高稳定发光特性的材料所制成，包含石榴石系(Garnet)、硫化物(Sulfate)、氮化物(Nitrate)、硅酸盐(Silicate)、铝酸盐(Aluminate)或上述材料的任意组合，其发光波长约为300nm至700nm，其中上述的萤光粉的粒径为1～25μm，其中上述的氮化物半导体元件所产生的一部分的光线可以激发上述的萤光粉，使得上述的萤光粉产生较长波长的光线，上述的氮化物半导体元件的剩余一部分未被上述的萤 光粉转换的光线与上述的萤光粉产生的光线可以混合成白光。
在本发明的一实施例中，上述的透明胶材包括环氧树脂。
在本发明的一实施例中，上述的导电引脚可为纯金属材料、金、银、铜、铝、低熔点金属合金、金锡合金、锡、铋或锡铋合金。
在本发明的一实施例中，上述的氮化物半导体元件可应用于车用照明领域。
在本发明的一实施例中，上述的氮化物半导体元件可应用于一般照明领域。
在本发明的一实施例中，上述的氮化物半导体元件可应用于闪光灯领域。
在本发明的一实施例中，上述的氮化物半导体元件可应用于背光领域。
在本发明的一实施例中，上述的氮化物半导体元件可应用于户外看板领域。
在本发明的一实施例中，上述的氮化物半导体元件的发光效率高于220流明每瓦(lm/W)。
在本发明的一实施例中，上述的氮化物半导体元件的显色指数中对红色的显示能力(R9)大于90。
在本发明的一实施例中，上述的氮化物半导体元件的演色性指数(Color Rendering Index；CRI)大于90。
在本发明的一实施例中，上述的氮化物半导体元件的平均演色评价指数(Ra)大于90。
在本发明的一实施例中，上述的氮化物半导体元件可以是水平式发光晶片。
在本发明的一实施例中，上述的氮化物半导体元件可以是垂直式发光晶片。
在本发明的一实施例中，上述的氮化物半导体元件可以是覆晶式发光晶片。
在本发明的一实施例中，上述的微结构为周期性突出结构，上述的周期性突出结构包括高度、宽度以及底面间距。
在本发明的一实施例中，上述的高度介于1微米至3微米之间。
在本发明的一实施例中，上述的宽度介于1微米至3微米之间。
在本发明的一实施例中，上述的底面间距介于0.1微米至3微米之间。
在本发明的一实施例中，上述的基板的上述的第二面的粗糙度大于上述的成长表面的粗糙度以及上述的多个微结构的表面的粗糙度。
在本发明的一实施例中，上述的微结构的外型为半球体(hemisphere)、锥体(cone)、截头锥体(truncated-cone)、金字塔(pyramid)、截头金字塔(truncated-pyramid)、方柱(square pillar)或圆桶(cylinder)。
在本发明的一实施例中，上述的穿隧接面还包括中间半导体，设置于上述的重掺杂P型(P+)氮化物半导体及上述的重掺杂N型(N+)氮化物半导体之间，上述的中间半导体相对于上述的重掺杂P型(P+)氮化物半导体及上述的重掺杂N型(N+)氮化物半导体形成异质接面，以建立极化场，使得上述的重掺杂P型(P+)氮化物半导体的价带及上述的重掺杂N型(N+)氮化物半导体的导带相互对应。
在本发明的一实施例中，上述的重掺杂P型(P+)氮化物半导体及上述的重掺杂N型(N+)氮化物半导体的至少一者的能隙大于上述的氮化物半导体量子井发光结构的能隙。
在本发明的一实施例中，上述的中间半导体包含氮化铝镓(AlGaN)、氮化镓(GaN)、氮化铟镓(InGaN)或氮化铟铝镓(InAlGaN)。
在本发明的一实施例中，上述的中间半导体具有内部带穿隧阻挡层(inter band tunnel barrier)，上述的重掺杂P型(P+)氮化物半导体具有P型空乏阻挡层(P-depletion barrier)，上述的重掺杂N型(N+)氮化物半导体具有N型空乏阻挡层(N-depletion barrier)。
在本发明的一实施例中，上述的中间半导体的厚度约为0.5nm～10nm。
在本发明的一实施例中，上述的中间半导体具有侧面材料能隙波动(lateral material energy bandgap fluctuations)，其包含多个低及高能隙区域(low and high bandgap regions)。
在本发明的一实施例中，上述的第二N型氮化物半导体及上述的重掺杂N型(N+)氮化物半导体不会吸收上述的氮化物半导体量子井发光结构所发出光线。
在本发明的一实施例中，上述的第二N型氮化物半导体及上述的重掺杂N型(N+)氮化物半导体的能隙大于上述的氮化物半导体量子井发光结构的能隙。
在本发明的一实施例中，上述的多个氮化物半导体元件是可电性串联而形成氮化物半导体高压元件。
在本发明的一实施例中，上述的氮化物半导体元件可以发出UV光线、蓝色光线或绿色光线。
在本发明的一实施例中，上述的氮化物半导体元件可以应用于灯丝 (Filament)产品。
在本发明的一实施例中，上述的氮化物半导体元件可以应用于COB(Chip on Board)产品。
在本发明的一实施例中，上述的氮化物半导体元件可以应用于激光二极管(Laser Diode)产品。
在本发明的一实施例中，上述的氮化物半导体元件可以应用于发光二极管(Light Emitting Diode)产品。
本发明提供一种氮化物半导体元件，其包括第一N型电极、第一N型氮化物半导体、氮化物半导体量子井发光结构、P型氮化物半导体、穿隧接面(Tunnel Junction)、第二N型氮化物半导体、高反射绝缘层、N型高反射欧姆电极、第一焊接金属层、第二焊接金属层、接合基板以及第二N型电极。上述的第一N型氮化物半导体设置于上述的第一N型电极上。上述的氮化物半导体量子井发光结构设置于上述的第一N型氮化物半导体上。上述的P型氮化物半导体设置于上述的氮化物半导体量子井发光结构上。上述的穿隧接面(Tunnel Junction)设置于上述的氮化物半导体量子井发光结构上。上述的穿隧接面包括重掺杂P型(P+)氮化物半导体以及重掺杂N型(N+)氮化物半导体。上述的重掺杂P型(P+)氮化物半导体设置于上述的氮化物半导体量子井发光结构上。上述的重掺杂N型(N+)氮化物半导体设置于上述的重掺杂P型氮化物半导体上。上述的第二N型氮化物半导体设置于上述的穿隧接面的上述的重掺杂N型氮化物半导体上。上述的高反射绝缘层设置于上述的第二N型氮化物半导体上，并暴露出部分的上述的第二N型氮化物半导体。上述的N型高反射欧姆电极设置于上述的第二N型氮化物半导体上，并覆盖上述的高反射绝缘层及上述的第二N型氮化物半导体。上述的第一焊接金属层设置于上述的N型高反射欧姆电极上。上述的第二焊接金属层设置于上述的第一焊接金属层上。上述的接合基板设置于上述的第二焊接金属层上，并与上述的第一焊接金属层电性连接。上述的第二N型电极设置上述的接合基板上，并与上述的接合基板电性连接。其中上述的氮化物半导体量子井发光结构具有多个井层和多个阻挡层，上述的多个阻挡层包含配置于最接近上述的P型氮化物半导体位置的第一阻挡层、配置于最接近上述的第一N型氮化物半导体位置的第二阻挡层以及多个第三阻挡层，其中上述的多个第三阻挡层被上述的多个井层夹住，其中上述的第一阻挡层的厚度小于100埃。
在本发明的一实施例中，上述的重掺杂P型半导体层的能隙越靠近上述的P型氮化物半导体越高，上述的重掺杂N型氮化物半导体层的能隙越靠近 上述的第二N型氮化物半导体越高。
在本发明的一实施例中，上述的重掺杂P型半导体层的厚度约为1nm～100nm，上述的重掺杂N型氮化物半导体层的厚度约为1nm～100nm。
在本发明的一实施例中，上述的第二阻挡层的厚度大于上述的第一阻挡层的厚度，第三阻挡层的厚度大于上述的第一阻挡层的厚度，第二阻挡层的厚度大于或是等于上述的第三阻挡层的厚度。
在本发明的一实施例中，上述的第二阻挡层的厚度大于上述的第一阻挡层的厚度，第三阻挡层的厚度大于上述的第一阻挡层的厚度，上述的第二阻挡层的厚度小于或是等于上述的第三阻挡层的厚度。
在本发明的一实施例中，上述的第一N型氮化物半导体及上述的第二N型氮化物半导体的至少一者具有粗糙表面，用以增加上述的氮化物半导体元件的出光效果。
在本发明的一实施例中，上述的P型氮化物半导体包括P侧应力释放层、高浓度空穴层以及电子阻挡层。其中配置于最接近上述的第一阻挡层为上述的P侧应力释放层，配置于最远离上述的第一阻挡层为上述的电子阻挡层，上述的高浓度空穴层被上述的高浓度空穴层以及上述的电子阻挡层所夹住。
在本发明的一实施例中，上述的P侧应力释放层可为超晶格结构，其材料包含氮化铝镓(AlGaN)以及氮化镓(GaN)所构成的超晶格结构，或是由氮化铝镓(AlxGaN)以及氮化铝镓(AlyGaN)所构成的超晶格结构，或是由氮化铝镓(AlGaN)以及氮化铝铟镓(InAlGaN)所构成的超晶格结构，其中，x不等于y，上述的超晶格结构小于20对。
在本发明的一实施例中，上述的高浓度空穴层可由氮化镓(GaN)或是氮化铝镓(AlGaN)所构成，上述的高浓度空穴层的镁掺杂浓度(concentration)高于上述的P侧应力释放层的镁掺杂浓度以及上述的电子阻挡层的镁掺杂浓度。
在本发明的一实施例中，上述的高浓度空穴层的镁(Mg)掺杂浓度高于1x1019(Atoms/cm3)。
在本发明的一实施例中，上述的电子阻挡层可由氮化铝镓(AlGaN)所构成，上述的电子阻挡层的铝成份百分比高于上述的P侧应力释放层的铝成份百分比以及高于上述的高浓度空穴层的铝成份百分比。
在本发明的一实施例中，上述的穿隧接面还包括中间半导体，设置于上述的重掺杂P型(P+)氮化物半导体及上述的重掺杂N型(N+)氮化物半导体之间。
在本发明的一实施例中，上述的高浓度空穴层的镁(Mg)掺杂浓度高于 1x1019(Atoms/cm3)且上述的高浓度空穴层的铝成份百分比低于上述的电子阻挡层的铝成份百分比。
在本发明的一实施例中，上述的第一N型氮化物半导体包括N侧第一应力释放层、N侧第二应力释放层、低浓度电子层以及N型欧姆接触层。其中配置于最接近上述的第二阻挡层为上述的N侧第一应力释放层，配置于最远离述上述的第二阻挡层为上述的N型欧姆接触层，上述的低浓度电子层以及上述的第二应力释放层依序堆迭于上述的N型欧姆接触层上方，上述的低浓度电子层被N型欧姆接触层及上述的N侧第二应力释放层所夹住。
在本发明的一实施例中，上述的N侧第一应力释放层可为超晶格结构，其材料包含氮化铟镓(InGaN)以及氮化镓(GaN)所构成的超晶格结构，或是由氮化铟镓(InxGaN))以及氮化铟镓(InyGaN)所构成的超晶格结构，其中x不等于y，上述的超晶格结构小于20对。
在本发明的一实施例中，上述的N侧第二应力释放层可为超晶格结构，其材料包含氮化铟镓(InGaN)以及氮化镓(GaN)所构成的超晶格结构，或是由氮化铟镓(InxGaN))以及氮化铟镓(InyGaN)所构成的超晶格结构，其中x不等于y，上述的超晶格结构小于20对。
在本发明的一实施例中，上述的N侧第一应力释放层的铟成份百分比高于上述的N侧第二应力释放层的铟成份百分比。
在本发明的一实施例中，上述的N型氮化物半导体，上述的低浓度电子层可由氮化镓(GaN)、氮化铟镓(InGaN)、氮化铝镓(AlGaN)或氮化铟铝镓(InAlGaN)所构成，上述的低浓度电子层的硅掺杂浓度低于上述的N型欧姆接触层的硅掺杂浓度。
在本发明的一实施例中，上述的低浓度电子层的硅掺杂浓度低于1x1018(Atoms/cm3)。
在本发明的一实施例中，上述的N型欧姆接触层可由氮化镓(GaN)、氮化铟镓(InGaN)、氮化铝镓(AlGaN)或氮化铟铝镓(InAlGaN)所构成，上述的N型欧姆接触层的硅掺杂浓度高于上述的N侧第一应力释放层的硅掺杂浓度、上述的N侧第二应力释放层的硅掺杂浓度及上述的低浓度电子层的硅掺杂浓度。
在本发明的一实施例中，上述的P侧应力释放层的上述的超晶格结构小于10对。
在本发明的一实施例中，上述的N侧第一应力释放层的上述的超晶格结构小于10对。
在本发明的一实施例中，上述的第一N侧第二应力释放层的上述的超晶 格结构小于10对。
在本发明的一实施例中，上述的第一N型电极的材料包括Ag、Al、Ni、Rh、Au、Cu、Ti、Pt、Pd、Mo、Cr、W或上述金属的合金。
在本发明的一实施例中，上述的N型高反射欧姆电极包括Ag、Al、Ni、Rh、Au、Cu、Ti、Pt、Pd、Mo、Cr、W或上述金属的合金。
在本发明的一实施例中，上述的第二N型电极包括Ag、Al、Ni、Rh、Au、Cu、Ti、Pt、Pd、Mo、Cr、W或上述金属的合金。
在本发明的一实施例中，上述的第一焊接金属层材料包含Ag、Al、Ni、Rh、Au、Cu、Ti、Pt、Pd、Mo、Cr、W、Sn、铟(In)或上述金属的合金。
在本发明的一实施例中，上述的第二焊接金属层材料包含Ag、Al、Ni、Rh、Au、Cu、Ti、Pt、Pd、Mo、Cr、W、Sn、In或上述金属的合金。
在本发明的一实施例中，上述的接合基板包含纯金属基板、铜基板、钨基板、铝基板、合金基板、铜钨基板、陶瓷基板、氧化铝基板、硅基板、或碳化硅基板。
在本发明的一实施例中，上述的接合基板的热膨胀系数高于或等于上述的第一N型氮化物半导体的热膨胀系数。
在本发明的一实施例中，上述的接合基板的热膨胀系数低于或等于上述的第一N型氮化物半导体的热膨胀系数。
在本发明的一实施例中，上述的第一N型氮化物半导体具有表面粗化结构，增加光取出效率。
在本发明的一实施例中，上述的高反射绝缘层由多个介电材料对(pair)组成，上述的多个介电材料对包括多个第一介电对以及多个第二介电对。
在本发明的一实施例中，上述的第一介电对包括第一材料层以及第二材料层。其中上述的第一材料层的介电系数大于上述的第二材料层的介电系数。
在本发明的一实施例中，上述的第一材料层以及上述的第二材料层的光学厚度小于四分之一的波长，上述的波长为上述的氮化物半导体量子井发光结构所发出的波长。
在本发明的一实施例中，上述的第二介电对包括第一材料层以及第二材料层，其中上述的第一材料层的介电系数大于上述的第二材料层的介电系数。
在本发明的一实施例中，上述的第一材料层的光学厚度小于四分之一的波长，上述的第二材料层的光学厚度大于四分之一的波长，上述的波长为上述的氮化物半导体量子井发光结构所发出的波长。
在本发明的一实施例中，上述的氮化物半导体元件设置于封装载体以及 封装基板上，其中上述的封装基板包括电路板以及二个焊垫。上述的二个焊垫设置于上述的电路板上。其中上述的封装载体包括支架或载板、二个导电引脚、树脂、二个导电材料、透明胶以及萤光粉。上述的支架或上述的载板设置于上述的电路板上。上述的二个导电引脚设置于上述的支架或上述的载板上，用以与上述的二个焊垫电性连接，其中上述的氮化物半导体元件设置于上述的二个导电引脚上，其中上述的第一N型电极及上述的第二N型电极并与上述的二个导电引脚对应地电性连接。上述的树脂设置于上述的支架或上述的载板上，并用以容纳上述的氮化物半导体元件及上述的二个导电引脚。上述的二个导电材料用以电性连接上述的上述的氮化物半导体元件的上述的第一N型电极及上述的第二N型电极以及上述的二个导电引脚。上述的透明胶用以包覆上述的上述的氮化物半导体元件及上述的二个导电引脚。上述的萤光粉用以填入于上述的透明胶中。
在本发明的一实施例中，上述的萤光粉是由具高稳定发光特性的材料所制成，包含石榴石系(Garnet)、硫化物(Sulfate)、氮化物(Nitrate)、硅酸盐(Silicate)、铝酸盐(Aluminate)或上述材料的任意组合，其发光波长约为300nm至700nm，其中上述的萤光粉的粒径为1～25μm，其中上述的氮化物半导体元件所产生的一部分的光线可以激发上述的萤光粉，使得上述的萤光粉产生较长波长的光线，上述的氮化物半导体元件的剩余一部分未被上述的萤光粉转换的光线与上述的萤光粉产生的光线可以混合成白光。
在本发明的一实施例中，上述的导电材料包含焊线、金、银、铜、铝、或是混合材料。
在本发明的一实施例中，上述的透明胶材包括环氧树脂。
在本发明的一实施例中，上述的导电引脚可为纯金属材料、金、银、铜、铝、或低熔点金属合金、金锡合金、锡、铋或锡铋合金。
在本发明的一实施例中，上述的第二N型氮化物半导体及上述的重掺杂N型(N+)氮化物半导体不会吸收上述的氮化物半导体量子井发光结构所发出光线。
在本发明的一实施例中，上述的第二N型氮化物半导体及上述的重掺杂N型(N+)氮化物半导体的能隙大于上述的氮化物半导体量子井发光结构的能隙。
在本发明的一实施例中，上述的多个氮化物半导体元件是可电性串联而形成氮化物半导体高压元件。
在本发明的一实施例中，上述的氮化物半导体元件可以发出UV光线、蓝 色光线或绿色光线。
在本发明的一实施例中，上述的氮化物半导体元件可以应用于灯丝(Filament)产品。
在本发明的一实施例中，上述的氮化物半导体元件可以应用于COB(Chip on Board)产品。
在本发明的一实施例中，上述的氮化物半导体元件可以应用于激光二极管(Laser Diode)产品。
在本发明的一实施例中，上述的氮化物半导体元件可以应用于发光二极管(Light Emitting Diode)产品。
本发明提供一种氮化物半导体元件，其包括基板、缓冲层、第一N型氮化物半导体、氮化物半导体量子井发光结构、P型氮化物半导体、穿隧接面以及第二N型氮化物半导体。上述的基板具有相对的第一面及第二面。上述的缓冲层设置于上述的基板的上述的第一面上。上述的第一N型氮化物半导体设置于上述的缓冲层上。上述的氮化物半导体量子井发光结构设置于上述的第一N型氮化物半导体上。上述的P型氮化物半导体设置于上述的氮化物半导体量子井发光结构上。上述的穿隧接面(Tunnel Junction)设置于上述的氮化物半导体量子井发光结构上。上述的穿隧接面包括重掺杂P型(P+)氮化物半导体以及重掺杂N型(N+)氮化物半导体。上述的重掺杂P型(P+)氮化物半导体设置于上述的氮化物半导体量子井发光结构上。上述的重掺杂N型(N+)氮化物半导体设置于上述的重掺杂P型氮化物半导体上。上述的第二N型氮化物半导体，设置于上述的穿隧接面的上述的重掺杂N型氮化物半导体上。其中上述的氮化物半导体量子井发光结构具有多个井层和多个阻挡层，上述的多个阻挡层包含配置于最接近上述的P型氮化物半导体位置的第一阻挡层、配置于最接近上述的第一N型氮化物半导体位置的第二阻挡层以及多个第三阻挡层，其中上述的多个第三阻挡层被上述的多个井层夹住，其中上述的第一阻挡层的厚度小于上述的第二阻挡层的厚度。
在本发明的一实施例中，上述的重掺杂P型半导体层的能隙越靠近上述的P型氮化物半导体越高，上述的重掺杂N型氮化物半导体层的能隙越靠近上述的第二N型氮化物半导体越高。
在本发明的一实施例中，上述的重掺杂P型半导体层的厚度约为1nm～100nm，上述的重掺杂N型氮化物半导体层的厚度约为1nm～100nm。
在本发明的一实施例中，上述的第二N型氮化物半导体及上述的重掺杂N型(N+)氮化物半导体不会吸收上述的氮化物半导体量子井发光结构所发出光 线。
在本发明的一实施例中，上述的第二N型氮化物半导体及上述的重掺杂N型(N+)氮化物半导体的能隙大于上述的氮化物半导体量子井发光结构的能隙。
在本发明的一实施例中，上述的多个氮化物半导体元件是可电性串联而形成氮化物半导体高压元件。
在本发明的一实施例中，上述的氮化物半导体元件可以发出UV光线、蓝色光线或绿色光线。
在本发明的一实施例中，上述的氮化物半导体元件可以应用于灯丝(Filament)产品。
在本发明的一实施例中，上述的氮化物半导体元件可以应用于COB(Chip on Board)产品。
在本发明的一实施例中，上述的氮化物半导体元件可以应用于激光二极管(Laser Diode)产品。
在本发明的一实施例中，上述的氮化物半导体元件可以应用于发光二极管(Light Emitting Diode)产品。
本发明提供一种氮化物半导体元件，其包括基板、缓冲层、第一N型氮化物半导体、氮化物半导体量子井发光结构、P型氮化物半导体、穿隧接面(Tunnel Junction)以及第二N型氮化物半导体。上述的基板具有相对的第一面及第二面。上述的缓冲层设置于上述的基板的上述的第一面上。上述的第一N型氮化物半导体设置于上述的缓冲层上。上述的氮化物半导体量子井发光结构设置于上述的第一N型氮化物半导体上。上述的P型氮化物半导体设置于上述的氮化物半导体量子井发光结构上。上述的穿隧接面(Tunnel Junction)设置于上述的氮化物半导体量子井发光结构上。上述的穿隧接面包括重掺杂P型(P+)氮化物半导体以及重掺杂N型(N+)氮化物半导体。上述的重掺杂P型(P+)氮化物半导体设置于上述的氮化物半导体量子井发光结构上。上述的重掺杂N型(N+)氮化物半导体设置于上述的重掺杂P型氮化物半导体上。上述的第二N型氮化物半导体设置于上述的穿隧接面的上述的重掺杂N型氮化物半导体上。其中上述的氮化物半导体量子井发光结构具有多个井层和多个阻挡层，上述的多个阻挡层包含配置于最接近上述的P型氮化物半导体位置的第一阻挡层、配置于最接近上述的第一N型氮化物半导体位置的第二阻挡层以及多个第三阻挡层，其中上述的多个第三阻挡层被上述的多个井层夹住，其中上述的第一阻挡层的厚度小于上述的第三阻挡层的厚度。
在本发明的一实施例中，上述的重掺杂P型半导体层的能隙越靠近上述的P型氮化物半导体越高，上述的重掺杂N型氮化物半导体层的能隙越靠近上述的第二N型氮化物半导体越高。
在本发明的一实施例中，上述的重掺杂P型半导体层的厚度约为1nm～100nm，上述的重掺杂N型氮化物半导体层的厚度约为1nm～100nm。
在本发明的一实施例中，上述的第二N型氮化物半导体及上述的重掺杂N型(N+)氮化物半导体不会吸收上述的氮化物半导体量子井发光结构所发出光线。
在本发明的一实施例中，上述的第二N型氮化物半导体及上述的重掺杂N型(N+)氮化物半导体的能隙大于上述的氮化物半导体量子井发光结构的能隙。
在本发明的一实施例中，上述的多个氮化物半导体元件是可电性串联而形成氮化物半导体高压元件。
在本发明的一实施例中，上述的氮化物半导体元件可以发出UV光线、蓝色光线或绿色光线。
在本发明的一实施例中，上述的氮化物半导体元件可以应用于灯丝(Filament)产品。
在本发明的一实施例中，上述的氮化物半导体元件可以应用于COB(Chip on Board)产品。
在本发明的一实施例中，上述的氮化物半导体元件可以应用于激光二极管(Laser Diode)产品。
在本发明的一实施例中，上述的氮化物半导体元件可以应用于发光二极管(Light Emitting Diode)产品。
本发明提供一种氮化物半导体元件，其包括第一N型电极、第一N型氮化物半导体、氮化物半导体量子井发光结构、P型氮化物半导体、穿隧接面(Tunnel Junction)、第二N型氮化物半导体、高反射绝缘层、N型高反射欧姆电极、第一焊接金属层、第二焊接金属层、接合基板以及第二N型电极。上述的第一N型氮化物半导体设置于上述的第一N型电极上。上述的氮化物半导体量子井发光结构设置于上述的第一N型氮化物半导体上。上述的P型氮化物半导体设置于上述的氮化物半导体量子井发光结构上。上述的穿隧接面(Tunnel Junction)设置于上述的氮化物半导体量子井发光结构上。上述的穿隧接面包括重掺杂P型(P+)氮化物半导体以及重掺杂N型(N+)氮化物半导体。上述的重掺杂P型(P+)氮化物半导体设置于上述的氮化物半导体量子井 发光结构上。上述的重掺杂N型(N+)氮化物半导体设置于上述的重掺杂P型氮化物半导体上。上述的第二N型氮化物半导体设置于上述的穿隧接面的上述的重掺杂N型氮化物半导体上。上述的高反射绝缘层设置于上述的第二N型氮化物半导体上，并暴露出部分的上述的第二N型氮化物半导体。上述的N型高反射欧姆电极设置于上述的第二N型氮化物半导体上，并覆盖上述的高反射绝缘层及上述的第二N型氮化物半导体。上述的第一焊接金属层设置于上述的N型高反射欧姆电极上。上述的第二焊接金属层设置于上述的第一焊接金属层上。上述的接合基板设置于上述的第二焊接金属层上，并与上述的第一焊接金属层电性连接。上述的第二N型电极设置于上述的接合基板上，并与上述的接合基板电性连接。其中上述的氮化物半导体量子井发光结构具有多个井层和多个阻挡层，上述的多个阻挡层包含配置于最接近上述的P型氮化物半导体位置的第一阻挡层、配置于最接近上述的第一N型氮化物半导体位置的第二阻挡层以及多个第三阻挡层，其中上述的多个第三阻挡层被上述的多个井层夹住，其中上述的第一阻挡层的厚度小于上述的第二阻挡层的厚度。
在本发明的一实施例中，上述的重掺杂P型半导体层的能隙越靠近上述的P型氮化物半导体越高，上述的重掺杂N型氮化物半导体层的能隙越靠近上述的第二N型氮化物半导体越高。
在本发明的一实施例中，上述的重掺杂P型半导体层的厚度约为1nm～100nm，上述的重掺杂N型氮化物半导体层的厚度约为1nm～100nm。
在本发明的一实施例中，上述的第二N型氮化物半导体及上述的重掺杂N型(N+)氮化物半导体不会吸收上述的氮化物半导体量子井发光结构所发出光线。
在本发明的一实施例中，上述的第二N型氮化物半导体及上述的重掺杂N型(N+)氮化物半导体的能隙大于上述的氮化物半导体量子井发光结构的能隙。
在本发明的一实施例中，上述的多个氮化物半导体元件是可电性串联而形成氮化物半导体高压元件。
在本发明的一实施例中，上述的氮化物半导体元件可以发出UV光线、蓝色光线或绿色光线。
在本发明的一实施例中，上述的氮化物半导体元件可以应用于灯丝(Filament)产品。
在本发明的一实施例中，上述的氮化物半导体元件可以应用于COB(Chip  on Board)产品。
在本发明的一实施例中，上述的氮化物半导体元件可以应用于激光二极管(Laser Diode)产品。
在本发明的一实施例中，上述的氮化物半导体元件可以应用于发光二极管(Light Emitting Diode)产品。
本发明提供一种氮化物半导体元件，其包括第一N型电极、第一N型氮化物半导体、氮化物半导体量子井发光结构、P型氮化物半导体、穿隧接面(Tunnel Junction)、第二N型氮化物半导体、高反射绝缘层、N型高反射欧姆电极、第一焊接金属层、第二焊接金属层、接合基板以及第二N型电极。上述的第一N型氮化物半导体设置于上述的第一N型电极上。上述的氮化物半导体量子井发光结构设置于上述的第一N型氮化物半导体上。上述的P型氮化物半导体设置于上述的氮化物半导体量子井发光结构上。上述的穿隧接面(Tunnel Junction)设置于上述的氮化物半导体量子井发光结构上。上述的穿隧接面包括重掺杂P型(P+)氮化物半导体以及重掺杂N型(N+)氮化物半导体。上述的重掺杂P型(P+)氮化物半导体设置于上述的氮化物半导体量子井发光结构上。上述的重掺杂N型(N+)氮化物半导体设置于上述的重掺杂P型氮化物半导体上。上述的第二N型氮化物半导体设置于上述的穿隧接面的上述的重掺杂N型氮化物半导体上。上述的高反射绝缘层设置于上述的第二N型氮化物半导体上，并暴露出部分的上述的第二N型氮化物半导体。上述的N型高反射欧姆电极设置于上述的第二N型氮化物半导体上，并覆盖上述的高反射绝缘层及上述的第二N型氮化物半导体。上述的第一焊接金属层设置于上述的N型高反射欧姆电极上。上述的第二焊接金属层设置于上述的第一焊接金属层上。上述的接合基板设置于上述的第二焊接金属层上，并与上述的第一焊接金属层电性连接。上述的第二N型电极设置上述的接合基板上，并与上述的接合基板电性连接。其中上述的氮化物半导体量子井发光结构具有多个井层和多个阻挡层，上述的多个阻挡层包含配置于最接近上述的P型氮化物半导体位置的第一阻挡层、配置于最接近上述的第一N型氮化物半导体位置的第二阻挡层以及多个第三阻挡层，其中上述的多个第三阻挡层被上述的多个井层夹住，其中上述的第一阻挡层的厚度小于上述的第三阻挡层的厚度。
在本发明的一实施例中，上述的重掺杂P型半导体层的能隙越靠近上述的P型氮化物半导体越高，上述的重掺杂N型氮化物半导体层的能隙越靠近上述的第二N型氮化物半导体越高。
在本发明的一实施例中，上述的重掺杂P型半导体层的厚度约为1nm～100nm，上述的重掺杂N型氮化物半导体层的厚度约为1nm～100nm。
在本发明的一实施例中，上述的第二N型氮化物半导体及上述的重掺杂N型(N+)氮化物半导体不会吸收上述的氮化物半导体量子井发光结构所发出光线。
在本发明的一实施例中，上述的第二N型氮化物半导体及上述的重掺杂N型(N+)氮化物半导体的能隙大于上述的氮化物半导体量子井发光结构的能隙。
在本发明的一实施例中，上述的多个氮化物半导体元件是可电性串联而形成氮化物半导体高压元件。
在本发明的一实施例中，上述的氮化物半导体元件可以发出UV光线、蓝色光线或绿色光线。
在本发明的一实施例中，上述的氮化物半导体元件可以应用于灯丝(Filament)产品。
在本发明的一实施例中，上述的氮化物半导体元件可以应用于COB(Chip on Board)产品。
在本发明的一实施例中，上述的氮化物半导体元件可以应用于激光二极管(Laser Diode)产品。
在本发明的一实施例中，上述的氮化物半导体元件可以应用于发光二极管(Light Emitting Diode)产品。
本发明提供一种氮化物半导体元件的制造方法，包括下列步骤。形成半导体晶圆。以隐形激光方式切割上述的半导体晶圆，形成如上述任一实施例中的氮化物半导体元件。
本发明提供一种封装结构，其包括电路板、支架或载板以及如上述任一实施例中的氮化物半导体元件。上述的支架或上述的载板设置于上述的电路板上。上述的氮化物半导体元件设置于上述的支架或上述的载板上。
在本发明的一实施例中，上述的封装结构还包括透明胶，覆盖如上述任一实施例中的氮化物半导体元件。
在本发明的一实施例中，上述的封装结构还包括萤光粉，填入于上述的透明胶内。
在本发明的一实施例中，上述的萤光粉的浓度是均匀分布于上述的透明胶内。
在本发明的一实施例中，上述的萤光粉的浓度是不均匀分布于上述的透 明胶内。
在本发明的一实施例中，上述的萤光粉的浓度是由如上述任一实施例中的氮化物半导体元件的表面往上述的透明胶的表面逐渐增加。
在本发明的一实施例中，上述的萤光粉的浓度是由如上述任一实施例中的氮化物半导体元件的表面往上述的透明胶的表面逐渐减少。
在本发明的一实施例中，上述的萤光粉是由具高稳定发光特性的材料所制成，包含石榴石系(Garnet)、硫化物(Sulfate)、氮化物(Nitrate)、硅酸盐(Silicate)、铝酸盐(Aluminate)或上述材料的任意组合，其发光波长约为300nm至700nm，其中上述的萤光粉的粒径为1～25μm，其中上述的氮化物半导体元件所产生的一部分的光线可以激发上述的萤光粉，使得上述的萤光粉产生较长波长的光线，上述的氮化物半导体元件的剩余一部分未被上述的萤光粉转换的光线与上述的萤光粉产生的光线可以混合成白光。
本发明提供一种氮化物半导体高压元件，其包括电路板以及多个氮化物半导体元件。上述的多个氮化物半导体元件设置于上述的电路板上并相互电性串联。其中各个上述的多个氮化物半导体元件包括第一N型氮化物半导体、氮化物半导体量子井发光结构、P型氮化物半导体、穿隧接面(Tunnel Junction)、第二N型氮化物半导体、第一N型电极以及第二N型电极。上述的第一N型氮化物半导体设置于上述的电路板上。上述的氮化物半导体量子井发光结构设置于上述的第一N型氮化物半导体上。上述的P型氮化物半导体设置于上述的氮化物半导体量子井发光结构上。上述的穿隧接面(Tunnel Junction)设置于上述的氮化物半导体量子井发光结构上。上述的穿隧接面包括重掺杂P型(P+)氮化物半导体以及重掺杂N型(N+)氮化物半导体。上述的重掺杂P型(P+)氮化物半导体设置于上述的氮化物半导体量子井发光结构上。上述的重掺杂N型(N+)氮化物半导体设置于上述的重掺杂P型氮化物半导体上。上述的第二N型氮化物半导体设置于上述的穿隧接面的上述的重掺杂N型氮化物半导体上。上述的第一N型电极设置于上述的第一N型氮化物半导体的一侧。上述的第二N型电极设置于上述的第二N型氮化物半导体上。其中上述的多个氮化物半导体元件的其中之一的上述的第一N型电极是与其他的上述的多个氮化物半导体元件的其中之一的上述的P型氮化物半导体电性连接。
在本发明的一实施例中，上述的重掺杂P型半导体层的能隙越靠近上述的P型氮化物半导体越高，上述的重掺杂N型氮化物半导体层的能隙越靠近上述的第二N型氮化物半导体越高。
在本发明的一实施例中，上述的重掺杂P型半导体层的厚度约为1nm～100nm，上述的重掺杂N型氮化物半导体层的厚度约为1nm～100nm。
在本发明的一实施例中，上述的穿隧接面还包括中间半导体，设置于上述的重掺杂P型(P+)氮化物半导体及上述的重掺杂N型(N+)氮化物半导体之间，上述的中间半导体相对于上述的重掺杂P型(P+)氮化物半导体及上述的重掺杂N型(N+)氮化物半导体形成异质接面，以建立极化场，使得上述的重掺杂P型(P+)氮化物半导体的价带及上述的重掺杂N型(N+)氮化物半导体的导带相互对应。
在本发明的一实施例中，上述的重掺杂P型(P+)氮化物半导体及上述的重掺杂N型(N+)氮化物半导体的至少一者的能隙大于上述的氮化物半导体量子井发光结构的能隙。
在本发明的一实施例中，上述的中间半导体包含氮化铝镓(AlGaN)、氮化镓(GaN)、氮化铟镓(InGaN)或氮化铟铝镓(InAlGaN)。
在本发明的一实施例中，上述的中间半导体具有内部带穿隧阻挡层(inter band tunnel barrier)，上述的重掺杂P型(P+)氮化物半导体具有P型空乏阻挡层(P-depletion barrier)，上述的重掺杂N型(N+)氮化物半导体具有N型空乏阻挡层(N-depletion barrier)。
在本发明的一实施例中，上述的中间半导体的厚度约为0.5nm～10nm。
在本发明的一实施例中，上述的中间半导体具有侧面材料能隙波动(lateral material energy bandgap fluctuations)，其包含多个低及高能隙区域(low and high bandgap regions)。
在本发明的一实施例中，上述的多个氮化物半导体单元是可以被一透明胶覆盖，且上述的透明胶包含一萤光粉。
在本发明的一实施例中，上述的萤光粉的浓度是均匀分布于上述的透明胶内。
在本发明的一实施例中，上述的萤光粉的浓度是不均匀分布于上述的透明胶内。
在本发明的一实施例中，上述的萤光粉的浓度是由上述的氮化物半导体单元的表面往上述的透明胶的表面逐渐增加。
在本发明的一实施例中，上述的萤光粉的浓度是由上述的氮化物半导体单元的表面往上述的透明胶的表面逐渐减少。
在本发明的一实施例中，上述的萤光粉是由具高稳定发光特性的材料所制成，包含石榴石系(Garnet)、硫化物(Sulfate)、氮化物(Nitrate)、硅酸 盐(Silicate)、铝酸盐(Aluminate)或上述材料的任意组合，其发光波长约为300nm至700nm，其中上述的萤光粉的粒径为1～25μm，其中上述的氮化物半导体元件所产生的一部分的光线可以激发上述的萤光粉，使得上述的萤光粉产生较长波长的光线，上述的氮化物半导体元件的剩余一部分未被上述的萤光粉转换的光线与上述的萤光粉产生的光线可以混合成白光。
在本发明的一实施例中，上述的氮化物半导体量子井发光结构具有多个井层和多个阻挡层，上述的多个阻挡层包含配置于最接近上述的P型氮化物半导体位置的第一阻挡层、配置于最接近上述的第一N型氮化物半导体位置的第二阻挡层以及多个第三阻挡层，其中上述的多个第三阻挡层被上述的多个井层夹住，其中上述的第二阻挡层的厚度大于上述的第一阻挡层的厚度，第三阻挡层的厚度大于上述的第一阻挡层的厚度，第二阻挡层的厚度大于或是等于上述的第三阻挡层的厚度。
在本发明的一实施例中，上述的氮化物半导体量子井发光结构具有多个井层和多个阻挡层，上述的多个阻挡层包含配置于最接近上述的P型氮化物半导体位置的第一阻挡层、配置于最接近上述的第一N型氮化物半导体位置的第二阻挡层以及多个第三阻挡层，其中上述的多个第三阻挡层被上述的多个井层夹住，其中上述的第二阻挡层的厚度大于上述的第一阻挡层的厚度，第三阻挡层的厚度大于上述的第一阻挡层的厚度，上述的第二阻挡层的厚度小于或是等于上述的第三阻挡层的厚度。
在本发明的一实施例中，上述的第一N型氮化物半导体及上述的第二N型氮化物半导体的至少一者具有粗糙表面，用以增加上述的氮化物半导体元件的出光效果。
本发明提供一种氮化物半导体高压元件，其包括电路板以及多个氮化物半导体元件。上述的多个氮化物半导体元件设置于上述的电路板上并相互电性串联。其中各个上述的多个氮化物半导体元件包括第一N型电极、第一N型氮化物半导体、氮化物半导体量子井发光结构、P型氮化物半导体、穿隧接面(Tunnel Junction)、第二N型氮化物半导体、高反射绝缘层、N型高反射欧姆电极、第一焊接金属层、第二焊接金属层、接合基板以及第二N型电极。上述的第一N型氮化物半导体设置于上述的第一N型电极上。上述的氮化物半导体量子井发光结构设置于上述的第一N型氮化物半导体上。上述的P型氮化物半导体设置于上述的氮化物半导体量子井发光结构上。上述的穿隧接面(Tunnel Junction)设置于上述的氮化物半导体量子井发光结构上。上述的穿隧接面包括重掺杂P型(P+)氮化物半导体以及重掺杂N型(N+)氮化物半导 体。上述的重掺杂P型(P+)氮化物半导体设置于上述的氮化物半导体量子井发光结构上。上述的重掺杂N型(N+)氮化物半导体设置于上述的重掺杂P型氮化物半导体上。上述的第二N型氮化物半导体设置于上述的穿隧接面的上述的重掺杂N型氮化物半导体上。上述的高反射绝缘层设置于上述的第二N型氮化物半导体上，并暴露出部分的上述的第二N型氮化物半导体。上述的N型高反射欧姆电极设置于上述的第二N型氮化物半导体上，并覆盖上述的高反射绝缘层及上述的第二N型氮化物半导体。上述的第一焊接金属层设置于上述的N型高反射欧姆电极上。上述的第二焊接金属层设置于上述的第一焊接金属层上。上述的接合基板设置于上述的第二焊接金属层上，并与上述的第一焊接金属层电性连接。上述的第二N型电极设置上述的接合基板上，并与上述的接合基板电性连接。其中上述的多个氮化物半导体元件的其中之一的上述的第一N型电极是与其他的上述的多个氮化物半导体元件的其中之一的上述的P型氮化物半导体电性连接。
在本发明的一实施例中，上述的重掺杂P型半导体层的能隙越靠近上述的P型氮化物半导体越高，上述的重掺杂N型氮化物半导体层的能隙越靠近上述的第二N型氮化物半导体越高。
在本发明的一实施例中，上述的重掺杂P型半导体层的厚度约为1nm～100nm，上述的重掺杂N型氮化物半导体层的厚度约为1nm～100nm。
在本发明的一实施例中，上述的穿隧接面还包括中间半导体，设置于上述的重掺杂P型(P+)氮化物半导体及上述的重掺杂N型(N+)氮化物半导体之间，上述的中间半导体相对于上述的重掺杂P型(P+)氮化物半导体及上述的重掺杂N型(N+)氮化物半导体形成异质接面，以建立极化场，使得上述的重掺杂P型(P+)氮化物半导体的价带及上述的重掺杂N型(N+)氮化物半导体的导带相互对应。
在本发明的一实施例中，上述的重掺杂P型(P+)氮化物半导体及上述的重掺杂N型(N+)氮化物半导体的至少一者的能隙大于上述的氮化物半导体量子井发光结构的能隙。
在本发明的一实施例中，上述的中间半导体包含氮化铝镓(AlGaN)、氮化镓(GaN)、氮化铟镓(InGaN)或氮化铟铝镓(InAlGaN)。
在本发明的一实施例中，上述的中间半导体具有内部带穿隧阻挡层(inter band tunnel barrier)，上述的重掺杂P型(P+)氮化物半导体具有P型空乏阻挡层(P-depletion barrier)，上述的重掺杂N型(N+)氮化物半导体具有N型空乏阻挡层(N-depletion barrier)。
在本发明的一实施例中，上述的中间半导体的厚度约为0.5nm～10nm。
在本发明的一实施例中，上述的中间半导体具有侧面材料能隙波动(lateral material energy bandgap fluctuations)，其包含多个低及高能隙区域(low and high bandgap regions)。
在本发明的一实施例中，上述的多个氮化物半导体单元是可以被一透明胶覆盖，且上述的透明胶包含一萤光粉。
在本发明的一实施例中，上述的萤光粉的浓度是均匀分布于上述的透明胶内。
在本发明的一实施例中，上述的萤光粉的浓度是不均匀分布于上述的透明胶内。
在本发明的一实施例中，上述的萤光粉的浓度是由上述的氮化物半导体单元的表面往上述的透明胶的表面逐渐增加。
在本发明的一实施例中，上述的萤光粉的浓度是由上述的氮化物半导体单元的表面往上述的透明胶的表面逐渐减少。
在本发明的一实施例中，上述的萤光粉是由具高稳定发光特性的材料所制成，包含石榴石系(Garnet)、硫化物(Sulfate)、氮化物(Nitrate)、硅酸盐(Silicate)、铝酸盐(Aluminate)或上述材料的任意组合，其发光波长约为300nm至700nm，其中上述的萤光粉的粒径为1～25μm，其中上述的氮化物半导体元件所产生的一部分的光线可以激发上述的萤光粉，使得上述的萤光粉产生较长波长的光线，上述的氮化物半导体元件的剩余一部分未被上述的萤光粉转换的光线与上述的萤光粉产生的光线可以混合成白光。
在本发明的一实施例中，上述的氮化物半导体量子井发光结构具有多个井层和多个阻挡层，上述的多个阻挡层包含配置于最接近上述的P型氮化物半导体位置的第一阻挡层、配置于最接近上述的第一N型氮化物半导体位置的第二阻挡层以及多个第三阻挡层，其中上述的多个第三阻挡层被上述的多个井层夹住，其中上述的第二阻挡层的厚度大于上述的第一阻挡层的厚度，第三阻挡层的厚度大于上述的第一阻挡层的厚度，第二阻挡层的厚度大于或是等于上述的第三阻挡层的厚度。
在本发明的一实施例中，上述的氮化物半导体量子井发光结构具有多个井层和多个阻挡层，上述的多个阻挡层包含配置于最接近上述的P型氮化物半导体位置的第一阻挡层、配置于最接近上述的第一N型氮化物半导体位置的第二阻挡层以及多个第三阻挡层，其中上述的多个第三阻挡层被上述的多个井层夹住，其中上述的第二阻挡层的厚度大于上述的第一阻挡层的厚度， 第三阻挡层的厚度大于上述的第一阻挡层的厚度，上述的第二阻挡层的厚度小于或是等于上述的第三阻挡层的厚度。
在本发明的一实施例中，上述的第一N型氮化物半导体及上述的第二N型氮化物半导体的至少一者具有粗糙表面，用以增加上述的氮化物半导体元件的出光效果。
本发明提供一种氮化物半导体元件，其包括基板、缓冲层、第一N型氮化物半导体、氮化物半导体量子井发光结构、P型氮化物半导体、穿隧接面(Tunnel Junction)以及第二N型氮化物半导体。上述的基板具有相对的第一面及第二面。上述的缓冲层设置于上述的基板的上述的第一面上。上述的第一N型氮化物半导体设置于上述的缓冲层上。上述的氮化物半导体量子井发光结构设置于上述的第一N型氮化物半导体上。上述的P型氮化物半导体设置于上述的氮化物半导体量子井发光结构上。其中上述的P型氮化物半导体包括、P侧应力释放层、高浓度空穴层以及电子阻挡层。上述的穿隧接面(Tunnel Junction)设置于上述的氮化物半导体量子井发光结构上。上述的穿隧接面包括重掺杂P型(P+)氮化物半导体以及重掺杂N型(N+)氮化物半导体。上述的重掺杂P型(P+)氮化物半导体设置于上述的氮化物半导体量子井发光结构上。上述的重掺杂N型(N+)氮化物半导体设置于上述的重掺杂P型氮化物半导体上。上述的第二N型氮化物半导体设置于上述的穿隧接面的上述的重掺杂N型氮化物半导体上。其中上述的氮化物半导体量子井发光结构具有多个井层和多个阻挡层，上述的多个阻挡层包含配置于最接近上述的P型氮化物半导体位置的第一阻挡层、配置于最接近上述的第一N型氮化物半导体位置的第二阻挡层以及多个第三阻挡层，其中上述的多个第三阻挡层被上述的多个井层夹住，其中配置于最接近上述的第一阻挡层为上述的P侧应力释放层，配置于最远离上述的第一阻挡层为上述的电子阻挡层，上述的高浓度空穴层被上述的P侧应力释放层以及上述的电子阻挡层所夹住。
在本发明的一实施例中，上述的P侧应力释放层可为超晶格结构，其材料包含氮化铝镓(AlGaN)以及氮化镓(GaN)所构成的超晶格结构，或是由氮化铝镓(AlxGaN)以及氮化铝镓(AlyGaN)所构成的超晶格结构，或是由氮化铝镓(AlGaN)以及氮化铝铟镓(InAlGaN)所构成的超晶格结构，其中，x不等于y，上述的超晶格结构小于20对。
在本发明的一实施例中，上述的高浓度空穴层可由氮化镓(GaN)或是氮化铝镓(AlGaN)所构成，上述的高浓度空穴层的镁掺杂浓度(concentration)高于上述的P侧应力释放层的镁掺杂浓度以及上述的电子阻挡层的镁掺杂浓度。
在本发明的一实施例中，上述的高浓度空穴层的镁(Mg)掺杂浓度高于1x1019(Atoms/cm3)。
在本发明的一实施例中，上述的电子阻挡层可由氮化铝镓(AlGaN)所构成，上述的电子阻挡层的铝成份百分比高于上述的P侧应力释放层的铝成份百分比以及高于上述的高浓度空穴层的铝成份百分比。
在本发明的一实施例中，上述的穿隧接面还包括中间半导体，设置于上述的重掺杂P型(P+)氮化物半导体及上述的重掺杂N型(N+)氮化物半导体之间。
在本发明的一实施例中，上述的高浓度空穴层的镁(Mg)掺杂浓度高于1x1019(Atoms/cm3)，且上述的高浓度空穴层的铝成份百分比低于上述的电子阻挡层的铝成份百分比。
在本发明的一实施例中，上述的第二N型氮化物半导体及上述的重掺杂N型(N+)氮化物半导体不会吸收上述的氮化物半导体量子井发光结构所发出光线。
在本发明的一实施例中，上述的第二N型氮化物半导体及上述的重掺杂N型(N+)氮化物半导体的能隙大于上述的氮化物半导体量子井发光结构的能隙。
在本发明的一实施例中，上述的多个氮化物半导体元件是可电性串联而形成氮化物半导体高压元件。
在本发明的一实施例中，上述的氮化物半导体元件可以发出UV光线、蓝色光线或绿色光线。
在本发明的一实施例中，上述的氮化物半导体元件可以应用于灯丝(Filament)产品。
在本发明的一实施例中，上述的氮化物半导体元件可以应用于COB(Chip on Board)产品。
在本发明的一实施例中，上述的氮化物半导体元件可以应用于激光二极管(Laser Diode)产品。
在本发明的一实施例中，上述的氮化物半导体元件可以应用于发光二极管(Light Emitting Diode)产品。
本发明提供一种氮化物半导体元件，其包括基板、缓冲层、第一N型氮化物半导体、氮化物半导体量子井发光结构、P型氮化物半导体、穿隧接面(Tunnel Junction)以及第二N型氮化物半导体。上述的基板具有相对的第一面及第二面。上述的缓冲层设置于上述的基板的上述的第一面上。上述的第 一N型氮化物半导体，设置于上述的缓冲层上。其中上述的第一N型氮化物半导体包括N侧第一应力释放层、N侧第二应力释放层、低浓度电子层以及N型欧姆接触层。上述的氮化物半导体量子井发光结构设置于上述的第一N型氮化物半导体上。上述的P型氮化物半导体设置于上述的氮化物半导体量子井发光结构上。上述的穿隧接面(Tunnel Junction)设置于上述的氮化物半导体量子井发光结构上。上述的穿隧接面包括重掺杂P型(P+)氮化物半导体以及重掺杂N型(N+)氮化物半导体。上述的重掺杂P型(P+)氮化物半导体，设置于上述的氮化物半导体量子井发光结构上。上述的重掺杂N型(N+)氮化物半导体，设置于上述的重掺杂P型氮化物半导体上。上述的第二N型氮化物半导体，设置于上述的穿隧接面的上述的重掺杂N型氮化物半导体上。其中上述的氮化物半导体量子井发光结构具有多个井层和多个阻挡层，上述的多个阻挡层包含配置于最接近上述的P型氮化物半导体位置的第一阻挡层、配置于最接近上述的第一N型氮化物半导体位置的第二阻挡层以及多个第三阻挡层，其中上述的多个第三阻挡层被上述的多个井层夹住，其中配置于最接近上述的第二阻挡层为上述的N侧第一应力释放层，配置于最远离述上述的第二阻挡层为上述的N型欧姆接触层，上述的低浓度电子层以及上述的第二应力释放层依序堆迭于上述的N型欧姆接触层上方，上述的低浓度电子层被上述的N型欧姆接触层及上述的N侧第二应力释放层所夹住。
在本发明的一实施例中，上述的N侧第一应力释放层可为超晶格结构，其材料包含氮化铟镓(InGaN)以及氮化镓(GaN)所构成的超晶格结构，或是由氮化铟镓(InxGaN)以及氮化铟镓(InyGaN)所构成的超晶格结构，其中x不等于y，上述的超晶格结构小于20对。
在本发明的一实施例中，上述的N侧第二应力释放层可为超晶格结构，其材料包含氮化铟镓(InGaN)以及氮化镓(GaN)所构成的超晶格结构，或是由氮化铟镓(InxGaN))以及氮化铟镓(InyGaN)所构成的超晶格结构，其中x不等于y，上述的超晶格结构小于20对。
在本发明的一实施例中，上述的N侧第一应力释放层的铟成份百分比高于上述的N侧第二应力释放层的铟成份百分比。
在本发明的一实施例中，上述的低浓度电子层可由氮化镓(GaN)、氮化铟镓(InGaN)、氮化铝镓(AlGaN)或氮化铟铝镓(InAlGaN)所构成，上述的低浓度电子层的硅掺杂浓度低于上述的N型欧姆接触层的硅掺杂浓度。
在本发明的一实施例中，上述的低浓度电子层的硅掺杂浓度低于1x1018(Atoms/cm3)。
在本发明的一实施例中，上述的N型欧姆接触层可由氮化镓(GaN)、氮化铟镓(InGaN)、氮化铝镓(AlGaN)或氮化铟铝镓(InAlGaN)所构成，上述的N型欧姆接触层的硅掺杂浓度高于上述的N侧第一应力释放层的硅掺杂浓度、上述的N侧第二应力释放层的硅掺杂浓度及上述的低浓度电子层的硅掺杂浓度。
在本发明的一实施例中，上述的第二N型氮化物半导体及上述的重掺杂N型(N+)氮化物半导体不会吸收上述的氮化物半导体量子井发光结构所发出光线。
在本发明的一实施例中，上述的第二N型氮化物半导体及上述的重掺杂N型(N+)氮化物半导体的能隙大于上述的氮化物半导体量子井发光结构的能隙。
在本发明的一实施例中，上述的多个氮化物半导体元件是可电性串联而形成氮化物半导体高压元件。
在本发明的一实施例中，上述的氮化物半导体元件可以发出UV光线、蓝色光线或绿色光线。
在本发明的一实施例中，上述的氮化物半导体元件可以应用于灯丝(Filament)产品。
在本发明的一实施例中，上述的氮化物半导体元件可以应用于COB(Chip on Board)产品。
在本发明的一实施例中，上述的氮化物半导体元件可以应用于激光二极管(Laser Diode)产品。
在本发明的一实施例中，上述的氮化物半导体元件可以应用于发光二极管(Light Emitting Diode)产品。
在本发明的一实施例中，基于穿隧接面(Tunnel Junction)的结构，可以省略之后电流阻挡层(Current Blocking Layer,CBL)及透明导电层(Transparent Conductive Layer,TCL)的结构及制程，一样可以达到电流均匀分布以及发光效率提升的效果。
基于上述，本发明的氮化物半导体元件，其可以提升发光效率及改善制程良率。本发明的氮化物半导体元件的制造方法可用以制作上述的氮化物半导体元件。本发明的封装结构可应用于上述的氮化物半导体元件。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
附图说明
图1是依照本发明的第一实施例的一种氮化物半导体元件的剖面示意 图。
图2是依照本发明的第二实施例的一种氮化物半导体元件的剖面示意图。
图3是依照本发明的第三实施例的一种氮化物半导体元件的剖面示意图。
图4是依照本发明的第四实施例的一种氮化物半导体元件的剖面示意图。
图5是依照本发明的第五实施例的一种氮化物半导体元件的剖面示意图。
图6是依照本发明的第六实施例的一种氮化物半导体元件的剖面示意图。
图7是依照本发明的第七实施例的一种氮化物半导体高压元件的剖面示意图。
图8是依照本发明的第八实施例的一种氮化物半导体高压元件的剖面示意图。
图9是依照本发明的第九实施例的一种氮化物半导体高压元件的剖面示意图。
图10是依照本发明的第十实施例的一种氮化物半导体高压元件的剖面示意图。
图11是依照本发明的第十一实施例的一种氮化物半导体元件的封装结构的剖面示意图。
图12是依照本发明的第十二实施例的一种氮化物半导体元件的封装结构的剖面示意图。
图13是依照本发明的第十三实施例的一种氮化物半导体元件的封装结构的剖面示意图。
图14是依照本发明的一种氮化物半导体元件的制造流程图。
附图标记说明：
100、200、300、400、500、600、1100a、1200a、1300a：氮化物半导体元件
700、800、900、1000：氮化物半导体高压元件
1100、1200、1300：封装结构
700a、800a、900a、1000a：第一氮化物半导体元件
700b、800b、900b、1000b：第二氮化物半导体元件
101：P型氮化物半导体
101A：P侧应力释放层
101B：高浓度空穴层
101C：电子阻挡层
101D：P型欧姆接触层
102：N型氮化物半导体
102A：N侧第一应力释放层
102B：N侧第二应力释放层
102C：低浓度电子层
102D：N型欧姆接触层
103：氮化物半导体量子井发光结构
103A：井层
103B：阻挡层
103B1：第一阻挡层
103B2：第二阻挡层
103B3：第三阻挡层
104、804a、804b：基板
104A：第一面
104A1：成长表面
104A2：微结构
104B：第二面
104C：周期性突出结构
104D：高度
104E：宽度
104F：底面间距
105：缓冲层
105A：第一缓冲层
105B：第二缓冲层
106：平台结构
107：N型电极
108：电流阻挡层
109：透明导电层
110：P型电极
111：绝缘层
112、212、312：高反射绝缘层
112A：第一介电对
112B：第二介电对
112C：第一材料层
112D：第二材料层
221：第一焊接金属层
222：第二焊接金属层
223：接合基板
224：基板电极
225：P型高反射欧姆电极
319、1119：电路板
321：第一焊垫层
322：第二焊垫层
323：第一连接电极
324：第二连接电极
470：穿隧接面
450：第二N型氮化物半导体
451：重掺杂N型氮化物半导体
452：第二N型氮化物半导体
401D：重掺杂P型氮化物半导体
760：金属连结
1120A、1120B：焊垫
1113：支架
1114A、1114B：导电引脚
1115：树脂
1116：导电材料
1117：透明胶
1118：萤光粉
S1、S2：步骤
具体实施方式
图1是依照本发明的第一实施例的一种氮化物半导体元件的剖面示意图。本实施例的氮化物半导体元件100包括P型氮化物半导体101、N型氮化物半 导体102、氮化物半导体量子井发光结构103、基板104以及缓冲层105。氮化物半导体量子井发光结构103位于P型氮化物半导体101以及N型氮化物半导体102之间。基板104具有相对的第一面104A以及第二面104B。缓冲层105位于N型氮化物半导体102以及基板104的第一面104A之间。氮化物半导体量子井发光结构103具有多个井层103A以及多个阻挡层103B。多个阻挡层103B包括一个配置于最接近P型氮化物半导体101位置的第一阻挡层103B1、一个配置于最接近N型氮化物半导体102位置的第二阻挡层103B2以及至少一个第三阻挡层103B3。在图1所绘示的实施例中，第三阻挡层103B3的数量是以一个为例，但本发明对于第三阻挡层103B3的数量并不加以限制。第三阻挡层103B3的相对两端分别被对应的两个井层103A夹住。换言之，多个井层103A以及各个多个阻挡层103B彼此交错配置。第一阻挡层103B1的厚度小于100埃
Figure PCTCN2017098626-appb-000008
。具体而言，本实施例的氮化物半导体元件100可以为具有水平(horizontal)结构的发光二极管元件(light emission diode；LED)。
在一些实施例中，第二阻挡层103B2的厚度可以大于第一阻挡层103B1的厚度，但本发明不限于此。
在一些实施例中，第三阻挡层103B3的厚度可以大于第一阻挡层103B1的厚度，但本发明不限于此。
在一些实施例中，第一阻挡层103B1的厚度可以小于50埃
Figure PCTCN2017098626-appb-000009
，但本发明不限于此。
在本实施例中，对于氮化物半导体元件100的氮化物半导体(例如可以包括：P型氮化物半导体101、N型氮化物半导体102及/或氮化物半导体量子井发光结构103)而言，前述得氮化物半导体可以包括氮化镓(GaN)、氮化铝(AlN)、氮化铟(InN)或为上述混晶的氮化镓是化合物半导体(InxAlyGa1-x-yN，0≦x，0≦y，x+y≦1)。除此之外，亦可以在对上述的氮化物半导体进行IIIA族元素(例如：硼(B))或VA族元素(例如：磷(P)、砷(As))掺杂，以将一部分的氮置换，而形成氮化镓是化合物的混晶(mixed crystal)。
在本实施例中氮化物半导体量子井发光结构103可以具有多重量子井(multiple quantum well；MQW)构造或单一量子井(single quantum well；SQW)构造，于本发明不加以限制。在一些实施例中，可以是形成多重量子井构造，以可提升输出或降低振荡临界值。除此之外，可以将多个井层103A以及多个阻挡层103B交错层迭交错配置，以形成具有层迭结构(stacked structure)的量子井构造。此外，就前述的层迭构造而言，可以是将阻挡层103B夹入对应的两个井层103A中，以形成层迭构造。
在单一量子井构造中，可以是在P型氮化物半导体101层的一侧与N型氮化物半导体102层的一侧分别具有至少一层阻挡层103B，以夹住井层103A。
在多重量子井构造中，可以具有多个多个井层103A以及多个阻挡层103B，且多个井层103A以及多个阻挡层103B交错层迭交错配置，以夹住各个井层103A。
在其他实施例中，量子井构造也可以具有其他的形态，于本发明不加以限制。
在一些实施例中，前述的多重量子井构造可以是在P型氮化物半导体101层的一侧具有至少一层阻挡层103B(即，第一阻挡层103B1)，N型氮化物半导体102层的一侧分别具有至少一层阻挡层103B(即，第二阻挡层103B2)，且第一阻挡层103B1以及第二阻挡层103B2之间具有至少一个阻挡层103B(即，第三阻挡层103B3)，以夹住多个井层103A。第一阻挡层103B1、第二阻挡层103B2以及第三阻挡层103B3分别为不同的膜层。换言之，氮化物半导体量子井发光结构103的相对的最外两侧可以分别为第一阻挡层103B1以及第二阻挡层103B2。
除此之外，在多重量子井构造中，被不同的井层103A所夹入的阻挡层103B并不限于是一层(例如：第一井层103A/阻挡层103B/第二井层103A)。在一些实施例中，也可以于不同的井层103A之间，将两层或两层以上的多个阻挡层103B夹入(例如：第一井层103A/第一阻挡层103B1/第二阻挡层103B2/第二井层103A)，且前述多个阻挡层103B之间的成分或杂质掺杂量可以彼此不同。
在本实施例中，井层103A可以是含有铟的氮化物半导体层。举例而言，井层103A的成分可以为InαGa1-αN(0<α≦1)或InAlGaN。如此一来，可以形成具有良好发光或振荡的井层103A。另外，井层103A中铟的混晶比也可以使氮化物半导体量子井发光结构103具有对应的发光波长。在一些实施例中，井层103A的成分也可以为不含铟的氮化物半导体，例如：AlGaN、GaN等，于本发明不限于此。
本发明对于井层103A的膜厚及数量并不加以限制。在一些实施例中，井层103A的膜厚可以是10埃以上以及300埃以下的范围。一般而言，井层103A的膜厚于20埃以上以及200埃以下的范围内，可以降低氮化物半导体元件100的正向电压(Forward Voltage；Vf)及/或临界电流(Critical Current)的密度。
就制程而言，于长晶(crystal growth)的过程中，井层103A的膜厚于20埃以上可以提升膜层的均匀度(uniformity)，且井层103A的膜厚于200埃以 下可以降低晶格缺陷(crystal defect)。并且，井层103A的数量可以是1以上。一般而言，若井层103A的数量为4以上时，则会对应的使氮化物半导体量子井发光结构103的各层的膜厚变厚，而进一步增加氮化物半导体量子井发光结构103的整体厚度，因而导致正向电压上升。在一些实施例中，可以使井层103A的膜厚为100埃以下的范围，因而可以进一步降低氮化物半导体量子井发光结构103的整体厚度。
于本发明中对于井层103A的掺杂并不加以限制。一般而言，若井层103A为含有铟的氮化物半导体，则若N型杂质的掺杂浓度增加，则可能会降低井层103A的有结晶性(crystallinity)。因此，可以降低井层103A的N型杂质的掺杂浓度，以提升井层103A的结晶性，而可以进一步提升氮化物半导体元件100的品质。
举例而言，在一般的半导体制程中，若N型杂质的掺杂浓度为5×1016atoms/cm3以下，则可以视为不具有N型杂质。除此之外，若N型杂质的掺杂浓度是在1×1018atoms/cm3以下以及5×1016atoms/cm3以上的范围内，则可具有良好的结晶性且可以提升载子浓度(carrier concentration)，而可降低氮化物半导体元件100的正向电压及/或临界电流的密度。
在一些实施例中，井层103A的N型杂质的掺杂浓度可以实质上小于或等于阻挡层103B的N型杂质的掺杂浓度。就制程上而言，相较于形成阻挡层103B的步骤，可以于形成井层103A的步骤中，掺入较少的N型杂质。或是，在形成阻挡层103B的步骤中掺入N型杂质，而在形成井层103A的步骤中不掺入N型杂质。如此一来，可以提升井层103A的发光再结合(radiative recombination)，而可进一步提升氮化物半导体元件100的发光效率。
一般而言，上述的杂质方式的发光元件可以降低其正向电压及/或临界电流的密度而具有良好的品质。此时，也可以使井层103A、阻挡层103B以无掺杂生长而构成氮化物半导体量子井发光结构103的一部分。
在一些实施例中，井层103A可以实质上不含N型杂质，而可以促进在井层103A内的载子再结合(recombination)，以提升井层103A的发光再结合，而可进一步提升氮化物半导体元件100的发光效率。换言之，若井层103A具有N型杂质，则由于井层103A的载子浓度较高，所以可能降低井层103A的发光再结合的几率，而使得在一定输出下产生驱动电流(driving circuit)上升，而可能降低氮化物半导体元件100的可靠性(reliability)或元件寿命(life time)。因此，上述的杂质方式可以使井层103A的N型杂质浓度为1×1018atoms/cm3以下，而可得到可高输出且稳定驱动的氮化物半导体元件 100。一般而言，井层103A的N型杂质浓度可以是无掺杂或成为实质上不含N型杂质。
在氮化物半导体元件100作为激光元件的使用方式之下，若井层103A具有N型杂质则可能会使激光光的峰值波长的光谱宽度变宽，或使因为井层103A内的结晶性降低而降低激光元件的元件寿命。因此，上述的杂质方式可以使井层103A的N型杂质浓度为1×1017atoms/cm3以提升氮化物半导体元件100的可靠性(reliability)或元件寿命(life time)。
在本实施例中，相较于井层103A的铟混晶比，可以使阻挡层103B为具有较低铟混晶含铟氮化物半导体，但本发明不限于此。在一些实施例中，阻挡层103B也可以为含有氮化镓、铝的氮化物的半导体等。举例而言，阻挡层103B的材质可以为InβAlγGa1-γN(0≦β≦1，0≦γ≦1)、InβGa1-βN(0≦β<1，α>β)、GaN或AlγGa 1-γN(0<γ≦1)。
值得注意的是，在作为最底层的阻挡层103B(如：下部阻挡层103B或第二阻挡层103B2)时，一般而言可以使用不含铝的氮化物半导体。举例而言，最底层的阻挡层103B(如：下部阻挡层103B或第二阻挡层103B2)的材质可以为InβGa1-βN(0≦β<1，α>β)或GaN。如此一来，可以避免后续形成于其上且含有In氮化物的井层103A直接形成于含有铝的氮化物半导体(如：InβAlγGa1-γN或AlγGa 1-γN)上，而降低井层103A的结晶性。除此之外，可以使阻挡层103B的带隙大于井层103A的带隙，而可适宜地调整阻挡层103B及/或井层103A的组成成分。
另外，除了上部阻挡层103B(即，较接近P型氮化物半导体101的阻挡层103B，例如为第一阻挡层103B1)之外，本发明对于其余的阻挡层103B(如：第二阻挡层103B2及/或第三阻挡层103B3)的N型杂质的掺杂浓度并不加以限制。一般而言，具有N型杂质的阻挡层103B其N型杂质的掺杂浓度可以为5×1016atoms/cm3至1×1020atoms/cm3。
在用于一般发光二极管的氮化物半导体元件100中，前述的N型杂质的掺杂浓度可以为5×1016atoms/cm3至2×1018atoms/cm3。并且，在用于高输出发光二极管的氮化物半导体元件100中，前述的N型杂质的掺杂浓度可以为5×1017atoms/cm3至1×1020atoms/cm3，且可以进一步为1×1018atoms/cm3至5×1019atoms/cm3。
在阻挡层103B具有高浓度的N型杂质掺杂浓度时，可以使井层103A实质上为不具有N型杂质的掺杂。在用于不同的发光二极管的氮化物半导体元件100中，可以为了要提升驱动电流而得到高的输出，而使的N型杂质的掺 杂浓度增加，以进一步提升载子浓度。因此，在用于前述的一般发光二极管的氮化物半导体元件100中，可以在部分的第二阻挡层103B2及/或第三阻挡层103B3中掺杂入N型杂质，或是不掺杂入N型杂质，于本发明不加以限制。
在本实施例中，阻挡层103B的膜厚可以小于或等于500埃，但本发明不限于此。在一些实施例中，阻挡层103B的膜厚与井层103A的膜厚可以基本上相同，也就是阻挡层103B的膜厚可以为10埃至300埃的范围。
在一些实施例中，阻挡层103B也可以具有P型掺杂。就具有P型掺杂的阻挡层103B而言，其P型杂质的掺杂浓度可以为为5×1016atoms/cm3至1×1020atoms/cm3。在一些实施例中，前述的P型杂质的掺杂浓度可以为5×1016atoms/cm3至1×1018atoms/cm3。若前述的P型杂质的掺杂浓度超过1×1020atoms/cm3，则即使增加p型杂质的掺杂浓度，载子浓度也几乎不会变化，反而会因为过量的杂质而造成的结晶性恶化，而导致光的散射作用增加，而进一步降低氮化物半导体量子井发光结构103的发光效率。并且，若前述的P型杂质的掺杂浓度低于1×1018atoms/cm3，则可抑制前述因为杂质增加所造成的发光效率降低的因素，并可以使氮化物半导体量子井发光结构103内的载子浓度稳定。此外，就P型杂质的掺杂量而言，一般而言至少会具有些微的P型杂质掺杂量。
在本实施例中，P型氮化物半导体101位置的阻挡层103B(即，第一阻挡层103B1)可以无掺杂N型杂质、实质上无掺杂(即，杂质浓度小于5×1016atoms/cm3)N型杂质或掺杂P型杂质，且第一阻挡层103B1的厚度小于100埃。如此一来，可以提升来自于P型氮化物半导体101的载子注入效率(injection efficiency)，而可进一步提升氮化物半导体元件100的发光效率。
在一些实施例中，P型氮化物半导体101可以包括P侧应力释放层101A、高浓度空穴层101B、电子阻挡层101C以及P型欧姆接触层101D，且自第一阻挡层103B1向远离于第一阻挡层103B1的方向上依序为P侧应力释放层101A、高浓度空穴层101B、电子阻挡层101C以及P型欧姆接触层101D。
P侧应力释放层101A可以为超晶格(super lattice)结构。超晶格结构的材料可以包含氮化铝镓(AlGaN)以及氮化镓(GaN)所构成的超晶格结构，或是由氮化铝镓(AlxGaN)以及氮化铝镓(AlyGaN)所构成的超晶格结构，或是由氮化铝镓(AlGaN)以及氮化铝铟镓(InAlGaN)所构成的超晶格结构，于本发明不加以限制。除此之外，前述的超晶格结构的对数可以小于20对，但本发明不限于此。在一些实施例中，前述的超晶格结构的对数也可以小于10对。
高浓度空穴层101B可以由氮化镓(GaN)或是氮化铝镓(AlGaN)所构成，高浓度空穴层101B的镁掺杂浓度(concentration)高于P侧应力释放层101A的镁掺杂浓度以及电子阻挡层101C的镁掺杂浓度。举例而言，高浓度空穴层101B的镁(Mg)掺杂浓度可以高于1x1019(Atoms/cm3)。
电子阻挡层101C可以由氮化铝镓(AlGaN)所构成，电子阻挡层101C的铝成份百分比高于P侧应力释放层101A的铝成份百分比以及高于高浓度空穴层101B的铝成份百分比。在一些实施例中，高浓度空穴层101B的铝成份百分比低于电子阻挡层101C的铝成份百分比，但本发明不限于此。
P型欧姆接触层101D可以由氮化镓(GaN)所构成，P型欧姆接触层101D的镁掺杂浓度高于电子阻挡层101C的镁掺杂浓度。
在一些实施例中，N型氮化物半导体102可以包括N侧第一应力释放层102A、N侧第二应力释放层102B、低浓度电子层102C以及N型欧姆接触层102D。且自第二阻挡层103B2向远离于第二阻挡层103B2的方向上依序为N侧第一应力释放层102A、N侧第二应力释放层102B、低浓度电子层102C以及N型欧姆接触层102D。
N侧第一应力释放层102A及/或N侧第二应力释放层102B可以为超晶格结构可以为超晶格(super lattice)结构。超晶格结构的材料可以包含氮化铝镓(AlGaN)以及氮化镓(GaN)所构成的超晶格结构，或是由氮化铝镓(AlxGaN)以及氮化铝镓(AlyGaN)所构成的超晶格结构，或是由氮化铝镓(AlGaN)以及氮化铝铟镓(InAlGaN)所构成的超晶格结构，于本发明不加以限制。除此之外，前述的超晶格结构的对数可以小于20对，但本发明不限于此。在一些实施例中，前述的超晶格结构的对数也可以小于10对。
N侧第一应力释放层102A的铟(Indium)成份百分比高于N侧第二应力释放层102B的铟成份百分比。
低浓度电子层102C可以由氮化镓(GaN)、氮化铟镓(InGaN)或是氮化铝镓(AlGaN)所构成。在一些实施例中，低浓度电子层102C的硅掺杂浓度低于N型欧姆接触层102D的硅掺杂浓度，但本发明不限于此。举例而言，低浓度电子层102C的硅(Si)掺杂浓度可以低于1x1018(Atoms/cm3)。
N型欧姆接触层102D可以由氮化镓(GaN)、氮化铟镓(InGaN)或是氮化铝镓(AlGaN)所构成。在一些实施例中，N型欧姆接触层102D的硅掺杂浓度高于N侧第一应力释放层102A、N侧第二应力释放层102B以及低浓度电子层102C，但本发明不限于此。
基板104的材质可以包含III-V族(例如：GaN)、IV族(例如：Si)、II-VI 族(例如：CdS、CdTe、ZnS)的元素与合金、氧化锌(ZnO)、尖晶石(spinel)、氮化镓(GaN)、蓝宝石(sapphire)或硅(Si)。
基板104的第一面104A包括成长表面104A1以及多个位于该成长表面104A1上的微结构104A2。在一些实施例中，微结构104A2具有非圆滑的蚀刻侧面。举例而言，成长表面104A1的表面粗糙度可以低于10埃
Figure PCTCN2017098626-appb-000010
，或是微结构104A2的表面粗糙度低于10埃
Figure PCTCN2017098626-appb-000011
。在一些实施例中，基板104的第二面104B的粗糙度大于成长表面104A1的粗糙度以及微结构104A2的表面粗糙度。
在一些实施例中，微结构104A2可以为周期性的突出结构，且前数周期性的突出结构可以具有对应的高度104D、宽度104E以及底面间距104F。高度104D可以介于1微米至3微米之间。宽度104E介于1微米至3微米之间。底面间距104F介于0.1微米至3微米之间。
举例而言，微结构104A2的外型可以为半球体(hemisphere)、锥体(cone)、截头锥体(truncated-cone)、金字塔(pyramid)、截头金字塔(truncated-pyramid)、方柱(square pillar)、圆桶(cylinder)或其他适宜的周期性突出结构104C，于本发明不加以限制。
在一些实施例中，缓冲层105可以包括第一缓冲层105A以及第二缓冲层105B。第一缓冲层105A可以与微结构104A2共形设置(conformal)。第二缓冲层105B位于第一缓冲层105A上，且第二缓冲层105B相对于第一缓冲层105A的一面可以为一平坦面，以使后续形成的膜层(如：N型欧姆接触层102D)可以位于第二缓冲层105B的平坦面上。
在本实施例中，氮化物半导体元件100可以还包括平台结构106、N型电极107、电流阻挡层108、透明导电层109、P型电极110、绝缘层111以及高反射绝缘层112。平台结构106露出部分的N型欧姆接触层102D。N型电极107与N型欧姆接触层102D电性连接。电流阻挡层108与P型欧姆接触层101D直接接触。透明导电层109覆盖电流阻挡层108且与P型欧姆接触层101D直接接触。P型电极110位于透明导电层109的上方，并通过透明导电层109以与P型欧姆接触层101D电性连接。绝缘层111覆盖N型电极107、P型电极110以及平台结构106的侧壁。高反射绝缘层112位于基板104的第二面104B。
在一些实施例中，高反射绝缘层112可以由多个介电材料对(pair)所组成。前述的多个介电材料对可以包括多个第一介电对112A以及多个第二介电对112B。第一介电对112A及/或第二介电对112B可以包括第一材料层112C以及第二材料层112D，其中第一材料层112C的介电系数大于第二材料层112D 的介电系数。
在一些实施例中，第一材料层112C及/或第二材料层112D的光学厚度小于四分之一的波长(波长/4)，且前述的波长基本上为氮化物半导体量子井发光结构103所发出的光的波长。
在一些实施例中，高反射绝缘层112的材料可以包括氧化物、氮化物、及/或至少包含硅(Si)、钛(Ti)、锆(Zr)、铌(Nb)、钽(Ta)或铝(Al)元素所组成的氧化物或氮化物，于本发明不限于此。
在一些实施例中，透明导电层109的材料可以包括铟锡氧化物(Indium Tin Oxide；ITO)、铟锌氧化物(indium zinc oxide；IZO)、氧化锌(Zinc Oxide；ZnO)或氧化锌铝(Aluminum Zinc Oxide；AZO)，于本发明不限于此。
在一些实施例中，绝缘层111的材料可以包括氧化硅(SiOX)、氮化硅(SiNX)、聚酰亚胺(Polyimide)、或其他高分子材料，于本发明不限于此。
在一些实施例中，N型电极107及/或P型电极110的材料可以包括银(Ag)、铝(Al)、镍(Ni)、铑(Rh)、金(Au)、铜(Cu)、钛(Ti)、铂(Pt)、钯(Pd)、钼(Mo)、铬(Cr)、钨(W)、其他适宜的金属及/或上述金属的合金，于本发明不限于此。
图2是依照本发明的第二实施例的一种氮化物半导体元件200的剖面示意图。第二实施例的氮化物半导体元件200与图1的氮化物半导体元件100类似，本实施例采用图2针对氮化物半导体元件200进行描述。值得注意的是，在图2中，相同或相似的标号表示相同或相似的构件，故针对图1中说明过的构件于此不再赘述。
请参照图2，第二实施例的氮化物半导体元件200与图1的氮化物半导体元件100类似，两者的差异在于：本实施例的氮化物半导体元件200还包括P型高反射欧姆电极225、第一焊接金属层221、第二焊接金属层222、接合基板223以及基板电极224。在本实施例中，高反射绝缘层212的组成可以类似于前述实施例(如：第一实施例)的高反射绝缘层112。P型高反射欧姆电极225覆盖于高反射绝缘层212以及P型氮化物半导体101上，并且与P型氮化物半导体101电性连接。第一焊接金属层221覆盖于P型高反射欧姆电极225上，并且与P型氮化物半导体101电性连接。第二焊接金属层222覆盖于第一焊接金属层221上，并且与P型氮化物半导体101电性连接。接合基板223覆盖于第二焊接金属层222上，并且与P型氮化物半导体101电性连接。基板电极224覆盖于接合基板223上，并且与P型氮化物半导体101电性连接。具体而言，本实施例的氮化物半导体元件100可以为具有垂直(vertical)结 构的发光二极管元件。
在一些实施例中，P型高反射欧姆电极225以及基板电极224的材料可以类似于N型电极107及/或前述实施例的P型电极110的材料，于本发明不限于此。
在一些实施例中，第一焊接金属层221及/或第二焊接金属层222的材料可以包括银(Ag)、铝(Al)、镍(Ni)、铑(Rh)、金(Au)、铜(Cu)、钛(Ti)、铂(Pt)、钯(Pd)、钼(Mo)、铬(Cr)、钨(W)、锡(Sn)其他适宜的金属及/或上述金属的合金，于本发明不限于此。
图3是依照本发明的第三实施例的一种氮化物半导体元件300的剖面示意图。第三实施例的氮化物半导体元件300与图1的氮化物半导体元件100类似，本实施例采用图3针对氮化物半导体元件300进行描述。值得注意的是，在图3中，相同或相似的标号表示相同或相似的构件，故针对图1中说明过的构件于此不再赘述。
请参照图3，第三实施例的氮化物半导体元件300与图1的氮化物半导体元件100类似，两者的差异在于：本实施例的氮化物半导体元件100还包括第一焊垫层321、第二焊垫层322、第一连接电极323以及第二连接电极324。在本实施例中，高反射绝缘层312的组成可以类似于前述实施例(如：第一实施例)的高反射绝缘层112。第一焊垫层321与N型电极107电性连接。第二焊垫层322与P型电极110电性连接。第一连接电极323与第一焊垫层321电性连接。第二连接电极324与第二焊垫层322电性连接。具体而言，本实施例的氮化物半导体元件300可以为具有覆晶(flip chip)结构的发光二极管元件。
在一些实施例中，第一连接电极323以及第二连接电极324可以分别电性连接至电路板319上的不同端点。
图4是依照本发明的第四实施例的一种氮化物半导体元件400的剖面示意图。第四实施例的氮化物半导体元件400与图1的氮化物半导体元件100类似，本实施例采用图4针对氮化物半导体元件400进行描述。值得注意的是，在图4中，相同或相似的标号表示相同或相似的构件，故针对图1中说明过的构件于此不再赘述。
请参照图4，第四实施例的氮化物半导体元件400与图1的氮化物半导体元件100类似，两者的差异在于：本实施例的氮化物半导体元件400还包括穿隧接面(Tunnel Junction)470以及第二N型氮化物半导体452。穿隧接面470包括重掺杂P型(P+)氮化物半导体401D以及重掺杂N型(N+)氮化物半导 体451，或是由重掺杂P型(P+)氮化物半导体401D以及重掺杂N型(N+)氮化物半导体451所形成的接面。重掺杂P型氮化物半导体401D设置于氮化物半导体量子井发光结构103上。重掺杂N型氮化物半导体451设置于重掺杂P型氮化物半导体401D上。第二N型氮化物半导体452设置于穿隧接面470的重掺杂N型氮化物半导体451上。
在一些实施例中，重掺杂N型氮化物半导体451的能隙(Energy Bandgap)大于氮化物半导体量子井发光结构103的能隙。如此一来，重掺杂N型氮化物半导体451基本上可以不吸收氮化物半导体量子井发光结构103所发出光线。
在一些实施例中，重掺杂P型氮化物半导体层401D的成分或形成方式可以类似于P型欧姆接触层101D。也就是说，重掺杂P型氮化物半导体层401D可以与P侧应力释放层101A、高浓度空穴层101B以及电子阻挡层101C构成P型氮化物半导体101。
在一些实施例中，重掺杂P型氮化物半导体层401D的能隙(Energy Bandgap)可以是越靠近P型氮化物半导体101越高，且重掺杂P型氮化物半导体层401D的厚度可以介于1纳米(namometer；nm)至100nm之间，但本发明不限于此。
在一些实施例中，重掺杂N型氮化物半导体451的能隙可以是越靠近N型氮化物半导体102越高，且重掺杂N型氮化物半导体451的厚度可以介于1纳米nm至100nm之间，但本发明不限于此。
在一些实施例中，第一N型氮化物半导体102及/或第二N型氮化物半导体452可以具有粗糙表面，以提升氮化物半导体元件400的出光效果。
在一些实施例中，穿隧接面470可以还包括设置于重掺杂P型氮化物半导体401D以及重掺杂N型氮化物半导体451之间的中间半导体(未绘示)。中间半导体可以具有内部带穿隧阻挡层(inter band tunnel barrier)，重掺杂P型氮化物半导体401D可以具有P型空乏阻挡层(P-depletion barrier)，重掺杂N型氮化物半导体451可以具有N型空乏阻挡层(N-depletion barrier)。如此一来，中间半导体相对于重掺杂P型氮化物半导体401D以及重掺杂N型氮化物半导体451形成异质接面(heterojunction)，以于重掺杂P型氮化物半导体401D以及重掺杂N型氮化物半导体451之间形成极化场(polarization field)，而使重掺杂P型氮化物半导体401D的价带以及该重掺杂N型氮化物半导体451的导带可以彼此相互对应。
在一些实施例中，中间半导体的材料可以包含氮化铝镓(AlGaN)、氮化镓 (GaN)、氮化铟镓(InGaN)或氮化铟铝镓(InAlGaN)。并且，中间半导体的厚度约为0.5nm～10nm，但本发明不限于此。
在一些实施例中，中间半导体具有一侧面材料能隙波动(lateral material energy bandgap fluctuation)，其包含多个低能隙及高能隙区域(low bandgap and high bandgap regions)。
在一些实施例中，若氮化物半导体元件400具有穿隧接面470的结构，则可以省略之后电流阻挡层(Current Blocking Layer,CBL)及透明导电层(Transparent Conductive Layer,TCL)的结构及制程，一样可以达到电流均匀分布以及发光效率提升的效果。
图5是依照本发明的第五实施例的一种氮化物半导体元件500的剖面示意图。第五实施例的氮化物半导体元件500与图2的氮化物半导体元件200类似，本实施例采用图5针对氮化物半导体元件500进行描述。值得注意的是，在图5中，相同或相似的标号表示相同或相似的构件，故针对图2中说明过的构件于此不再赘述。
请参照图5，第五实施例的氮化物半导体元件500与图2的氮化物半导体元件200类似，两者的差异在于：本实施例的氮化物半导体元件500还包括穿隧接面470以及第二N型氮化物半导体452。
在本实施例中，穿隧接面470以及第二N型氮化物半导体452可以类似前述实施例(如：第四实施例)的穿隧接面470以及第二N型氮化物半导体452，故于此不加以赘述。
图6是依照本发明的第六实施例的一种氮化物半导体元件600的剖面示意图。第六实施例的氮化物半导体元件600与图3的氮化物半导体元件300类似，本实施例采用图6针对氮化物半导体元件600进行描述。值得注意的是，在图6中，相同或相似的标号表示相同或相似的构件，故针对图3中说明过的构件于此不再赘述。
请参照图6，第六实施例的氮化物半导体元件600与图3的氮化物半导体元件300类似，两者的差异在于：本实施例的氮化物半导体元件600还包括穿隧接面470以及第二N型氮化物半导体452。
在本实施例中，穿隧接面470以及第二N型氮化物半导体452可以类似前述实施例(如：第四实施例)的穿隧接面470以及第二N型氮化物半导体452，故于此不加以赘述。
图7是依照本发明的第七实施例的一种氮化物半导体高压元件的剖面示意图。第七实施例的氮化物半导体高压元件700与图4的氮化物半导体元件 400类似，本实施例采用图7针对氮化物半导体高压元件700进行描述。值得注意的是，在图7中，相同或相似的标号表示相同或相似的构件，故针对图4中说明过的构件于此不再赘述。
请参照图7，第七实施例的氮化物半导体高压元件700与图4的氮化物半导体元件400类似，两者的差异在于：本实施例的氮化物半导体高压元件可以是多个如图4的氮化物半导体元件400彼此串接而构成的氮化物半导体高压元件700。
举例而言，在本实施例中，第一氮化物半导体元件700a及/或第二氮化物半导体元件700b可以类似于图4的氮化物半导体元件400，且第一氮化物半导体元件700a的N型氮化物半导体102可以通过N型电极107、金属连结760以及P型电极110以与第二氮化物半导体元件700b的P型氮化物半导体101电性连接。
在本实施例中，第一氮化物半导体元件700a的基板104与第二氮化物半导体元件700b的基板104彼此相连。也就是说，第一氮化物半导体元件700a以及第二氮化物半导体元件700b可以具有共同的基板104，但本发明不限于此。
图8是依照本发明的第八实施例的一种氮化物半导体高压元件的剖面示意图。第八实施例的氮化物半导体高压元件800与图7的氮化物半导体元件700类似，本实施例采用图8针对氮化物半导体高压元件800进行描述。值得注意的是，在图8中，相同或相似的标号表示相同或相似的构件，故针对图7中说明过的构件于此不再赘述。
请参照图8，第八实施例的氮化物半导体高压元件800与图7的氮化物半导体元件700类似，两者的差异在于：本实施例的氮化物半导体高压元件其第一氮化物半导体元件800a的基板804a与第二氮化物半导体元件800b的基板804b彼此分离。
图9是依照本发明的第九实施例的一种氮化物半导体高压元件的剖面示意图。第九实施例的氮化物半导体高压元件900与图5的氮化物半导体元件500类似，本实施例采用图9针对氮化物半导体高压元件900进行描述。值得注意的是，在图9中，相同或相似的标号表示相同或相似的构件，故针对图5中说明过的构件于此不再赘述。
请参照图9，第九实施例的氮化物半导体高压元件900与图5的氮化物半导体元件500类似，两者的差异在于：本实施例的氮化物半导体高压元件可以是多个如图5的氮化物半导体元件500彼此串接而构成的氮化物半导体高 压元件900。
举例而言，在本实施例中，第一氮化物半导体元件900a及/或第二氮化物半导体元件900b可以类似于图5的氮化物半导体元件500，且第一氮化物半导体元件900a的N型氮化物半导体102可以通过N型电极107、金属连结706以及基板电极224以与第二氮化物半导体元件900a的P型氮化物半导体101电性连接。
图10是依照本发明的第十实施例的一种氮化物半导体高压元件的剖面示意图。第十实施例的氮化物半导体高压元件1000与图6的氮化物半导体元件600类似，本实施例采用图10针对氮化物半导体高压元件1000进行描述。值得注意的是，在图10中，相同或相似的标号表示相同或相似的构件，故针对图6中说明过的构件于此不再赘述。
请参照图10，第十实施例的氮化物半导体高压元件1000与图6的氮化物半导体元件600类似，两者的差异在于：本实施例的氮化物半导体高压元件可以是多个如图6的氮化物半导体元件600彼此串接而构成的氮化物半导体高压元件1000。
举例而言，在本实施例中，第一氮化物半导体元件1000a及/或第二氮化物半导体元件1000b可以类似于图6的氮化物半导体元件600，且第一氮化物半导体元件1000a的N型氮化物半导体102可以通过N型电极107、位于电路板319的金属连结(未绘示)以及第二连接电极324以与第二氮化物半导体元件1000b的P型氮化物半导体101电性连接。
图11是依照本发明的第十一实施例的一种氮化物半导体元件的封装结构的剖面示意图。在本实施例中，氮化物半导体元件1100a可以为水平结构的发光二极管元件。举例而言，氮化物半导体元件1100a可以是类似于第一实施例的氮化物半导体元件100或是类似于第四实施例的氮化物半导体元件400，但本发明不限于此。
封装结构1100包括封装载体、封装基板以及氮化物半导体元件1100a。氮化物半导体元件1100a设置于封装载体以及封装基板上。封装基板包括电路板1119、二个焊垫1120A、1120B。二个焊垫1120A、1120B分别设置于电路板1119上且彼此分离。封装载体包括支架1113、二个导电引脚1114A、1114B、树脂1115、透明胶1117以及萤光粉1118。二个导电引脚1114A、1114B分别设置于该支架1113上，用以分别与二个焊垫1120A、1120B电性连接。氮化物半导体元件1100a设置于二个导电引脚1114A、1114B上，并与二个导电引脚1114A、1114B电性连接。树脂1115设置于支架1113上，并用以容纳 氮化物半导体元件1100a及二个导电引脚1114A、1114B。透明胶1117用以包覆氮化物半导体元件1100a及二个导电引脚1114A、1114B。萤光粉1118用以填入于透明胶1117中。
在本实施例中，封装载体还包括二个导电材料1116。二个导电材料1116用以电性连接氮化物半导体元件1100a以及二个导电引脚1114A、1114B。
在一些实施例中，萤光粉1118是由具高稳定发光特性的材料所制成，其材料例如可以包括石榴石系(Garnet)、硫化物(Sulfate)、氮化物(Nitrate)、硅酸盐(Silicate)、铝酸盐(Aluminate)或其上述材料的任意组合，但本发明不限于此。萤光粉1118的发光波长约为300nm至700nm。萤光粉1118的粒径为1～25μm。
在一些实施例中，导电材料1116可以为焊线、金、银、铜、铝、焊锡或是混合材料。在本实施例中，导电材料1116是以焊线为例，但本发明不限于此。
在一些实施例中，透明胶1117的材料可以包括环氧树脂(epoxy resin)，但本发明不限于此。
在一些实施例中，导电引脚1114A、1114B的材料可以可为纯金属材料、金、银、铜、铝、低熔点金属合金、金锡合金、锡、铋或锡铋合金，但本发明不限于此。
图12是依照本发明的第十二实施例的一种氮化物半导体元件的封装结构的剖面示意图。第十二实施例的封装结构1200与图11的封装结构1100类似，本实施例采用图12针对封装结构1200进行描述。值得注意的是，在图12中，相同或相似的标号表示相同或相似的构件，故针对图11中说明过的构件于此不再赘述。
请参照图12，第十二实施例的封装结构1200与图11的封装结构1100类似，两者的差异在于：在本实施例中，氮化物半导体元件1200a可以为垂直结构的发光二极管元件。举例而言，氮化物半导体元件1200a可以是类似于第二实施例的氮化物半导体元件200或是类似于第五实施例的氮化物半导体元件500，但本发明不限于此。
在本实施例中，封装载体包括第一导电材料1116以及第二导电材料1116。第一导电材料1116以及第二导电材料1116可以类似于前述实施例的导电材料1116。第一导电材料1116可以为焊线，且第二导电材料1116可以为焊球(solder ball)、凸块(bump)或类似物，但本发明不限于此。
图13是依照本发明的第十三实施例的一种氮化物半导体元件100的封装 结构的剖面示意图。第十三实施例的封装结构1300与图11的封装结构1100类似，本实施例采用图13针对封装结构1300进行描述。值得注意的是，在图13中，相同或相似的标号表示相同或相似的构件，故针对图11中说明过的构件于此不再赘述。
请参照图13，第十三实施例的封装结构1300与图11的封装结构1100类似，两者的差异在于：在本实施例中，氮化物半导体元件1300a可以为覆晶结构的发光二极管元件。举例而言，氮化物半导体元件1300a可以是类似于第三实施例的氮化物半导体元件100300或是类似于第六实施例的氮化物半导体元件600，但本发明不限于此。
在本实施例中，封装载体还包括二个导电材料1116。导电材料1116可以类似于前述实施例的导电材料1116。在本实施例中，导电材料1116可以为焊球(solder ball)、凸块(bump)或类似物，但本发明不限于此。
图14是依照本发明的一种氮化物半导体元件的制造流程图。
请参照图14。首先，在步骤S1中，形成一半导体晶圆。接着，在步骤S2中，以隐形激光方式(stealth dicing process)切割半导体晶圆，以形成氮化物半导体元件。
在本实施例中，氮化物半导体元件例如是前述任一实施中的氮化物半导体元件。举例而言，本实施例的氮化物半导体元件的制造方法可以为氮化物半导体元件100、200、300、400、500、600的制造方法，或是氮化物半导体高压元件700、800、900、1000的制造方法，但本发明不限于此。
氮化物半导体元件可以发出UV光线、蓝色光线或绿色光线。氮化物半导体元件可以应用于灯丝(Filament)产品、COB(Chip on Board)产品、激光二极管(Laser Diode)产品或发光二极管(Light Emitting Diode)产品。
综上所述，本发明的氮化物半导体元件，其可以提升发光效率及改善制程良率。本发明的氮化物半导体元件的制造方法，可用以制作上述的氮化物半导体元件。本发明的封装结构，可应用于上述的氮化物半导体元件。
虽然本发明已以实施例公开如上，然其并非用以限定本发明，任何所属技术领域技术人员，在不脱离本发明的精神和范围内，当可作些许的变动与润饰，故本发明的保护范围当视后附的权利要求所界定者为准。

Claims (20)

  1. 一种氮化物半导体元件，包括：
    P型氮化物半导体；
    N型氮化物半导体；以及
    氮化物半导体量子井发光结构，位于所述P型氮化物半导体以及所述N型氮化物半导体之间，所述氮化物半导体量子井发光结构包括多个井层以及多个阻挡层，各个所述多个井层以及各个所述多个阻挡层彼此交错配置，其中所述多个阻挡层包括：
    配置于最接近所述P型氮化物半导体位置的第一阻挡层，其中所述第一阻挡层的厚度小于100埃；
    配置于最接近所述N型氮化物半导体位置的第二阻挡层；以及
    至少一个第三阻挡层，其中所述至少一个第三阻挡层位于相邻的两个所述多个井层之间。
  2. 如权利要求1所述的氮化物半导体元件，其中所述第二阻挡层的厚度大于所述第一阻挡层的厚度。
  3. 如权利要求1所述的氮化物半导体元件，其中所述至少一个第三阻挡层的厚度大于所述第一阻挡层的厚度。
  4. 如权利要求1所述的氮化物半导体元件，还包括：穿隧接面，设置于所述氮化物半导体量子井发光结构上，所述穿隧接面包括：
    重掺杂P型氮化物半导体，设置于所述氮化物半导体量子井发光结构上；以及
    重掺杂N型氮化物半导体，设置于所述重掺杂P型氮化物半导体上。
  5. 如权利要求4所述的氮化物半导体元件，其中所述重掺杂N型氮化物半导体的能隙大于所述氮化物半导体量子井发光结构的能隙。
  6. 如权利要求4所述的氮化物半导体元件，其中所述重掺杂N型氮化物半导体基本上不吸收所述氮化物半导体量子井发光结构所发出光线。
  7. 如权利要求4所述的氮化物半导体元件，其中所述穿隧接面还包括：中间半导体，位于所述重掺杂P型氮化物半导体以及所述重掺杂N型氮化物半导体之间。
  8. 如权利要求4所述的氮化物半导体元件，还包括：
    第二N型氮化物半导体，位于所述穿隧接面的所述重掺杂N型氮化物半导体上。
  9. 如权利要求8所述的氮化物半导体元件，还包括：
    反射绝缘层，位于所述第二N型氮化物半导体上，并暴露出部分的所述第二N型氮化物半导体。
  10. 如权利要求9所述的氮化物半导体元件，其中所述反射绝缘层包括多个第一介电对以及多个第二介电对，其中所述多个第一介电对或所述多个第二介电对包括：
    第一材料层；以及
    第二材料层，其中所述第一材料层的介电系数大于所述第二材料层的介电系数。
  11. 如权利要求1所述的氮化物半导体元件，其中所述P型氮化物半导体包括：
    P侧应力释放层，其中所述P侧应力释放层为超晶格结构；
    高浓度空穴层；
    电子阻挡层；以及
    P型欧姆接触层，其中自所述第一阻挡层向远离于所述第一阻挡层的方向上依序为所述P侧应力释放层、所述高浓度空穴层、所述电子阻挡层以及所述P型欧姆接触层。
  12. 如权利要求11所述的氮化物半导体元件，其中所述高浓度空穴层的镁掺杂浓度高于所述P侧应力释放层的镁掺杂浓度以及所述电子阻挡层的镁掺杂浓度。
  13. 如权利要求11所述的氮化物半导体元件，其中所述电子阻挡层的铝成份百分比高于所述P侧应力释放层的铝成份百分比以及所述高浓度空穴层的铝成份百分比。
  14. 如权利要求11所述的氮化物半导体元件，其中所述P型欧姆接触层的镁掺杂浓度高于所述电子阻挡层的镁掺杂浓度。
  15. 如权利要求11所述的氮化物半导体元件，其中所述高浓度空穴层的镁掺杂浓度高于1x1019Atoms/cm3，且所述的高浓度空穴层的铝成份百分比低于所述的电子阻挡层的铝成份百分比。
  16. 如权利要求1所述的氮化物半导体元件，其中所述N型氮化物半导体包括：
    N侧第一应力释放层；
    N侧第二应力释放层，其中所述N侧第一应力释放层或所述N侧第二应力释放层为超晶格结构；
    低浓度电子层；以及
    N型欧姆接触层，其中自所述第二阻挡层向远离于所述第二阻挡层的方向上依序为所述N侧第一应力释放层、所述N侧第二应力释放层、所述低浓度电子层以及所述N型欧姆接触层。
  17. 如权利要求16所述的氮化物半导体元件，其中所述N侧第一应力释放层的铟成份百分比高于所述N侧第二应力释放层的铟成份百分比。
  18. 如权利要求16所述的氮化物半导体元件，其中所述低浓度电子层的硅掺杂浓度低于所述N型欧姆接触层的硅掺杂浓度。
  19. 如权利要求16所述的氮化物半导体元件，其中所述N型欧姆接触层的硅掺杂浓度高于所述N侧第一应力释放层的硅掺杂浓度、所述N侧第二应力释放层的硅掺杂浓度以及所数低浓度电子层的硅掺杂浓度。
  20. 一种半导体元件，包括：
    电路板；
    多个如权利要求1的氮化物半导体元件，设置于所述电路板上，其中所述多个氮化物半导体元件的其中之一的所述N型氮化物半导体电性连接至其余的所述多个氮化物半导体元件的其中之一的所述P型氮化物半导体。
PCT/CN2017/098626 2016-08-25 2017-08-23 氮化物半导体元件及其制造方法与所应用的封装结构 WO2018036513A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201780045923.0A CN109863609A (zh) 2016-08-25 2017-08-23 氮化物半导体元件及其制造方法与所应用的封装结构

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201662379738P 2016-08-25 2016-08-25
US62/379,738 2016-08-25
US201762471946P 2017-03-15 2017-03-15
US62/471,946 2017-03-15

Publications (1)

Publication Number Publication Date
WO2018036513A1 true WO2018036513A1 (zh) 2018-03-01

Family

ID=61246393

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/098626 WO2018036513A1 (zh) 2016-08-25 2017-08-23 氮化物半导体元件及其制造方法与所应用的封装结构

Country Status (3)

Country Link
CN (1) CN109863609A (zh)
TW (1) TWI668885B (zh)
WO (1) WO2018036513A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI730472B (zh) * 2019-10-25 2021-06-11 進化光學有限公司 使用雷射切割道絕緣之全彩ｌｅｄ顯示面板及其製造方法
TWI730460B (zh) * 2019-10-18 2021-06-11 進化光學有限公司 高出光效率的背接觸式全彩ｌｅｄ顯示面板及其製造方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110137323A (zh) * 2019-05-29 2019-08-16 福建兆元光电有限公司 带有AlN缓冲层的LED芯片及制造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101071841A (zh) * 2006-05-12 2007-11-14 日立电线株式会社 氮化物半导体发光元件
US20090162999A1 (en) * 2007-12-20 2009-06-25 Hung-Cheng Lin Method of Growing Nitride Semiconductor material
CN101931036A (zh) * 2010-07-21 2010-12-29 中国科学院半导体研究所 一种氮化镓系发光二极管
CN103972343A (zh) * 2013-01-25 2014-08-06 新世纪光电股份有限公司 氮化物半导体结构及半导体发光元件

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100380536B1 (ko) * 2000-09-14 2003-04-23 주식회사 옵토웰 터널접합 구조를 가지는 질화물반도체 발광소자
KR100764433B1 (ko) * 2006-04-06 2007-10-05 삼성전기주식회사 질화물 반도체 소자
CN101859839A (zh) * 2009-04-07 2010-10-13 璨扬投资有限公司 发光二极管芯片
WO2013015035A1 (ja) * 2011-07-26 2013-01-31 日亜化学工業株式会社 半導体発光素子
TWI466328B (zh) * 2012-06-11 2014-12-21 Ritedia Corp 覆晶式發光二極體及其製法與應用
TWI499080B (zh) * 2012-11-19 2015-09-01 Genesis Photonics Inc 氮化物半導體結構及半導體發光元件
TW201426969A (zh) * 2012-12-28 2014-07-01 Helio Optoelectronics Corp 高壓覆晶ｌｅｄ結構及其製造方法
KR101934000B1 (ko) * 2013-01-10 2019-04-05 엘지이노텍 주식회사 발광 소자
CN103137807A (zh) * 2013-02-22 2013-06-05 中国科学院半导体研究所 具有应力释放层的绿光led外延结构及制作方法
JPWO2014178248A1 (ja) * 2013-04-30 2017-02-23 シャープ株式会社 窒化物半導体発光素子
CN103972334B (zh) * 2014-05-14 2017-01-18 湘能华磊光电股份有限公司 Led外延层结构、生长方法及具有该结构的led芯片
US20170125632A1 (en) * 2014-07-04 2017-05-04 Sharp Kabushiki Kaisha Nitride-semiconductor light-emitting element
KR102301513B1 (ko) * 2015-02-16 2021-09-15 쑤저우 레킨 세미컨덕터 컴퍼니 리미티드 발광소자, 이를 포함하는 발광소자 패키지, 및 이를 포함하는 조명시스템
CN104766914A (zh) * 2015-04-20 2015-07-08 电子科技大学 一种高取光率的高压led芯片结构

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101071841A (zh) * 2006-05-12 2007-11-14 日立电线株式会社 氮化物半导体发光元件
US20090162999A1 (en) * 2007-12-20 2009-06-25 Hung-Cheng Lin Method of Growing Nitride Semiconductor material
CN101931036A (zh) * 2010-07-21 2010-12-29 中国科学院半导体研究所 一种氮化镓系发光二极管
CN103972343A (zh) * 2013-01-25 2014-08-06 新世纪光电股份有限公司 氮化物半导体结构及半导体发光元件

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI730460B (zh) * 2019-10-18 2021-06-11 進化光學有限公司 高出光效率的背接觸式全彩ｌｅｄ顯示面板及其製造方法
TWI730472B (zh) * 2019-10-25 2021-06-11 進化光學有限公司 使用雷射切割道絕緣之全彩ｌｅｄ顯示面板及其製造方法

Also Published As

Publication number Publication date
CN109863609A (zh) 2019-06-07
TWI668885B (zh) 2019-08-11
TW201807845A (zh) 2018-03-01

Similar Documents

Publication Publication Date Title
US8217568B2 (en) Light emitting element and light emitting device using the light emitting element
TWI354380B (en) Light emitting device
US9324904B2 (en) Semiconductor light emitting device and light emitting apparatus
JP4101468B2 (ja) 発光装置の製造方法
TW552723B (en) Group III nitride compound semiconductor light-emitting element
US8183576B2 (en) Light-emitting diodes including perpendicular-extending nano-rods
JP5040355B2 (ja) 半導体発光素子及びこれを備えた発光装置
US20130313514A1 (en) Semiconductor light emitting device
JP2019519935A (ja) 半導体素子
KR101974353B1 (ko) 발광소자 및 발광소자 패키지
US11094865B2 (en) Semiconductor device and semiconductor device package
TWI668885B (zh) 氮化物半導體元件及其製造方法與所應用之封裝結構
JP5557649B2 (ja) 発光ダイオード、発光ダイオードランプ及び照明装置
US9627584B2 (en) Light emitting device and light emitting device package
US10862015B2 (en) Semiconductor light emitting device package
KR20070028095A (ko) 저저항 발광 다이오드
KR102070092B1 (ko) 반도체 발광소자
KR101039948B1 (ko) 발광 소자, 발광 소자 제조방법 및 발광 소자 패키지
TWI446580B (zh) 發光二極體、發光二極體燈及照明裝置
KR101700792B1 (ko) 발광 소자
US20210305475A1 (en) Light emitting device package and light source module
TWI433356B (zh) 發光二極體及發光二極體燈
KR20140028288A (ko) 발광 소자
KR20120048401A (ko) 발광소자
KR102353566B1 (ko) 반도체 소자 및 반도체 소자 패키지

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17842935

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17842935

Country of ref document: EP

Kind code of ref document: A1