WO2018035515A1

WO2018035515A1 - Test stack having wafer translator and stiffening interface, and associated systems and methods

Info

Publication number: WO2018035515A1
Application number: PCT/US2017/047756
Authority: WO
Inventors: Christopher T. Lane
Original assignee: Translarity, Inc.
Priority date: 2016-08-19
Filing date: 2017-08-21
Publication date: 2018-02-22
Also published as: TW201818081A

Abstract

Systems and methods for testing semiconductor wafers are disclosed herein. In one embodiment, an apparatus for testing dies of a semiconductor wafer includes: a wafer translator having a wafer-side configured to face the wafer, and an inquiry-side facing away from the wafer-side. The wafer-side carries wafer-side contact structures, and the inquiry-side carries inquiry-side contact structures. The apparatus also includes a stiffening interface (SIF) board having a first side facing the inquiry-side of the wafer translator, and a second side facing away from the first side. The apparatus also includes a tester translator interface (TTI) board having a first face facing the second side of the SIF, and a second face facing away from the first face.

Description

TEST STACK HAVING WAFER TRANSLATOR AND STIFFENING INTERFACE, AND ASSOCIATED SYSTEMS AND METHODS

CROSS-REFERENCE(S) TO RELATED APPLICATION S) This application claims the benefit of U.S. Provisional Application No. 62/377241, filed August 19, 2016, which is hereby incorporated by reference in its entirety.

BACKGROUND

Integrated circuits are used in a wide variety of products. Integrated circuits have continuously decreased in price and increased in performance, becoming ubiquitous in modern electronic devices. These improvements in the performance/cost ratio are based, at least in part, on miniaturization, which enables more semiconductor dies to be produced from a wafer with each new generation of the integrated circuit manufacturing technology. Furthermore, the total number of the signal and power/ground contacts on a semiconductor die generally increases with new, more complex die designs.

Prior to shipping semiconductor dies to customers, the performance of the integrated circuits is tested, either based on a statistical sample or by testing each die. An electrical test of the semiconductor die typically includes powering the die through the power/ground contacts, transmitting signals to the input contacts of the die, and measuring the resulting signals at the output contacts of the die. Therefore, during the electrical test at least some contacts on the die must be electrically contacted to connect the die to sources of power and test signals.

Conventional test contactors include an array of contact pins attached to a substrate, for example a relatively stiff printed circuit board (PCB). In operation, the test contactor is pressed against a wafer such that the array of contact pins makes electrical contact with the corresponding array of die contacts (e.g., pads or solderballs) on the dies (i.e., devices under test or DUTs) of the wafer. Next, a wafer tester sends electrical test sequences (e.g., test vectors) through the test contactor to the input contacts of the dies of the wafer. In response to the test sequences, the integrated circuits of the tested die produce output signals that are routed through the test contactor back to the wafer tester for analysis and determination whether a particular die passes the test. Next, the wafer is lowered, moved sideways, and moved up such that another die or a group of dies contacts the test contactor (also referred to as "test contactor stack" or "test stack"). The process continues till the entire wafer is tested.

In general, an increasing number of die contacts distributed over a decreasing area of the die results in smaller contacts that are spaced apart by smaller distances (e.g., a smaller pitch). Furthermore, the characteristic diameter of the contact pins of the test contactor generally scales with a characteristic dimension of the contact structures on the semiconductor die or the package. Therefore, as the contact structures on the die become smaller and/or have a smaller pitch, the contact pins of the test contactors become smaller, too. However, it is difficult to significantly reduce the diameter and pitch of the contact pins of the test contactor, e.g., because of the difficulties in machining and assembling such small parts, resulting in low yield and inconsistent performance from one test contactor to another.

Figure 1A is an exploded view of a portion of a test stack 50 for testing semiconductor wafers in accordance with prior art technology. The test stack 50 routes signals and power from a tester (not shown) to a wafer 20 or other substrate carrying one or more devices under test (DUTs), and then transfers the output signals from the DUTs (e.g., semiconductor dies) back to the tester for analysis and determination about an individual DUT's performance (e.g., whether the DUT is suitable for packaging and shipment to the customer). The signals and power from the tester are routed through a tester translator interface board (TTI board) 30 to a wafer translator 10, and further to the semiconductor dies on the wafer 20.

The signals and power are routed from the tester to the TTI board 30 using cables 39. Conductive traces 38 carried by a test contactor substrate 32 can electrically connect the cables 39 to contacts 36 on the opposite side of the TTI substrate 32. In some embodiments, the TTI substrate 32 may be a printed circuit board (PCB). In operation, the TTI board 30 can contact an inquiry-side 13 of a wafer translator 10 as indicated by arrows A. In at least some embodiments, relatively large inquiry-side contact structures 14 can improve alignment with the corresponding contacts 36 of the TTI board 30. The contact structures 14 at the inquiry-side 13 are electrically connected with relatively small wafer-side contact structures 16 on a wafer-side 15 of the translator 10 through conductive traces 18 of a wafer translator substrate 12. The size and/or pitch of the wafer-side contact structures 16 are suitable for contacting the corresponding die contact pads 26 of the wafer 20. The die contact pads may be relatively flat surfaces on the die, solder balls, copper balls, or other contact structures carried by the die. Arrows B indicate a movement of the wafer translator 10 to make contact with the contact pads 26 on an active side 25 of the wafer 20. As explained above, the signals and power from the tester can exercise the DUTs of the wafer 20, and the output signals from the tested DUTs can be routed back to the tester for analysis and a determination as to whether the DUTs operate per the specifications.

A wafer chuck 40 supports the wafer 20. Arrows C indicate the direction of the wafer 20 mating with the wafer chuck 40. In operation, the wafer 20 can be held against the wafer chuck 40 using, e.g., vacuum or mechanical clamping. In some cases, the contact structures 16 on the wafer-side of the wafer translator 10 may simultaneously contact all or almost all dies 20a, 20b, etc. on the wafer 20. In some cases, the diameter of the wafer translator 10 may generally correspond to the diameter of the wafer 20, or the wafer translator may have larger diameter than the corresponding wafer under test ("edge-extended wafer translator").

Figures IB and 1C are partially schematic, top and bottom views, respectively, of a wafer translator configured in accordance with embodiments of the presently disclosed technology. Figure IB illustrates the inquiry-side 13 of the wafer translator 10. Distances between the adjacent inquiry-side contact structures 14 (e.g., pitch) are denoted Pi in the horizontal direction and P₂ in the vertical direction. The illustrated inquiry-side contact structures 14 have a width Di and a height D₂. The pitch, width and height of the contact structures 14 may be collectively termed "the characteristic dimensions." In different embodiments, the inquiry-side contact structures 14 may be squares, rectangles, circles or other shapes. Furthermore, the inquiry-side contact structures 14 can have a uniform pitch (e.g., Pi and P₂ being equal across the wafer translator 10) or a non-uniform pitch.

Figure 1C illustrates the wafer-side 15 of the wafer translator 10. In some embodiments, the pitch between the adjacent wafer-side contact structures 16 can be pi in the horizontal direction and p₂ in the vertical direction. The width and height of the wafer-side contact structures 16 ("characteristic dimensions") are denoted as di and d₂. In some embodiments, the wafer-side contact structures 16 can be pins that touch corresponding die contacts on the wafer 20. Lines 19 correspond to wafer streets that separate individual dies of the wafer 20 from each other. In general, the size/pitch of the inquiry-side contact structures 14 is larger than the size/pitch of the wafer-side contact structures 16. As a result, the alignment and contact is improved between the test contactor and the wafer translator.

However, it may be difficult to maintain a consistent contact between the die contact 26 and the wafer-side contact structures 16 when contacting dies over a relatively large wafer 20 (e.g., over a wafer having 150 mm, 200 mm, or 300 mm diameter). Analogously, it may be difficult to maintain consistent contact between the contacts 36 on the TTI board 30 and the corresponding inquiry-side contact structures 14. For example, tilting or undulation (waviness) of the wafer translator may compress some contact pairings 14/36 and/or 16/26 too much, while some other contact structures do not have enough contact force or do not make contact at all. Generally, as the wafers 20 become larger, and the die contacts 26 become smaller, the consistency and reliability of contact degrades. Accordingly, there remains a need for cost effective test contactors that can provide consistent contact with all devices under test (DUTs) on the wafer.

DESCRIPTION OF THE DRAWINGS

The aspects of the present disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale. Instead, emphasis is placed on clearly illustrating the principles of the present disclosure.

FIGURE 1A is an exploded view of a portion of a test stack for testing semiconductor wafers in accordance with prior art technology.

FIGURE IB is a partially schematic, top view of a wafer translator configured in accordance with prior art technology.

FIGURE 1C is a partially schematic, bottom view of a wafer translator configured in accordance with prior art technology.

FIGURE 2 is an exploded, cross-sectional view of a test stack in accordance with embodiments of the presently disclosed technology.

FIGURE 2A is a detail view of a contact structure of a stiffening interface board shown in FIGURE 2.

FIGURE 3 is an isometric view of a test stack in accordance with embodiments of the presently disclosed technology.

FIGURES 4A-4C are cross-sectional views of a test stack in accordance with embodiments of the presently disclosed technology.

FIGURES 4D and 4E are detail views of the test stack shown in FIGURE 4B. FIGURE 5 is an isometric view of several elements in a test stack in accordance with embodiments of the presently disclosed technology. FIGURE 6 is a side, cross-sectional view of a test stack in accordance with embodiments of the presently disclosed technology.

DETAILED DESCRIPTION

Specific details of several embodiments of representative wafer translators and associated methods for use and manufacture are described below. A person skilled in the relevant art will also understand that the inventive technology may have additional embodiments, and that the technology may be practiced without several of the details of the embodiments described below with reference to Figures 2-6.

The inventive technology relates generally to equipment for semiconductor wafer test. More particularly, the present technology relates to methods and systems for contacting ("probing") the dies of the semiconductor wafer using a wafer translator having improved flatness for more uniform and consistent contacts with wafer.

In some embodiments, a stiffening interface board (SIF board) is inserted in the test stack between the wafer translator and the tester translator interface board (TTI board) to improve flatness of the wafer translator. Generally, the improved flatness of the wafer translator and improved rigidity of the overall test stack promotes uniformity of contact between the wafer translator and the wafer.

In some embodiments, the SIF board includes a substrate made of ceramic, glass or other rigid material. The SIF board may include compliant through- substrate pins, for example, pogo pins that require relatively low vertical compression force for reliable contact. The SIF board that includes a combination of relatively stiff substrate (e.g., ceramic) and relatively compliant contacts (e.g., pogo pins) may both flatten the wafer translator (based on the stiffness of the substrate) and accommodate the remaining waviness/tilting of the wafer translator (based on the vertical compliance of the contacts).

In some embodiments, a vacuum between the elements of the test stack secures the contact between the elements. In some embodiments, the wafer translator, the SIF board and/or the TTI board may have apertures for evacuating gas from the space between the elements.

Figure 2 is an exploded, cross-sectional view of a test stack 1000 in accordance with embodiments of the presently disclosed technology. In operation, the chuck 40 carries the wafer 20. The wafer-side contact structures 16 of the wafer translator 100 contact the corresponding die contact pads 26 on the dies 20a, 20b (also referred to as devices under test or DUTs). However, in some cases this contact may not be sufficiently uniform and/or consistent because of, for example, tilting or waviness of the wafer translator 100. In some embodiments, a SIF board 200 may provide additional stiffness and flatness to the test stack 1000. For example, a substrate 202 of the SIF board 200 may be made of ceramic, glass, hard plastic, or other relatively stiff material. In some embodiments, the SIF board is at least an order of magnitude stiffer than the wafer translator. When in contact with the wafer translator 100, the SIF board 200 may reduce the waviness and/or tilting of the wafer translator 100.

The SIF board 200 may include compliant contact structures 210. Some non- limiting examples of such compliant contact structures are pogo pins and slender contact beams (needles). In general, compliant contact structures 210 can compress relatively easily, thus being capable of maintaining contact with the corresponding inquiry-side contact structures 14 when the wafer-translator 100 is tilted or wavy, therefore further improving the consistency and reliability of contact with the wafer translator.

In some embodiments, the SIF board 200 may include conductive traces distributed within routing layers. Generally, the availability of the routing layer(s) in the SIF board 200 tends to correspondingly reduce routing requirements for the TTI board 30 and/or the wafer translator 100. As a result, the overall routing of the signals/power from the tester to the DUTs 20a, 20b and back may become less congested, have better signal- to-noise ratio (S R), and/or smaller power loss.

In operation, the TTI board 30 may press the SIF board 200 against the inquiry- side 13 of the wafer translator 100. In some embodiments, the TTI board 30 is supported by a stiff ener plate 300 that may be made of metal, for example, stainless steel.

Figure 2A is a detail view of the contact structure 210 of the stiffening interface board 210 shown in Figure 2. The illustrated detail C shows the substrate 202 having two aligned pogo pins 210, one facing the TTI board 30, another facing the wafer translator 100. In some embodiments, the pogo pins 210 may share the same spring. In some embodiments, the pogo pins 210 may not be axially aligned. For example, the upper pogo pin 210 may be axially offset from the lower pogo pin 210 to properly contact their corresponding contacts 36 on the TTI board 30 and inquiry-side contact structures 14, respectively, on the wafer-translator 100.

The illustrated contact structures 210 are spring-loaded pogo pins. However, in some embodiments, the contact structures 210 may be compliant solid-metal pins (e.g., relatively slender, curved, needle-like beams). Figure 3 is an isometric view of the test stack 1000 in accordance with embodiments of the presently disclosed technology. The test stack 1000 is mounted inside a prober 400. The upper part of the test stack includes the stiffener plate 300, the SIF board 200, and the TTI board 30. The illustrated stiffener plate 300 is attached to a prober plate 410.

The lower part of the test stack includes the wafer translator 100, the wafer under test 20 (covered by the wafer translator), and the wafer chuck 40. Before testing, the prober 400 in the clamshell arrangement of Figure 3 is closed by lowering the prober plate 410, and the elements of the test stack 1000 are brought into contact. Next, the wafer translator 100 may be picked up by the upper part of the test stack, aligned against the wafer 20, and then brought into contact with the wafer 20. In some embodiments, the wafer may be a blank (unpatterned) wafer that may be replaced with a production wafer before the test starts. An illustrative method of bringing the elements of the test stack 1000 into contact is discussed with reference to Figures 4A-4C below.

Figure 4A is an exploded, cross-sectional view of a test stack 1000 in accordance with embodiments of the presently disclosed technology. In some embodiments, the tester cables 39 are attached to the TTI board 30 through openings in the stiffener plate 300.

In some embodiments, gaskets 228a/228b are placed between the SIF board 200 and the TTI board 30, and/or between the SIF board 200 and the wafer translator 100. The illustrated gaskets 228a/228b are carried by the SIF board 200, but, in some embodiments, the gaskets 228a/228b may be carried by the TTI board 30 and/or the wafer translator 100. The gaskets 228a/228b may be made of soft, compliant materials, for example, rubber, PVC sheet, etc. In operation, the gaskets 228a/228b may provide sealing of the spaces between the TIF board 30 and SIF board 200, and/or the SIF board 200 and the wafer translator 100, as explained with reference to Figure 4B below.

Figure 4B is a cross-sectional view of the test stack 1000 in accordance with embodiments of the presently disclosed technology. In some embodiments, a vacuum may be applied to a test stack 1000a by evacuating gas through apertures 37 and 207. In some embodiments, the gaskets 228a/228b seal the facing surfaces of the TIF board 30, SIF board 200, and the wafer translator 100 to preserve vacuum in the sealed spaces. In some embodiments, the vacuum may be sufficient to keep the TIF board 30, SIF board 200, and the wafer translator 100 in a consistent and reliable electrical contact. A test stack 1000b includes the wafer 20 and the prober chuck 40. In operation, the test stacks lOOOa/lOOOb can be brought into contact as explained with reference to Figure 4C below.

Figure 4C is a cross-sectional view of the test stack 1000 in accordance with embodiments of the presently disclosed technology. In the illustrated embodiment, the test stack 1000a is in contact with the test stack 1000b. For example, the die contact pads 26 are in contact with the corresponding wafer-side contact structures 16. Some production probers can apply vertical force F on the wafer chuck 40 and/or the stiffener plate 300, therefore flattening the wafer translator 100, and improving contacts between the wafer translator 100 and the wafer 20.

In some embodiments, a wafer gasket may seal a space between the wafer translator 100 and the wafer chuck 40. When a source of vacuum is connected to apertures 47 in the wafer chuck 40, vacuum can be generated between the wafer translator 100 and the wafer 20, therefore improving the contact between the die contact pads 26 and corresponding wafer-side contact structures 16. This vacuum may further improve flattening of the wafer translator 100, and improve contacts between the wafer translator 100 and the wafer 20. In some embodiments, the vertical force F and vacuum may be used in combination.

Figures 4D and 4E are detail views of the test stack shown in Figure 4B. Figure 4D shows the wafer translator 100 having vertical wafer-side contact structure 117 that are shaped as compliant contact beams. In operation, the tips of the contact structures 117 contact the corresponding dies contact pads 26 on the wafer. In some embodiments, the relatively thin and long contact structures 1 17 can accommodate some waviness and/or lack of flatness of the substrate 12 of the wafer translator, therefore further improving contact between the wafer translator and the wafer.

Figure 4E shows the wafer translator 100 having MEMS contact structure 118. In some embodiments, the MEMS contact structure 118 can have two positions: an un- extended position 118a and an extended position 118b. In operation, the MEMS contact structures may be driven into the extended positon 118b when contacting die contact pads 26 on the wafer.

Figure 5 is an isometric view of several elements in a test stack in accordance with embodiments of the presently disclosed technology. The illustrated test stack includes the SIF board 200, the TTI board 30, and the stiffener plate 300. In some embodiments, the SIF board 200 may be attached to the TTI board 30 with fasteners 220, for example screws or rivets.

Figure 6 is a side, cross-sectional view of the test stack 1000 in accordance with embodiments of the presently disclosed technology. The illustrated test stack 1000 includes the SIF board 200 in contact with the TTI board 30. In some embodiments a universal adapter 420 may align the TTI board 30 against the prober plate 410. In some embodiments, one or more inserts 310 support the TTI board 30 against the stiffener plate 300.

Many embodiments of the technology described above may take the form of computer- or controller-executable instructions, including routines executed by a programmable computer or controller. Those skilled in the art will appreciate that the technology can be practiced on computer/controller systems other than those shown and described below. The technology can be embodied in a special-purpose computer, controller, or data processor that is specifically programmed, configured, or constructed to perform one or more of the computer-executable instructions described below. Accordingly, the terms "computer" and "controller" as generally used herein refer to any data processor and can include Internet appliances and hand-held devices (including palm-top computers, wearable computers, cellular or mobile phones, multi-processor systems, processor-based or programmable consumer electronics, network computers, mini computers and the like). Information handled by these computers can be presented by any suitable display medium, including a CRT display or LCD.

From the foregoing, it will be appreciated that specific embodiments of the technology have been described herein for purposes of illustration, but that various modifications may be made without deviating from the disclosure. Moreover, while various advantages and features associated with certain embodiments have been described above in the context of those embodiments, other embodiments may also exhibit such advantages and/or features, and not all embodiments need necessarily exhibit such advantages and/or features to fall within the scope of the technology. Accordingly, the disclosure can encompass other embodiments not expressly shown or described herein.

Claims

CLAIMS The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. An apparatus for testing dies of a semiconductor wafer, comprising:

a wafer translator having a wafer-side configured to face the wafer, and an inquiry-side facing away from the wafer-side, wherein the wafer-side carries wafer-side contact structures, and the inquiry-side carries inquiry-side contact structures;

a stiffening interface (SIF) board having a first side configured to face the inquiry- side of the wafer translator, and a second side facing away from the first side; and

a tester translator interface (TTI) board having a first face configured to face the second side of the SIF, and a second face facing away from the first face.

2. The apparatus of Claim 1, wherein the SIF board comprises a substrate made of ceramic.

3. The apparatus of Claim 1, wherein the SIF board comprises a substrate made of glass.

4. The apparatus of Claim 1, wherein the SIF board is at least an order of magnitude stiffer than the wafer translator.

5. The apparatus of Claim 1, wherein the SIF board comprises compressible pins.

6. The apparatus of Claim 5, wherein the compressible pins are pogo pins.

7. The apparatus of Claim 1, wherein the SIF board includes at least one aperture in a substrate of the SIF board, and wherein the aperture is configured for evacuating gas between the SIF board and the wafer translator.

8. The apparatus of Claim 1, wherein the TTI board includes at least one aperture in a wafer translator substrate, and wherein the aperture is configured for evacuating gas between the TTI board and the SIF board.

9. The apparatus of Claim 1, further comprising: a first gasket for sealing a first space between the SIF board and the wafer translator; and

a second gasket for sealing a second space between the SIF board and the TTI board.

10. The apparatus of Claim 1, further comprising a plurality of fasteners for securing the SIF board and the TTI board together.

11. The apparatus of Claim 1, further comprising a wafer gasket for sealing a space between the wafer translator and the wafer.

12. The apparatus of Claim 1, further comprising the wafer in contact with the wafer-side contact structures of the wafer translator.

13. The apparatus of Claim 1, further comprising:

a metal stiffener plate in contact with the TTI board; and

a prober plate in contact with the stiffener plate.

14. The apparatus of Claim 1, wherein the wafer-side contact structures of the wafer translator are MEMS based contactors.

15. The apparatus of Claim 1, wherein the wafer-side contact structures of the wafer translator are compliant contact beams.

16. A method for testing a semiconductor wafer, comprising:

contacting a tester translator interface (TTI) board with contact structures carried by a second side of a stiffening interface (SIF) board;

contacting an inquiry-side of a wafer translator with the contact structures carried by a first side of a stiffening interface (SIF) board; and

contacting a die on the semiconductor wafer with a plurality of wafer-side contact structures carried by a wafer-side of a wafer translator, wherein the inquiry-side of the wafer translator faces away from the wafer-side.

17. The method of Claim 16, wherein the TTI board is attached to a metal stiffener plate.

18. The method of Claim 17, wherein the metal stiffener is attached to a prober plate.

19. The method of Claim 16, further comprising:

evacuating gas from a first space between the wafer translator and the SIF board; and

evacuating gas from a second space between the TTI board and the SIF board.

20. The method of Claim 16, further comprising evacuating gas from a space between the wafer translator and the wafer.

21. The method of Claim 16, wherein the contact structures of the SIF board include compressible pins.

22. The method of Claim 21, wherein the compressible pins are pogo pins.

23. The method of Claim 16, wherein the SIF board comprises a substrate made of ceramic.

24. The method of Claim 16, wherein the SIF board comprises a substrate made of glass.

25. The method of Claim 16, wherein the SIF board is at least an order of magnitude stiffer than the wafer translator.