WO2018027839A1 - 一种页表缓存tlb中表项的访问方法，及处理芯片 - Google Patents

一种页表缓存tlb中表项的访问方法，及处理芯片 Download PDF

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Publication number
WO2018027839A1
WO2018027839A1 PCT/CN2016/094732 CN2016094732W WO2018027839A1 WO 2018027839 A1 WO2018027839 A1 WO 2018027839A1 CN 2016094732 W CN2016094732 W CN 2016094732W WO 2018027839 A1 WO2018027839 A1 WO 2018027839A1
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virtual
page number
entry
page
physical
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PCT/CN2016/094732
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English (en)
French (fr)
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蔡卫光
顾雄礼
方磊
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华为技术有限公司
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Priority to PCT/CN2016/094732 priority Critical patent/WO2018027839A1/zh
Priority to CN201680057302.XA priority patent/CN108139981B/zh
Priority to EP16912294.2A priority patent/EP3454218B1/en
Publication of WO2018027839A1 publication Critical patent/WO2018027839A1/zh
Priority to US16/211,225 priority patent/US10740247B2/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1041—Resource optimization
    • G06F2212/1044—Space efficiency improvement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]

Definitions

  • the present invention relates to the field of information technology, and in particular, to a method for accessing an entry in a page table cache TLB, and a processing chip.
  • the operating system looks for the currently available physical addresses and maps the virtual addresses used by the program to these physical addresses. Therefore, when multiple programs are executed at the same time, they are actually at different physical addresses, thus ensuring the normal execution of the program.
  • the physical address space in memory is organized in units of pages. When the operating system manages memory, it divides the physical address space into consecutive pages.
  • the virtual address space is also divided into consecutive pages in pages.
  • the virtual address consists of two parts, namely Virtual Page Number (VPN) and Offset (Offset).
  • the physical address is also composed of two parts, namely the physical frame number (also called the physical page number). (Physical Frame Number, PFN) and Intrapage Offset (Offset). Therefore, mapping virtual addresses to these physical addresses is the page number of a virtual address.
  • the process of mapping to the page number of a physical address The mapping relationship between the virtual page number and the physical page number is stored in the memory in the form of a Page Table entry.
  • a part of the space is allocated in the buffer of the processing chip, that is, a Translation Lookaside Buffer (TLB) to store a part of the page table entry.
  • TLB Translation Lookaside Buffer
  • the embodiment of the invention provides a method for using a page table, and a processing chip, which is used to reduce the probability of TLB Miss, reduce the processing delay of the program, and improve the processing efficiency of the processing chip.
  • an embodiment of an access method for an entry in a TLB is provided.
  • this embodiment there is exactly one combined entry in the entry in the TLB, that is, a virtual entry to a physical page is represented by a combined entry.
  • TLB Hit the scene of the TLB hit (TLB Hit) occurs as follows:
  • the entry of the TLB includes at least one combination table entry, where the combination table entry includes a virtual large page number, a bit vector field, and a physical large page number, wherein the virtual large page number is an identifier of N consecutive virtual pages.
  • the bit vector field includes N bits, the N bits are in one-to-one correspondence with the N consecutive virtual pages, and the N bits are respectively used to identify a page table of the N consecutive virtual pages a state of existence, the physical large page number being an identifier of N consecutive physical pages corresponding to the N consecutive virtual pages, the method comprising:
  • a virtual large page number of the virtual address is owned by the virtual address
  • the virtual page number is obtained by dividing N by the N
  • the offset of the virtual page belonging to the virtual address in the virtual large page is obtained by dividing the virtual page number to which the virtual address belongs by N; the N is greater than An integer of 1;
  • the two determination results are all yes, determining that the physical page number corresponding to the virtual address is: a product of the physical large page number in the combination table item and the N, and then the virtual address belongs to the virtual The sum of the offsets of the pages within the virtual large page.
  • an entry is used to indicate the mapping of multiple virtual pages to physical pages.
  • the number of entries in the TLB can be multiplied, thereby increasing the probability of TLB hits and reducing TLB. Miss, therefore, can reduce the processing delay of the program to improve the processing efficiency of the processing chip.
  • TLB Hit is generated, as follows:
  • the entry includes at least one independent entry, the virtual entry includes a virtual large page number, a virtual large page offset, a physical large page number, and a physical large page offset, wherein the virtual large page
  • the virtual large page number is an identifier of the N consecutive virtual pages
  • the virtual large page offset is a virtual large page number relative to the independent entry.
  • This embodiment provides that when there is a mapping relationship that cannot be used to represent a virtual page to a physical page, the independent table entry is used to represent the mapping relationship as a supplement to the combined table entry.
  • the combined table entry may be used to predict the physical page number. Therefore, in the case of TLB Miss, there is a case where the virtual large page number Hit is in the combined table, in this case, for example. If the combination table entry is marked as address prediction, then the details are as follows:
  • the combination table further includes an identifier for indicating whether the combined entry is available for address prediction, and the method further includes:
  • the page number is fetched by the predicted page, and the page table movement is performed; the predicted page number is: the product of the physical large page number in the combined table item and the N, and then the virtual address belongs to the virtual The sum of the offsets of the pages within the virtual large page.
  • the present embodiment uses the combination table for address prediction, and does not necessarily need to wait for the page table movement result, so the access speed can be improved.
  • the embodiment of the present invention further provides a solution for modifying the entry, as follows: after the execution of the page table movement, the method Also includes:
  • the bit corresponding to the offset of the virtual page of the virtual address in the virtual large page in the bit vector field in the combined table entry Modified to the predetermined value.
  • a new mapping between a virtual page and a physical page is added to the TLB, but no new entry is added, which can save the cost of the entry in the TLB.
  • the embodiment of the present invention further provides a modification scheme of the entry, as follows: after the execution of the page table movement, the method Also includes:
  • an identifier for indicating that the combined entry is not available for address prediction is set in the combined entry.
  • the combined entry of the error address prediction is identified as unavailable for address prediction, so that the situation of address prediction error reoccurring can be avoided.
  • the embodiment of the present invention further provides an implementation of the newly added independent entry, which is specifically as follows: after determining that the result of the page table movement indicates that the predicted page number is incorrect, the method further includes:
  • a new independent entry is added, and the new independent entry includes: a virtual large page number, an offset within the virtual large page, a physical large page number, and an offset within the physical large page;
  • the virtual large page of the new independent entry is composed of N consecutive virtual pages, and the virtual large page number of the new independent entry is obtained by dividing the virtual page number of the virtual address by N.
  • the virtual large page offset of the new independent entry is obtained by dividing the virtual page number to which the virtual address belongs by N; the result of the page table moving is the real physical page number corresponding to the virtual address;
  • the physical large page number of the new independent entry is obtained by dividing the real physical page number by N, and the physical large page offset of the new independent entry is divided by the real physical page number by N. I got it.
  • This embodiment provides an implementation scheme of adding a separate entry in the TLB.
  • the new independent entry cannot be merged with other combined or independent entries.
  • the new independent entry can replace an independent table in the TLB. item.
  • the embodiment of the present invention further provides a situation in which, in the case that the TLB Miss is not performed, the address prediction is not performed, and a new entry is required, the table may be saved.
  • the TLB successfully determines the physical page number corresponding to the virtual address, and the method further includes:
  • the target entry includes: a virtual large page number, a virtual large page offset, a physical large page number, and a physical large page offset; wherein, the target entry The virtual large page is composed of N consecutive virtual pages, and the virtual large page number of the target entry is obtained by dividing the virtual page number of the virtual address by N, and the target entry is in a virtual large page.
  • the offset is obtained by dividing the virtual page number to which the virtual address belongs by N;
  • the result of the page table movement is the real physical page number corresponding to the virtual address;
  • the physical large page number of the target entry is The real physical page number is divided by N, and the physical large page offset of the target entry is obtained by dividing the real physical page number by N;
  • the target combination table entry includes: a virtual large page number, a bit vector field, and a physical large page number; the virtual large page number of the target combination table item is equal to a virtual large page number of the independent entry, and the target combination table entry.
  • the physical large page number is equal to the physical large page number of the independent table entry, and the bit corresponding to the virtual page to which the virtual address belongs in the bit vector field in the target combination table entry is the predetermined value, and the target combination The bit corresponding to the virtual page of the independent entry in the bit vector field in the entry is the predetermined value;
  • the target entry is added as a new independent entry.
  • the physical page number corresponding to the virtual address is not successfully determined by the TLB, and the corresponding relationship between the virtual page number and the physical page number required for storing the virtual address in the TLB is not specifically generated.
  • the mapping between the virtual page and the physical page is added in the TLB, but the entry is not required to be added to the TLB. Therefore, the cost of the entry can be saved and the occurrence of the TLB Miss can be reduced.
  • the N is 2 to the power of M, and M is greater than or equal to 1;
  • the large page number of the virtual address is obtained by shifting the virtual page number of the virtual address to the right by M bits; and/or the offset of the virtual address is obtained by intercepting the last M bits of the virtual page number of the virtual address. .
  • the specific N is used to realize the address operation by shifting and intercepting, and the relatively complicated operations such as multiplication and division are not required, so that the processing efficiency of the processing chip can be improved.
  • a processing chip embodiment is further provided, where the processing chip includes: a page table cache TLB and a cache control unit;
  • a page table is stored in the page table cache, and the entry of the page table includes at least one combination table entry, where the combination table entry includes a virtual large page number, a bit vector field, and a physical large page number, wherein the virtual table number
  • the large page number is an identifier of N consecutive virtual pages
  • the bit vector field includes N bits
  • the N bits are in one-to-one correspondence with the N consecutive virtual pages
  • the N bits are respectively used Identifying a page table existence state of the N consecutive virtual pages, the physical large page number being the N consecutive virtual The identifier of the N consecutive physical pages corresponding to the page;
  • the cache control unit includes a first input end, a first output end, a second input end, and a second output end; the first input end is configured to receive a virtual address; and the second input end is configured to connect the page a table cache, the second input is configured to connect to the page table cache, and the second output is configured to output a result of the entry of the entry;
  • the cache control unit is configured to receive, by the first input end, the virtual address, calculate a virtual large page number of the virtual address, and an offset of a virtual page to which the virtual address belongs in the virtual large page
  • the virtual large page number of the virtual address is obtained by dividing the virtual page number to which the virtual address belongs by N; the offset of the virtual page to which the virtual address belongs is within the virtual large page by the virtual address
  • the associated virtual page number is obtained by dividing N by the remainder; the N is an integer greater than 1;
  • the combined page table is accessed by the first output terminal and the access result is received by the second input, according to the access
  • it is determined whether the virtual large page number of the virtual address is the same as the virtual large page number in the combined entry included in the TLB, and determining a virtual page in the bit vector field in the combined entry and the virtual address belongs to Whether the corresponding bit is a predetermined value; if the two determination results are all, determining that the physical page number corresponding to the virtual address is: a product of
  • the entry of the page table stored in the page table cache includes at least one independent entry, where the independent entry includes a virtual large page number, an offset within the virtual large page, and a physical large a page number and an offset within the physical large page, wherein the virtual large page is composed of N consecutive virtual pages, the virtual large page number being an identifier of the N consecutive virtual pages, the virtual large page
  • the internal offset is an offset from the first virtual page number of the virtual large page number of the independent entry, the physical large page being N consecutive of the N consecutive virtual pages a physical page number, where the physical large page number is an identifier of N consecutive physical pages corresponding to the N consecutive virtual pages, and the physical large page offset is a physical value relative to the independent entry
  • the cache control unit is further configured to determine, according to the access result, whether a virtual large page number of the virtual address is the same as a virtual large page number in the independent entry included in the TLB, and determine the independent entry.
  • the virtual large page offset and the virtual page to which the virtual address belongs are within the virtual large page If the two determination results are the same, determining that the physical page number corresponding to the virtual address is: the product of the physical large page number of the independent entry and the N, and then The sum of the offsets within the physical large page of the independent entry.
  • the cache control unit is further configured to determine, in the bit vector field in the combination table entry, a bit corresponding to the virtual page to which the virtual address belongs, which is a non-predetermined value, and The offset of the virtual large page in the independent table item is different from the offset of the virtual page to which the virtual address belongs in the virtual large page
  • the combination table item further includes If the item is available for the address of the address prediction, if it is determined that the virtual large page number of the virtual address is the same as the virtual large page in the combination entry, and the combination table item is included to represent the combination table
  • the item can be used for the address of the address prediction, and then the predicted page number is determined to be fetched by the predicted page, and the page table movement is performed; the predicted page number is: the physical large page number in the combined table item and the The product of N, and the sum of the offsets of the virtual pages to which the virtual address belongs within the virtual large page.
  • the cache control unit further includes a third input end, where the third input end is configured to receive a result of moving the page table
  • the cache control unit is further configured to: if the result of the page table movement indicates that the predicted page is correct, use the first output end to associate the bit vector field in the combined table item with the virtual address The bit corresponding to the offset of the page within the virtual large page is modified to the predetermined value.
  • the cache control unit is further configured to: after the performing the page table movement, if the result of the page table movement indicates that the predicted page number is incorrect, pass the first output unit An identifier bit for indicating that the combined entry is not available for address prediction is set in the combined entry in the page table cache.
  • the cache control unit is further configured to: in the page table cache, by the first output unit, after determining that the result of the page table movement indicates that the predicted page number is incorrect A new independent entry is added, and the new independent entry includes: a virtual large page number, an offset within the virtual large page, a physical large page number, and an offset within the physical large page;
  • the virtual large page of the new independent entry is composed of N consecutive virtual pages, and the virtual large page number of the new independent entry is obtained by dividing the virtual page number of the virtual address by N.
  • the virtual large page offset of the new independent entry is divided by the virtual page number to which the virtual address belongs by N.
  • the result of the page table movement is a real physical page number corresponding to the virtual address;
  • the physical large page number of the new independent entry is obtained by dividing the real physical page number by N, the new independent
  • the physical large intrapage offset of the entry is obtained by dividing the real physical page number by N.
  • the cache control unit is further configured to: if the physical page number corresponding to the virtual address is not successfully determined by the TLB, perform page table movement to determine a real physical page corresponding to the virtual address. Number; determining a target entry to be added, the target entry includes: a virtual large page number, a virtual large page offset, a physical large page number, and a physical large page offset; wherein the target table The virtual large page of the item is composed of N consecutive virtual pages, and the virtual large page number of the target entry is obtained by dividing the virtual page number of the virtual address by N, and the target entry is virtualized.
  • the in-page offset is obtained by dividing the virtual page number to which the virtual address belongs by N;
  • the result of the page table moving is the real physical page number corresponding to the virtual address;
  • the physical large page of the target entry The number is obtained by dividing the real physical page number by N, and the physical large page offset of the target entry is obtained by dividing the real physical page number by N;
  • the target combination table is The item includes: a virtual large page number, a bit vector field, and a physical large page number; the virtual large page number of the target combination table item is equal to the virtual large page number of the independent table item, and the target combination table item is physically large.
  • the page number is equal to the physical large page number of the independent entry, and the bit corresponding to the virtual page to which the virtual address belongs in the bit vector field in the target combination entry is the predetermined value, and the target combination entry is Ratio of the bit vector field corresponding to the virtual page of the independent table
  • the target entry is added to the page table cache by the first output unit as a new independent entry.
  • the cache control unit is configured to: if the N is 2 a power, M is greater than or equal to 1; then the virtual page number of the virtual address is shifted to the right by M bits to obtain a large page number of the virtual address; and/or, by intercepting the virtual page number of the virtual address, M The bit gets the offset of the virtual address.
  • FIG. 1 is a schematic diagram of an address translation structure according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a page table according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of an address translation structure according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of an address mapping relationship according to an embodiment of the present invention.
  • FIG. 5A is a schematic structural diagram of an entry according to an embodiment of the present invention.
  • FIG. 5B is a schematic structural diagram of an entry according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of an address mapping relationship according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of an entry according to an embodiment of the present invention.
  • FIG. 8A is a schematic diagram of an address mapping relationship according to an embodiment of the present invention.
  • FIG. 8B is a schematic structural diagram of an entry according to an embodiment of the present invention.
  • FIG. 8C is a schematic structural diagram of an entry according to an embodiment of the present invention.
  • FIG. 9 is a schematic flowchart of a method according to an embodiment of the present invention.
  • FIG. 10 is a schematic structural diagram of a processing chip according to an embodiment of the present invention.
  • FIG. 11 is a schematic structural diagram of a TLB in a processing chip according to an embodiment of the present invention.
  • the address used by the program during the execution of the program is a virtual address.
  • the operating system loads a program into memory, it allocates the available physical address space for the program, namely: physical memory space;
  • the operating system maps the virtual addresses used in the program to specific physical addresses, in units of pages.
  • the physical address space is divided into pages.
  • the program's own virtual address space is also divided into pages.
  • the pages corresponding to the virtual address and the physical address are sequentially numbered as page numbers.
  • the so-called address mapping is to map a virtual page to a physical page; that is, replace the upper bits of the virtual address with the upper bits of the physical address.
  • both the virtual address and the physical address are 64 bits, and the corresponding page occupies 4 KB; the virtual address and the lower 12 bits of the physical address (ie Addr[11:0] ) remains unchanged, ie the lower 12 bits of the virtual address and the lower 12 bits of the physical address are identical. This is because these 12 bits are used to represent the offset within the 4KB page.
  • the upper part of the virtual address and physical address, the Addr[63:12] field is called VPN in the virtual address and PFN in the physical address.
  • the lower part of the address, the Addr[11:0] field is called the Offset part. It can be seen that during the mapping process, the Offset portion of the address remains unchanged.
  • the operating system establishes a complete mapping from virtual address to physical address for the program. This mapping relationship is stored in a data structure called a "Page Table". Each entry in the page table contains the corresponding VPN information and PFN information.
  • the address translation in the processor is usually done by hardware, and the hardware that performs this function is called TLB, which is a Translation Lookaside Buffer, in which the above page table can be stored.
  • the general structure of a page table in a TLB contains 32 entries.
  • the structure of each entry in the TLB is similar to the structure of each entry in the page table.
  • the TLB can be viewed as a cache of page tables, storing a portion of the complete page table.
  • VPN is the high position of the virtual address.
  • a virtual address can be represented as Vir_Addr[63:0].
  • the VPN is Vir_Addr[63:12]
  • the VPN does not contain the lower 12 bits of the address.
  • the PFN is the high bit of the physical address.
  • the physical frame physical frame, rather than the physical page, is caused by historical reasons and will not be described in detail here.
  • the address can be expressed as Phy_Addr[63:0].
  • the PFN is Phy_Addr[63:12]. It can be seen that the PFN also does not contain the lower 12 bits of the address.
  • the processor when the processor performs an address fetch operation or a fetch operation, the corresponding virtual address is sent to the TLB.
  • the TLB intercepts the VPN from the virtual address and compares the entries in the VPN and the TLB. If the VPN in one of the entries is the same, the PFN field in the entry is output, which is considered to be a TLB hit. If the VPN without an entry is the same as the VPN to be converted, it is considered that a TLB miss occurs.
  • TLB Miss When the TLB Miss, you need to search the PFN corresponding to the VPN from the page table, and then fill the VPN and PFN information into the TLB (usually overwrite an existing entry). This process is called a page. Table Table Walk.
  • the Page Table Walk task can be done automatically by hardware or by the operating system.
  • the multi-level TLB structure In order to reduce the frequency of TLB Miss, in addition to increasing the capacity of the TLB, a multi-level TLB structure has emerged. Among them, the multi-level TLB structure, although the number of stages increases, although the number of entries is more, the operating frequency is greatly reduced, and the delay time is long. In addition to the multi-level TLB structure, another method is to increase the space occupied by the page. For example, if you use a 2MB page, the number of Pages used by the same program will be reduced, and the number of entries in the page table will be reduced, so the probability of TLB Miss can be reduced to some extent.
  • the current processor can convert the virtual and real addresses through the TLB, but the capacity of the TLB is limited, resulting in a high TLB Miss overhead. Therefore, embodiments of the present invention aim to provide a method for reducing TLB Miss and its overhead.
  • the embodiment of the present invention proposes a page table structure cached in a new TLB, so that the entry of one page table is used for address translation of multiple pages, and the probability of increasing TLB Hit is reduced under the premise that the entry is fixed.
  • the embodiment of the present invention further provides a method for predicting a physical address based on the structure of a page table item according to an embodiment of the present invention.
  • the page table search operation may still be performed. Use the predicted address for the memory access operation. This fetch operation and page table move operation can be processed in parallel. If the prediction is correct, the processing time is reduced; if the prediction is wrong, the memory access operation is restarted after the TLB Miss is completed, and the delay is the same as the delay when the method of the embodiment of the present invention is not used.
  • the specific implementation plan includes the following aspects:
  • the left side is the four virtual pages of VPN0 ⁇ VPN3, and the right side is the physical page of PFN0 ⁇ 7, and the mapping relationship between the virtual page and the physical page is as indicated by the arrow;
  • an entry may be used to represent the two mapping relationships.
  • a 1-bit format (Fmt) field (Format) is added to the entry of the page table cached in the TLB, which is used to indicate the format of the entry; a 1-bit prediction (Pred) is also added.
  • Fmt field When the Fmt field is 0, it indicates that the entry is in the traditional format. In this case, the Pred field is also 0, that is, it does not participate in the prediction of the physical address. In this case, only one VPN mapping can be configured for one TLB entry. To 1 PFN. When the Fmt field is 1, it indicates a new format proposed by the embodiment of the present invention. At this time, one TLB entry can map multiple VPNs.
  • Fmt and Pred are mainly used to guide the prediction of physical addresses, and a detailed description will be given in the section regarding physical address prediction in the subsequent embodiments.
  • the fourth box “10" from the left is the binary code of "2" of VPN2, which is the offset of the large virtual page of "VPN0/4", and the last cell is "10".
  • the binary code of "2" for PFN2 is its offset of the large physical page of "PFN0/4".
  • Large virtual pages and large physical pages can be logical concepts. When paging the storage space, it is still used. The original scheme for paging does not have to expand the address space of a single page.
  • the next entry in Figure 5A is used to indicate the mapping between VPN1 and PFN1. The principle is the same as that of VPN2 to PFN2.
  • the entry of FIG. 5B includes a “BitVec” field having 4 bits, namely: 4 bits; each bit corresponds to a VPN to PFN mapping; for example, the second bit from the left is 1, indicating a mapping relationship between VPN2 and PFN2. The third bit from the left is 1, indicating the mapping relationship between VPN1 and PFN1. The other bits of 0 indicate that the mapping relationship between VPN3 and PFN3 and VPN0 to PFN0 is uncertain.
  • Figure 5B is an example of an example.
  • the example is used to indicate the application scenario of the mapping between the VPN and the PFN. Therefore, the value of BitVec is BitVec[3:0], and the large virtual page and Large physical pages are represented in the table entries as "VPN0/4" and "PFN0/4", that is, "0/4" here.
  • TLB entry can map four VPNs.
  • the embodiment of the present invention is not limited to the case where one TLB entry can map four VPNs.
  • the description is only for convenience of description; one TLB entry is used to map other special VPNs, and the principle is the same. Narration.
  • the VPN field can be divided into two parts, as shown in the dotted line frame of the upper row of FIG. 5A, one part represents the lowest 2 bits "10" of the original VPN field, and the other part represents the high position except the lowest 2 bits. Bit "VPN0/4".
  • the PFN field can also be divided into two parts, representing the lowest 2 bits and the remaining high bits.
  • VPN0 to VPN3 are four virtual pages in which virtual addresses are consecutive
  • PFN0 to PFN3 are four physical pages in which physical addresses are consecutive
  • a virtual large page number is assumed to represent four consecutive virtual pages.
  • VPN0/4 The large page number of VPN0 is "VPN0/4", that is, VPN0 is divided by 4, and the offset is "00": VPN0/4 takes the rest; other virtual pages and physical pages are calculated in the same way. Narration.
  • the virtual page number of the address ie, the virtual page number (virPageNum)
  • pageSize page size
  • mapping from VPN1 to PFN1 Taking the mapping from VPN1 to PFN1 as an example, first enter the virtual address virAddr, calculate virAddr/pageSize, and get virPageNum, where virPageNum is VPN1; then calculate virPageNum/4 to get VPN0/4, and use VPN0/4 to look up the table. The entry shown in 5B; calculate virPageNum%4 to get pageIdx.
  • BitVec[pageIdx] corresponding to pageIdx is 1 is BitVec[1] corresponding to the 2nd digit from the right, and the found value is 1, thus indicating TLB Hit;
  • Figure 5B The physical page number in the table shown is PFN0/4, so the physical page number corresponding to virPageNum is offset 1 in PFN0/4, that is, PFN1. If the value of BitVec[pageIdx] is 0, it indicates that TLB Miss has occurred. For example, the first digit from the left of BitVec[3] is 0. Therefore, TLB Miss occurs when VPN3 uses the entry shown in 5B.
  • the offset of VPN0 in VPN0/4 is different from the offset of PFN3 in PFN0/4. Therefore, the mapping from VPN0 to PFN3 cannot be combined with the previous mapping as shown in Figure 5B in a TLB entry.
  • the TLB entry represents the mapping, as shown in Figure 7.
  • mapping from the VPN0 to the PFN0 and the VPN1 to the PFN1 is in the entry of the TLB, and the address to be converted falls into the VPN2, and the TLB entry is missing. Mapping to VPN2. Then, at this time, you will encounter the situation of "big page hit, small page missing".
  • the Pred field is 1, that is, the entry of the TLB is allowed to be used for prediction, so the VPN2 is predicted to be mapped to PFN2, that is, the second bit from the left of the prediction FIG. 8B is 1, so that the table of FIG. 8B can be used.
  • the item gets the physical address of VPN2.
  • An embodiment of the present invention provides a method for accessing an entry in a page table cache TLB, as shown in FIG. 9, including:
  • the entry in the TLB includes at least one combination table entry, where the combination table entry includes a virtual large page number, a bit vector field, and a physical large page number, wherein the virtual large page number is N consecutive virtual numbers.
  • the physical large page number is an identifier of N consecutive physical pages corresponding to the N consecutive virtual pages;
  • VPN0/4 corresponds to a virtual large page number
  • PFN0/4 corresponds to a physical large page number
  • bit vector field corresponds to BitVec[3:0]
  • the previous Pred and Fmt fields are not in progress.
  • the address is predicted, it can be a non-essential field.
  • the value of N is 4, and it is also possible to take other values. Therefore, FIG. 5B should not be construed as an exclusive limitation of the embodiment of the present invention.
  • the virtual address virAddr calculate virAddr/pageSize, get the virtual page number virPageNum; then calculate virPageNum/N to get the virtual large page number in Figure 5B for VPN0/4, where N is 4, use virtual large page number Check the entry.
  • VPN2 is a virtual page with a virtual page number of 2
  • the corresponding virtual large page number is 0,
  • the offset in the virtual large page is 2
  • PFN2 is the physical page number 2.
  • the physical page has a corresponding physical large page number of 0 and an offset of 2 in the physical large page.
  • This step is a step for determining whether a combined entry Hit occurs.
  • the mapping between multiple virtual pages to physical pages is represented by using one entry.
  • the number of entries in the TLB can be multiplied, thereby increasing the probability of TLB hit and reducing the TLB. Miss, therefore, can reduce the processing delay of the program and improve the processing efficiency of the processing chip.
  • the previous steps 901-903 are that there is exactly one combination entry in the entry in the TLB, that is, a combination table entry indicates a mapping relationship between multiple virtual pages to physical pages;
  • a combination table entry indicates a mapping relationship between multiple virtual pages to physical pages;
  • an independent entry that only represents a mapping from a virtual page to a physical page.
  • the entry in the TLB includes at least one independent entry, and the independent entry includes a virtual large Page number, virtual large page offset, physical large page number, and physical large page offset, wherein the virtual large page is composed of N consecutive virtual pages, and the virtual large page number is the above N consecutive An identifier of the virtual page, wherein the offset within the virtual large page is an offset from a first virtual page number of the virtual large page number of the independent entry, wherein the physical large page is represented by the N consecutive virtual pages Corresponding N consecutive physical page configurations, wherein the physical large page number is an identifier of N consecutive physical pages corresponding to the N consecutive virtual pages, and the physical large page offset is relative to the above
  • the offset of the first physical page number of the physical large page number of the entry the method further includes:
  • the independent entry can be referred to FIG. 5A, and each row is an independent entry; in the above behavior example, the virtual large page number corresponds to VPN0/4, the physical large page number corresponds to PFN0/4, and the virtual large page offset
  • the quantity is "10" contained in the dotted line box on the left side, where "10” is the actual offset of the binary number is 2; the offset within the physical large page is "10" contained in the dotted line box on the right side, where "10" is The actual offset of the binary number is also 2.
  • This step may be caused by the fact that there is no hit in the combined table item; in the previous embodiment, BitVec[pageIdx] is 0, indicating that there is no hit in the combined entry, then it is possible to hit in the independent entry.
  • VPN0/4 is a hit, then if pageIdx is exactly the same as the first offset, then TLB Hit, directly determine that PFN0/4 is the physical large page number, to the physical large page.
  • the offset within the number is "10", that is, 2, which is the physical page number corresponding to the virtual address.
  • This step may also not be based on the hit combination table item scheme in the previous embodiment, and step 904 of this embodiment may exist independently.
  • the combination table item further includes the combination table item for indicating the above combination. Whether it can be used for the identification of address prediction.
  • the other two identifiers are used in the entry.
  • the identifier is used to indicate whether the entry format is a combination entry or an independent entry.
  • the format is used to represent Fmt.
  • This entry uses the format of Figure 5B or the format of Figure 5A; the other identifier is used to indicate whether the address can be used for address prediction.
  • the address can be used for address prediction.
  • this usually occurs.
  • Fmt is represented by the format of FIG. 5B
  • the value of Fmt can be represented by 0, or the value of 1 can be represented by 1 in advance, and the value of Fmt is 1; 0 or 1 to indicate that address prediction can be performed, which is also pre-agreed and can be Arbitrary agreement.
  • the combination table further includes an identifier for indicating whether the combined entry is available for address prediction, and the method further includes:
  • the calculated virtual large page number is VPN0/4, even if the virtual large page number is hit, if BitVec[pageIdx] is 3, then the small page does not hit;
  • the default BitVec[3] can be predicted, that is, the first digit from the left of BitVec in Figure 5B is 1, that is, the PFN0/4 is determined to be the physical large page number, and the offset is 3 in the physical large page number.
  • the physical page number corresponding to the virtual address. This prediction may be correct or incorrect.
  • the memory access operation can be performed first; in addition, in order to determine that the predicted physical page number is not correct, the result of the page table movement can be performed. It is determined that the page table movement is an operation process of checking the complete page table, and usually requires multiple memory accesses, which is slower than performing the memory access after the address prediction, and is not described in this embodiment.
  • the correctness of the address prediction can be determined by the result of the page table movement. After the completion, the table table entries in the TLB can be updated.
  • the method further includes:
  • the correct situation is predicted by using the combined page table; in this case, only the value in the bit vector of the combined table item needs to be modified; for example, if the prediction is that the VPN3 is correct, then The first bit from the left in Fig. 5B is modified to 1.
  • the above methods also include:
  • a new independent entry is added, and the new independent entry includes: a virtual large page number, an offset within the virtual large page, a physical large page number, and an offset within the physical large page;
  • the virtual large page of the new independent entry is composed of N consecutive virtual pages, and the virtual large page number of the new independent entry is obtained by dividing the virtual page number of the virtual address by N, and the new independent table is obtained.
  • the virtual large page offset of the item is obtained by dividing the virtual page number to which the virtual address belongs by N remainder; the result of moving the page table is the real physical page number corresponding to the virtual address; the physical size of the new independent entry is large
  • the page number is obtained by dividing the above-mentioned real physical page number by N, and the physical large-page offset of the new independent entry is obtained by dividing the above-mentioned real physical page number by N.
  • This step is to add a separate entry.
  • the structure of the independent entry is the same.
  • the target entry includes: a virtual large page number, a virtual large page offset, a physical large page number, and a physical large page offset; wherein the target entry is virtual large
  • the page is composed of N consecutive virtual pages, and the virtual large page number of the target entry is obtained by dividing the virtual page number of the virtual address by N, and the virtual large page offset of the target entry is determined by the virtual
  • the virtual page number to which the address belongs is obtained by dividing N;
  • the result of moving the page table is the real physical page number corresponding to the virtual address;
  • the physical large page number of the target entry is divided by the real physical page number by N Rounding out, the physical large page offset of the above target entry is obtained by dividing the above real physical page number by N;
  • the independent entry is the same as the virtual large page number of the target entry, and the physical large page number of the independent entry is the same as the physical large page number of the target entry, and the independent entry is The difference between the offset within the virtual large page and the offset within the virtual large page of the target entry is equal to the physical large intra-page offset of the independent entry and the physical large intra-page offset of the target entry.
  • the target combination table includes: a virtual large page number, a bit vector field, and a physical large page number; the virtual of the target combination table item
  • the large page number is equal to the virtual large page number of the independent entry
  • the physical large page number of the target combination entry is equal to the physical large page number of the independent entry
  • the virtual address in the bit vector field in the target combination entry The bit corresponding to the virtual page is the predetermined value
  • the bit corresponding to the virtual page of the independent entry in the bit vector field in the target combination table entry is the predetermined value
  • the virtual page of the independent entry Page number N is the product of the above-described physical page number of large independent entry, and then separate within said large page table entry physical offsets and;
  • N is 2 to the power of M, and M is greater than or equal to 1;
  • the calculating the large page number of the virtual address and the offset of the virtual address including:
  • the large page number of the virtual address is obtained by shifting the virtual page number of the virtual address to the right by M bits; and/or the offset of the virtual address is obtained by intercepting the last M bits of the virtual page number of the virtual address.
  • N 4 and M is 2, so the virtual large page number can be the virtual page number to intercept other bits except the last 2 bits; the offset is the last 2 bits; if applied to the calculation virtual page at the same time No., assuming that the page address space is 2 to the power of J, then the large page number is the other bits except the last J+2, and the offset is 2 bits after the large page number.
  • Other values are the same, and are not described in this embodiment.
  • the embodiment of the present invention further provides a processing chip.
  • the processing chip includes: a page table cache 1001 and a cache control unit 1002.
  • the cache control unit 1002 may further have an input and an output interface, and the input portion may be input.
  • the virtual address, the result of the page table movement, etc.; the output may have a predicted page (corresponding to the predicted address), a physical page (corresponding to the physical address), and the like;
  • the page table cache 1001 stores a page table, and the table item of the page table includes at least one combination table item, where the combination table item includes a virtual large page number, a bit vector field, and a physical large page number, wherein the virtual large page number
  • the bit vector field includes N bits, the N bits are corresponding to the N consecutive virtual pages, and the N bits are used to identify the N consecutive virtual a page table existence state of the page, wherein the physical large page number is an identifier of N consecutive physical pages corresponding to the N consecutive virtual pages;
  • the cache control unit 1002 includes a first input end, a first output end, a second input end, and a second output end.
  • the first input end is configured to receive a virtual address
  • the second input end is configured to connect to the page table cache 1001.
  • the second input end is configured to connect to the page table cache 1001, and the second output end is configured to output a result of accessing the entry;
  • the cache control unit 1002 is configured to receive, by using the first input end, the virtual address, and calculate an offset of the virtual large page number of the virtual address and the virtual page of the virtual address in the virtual large page;
  • the virtual large page number is obtained by dividing the virtual page number to which the virtual address belongs by N; the offset of the virtual page belonging to the virtual address in the virtual large page is divided by the virtual page number to which the virtual address belongs by N.
  • N is an integer greater than 1; accessing the combined page table by using the first output end, and receiving an access result by using the second input end, determining, according to the access result, a virtual large page number of the virtual address and the TLB included Whether the virtual large page numbers in the combined table items are the same, and determining whether a bit corresponding to the virtual page to which the virtual address belongs in the bit vector field in the combination table item is a predetermined value; if both the determination results are yes, then Determining that the physical page number corresponding to the virtual address is: a product of the physical large page number in the combination table item and the N, and then Quasi virtual page address belongs in said large virtual page offset and, via the The second output terminal outputs the physical page number corresponding to the virtual address.
  • FIG. 9 there is also a case where there is a single table item indicating only a mapping relationship between a virtual page and a physical page.
  • a TLB Hit is generated.
  • the entry of the page table stored in the page table cache 1001 includes at least one independent entry, where the independent entry includes a virtual large page number, a virtual large page offset, a physical large page number, and The physical large page offset, wherein the virtual large page is composed of N consecutive virtual pages, and the virtual large page number is an identifier of the N consecutive virtual pages, and the virtual large page offset is relative to The offset of the first virtual page number of the virtual large page number of the independent entry, wherein the physical large page is composed of N consecutive physical pages corresponding to the N consecutive virtual pages, and the physical large page number is The identifier of the N consecutive physical pages corresponding to the N consecutive virtual pages, where the offset within the physical large page is an offset from the first physical page number of the physical large page number of the independent entry ;
  • the cache control unit 1002 is further configured to determine, according to the foregoing access result, whether the virtual large page number of the virtual address is the same as the virtual large page number in the independent entry included in the TLB, and determine a virtual large page in the independent entry. Whether the internal offset is the same as the offset of the virtual page to which the virtual address belongs in the virtual large page; if the two determination results are the same, the physical page number corresponding to the virtual address is determined as: the independent entry The product of the physical large page number and the above-mentioned N, and then the sum of the physical large page offsets of the above independent entries.
  • the combination entry may be used to predict the physical page number. Therefore, in the case of TLB Miss, there is a case where the virtual large page number Hit is in the combination table.
  • the combined entry identifier is The address prediction may be performed as follows: further, the cache control unit 1002 is further configured to determine, in the bit vector field in the combination table item, that the bit corresponding to the virtual page to which the virtual address belongs is an undetermined value, and The offset of the virtual large page in the independent entry is different from the offset of the virtual page to which the virtual address belongs in the virtual large page, and the combination entry further includes whether the combined entry is available for use.
  • the combination table item After determining the identifier bit of the address prediction, if it is determined that the virtual large page number of the virtual address is the same as the virtual large page in the combination entry, and the combination table item includes an identifier bit for indicating that the combination table item is available for address prediction. , determining that the predicted page number is fetched by using the above predicted page, and performing page table movement; the predicted page number is: the physical size in the combination table item Page The sum of the number and the above-mentioned N, and the offset of the virtual page belonging to the virtual address in the virtual large page.
  • the embodiment of the present invention further provides a solution for modifying the entry, as follows: further, the cache control unit 1002 further includes a third input end, where the third input end is used. The result of receiving the page table movement;
  • the cache control unit 1002 is further configured to: if the result of the page table movement indicates that the predicted page is correct, the virtual output page in the bit vector field in the combination table and the virtual address belong to the virtual page by the first output end The bit corresponding to the offset within the page is modified to the above predetermined value.
  • a new mapping between a virtual page and a physical page is added to the TLB, but no new entry is added, which can save the cost of the entry in the TLB.
  • the embodiment of the present invention further provides a modification of the entry, as follows: further, the cache control unit 1002 is further configured to: after the execution of the page table movement, The result of the above page table movement indicates that the predicted page number is incorrect, and the above-mentioned combination table item in the page table cache 1001 is set by the first output unit to set an identifier bit for indicating that the combination table item is not available for address prediction.
  • the combined entry of the error address prediction is identified as unavailable for address prediction, so that the situation of address prediction error reoccurring can be avoided.
  • the embodiment of the present invention further provides an implementation scheme of adding a separate entry, as follows.
  • the cache control unit 1002 is further configured to determine the movement of the page table. The result indicates that after the predicted page number is incorrect, a new independent entry is added to the page table cache 1001 by using the first output unit, and the new independent entry includes: a virtual large page number, a virtual large page offset, and a physical Large page number and offset within the physical large page;
  • the virtual large page of the new independent entry is composed of N consecutive virtual pages, and the virtual large page number of the new independent entry is obtained by dividing the virtual page number of the virtual address by N, and the new independent table is obtained.
  • the virtual large page offset of the item is obtained by dividing the virtual page number to which the virtual address belongs by N remainder; the result of moving the page table is the real physical page number corresponding to the virtual address; the physical size of the new independent entry is large
  • the page number is obtained by dividing the above-mentioned real physical page number by N, and the physical large-page offset of the new independent entry is obtained by dividing the above-mentioned real physical page number by N.
  • a case may be saved, as follows: Further, the cache control unit 1002, And if the physical page number corresponding to the virtual address is not successfully determined by the foregoing TLB, performing a page table move to determine a real physical page number corresponding to the virtual address; determining a target entry to be added, the target entry includes: virtual Large page number, virtual large page offset, physical large page number, and physical large page offset; wherein the virtual large page of the target entry is composed of N consecutive virtual pages, and the target entry is virtual The large page number is obtained by dividing the virtual page number of the virtual address by N, and the virtual large page offset of the target entry is obtained by dividing the virtual page number to which the virtual address belongs by N; the page table The result of the movement is the real physical page number corresponding to the virtual address; the physical large page number of the target entry is obtained by dividing the real physical page number by N, and the target entry
  • the independent entry is the same as the virtual large page number of the target entry, and the physical large page number of the independent entry is the same as the physical large page number of the target entry, and the independent entry is The difference between the offset within the virtual large page and the offset within the virtual large page of the target entry is equal to the physical large intra-page offset of the independent entry and the physical large intra-page offset of the target entry.
  • the difference between the foregoing independent entry and the target entry in the page table cache 1001 is a target combination entry, where the target combination entry includes: a virtual large page number, a bit vector field And a physical large page number; the virtual large page number of the target combination table item is equal to the virtual large page number of the independent table item, and the physical large page number of the target combination table item is equal to the physical large page number of the independent table item, the foregoing target
  • the bit corresponding to the virtual page to which the virtual address belongs in the bit vector field in the combination table entry is the predetermined value, and the bit vector field in the target combination table entry corresponds to the virtual page of the independent entry.
  • the bit is the predetermined value; the page number of the virtual page of the independent entry is the product of the physical large page number of the independent entry and the N, and the offset of the physical large page offset of the independent entry;
  • the target entry is added to the page table cache 1001 by the first output unit as a new independent entry.
  • the physical page number corresponding to the virtual address is not determined by the TLB, and the virtual page number to the physical page number required for the virtual address is not stored in the TLB.
  • the page number Hit case is not determined by the TLB, and the virtual page number to the physical page number required for the virtual address is not stored in the TLB.
  • the cache control unit 1002 is configured to obtain the virtual address by shifting the virtual page number of the virtual address to the right by M bits if the N is 2 to the power of M, and M is greater than or equal to 1.
  • the large page number; and/or, the offset of the virtual address is obtained by intercepting the last M bits of the virtual page number of the virtual address.
  • the shift operation can be implemented by using a shift register, and whether the same can be realized by a logic gate circuit. Each function in the above steps can be implemented by a logic circuit.
  • the specific logic circuit layout has various types, and the embodiment of the present invention does not uniquely.
  • the embodiment of the present invention further provides another processing chip, and the TLB and the control structure thereof included in the processing chip, as shown in FIG. 11, mainly include: Match Logic and Control Logic ( Control Logic); these two parts can correspond to the cache control unit 1002 in the structure shown in FIG. 10;
  • the input content mainly includes: Page Table Walk Result and Virtual Address; these two are not necessarily present, and the subsequent processes are described.
  • Item0 to ItemN indicate respective entries in the TLB. This portion can correspond to the cache in the structure shown in FIG.
  • Virtual Address is the input signal of the TLB, indicating the virtual address that needs to be converted.
  • Each TLB entry has a matching logic (Match Logic). Based on the input virtual address and the content of the TLB entry, the Match Logic uses the method of the previous method to calculate whether the virtual address and the TLB entry are Matches, if there is no match, whether information can be predicted, if it matches, the PFN information (Info) of the entry is output, if it does not match, but the predicted PFN information can be output.
  • Match Logic uses the method of the previous method to calculate whether the virtual address and the TLB entry are Matches, if there is no match, whether information can be predicted, if it matches, the PFN information (Info) of the entry is output, if it does not match, but the predicted PFN information can be output.
  • the TLB has a Control Logic that outputs TLB_Match_Flag (used to indicate whether the physical address is valid), TLB_Phy_Addr (physical address), TLB_Pred_Flag (used to indicate whether the predicted address is valid), and Pred_Phy_Addr (predicted) according to the output of each TLB entry. Physical address) These four signals. If TLB Hit then only the first two, if the predicted address can only have the last two.
  • TLB_Match_Flag If TLB_Match_Flag is valid, it indicates TLB Hit, at which time TLB_Phy_Addr represents the physical address corresponding to the input virtual address. If TLB_Match_Flag is invalid but TLB_Pred_Flag is valid, then Pred_Phy_Addr indicates the predicted physical address.
  • Control Logic updates the entries in the TLB according to the results of the Page Table Walk and the contents of the current entries.
  • the physical address may be a physical page number, or may be a more accurate physical address calculated according to the physical page number and the physical page offset, and corresponding to different address access management system settings.
  • the embodiment of the present invention is not limited to this.
  • the technical content in the foregoing embodiment of the processing chip can be referred to the description in the method embodiment, and details are not described herein again.
  • the storage medium may be a read only memory, a magnetic disk or an optical disk or the like.

Abstract

一种页表缓存TLB中表项的访问方法，及处理芯片，其中方法包括：所述表项包括至少一个组合表项，所述组合表项包括虚拟大页号，位向量字段以及物理大页号，其中，所述虚拟大页号为N个连续的虚拟页的标识，所述位向量字段包含N个比特，所述N个比特和所述N个连续的虚拟页一一对应，且所述N个比特分别用来标识所述N个连续的虚拟页的页表存在状态，所述物理大页号为所述N个连续的虚拟页所对应的N个连续的物理页的标识。使用一个表项表示了多个虚拟页到物理页的映射，在页表长度固定的情况下，可以将TLB中表项的数量成倍增加，从而提高TLB命中概率，减少TLB Miss，因此可以降低程序处理延迟提高处理芯片的处理效率。

Description

一种页表缓存TLB中表项的访问方法，及处理芯片 技术领域
本发明涉及信息技术领域，特别涉及一种页表缓存TLB中表项的访问方法，及处理芯片。
背景技术
程序员编写程序时，需要约定代码段的起始地址和数据段的起始地址。有了这些地址，才能够知道每条指令的地址和每个数据的地址。有了指令的地址，跳转指令和函数调用指令才能够执行；有了数据的地址，访存指令才可以执行。
但是，不同的程序员在编写各自的程序的时候，以及一个程序员在编写不同的程序的时候，如何约定各个程序的代码段起始地址和数据段起始地址就成为比较关键的问题。为了解决这个问题，引入了虚拟地址(Virtual Address)与物理地址(Physical Address)的概念和技术。
有了虚拟地址技术后，程序员在编写程序的时候，所看到的都是虚拟地址。此时，任何一个程序的代码段起始地址和数据段起始地址都是一个固定的数值。即，一个程序的代码段起始地址和另一个程序的代码段起始地址是相同的；同理，一个程序的数据段起始地址和另一个程序的数据段起始地址也是相同的。因此，程序员无需自己去约定或决定它们的取值。
而在程序真正开始执行的时候，操作系统(Operating System，OS)会寻找当前可用的物理地址，并将程序所用的虚拟地址映射到这些物理地址。因此，多个程序同时执行时，它们实际上处于不同的物理地址，从而保证了程序的正常执行。
内存中的物理地址空间是以页(Page)为单位进行组织的，操作系统在对内存管理时，会将物理地址空间划分为连续的页面。虚拟地址空间也会被划分为以页为单位的连续页面。虚拟地址由两部分构成，即虚拟页号(Virtual Page Number，VPN)和页内偏移(Offset)，相应的，物理地址也由两部分构成，即物理框架号(也称为物理页号)(Physical Frame Number，PFN)以及页内偏移(Offset)。因此，虚拟地址映射到这些物理地址是将一个虚拟地址的页编号 映射到一个物理地址的页编号的过程，这种虚拟页号到物理页号的映射关系是采用页表(Page Table)表项的方式保存在内存中。为了加快虚拟页号到物理页号的转换过程，在处理芯片的缓存中划出一部分空间，即快速转换缓冲区(Translation Lookaside Buffer，TLB)来存储部分页表表项。
由于缓存空间非常有限，存储在其中的页表表项的数目受到限制，采用以上页表在实现虚拟地址向物理地址转换过程中，大量出现无法在缓存中的页表中找到虚拟页号对应的物理页号的情况，即：称为TLB缺失(TLB Miss)，这将导致程序处理的严重延迟，进而导致处理芯片处理效率降低。
发明内容
本发明实施例提供了一种页表的使用方法，及处理芯片，用于降低TLB Miss的几率，降低程序处理延迟并提高处理芯片的处理效率。
一方面，提供了一种TLB中表项的访问方法的实施例，本实施例是TLB内的表项中正好有一个组合表项，即：用一个组合表项表示多个虚拟页到物理页的映射关系的情况；在这种情况下发生TLB命中(TLB Hit)的场景，具体如下：
所述TLB的表项包括至少一个组合表项，所述组合表项包括虚拟大页号，位向量字段以及物理大页号，其中，所述虚拟大页号为N个连续的虚拟页的标识，所述位向量字段包含N个比特，所述N个比特和所述N个连续的虚拟页一一对应，且所述N个比特分别用来标识所述N个连续的虚拟页的页表存在状态，所述物理大页号为所述N个连续的虚拟页所对应的N个连续的物理页的标识，所述方法包括：
接收虚拟地址，计算所述虚拟地址的虚拟大页号以及所述虚拟地址所属虚拟页在所述虚拟大页内的偏移量；所述虚拟地址的虚拟大页号由所述虚拟地址所属的虚拟页号除以N取整得到；所述虚拟地址所属虚拟页在所述虚拟大页内的偏移量由所述虚拟地址所属的虚拟页号除以N取余得到；所述N为大于1的整数；
确定所述虚拟地址的虚拟大页号与所述TLB包括的组合表项中的虚拟大 页号是否相同，并确定所述组合表项中的位向量字段中与所述虚拟地址所属虚拟页对应的比特是否为预定值；
若所述两个确定结果均为是，则确定所述虚拟地址对应的物理页号为：所述组合表项中的物理大页号与所述N的乘积，再与所述虚拟地址所属虚拟页在所述虚拟大页内的偏移量的和。
在本实施中，使用一个表项表示了多个虚拟页到物理页的映射，在页表长度固定的情况下，可以将TLB中表项的数量成倍增加，从而提高TLB命中概率，减少TLB Miss，因此可以降低程序处理延迟提高处理芯片的处理效率。
在一个可选的实现方式中，还有一种情况是有一个独立表项只表示一个虚拟页到物理页的映射关系，在这种情况下产生TLB Hit的情况，具体如下：
所述表项包括至少一个独立表项，所述独立表项包括虚拟大页号，虚拟大页内偏移量，物理大页号以及物理大页内偏移量，其中，所述虚拟大页由N个连续的虚拟页构成，所述虚拟大页号为所述N个连续的虚拟页的标识，所述虚拟大页内偏移量为相对于所述独立表项的虚拟大页号的第一个虚拟页号的偏移量，所述物理大页由所述N个连续的虚拟页所对应的N个连续的物理页构成，所述物理大页号为所述N个连续的虚拟页所对应的N个连续的物理页的标识，所述物理大页内偏移量为相对于所述独立表项的物理大页号的第一个物理页号的偏移量，所述方法还包括：
确定所述虚拟地址的虚拟大页号与所述TLB包括的独立表项中的虚拟大页号是否相同，并确定所述独立表项中的虚拟大页内偏移量与所述虚拟地址所属虚拟页在所述虚拟大页内的偏移量是否相同；
若所述两个确定结果均为相同，则确定所述虚拟地址对应的物理页号为：所述独立表项的物理大页号与所述N的乘积，再与所述独立表项的物理大页内偏移量的和。
本实施例提供了在存在不能使用组合表项表示虚拟页到物理页的映射关系的时候，使用独立表项来表示这种映射关系，作为组合表项的补充。
在一个可选的实现方式中，组合表项可能可以用于预测物理页号，因此TLB Miss的情况下，有一种在组合表中虚拟大页号Hit的情况，这种情况下如 果组合表项标识为可以进行地址预测，那么具体如下：
若所述组合表项中的位向量字段中与所述虚拟地址所属虚拟页对应的比特为非预定值，并且，所述独立表项中的虚拟大页内偏移量与所述虚拟地址所属虚拟页在所述虚拟大页内的偏移量不相同，所述组合表项还还包括用于表示所述组合表项是否可用于地址预测的标识位，所述方法还包括：
若所述虚拟地址的虚拟大页号与所述组合表项中的虚拟大页相同，且所述组合表项中包含用于表示所述组合表项可用于地址预测的标识位，则确定预测页号以所述预测页进行访存，并执行页表移动；所述预测页号为：所述组合表项中的物理大页号与所述N的乘积，再与所述虚拟地址所属虚拟页在所述虚拟大页内的偏移量的和。
本实施例在TLB Miss的情况下，使用组合表进行地址预测，并不一定需要等待页表移动结果，因此可以提高访存速度。
在一个可选的实现方式中，基于地址预测的结果正确性，如果地址预测正确，本发明实施例还提供了表项修改的方案，具体如下：在所述执行页表移动之后，所述方法还包括：
若所述页表移动的结果表明所述预测页号正确，将所述组合表项中的位向量字段中与所述虚拟地址所属虚拟页在所述虚拟大页内的偏移量对应的比特修改为所述预定值。
本实施例新增了一个虚拟页与物理页之间的映射关系到TLB中，但是并没有新增表项，可以节省TLB中表项开销。
在一个可选的实现方式中，基于地址预测的结果正确性，如果地址预测错误，本发明实施例还提供了表项的修改方案，具体如下：在所述执行页表移动之后，所述方法还包括：
若所述页表移动的结果表明所述预测页号错误，在所述组合表项中设置用于表示所述组合表项不可用于地址预测的标识位。
本实施例将发生错误地址预测的组合表项标识为不可用于地址预测，这样可以避免再次出现地址预测错误的情况。
在一个可选的实现方式中，基于地址预测的正确性，如果地址预测错误， 本发明实施例还提供了新增独立表项的实现方案，具体如下：在确定所述页表移动的结果表明所述预测页号错误之后，所述方法还包括：
新增新独立表项，所述新独立表项包含：虚拟大页号，虚拟大页内偏移量，物理大页号以及物理大页内偏移量；
其中，所述新独立表项的虚拟大页由N个连续的虚拟页构成，所述新独立表项的虚拟大页号由所述虚拟地址所述的虚拟页号除以N取整得到，所述新独立表项的虚拟大页内偏移量由所述虚拟地址所属的虚拟页号除以N取余得到；所述页表移动的结果为所述虚拟地址对应的真实物理页号；所述新独立表项的物理大页号由所述真实物理页号除以N取整得到，所述新独立表项的物理大页内偏移量由所述真实物理页号除以N取余得到。
本实施例提供了在TLB中新增独立表项的实现方案，该新独立表项属于不能与其他组合表项或者独立表项合并的情况，新独立表项可以替换掉TLB中的一个独立表项。
在一个可选的实现方式中，本发明实施例还提供了在发生TLB Miss的情况下，未进行地址预测，需要新增表项的情况下，可能节省表项的一种情况，若未通过所述TLB成功确定所述虚拟地址对应的物理页号，所述方法还包括：
执行页表移动确定所述虚拟地址对应的真实物理页号；
确定需要新增的目标表项，所述目标表项包含：虚拟大页号，虚拟大页内偏移量，物理大页号以及物理大页内偏移量；其中，所述目标表项的虚拟大页由N个连续的虚拟页构成，所述目标表项的虚拟大页号由所述虚拟地址所述的虚拟页号除以N取整得到，所述目标表项的虚拟大页内偏移量由所述虚拟地址所属的虚拟页号除以N取余得到；所述页表移动的结果为所述虚拟地址对应的真实物理页号；所述目标表项的物理大页号由所述真实物理页号除以N取整得到，所述目标表项的物理大页内偏移量由所述真实物理页号除以N取余得到；
若所述独立表项的虚拟大页号与所述目标表项的虚拟大页号相同，且所述独立表项的物理大页号与所述目标表项的物理大页号相同，且所述独立表项的虚拟大页内偏移量与所述目标表项的虚拟大页内偏移量的差值等于所述独立 表项的物理大页内偏移量与所述目标表项的物理大页内偏移量的差值，则合并所述独立表项和所述目标表项为目标组合表项，在所述目标组合表项中包含：虚拟大页号，位向量字段以及物理大页号；所述目标组合表项的虚拟大页号等于所述独立表项的虚拟大页号，所述目标组合表项的物理大页号等于所述独立表项的物理大页号，所述目标组合表项中的位向量字段中与所述虚拟地址所属虚拟页对应的比特为所述预定值，所述目标组合表项中的位向量字段中与所述独立表项的虚拟页对应的比特为所述预定值；所述独立表项的虚拟页的页号为所述独立表项的物理大页号与所述N的乘积，再与所述独立表项的物理大页内偏移量的和；
否则，新增所述目标表项为新的独立表项。
在本实施例中，未通过所述TLB成功确定所述虚拟地址对应的物理页号，是指TLB中没有存储虚拟地址所需要的虚拟页号到物理页号的对应关系，具体可以是没有发生虚拟大页号Hit的情况。本实施例在TLB中新增了虚拟页到物理页的对应关系，但是并不需要在TLB中新增表项，因此可以节省表项的开销，减少TLB Miss的发生。
在一个可选的实现方式中，为了进一步提高处理芯片的运算效率，所述N为2的M次方，M大于或等于1；
所述虚拟地址的大页号通过所述虚拟地址的虚拟页号右移M位得到；和/或，所述虚拟地址的偏移量通过截取所述虚拟地址的虚拟页号的后M位得到。
本实施例采用特定的N使得地址运算通过移位和截取实现，不需要进行乘法和除法这些相对复杂的运算，因此可以提高处理芯片的运算效率。
二方面，还提供了一种处理芯片实施例，所述处理芯片包括：页表缓存TLB和缓存控制单元；
所述页表缓存中存储有页表，所述页表的表项包括至少一个组合表项，所述组合表项包括虚拟大页号，位向量字段以及物理大页号，其中，所述虚拟大页号为N个连续的虚拟页的标识，所述位向量字段包含N个比特，所述N个比特和所述N个连续的虚拟页一一对应，且所述N个比特分别用来标识所述N个连续的虚拟页的页表存在状态，所述物理大页号为所述N个连续的虚拟 页所对应的N个连续的物理页的标识；
所述缓存控制单元包括第一输入端、第一输出端、第二输入端、第二输出端；所述第一输入端用于接收虚拟地址；所述第二输入端用于连接所述页表缓存，所述第二输入端用于连接所述页表缓存，所述第二输出端用于输出表项访问的结果；
所述缓存控制单元，用于通过所述第一输入端接收所述虚拟地址，计算所述虚拟地址的虚拟大页号以及所述虚拟地址所属虚拟页在所述虚拟大页内的偏移量；所述虚拟地址的虚拟大页号由所述虚拟地址所属的虚拟页号除以N取整得到；所述虚拟地址所属虚拟页在所述虚拟大页内的偏移量由所述虚拟地址所属的虚拟页号除以N取余得到；所述N为大于1的整数；通过所述第一输出端访问所述组合页表并通过所述第二输入端接收访问结果，依据所述访问结果确定所述虚拟地址的虚拟大页号与所述TLB包括的组合表项中的虚拟大页号是否相同，并确定所述组合表项中的位向量字段中与所述虚拟地址所属虚拟页对应的比特是否为预定值；若所述两个确定结果均为是，则确定所述虚拟地址对应的物理页号为：所述组合表项中的物理大页号与所述N的乘积，再与所述虚拟地址所属虚拟页在所述虚拟大页内的偏移量的和，通过所述第二输出端输出所述虚拟地址对应的物理页号。
在一个可选的实现方式中，所述页表缓存中存储的页表的表项包括至少一个独立表项，所述独立表项包括虚拟大页号，虚拟大页内偏移量，物理大页号以及物理大页内偏移量，其中，所述虚拟大页由N个连续的虚拟页构成，所述虚拟大页号为所述N个连续的虚拟页的标识，所述虚拟大页内偏移量为相对于所述独立表项的虚拟大页号的第一个虚拟页号的偏移量，所述物理大页由所述N个连续的虚拟页所对应的N个连续的物理页构成，所述物理大页号为所述N个连续的虚拟页所对应的N个连续的物理页的标识，所述物理大页内偏移量为相对于所述独立表项的物理大页号的第一个物理页号的偏移量；
所述缓存控制单元，还用于依据所述访问结果确定所述虚拟地址的虚拟大页号与所述TLB包括的独立表项中的虚拟大页号是否相同，并确定所述独立表项中的虚拟大页内偏移量与所述虚拟地址所属虚拟页在所述虚拟大页内的 偏移量是否相同；若所述两个确定结果均为相同，则确定所述虚拟地址对应的物理页号为：所述独立表项的物理大页号与所述N的乘积，再与所述独立表项的物理大页内偏移量的和。
在一个可选的实现方式中，所述缓存控制单元，还用于在确定所述组合表项中的位向量字段中与所述虚拟地址所属虚拟页对应的比特为非预定值，并且，所述独立表项中的虚拟大页内偏移量与所述虚拟地址所属虚拟页在所述虚拟大页内的偏移量不相同，所述组合表项还还包括用于表示所述组合表项是否可用于地址预测的标识位之后，若确定所述虚拟地址的虚拟大页号与所述组合表项中的虚拟大页相同，且所述组合表项中包含用于表示所述组合表项可用于地址预测的标识位，则确定预测页号以所述预测页进行访存，并执行页表移动；所述预测页号为：所述组合表项中的物理大页号与所述N的乘积，再与所述虚拟地址所属虚拟页在所述虚拟大页内的偏移量的和。
在一个可选的实现方式中，所述缓存控制单元还包括第三输入端，所述第三输入端用于接收页表移动的结果；
所述缓存控制单元，还用于若所述页表移动的结果表明所述预测页正确，通过所述第一输出端将所述组合表项中的位向量字段中与所述虚拟地址所属虚拟页在所述虚拟大页内的偏移量对应的比特修改为所述预定值。
在一个可选的实现方式中，所述缓存控制单元，还用于在所述执行页表移动之后，若所述页表移动的结果表明所述预测页号错误，通过所述第一输出单元在所述页表缓存中的所述组合表项中设置用于表示所述组合表项不可用于地址预测的标识位。
在一个可选的实现方式中，所述缓存控制单元，还用于在确定所述页表移动的结果表明所述预测页号错误之后，通过所述第一输出单元在所述页表缓存中新增新独立表项，所述新独立表项包含：虚拟大页号，虚拟大页内偏移量，物理大页号以及物理大页内偏移量；
其中，所述新独立表项的虚拟大页由N个连续的虚拟页构成，所述新独立表项的虚拟大页号由所述虚拟地址所述的虚拟页号除以N取整得到，所述新独立表项的虚拟大页内偏移量由所述虚拟地址所属的虚拟页号除以N取余 得到；所述页表移动的结果为所述虚拟地址对应的真实物理页号；所述新独立表项的物理大页号由所述真实物理页号除以N取整得到，所述新独立表项的物理大页内偏移量由所述真实物理页号除以N取余得到。
在一个可选的实现方式中，所述缓存控制单元，还用于若未通过所述TLB成功确定所述虚拟地址对应的物理页号，执行页表移动确定所述虚拟地址对应的真实物理页号；确定需要新增的目标表项，所述目标表项包含：虚拟大页号，虚拟大页内偏移量，物理大页号以及物理大页内偏移量；其中，所述目标表项的虚拟大页由N个连续的虚拟页构成，所述目标表项的虚拟大页号由所述虚拟地址所述的虚拟页号除以N取整得到，所述目标表项的虚拟大页内偏移量由所述虚拟地址所属的虚拟页号除以N取余得到；所述页表移动的结果为所述虚拟地址对应的真实物理页号；所述目标表项的物理大页号由所述真实物理页号除以N取整得到，所述目标表项的物理大页内偏移量由所述真实物理页号除以N取余得到；
若所述独立表项的虚拟大页号与所述目标表项的虚拟大页号相同，且所述独立表项的物理大页号与所述目标表项的物理大页号相同，且所述独立表项的虚拟大页内偏移量与所述目标表项的虚拟大页内偏移量的差值等于所述独立表项的物理大页内偏移量与所述目标表项的物理大页内偏移量的差值，则通过所述第一输出单元合并所述页表缓存中的所述独立表项和所述目标表项为目标组合表项，在所述目标组合表项中包含：虚拟大页号，位向量字段以及物理大页号；所述目标组合表项的虚拟大页号等于所述独立表项的虚拟大页号，所述目标组合表项的物理大页号等于所述独立表项的物理大页号，所述目标组合表项中的位向量字段中与所述虚拟地址所属虚拟页对应的比特为所述预定值，所述目标组合表项中的位向量字段中与所述独立表项的虚拟页对应的比特为所述预定值；所述独立表项的虚拟页的页号为所述独立表项的物理大页号与所述N的乘积，再与所述独立表项的物理大页内偏移量的和；
否则，通过所述第一输出单元在所述页表缓存中新增所述目标表项为新的独立表项。
在一个可选的实现方式中，所述缓存控制单元，用于若所述N为2的M 次方，M大于或等于1；则通过所述虚拟地址的虚拟页号右移M位得到所述虚拟地址的大页号；和/或，通过截取所述虚拟地址的虚拟页号的后M位得到所述虚拟地址的偏移量。
附图说明
下面将对实施例描述中所需要使用的附图作简要介绍。
图1为本发明实施例地址转换结构示意图；
图2为本发明实施例页表结构示意图；
图3为本发明实施例地址转换结构示意图；
图4为本发明实施例地址映射关系示意图；
图5A为本发明实施例表项结构示意图；
图5B为本发明实施例表项结构示意图；
图6为本发明实施例地址映射关系示意图；
图7为本发明实施例表项结构示意图；
图8A为本发明实施例地址映射关系示意图；
图8B为本发明实施例表项结构示意图；
图8C为本发明实施例表项结构示意图；
图9为本发明实施例方法流程示意图；
图10为本发明实施例处理芯片结构示意图；
图11为本发明实施例处理芯片中TLB的结构示意图。
具体实施方式
下面将结合附图对本发明作进一步地详细描述。
在介绍本发明实施例之前，首先介绍一下在本发明实施例中将会涉及到的技术背景资料。
一、虚拟地址与物理地址：
在程序被执行的过程中，程序使用的地址均为虚拟地址。当操作系统将一个程序载入内存时，会为该程序分配可用的物理地址空间，即：物理内存空间； 操作系统会将程序中使用的虚拟地址映射到具体的物理地址，这种映射，以页(Page)为单位。操作系统在进行内存管理时，会将物理地址空间划分成页；同样，程序自己的虚拟地址空间也会被划分成页，虚拟地址和物理地址对应的页均会按顺序编号称为页号。
所谓的地址映射，就是将一个虚拟页映射到一个物理页；也就是说，将虚拟地址的高位比特替换成物理地址的高位比特即可。
在这个映射过程中，如图1所示，虚拟地址和物理地址均为64比特，相应地页所占的空间为4KB；虚拟地址和物理地址的低12位比特(即Addr[11:0])保持不变，即虚拟地址的低12位比特和物理地址的低12位比特是相同的。这是因为，这12个比特用来表示在4KB页内的偏移量。虚拟地址和物理地址的高位部分，即Addr[63:12]字段，在虚拟地址中称之为VPN，在物理地址中称之为PFN。地址的低位部分，即Addr[11:0]字段，称之为偏移量(Offset)部分。可以看到，在映射过程中，地址的Offset部分保持不变。
二、TLB：
在程序运行过程中，操作系统会为该程序建立完整的从虚拟地址到物理地址的映射关系。这个映射关系保存到称之为“页表”(Page Table)的数据结构中，页表中的每个表项包含了相应的VPN信息和PFN信息。在处理器内地址转换通常由硬件完成，完成该功能的硬件称之为TLB，即快速转换缓冲区(Translation Lookaside Buffer)，其中可以存储上述页表。
如图2所示是一个TLB内页表的大致结构，包含了32个表项。TLB内每个表项的结构和页表内每个表项的结构是相似的，TLB可以看成是页表的缓存，存储有完整的页表的一部分。
其中，VPN是虚拟地址的高位。以64位地址宽度(即64比特的地址)为例，一个虚拟地址可以表示为Vir_Addr[63:0]。当页设定为4KB的时候，VPN就是Vir_Addr[63:12]，即VPN不包含地址的低12个比特。PFN是物理地址的高位。这里称之为物理帧(Physical Frame)而不是物理页(Physical Page)是由历史原因造成的，在此不再详述。当物理地址为64比特位宽的时候，物 理地址可以表示为Phy_Addr[63:0]。当页设定为4KB的时候，PFN就是Phy_Addr[63:12]。可以看到，PFN也不包含地址的低12个比特。
如图3所示，当处理器进行取地址操作或访存操作时，相应的虚拟地址会被送入TLB。TLB会从该虚拟地址中截取出VPN，然后使用该VPN和TLB内的各个表项进行对比。如果和其中某一个表项内的VPN相同，则输出该表项内的PFN字段，这被认为是发生了TLB命中(Hit)。如果没有一个表项的VPN和该待转换的VPN相同，则被认为是发生了TLB丢失(Miss)。
TLB的容量是非常有限的，要远远小于完整的页表所需的存储空间，因此经常会发生TLB Miss，这是因为页表中大量的映射关系并没有保存在TLB内。当TLB Miss后，需要从页表内搜索和该VPN对应的PFN，然后将这一VPN和PFN信息填充入TLB内(通常会覆盖某个已有的表项)，该过程被称之为页表移动(Page Table Walk)。Page Table Walk任务，可以由硬件自动完成，也可以由操作系统来完成。
三、TLB Miss、以及TLB Miss的开销：
随着程序规模的增加，程序本身的代码段、以及程序所需要处理的数据量都在变的越来越大，导致其所需的地址空间也相应的越来越大。
也就是说，一个程序在运行期内，会使用到更多的Page；然而受限于TLB缓存的规模，TLB Miss发生的频率就越来越高。近期的研究表明，当使用传统的4KB页时，会有50％的程序运行时间用于处理TLB Miss。
为了减少TLB Miss的频率，除了增加TLB的容量之外，还出现了多级的TLB结构。其中，多级的TLB结构，随着级数增加虽然表项更多，但是工作频率降低非常大，延迟时间长。除了多级TLB结构外，另一种方法是增加页所占的空间。例如：使用2MB的页，那么对于同样的程序，它使用的Page数量就会减少，从而页表中表项的数量会减少，所以在一定程度上可以减少TLB Miss的几率。但是在程序运行期间，一个Page的数据从硬盘换入到内存后，如果程序修改了某个数据，该Page被换出时，该Page需要写入到硬盘上保存(未修改的Page不需要写入硬盘)；Page所占的空间越大，被修改的几率首先越大，将整个Page保存到硬盘上所需的时间也将会更长，因此效果并 不理想。
基于以上三个方面的说明可以看出：目前的处理器通过TLB来进行虚实地址的转换，但是TLB的容量是有限的，从而导致较高的TLB Miss开销。因此，本发明实施例旨在提供减少TLB Miss及其开销的方法。其中，一方面本发明实施例提出了新的TLB中缓存的页表结构，让一个页表的表项用于多个页的地址转换，在表项一定的前提下增加TLB Hit的几率，减少TLB Miss；另一方面，本发明实施例还提供基于本发明实施例所提出的页表项的结构，预测物理地址的方法，在发生TLB Miss时，仍然可以在进行页表查找操作的同时，使用预测出来的地址进行访存操作。这样访存操作和页表移动操作可以并行处理。如果预测正确，则减少了处理时间；如果预测错误，则在TLB Miss完成后重新开始访存操作，其延时与未采用本发明实施例方法时的延时相同。具体的实现方案，包含如下几个方面：
一、TLB内缓存的页表的表项结构：
如图4所示，假定左侧的是VPN0～VPN3的四个虚拟页，右侧的是PFN0～7的物理页，虚拟页和物理页的映射关系如箭头所示；
为了表示这两个箭头所示的映射关系，如果使用一个表项表示一个虚拟页和物理页映射关系，那如图4所示；由于VPN1和VPN2是连续的，PFN1和PFN2也是连续的，在本发明实施例中，如果5B所示，可以使用一个表项表示这两个映射关系。
在本发明实施例中，TLB内缓存的页表的表项中，增加了1比特的格式(Fmt)字段(Format)，用于表示表项的格式；还增加了1比特的预测(Pred)字段(Prediction)，表示该表项是否可以用于预测物理地址。当Fmt字段为0时，可以表示该表项为传统格式，此时Pred字段也为0，即不参与预测物理地址；这种情况下，此时一个TLB的表项只可以将1个VPN映射到1个PFN。当Fmt字段为1时，表示为本发明实施例所提出的新格式，此时一个TLB表项可以映射多个VPN。Fmt和Pred主要用于指导物理地址的预测，在后续实施例中关于物理地址预测的部分将给出详细说明。
图5A上面一个表项，左起第4格“10”为VPN2的“2”的二进制码，是其在“VPN0/4”这个大的虚拟页的偏移量，最后一格是“10”为PFN2的“2”的二进制码，是其在“PFN0/4”这个大的物理页的偏移量，大虚拟页和大物理页可以是逻辑的概念，在对存储空间分页时，仍然采用原方案进行分页不必扩大单个页的地址空间。图5A的下一个表项用于表示的是VPN1到PFN1的映射关系，原理与VPN2到PFN2的映射关系原理相同，在此不再赘述。
图5B的表项，包含一个“BitVec”字段有4个比特，即：4位；每1位对应一个VPN到PFN的映射；例如，左起第2位为1，表示VPN2到PFN2的映射关系，左起第3位为1，表示VPN1到PFN1的映射关系，其他位为0表示的是VPN3到PFN3以及VPN0到PFN0的映射关系不确定。
以上图5B是一个实例的举例，该举例是以一个表项用于表示4对VPN到PFN的映射关系的应用场景；因此BitVec的取值为BitVec[3:0]，并且大的虚拟页和大的物理页在表项中分别表示为“VPN0/4”和“PFN0/4”，即这里的“0/4”。
为了不失一般性，下文将以一个TLB的表项可以映射4个VPN的情况为例进行举例说明。本发明实施例并不局限于一个TLB表项可以映射4个VPN的情况，这里只是为了阐述方便而进行论述；一个TLB表项用于映射其他特殊的VPN的情况，与此原理相同，不再赘述。
以上图5A，可以将VPN字段分成两部分，如图5A上一行的表项虚线框内，一部分表示原VPN字段的最低2个比特“10”，另一部分表示除了最低2个比特之外的高位比特“VPN0/4”。同理，PFN字段也可以分成两部分，分别表示最低2个比特和其余的高位比特。
在图4所示的示例中，VPN0～VPN3是虚拟地址连续的4个虚拟页，而PFN0～PFN3是物理地址连续的4个物理页，假定一个虚拟大页号表示4个连续的虚拟页，那么有如下的换算关系：
VPN0的大页号为“VPN0/4”，即VPN0除以4取整，偏移量为“00”即：VPN0/4取余；其他虚拟页和物理页的计算方式与此相同，不再赘述。
在图4中，由于VPN1和VPN2在虚拟地址上是连续的，另外，由于PFN1 和PFN2在物理地址上也是连续的。因此，可以将这VPN2到PFN2的映射关系和VPN1到PFN1的映射关系合并成一个表项，并在BitVec字段中予以标记，如上图5B所示。
二、TLB的表项的查找：
基于以上关于TLB中的表项结构的介绍，图5A这种表项查找方式不再赘述，图5B这种表项的查找方式下面详细介绍。
当输入地址为虚拟地址(virAddr)时，通过virAddr/页大小(pageSize)可以得到该地址所在的虚拟页号，即虚拟页号码(virPageNum)，在如图4和图5B中；
以VPN1到PFN1的映射为例，首先输入了虚拟地址virAddr，计算virAddr/pageSize，得到virPageNum，此处virPageNum为VPN1；然后计算virPageNum/4得到的是VPN0/4，使用VPN0/4查表得到图5B所示的表项；计算virPageNum％4得到pageIdx，此时pageIdx为1对应的BitVec[pageIdx]是BitVec[1]对应右起第2位，发现值是1，因此表明TLB Hit；图5B中所示的表项中物理大页号为PFN0/4，因此virPageNum对应的物理页号为PFN0/4内偏移1，即PFN1。如果若BitVec[pageIdx]的值为0，表明发生了TLB Miss，例如：BitVec[3]对应的左起第一位是0，因此VPN3使用5B所示表项会发生TLB Miss。
三、插入新的表项：
如图6所示，假定在图4所示的基础上，有VPN0映射到VPN3需要写入到TLB缓存中。
如果已经有图5B所示的表项在TLB中，由于VPN1到PFN1以及与VPN2到PFN2均为连续页号，而VPN0映射到VPN3打破了这种连续性，因此其不能增加到图5B这条表项中，需要增加以表项，如图7所示，其原理与图5A相同，在此不再赘述；如果VPN0映射到VPN0，只需修改图5B右起第1位的值为1就可以了，不必新增表项。
再如，假定TLB中已经有图5A所示的上个表项；即该TLB的表项内保 存了VPN2到PFN2的映射关系。此时若访问VPN0或VPN1，则会发生TLB Miss，于是会执行Page Table Walk任务。假定发现VPN0被映射到PFN3，而VPN1被映射到PFN1。
由于VPN1在VPN0/4内的偏移量与PFN1在PFN0/4内的偏移量相同，所以VPN1到PFN1的映射可以和VPN2到PFN2的映射保存在同一个TLB表项内，即图5A上一行的表项修改为图5B的格式。
而VPN0在VPN0/4的偏移量与PFN3在PFN0/4的偏移量不相同，因此从VPN0到PFN3的映射不能和之前的映射如图5B合并在一个TLB表项内，需要使用一个独立的TLB表项来表示该映射，如图7所示。
四、地址预测：
如图8A和图8B所示，假定该TLB的表项中已经具备了VPN0到PFN0、VPN1到PFN1的映射，且此时待转换的地址落入VPN2内，且此时该TLB表项内缺少对VPN2的映射。那么，此时会遇到“大页命中，小页缺失”的情况。
此时，如果Pred字段为1，即允许使用该TLB的表项进行预测，因此预测VPN2映射到PFN2，即预测图8B的左起第2个比特位为1，这样可以使用该图8B的表项获得VPN2的物理地址。
在执行地址预测之后，同时做两件事情：一方面，按照预测出来的物理地址进行访存操作，另一方面，执行Page Table Walk任务获得物理地址。
由于Page Table Walk任务需要多次进行页表查询操作，且每次页表查询操作相当于一次访存操作，因此当Page Table Walk操作返回时，按照预测出来的地址进行的访存操作通常已经结束。
若Page Table Walk的结果表明地址预测的结果正确，则访存操作的结果可用，那么相当于节省了一次访存操作的延迟。此时可以确定如图8A中VPN2映射到VPN2，可以将图8B中的左起第2个比特位修改为1。
若Page Table Walk的结果表明地址预测的结果不正确，如上图8C所示。假定VPN2实际映射到PFN3，则Page Table Walk结果返回后，表明之前的地址预测是错误的。此时，重新对正确的物理地址进行访存操作，另外还将TLB 的表项中，图8B的Pred字段设置为0，表明该TLB表项不再进行预测。然后还可以插入一个新的TLB的表项，以表示从VPN2到PFN3的映射关系，此TLB表项需要采用图5A的表项格式来表示，Fmt字段为0。具体如图8C所示，增加的表项为图8C的下一行，在此不再赘述。
本发明实施例提供了一种页表缓存TLB中表项的访问方法，如图9所示，包括：
在本实施例中，TLB中的表项包括至少一个组合表项，上述组合表项包括虚拟大页号，位向量字段以及物理大页号，其中，上述虚拟大页号为N个连续的虚拟页的标识，上述位向量字段包含N个比特，上述N个比特和上述N个连续的虚拟页一一对应，且上述N个比特分别用来标识上述N个连续的虚拟页的页表存在状态，上述物理大页号为上述N个连续的虚拟页所对应的N个连续的物理页的标识；
请参阅图5B所示VPN0/4对应的是虚拟大页号，PFN0/4对应物理大页号；位向量字段对应到BitVec[3:0]；在图5B中，前面Pred和Fmt字段在不作地址预测的时候，可以是非必要的字段。在图5B中，N的取值是4，若取值为其他数字也是可以的，因此图5B作为一个举例不应理解为对本发明实施例的唯一性限定。
901：接收虚拟地址，计算上述虚拟地址的虚拟大页号以及上述虚拟地址所属虚拟页在上述虚拟大页内的偏移量；上述虚拟地址的虚拟大页号由上述虚拟地址所属的虚拟页号除以N取整得到；上述虚拟地址所属虚拟页在上述虚拟大页内的偏移量由上述虚拟地址所属的虚拟页号除以N取余得到；上述N为大于1的整数；
虚拟地址所属的虚拟页计算方式可以参考前文介绍，在此不再赘述。本步骤中，虚拟地址virAddr，计算virAddr/pageSize，得到虚拟页号virPageNum；然后计算virPageNum/N得到虚拟大页号在图5B中为VPN0/4，这里N取值为4，使用虚拟大页号查表项。以图5B对应的图4为例，VPN2是虚拟页号为2的虚拟页，对应的虚拟大页号为0，在虚拟大页内的偏移量为2；PFN2是物理页号为2的物理页，对应的物理大页号为0，在物理大页内的偏移量为2。
902：确定上述虚拟地址的虚拟大页号与上述TLB包括的组合表项中的虚拟大页号是否相同，并确定上述组合表项中的位向量字段中与上述虚拟地址所属虚拟页对应的比特是否为预定值；
本步骤是用于确定是否发生组合表项Hit的步骤。
903：若上述两个确定结果均为是，则确定上述虚拟地址对应的物理页号为：上述组合表项中的物理大页号与上述N的乘积，再与上述虚拟地址所属虚拟页在上述虚拟大页内的偏移量的和。
本步骤中，VPN0/4与TLB中的表项存在相同的情况，那么可以确定大页命中了，这里还需要确定小页也命中，因此还需要计算virPageNum％4得到pageIdx，此时pageIdx在位向量中对应的比特位是：BitVec[pageIdx]，如果BitVec[pageIdx]是1，表明TLB Hit；需要说明的是，也可以用0表示命中用1表示Miss，原理是相同的在此不予赘述。如果TLB Hit，那么就可以确定物理页号具体为：在物理大页内偏移上述pageIdx，在图5B中是在PFN0/4内偏移pageIdx。
本发明实施例，使用一个表项表示了多个虚拟页到物理页的映射，在页表长度固定的情况下，可以将TLB中表项的数量成倍增加，从而提高TLB命中概率，减少TLB Miss，因此可以降低程序处理延迟并提高处理芯片的处理效率。
仍然参考图9所示，前面步骤901～903是TLB内的表项中正好有一个组合表项，即：用一个组合表项表示多个虚拟页到物理页的映射关系的情况；还有一种情况是有一个独立表项只表示一个虚拟页到物理页的映射关系，独立表项的结构，可参考图5A，上述TLB中的表项包括至少一个独立表项，上述独立表项包括虚拟大页号，虚拟大页内偏移量，物理大页号以及物理大页内偏移量，其中，上述虚拟大页由N个连续的虚拟页构成，上述虚拟大页号为上述N个连续的虚拟页的标识，上述虚拟大页内偏移量为相对于上述独立表项的虚拟大页号的第一个虚拟页号的偏移量，上述物理大页由上述N个连续的虚拟页所对应的N个连续的物理页构成，上述物理大页号为上述N个连续的虚拟页所对应的N个连续的物理页的标识，上述物理大页内偏移量为相对于上述独 立表项的物理大页号的第一个物理页号的偏移量，上述方法还包括：
这里独立表项可以参考图5A所示，每一行是一个独立表项；以上一行为例，虚拟大页号对应到VPN0/4，物理大页号对应到PFN0/4，虚拟大页内偏移量是左侧虚线框内包含的“10”，这里“10”是二进制数实际偏移为2；物理大页内偏移量是右侧虚线框内包含的“10”，这里“10”是二进制数实际偏移也为2。
904：确定上述虚拟地址的虚拟大页号与上述TLB包括的独立表项中的虚拟大页号是否相同，并确定上述独立表项中的虚拟大页内偏移量与上述虚拟地址所属虚拟页在上述虚拟大页内的偏移量是否相同；若上述两个确定结果均为相同，则确定上述虚拟地址对应的物理页号为：上述独立表项的物理大页号与上述N的乘积，再与上述独立表项的物理大页内偏移量的和。
本步骤可能是因为在组合表项目中没有命中的情况产生的；在前一实施例中BitVec[pageIdx]是0的情况，表示在组合表项中没有命中，那么有可能在独立表项中Hit，按照图5A上一行的举例，VPN0/4是命中的，那么如果pageIdx正好和第一偏移量相同，那么TLB Hit，直接确定后面PFN0/4为物理大页号，以该物理的大页号内偏移“10”，即：2，为虚拟地址对应的物理页号。本步骤也可以不基于前一实施例中关于命中组合表项方案，本实施例步骤904可以独立存在。
还有一种情况是，真的出现了TLB Miss，这种情况下的一个子情况是虚拟大页命中小页没命中的情况，具体如下：上述组合表项中还包含用于表示上述组合表项是否可以用于地址预测的标识。
这种情况下，在表项中需要使用到另外两个标识，一个标识是用来表示表项格式是组合表项还是独立表项的标识，在图5B中对应到Fmt，格式是用来表示这个表项采用的是图5B这样的格式还是图5A这样的格式；另一个标识是用来表示能不能用这个表项进行地址预测的标识，在图5B中对应到Pred，这种情况通常出现在Fmt表示为图5B这样的格式的情况下，可以用Fmt取值为0表示，也可以取值为1表示，预先约定好就行；图5B使用Fmt取值为1表示；Pred到底取值为0或1来表示能进行地址预测，也是预先约定的，可以 任意约定。
基于这种应用场景，若上述组合表项中的位向量字段中与上述虚拟地址所属虚拟页对应的比特为非预定值，并且，上述独立表项中的虚拟大页内偏移量与上述虚拟地址所属虚拟页在上述虚拟大页内的偏移量不相同，上述组合表项还还包括用于表示上述组合表项是否可用于地址预测的标识位，上述方法还包括：
905：若上述虚拟地址的虚拟大页号与上述组合表项中的虚拟大页相同，且上述组合表项中包含用于表示上述组合表项可用于地址预测的标识位，则确定预测页号以上述预测页进行访存，并执行页表移动；上述预测页号为：上述组合表项中的物理大页号与上述N的乘积，再与上述虚拟地址所属虚拟页在上述虚拟大页内的偏移量的和。
本不是是在组合表项和独立表项均未Hit的情况下，发生虚拟大页号Hit的情况下，并且组合表的标识标识能够执行地址预测的情况。
在以图5B为例的情况下，假定计算得到的虚拟大页号是VPN0/4，也即使说虚拟大页号是命中的，假如BitVec[pageIdx]是3，那么小页没有命中；此时可以预测默认BitVec[3]，即：图5B中BitVec对应的左起第一个数字为1，即：确定后面PFN0/4为物理大页号，以该物理大页号内偏移3，为虚拟地址对应的物理页号。这个预测可能是正确的，也可能是错误的，此时还不能确定；不过可以先执行访存操作；另外为了确定预测到的物理页号是还不是正确的，可以通过执行页表移动的结果来确定，页表移动是查完整页表的操作过程，通常需要多次访存，会比地址预测后执行访存要慢，在本实施例中不作赘述。
真的出现了TLB Miss，的另一种情况是虚拟大页未命中小页也未命中的情况，那么执行页表移动就可以了，在此不再赘述。
基于地址预测的实现方式，通过页表移动的结果可以确定地址预测的正确性，完成后可以更新TLB中的页表的表项，上述方法还包括：
906：若上述页表移动的结果表明上述预测页号正确，将上述组合表项中的位向量字段中与上述虚拟地址所属虚拟页在上述虚拟大页内的偏移量对应的比特修改为上述预定值。
本实施例其中一种情况，即：使用组合页表预测正确的情况；这种情况下，只需要修改组合表项中位向量中的值就可以；例如，假定预测是的VPN3正确，那么将图5B中左起第1位修改为1。
还有一种情况是预测错误了，具体操作如下：上述方法还包括：
907：若上述页表移动的结果表明上述预测页号错误，在上述组合表项中设置用于表示上述组合表项不可用于地址预测的标识位。
新增新独立表项，上述新独立表项包含：虚拟大页号，虚拟大页内偏移量，物理大页号以及物理大页内偏移量；
其中，上述新独立表项的虚拟大页由N个连续的虚拟页构成，上述新独立表项的虚拟大页号由上述虚拟地址上述的虚拟页号除以N取整得到，上述新独立表项的虚拟大页内偏移量由上述虚拟地址所属的虚拟页号除以N取余得到；上述页表移动的结果为上述虚拟地址对应的真实物理页号；上述新独立表项的物理大页号由上述真实物理页号除以N取整得到，上述新独立表项的物理大页内偏移量由上述真实物理页号除以N取余得到。
本步骤是新增了一个独立表项，独立表项的结构都是相同的本实施例对此不再赘述。
还有一种情况需要更新TLB内页表的表项的情况，是之前没有发生组合表项Hit、没有进行地址预测，也没有发生独立表项Hit这种情况下有一种比较特殊的情况是需要新增的表项可以与已有的Fmt＝0的独立表项进行合并；具体如下：若未通过上述TLB成功确定上述虚拟地址对应的物理页号，上述方法还包括：
908：执行页表移动确定上述虚拟地址对应的真实物理页号；
确定需要新增的目标表项，上述目标表项包含：虚拟大页号，虚拟大页内偏移量，物理大页号以及物理大页内偏移量；其中，上述目标表项的虚拟大页由N个连续的虚拟页构成，上述目标表项的虚拟大页号由上述虚拟地址上述的虚拟页号除以N取整得到，上述目标表项的虚拟大页内偏移量由上述虚拟地址所属的虚拟页号除以N取余得到；上述页表移动的结果为上述虚拟地址对应的真实物理页号；上述目标表项的物理大页号由上述真实物理页号除以N 取整得到，上述目标表项的物理大页内偏移量由上述真实物理页号除以N取余得到；
若上述独立表项的虚拟大页号与上述目标表项的虚拟大页号相同，且上述独立表项的物理大页号与上述目标表项的物理大页号相同，且上述独立表项的虚拟大页内偏移量与上述目标表项的虚拟大页内偏移量的差值等于上述独立表项的物理大页内偏移量与上述目标表项的物理大页内偏移量的差值，则合并上述独立表项和上述目标表项为目标组合表项，在上述目标组合表项中包含：虚拟大页号，位向量字段以及物理大页号；上述目标组合表项的虚拟大页号等于上述独立表项的虚拟大页号，上述目标组合表项的物理大页号等于上述独立表项的物理大页号，上述目标组合表项中的位向量字段中与上述虚拟地址所属虚拟页对应的比特为上述预定值，上述目标组合表项中的位向量字段中与上述独立表项的虚拟页对应的比特为上述预定值；上述独立表项的虚拟页的页号为上述独立表项的物理大页号与上述N的乘积，再与上述独立表项的物理大页内偏移量的和；
否则，新增上述目标表项为新的独立表项。
这种情况，假定如图5A所示中，初始状态下只有上一行的独立表项；由于发生了TLB Miss执行了地址预测或者执行了页表移动后确定了VPN1的物理页，即下一行；此种情况下，如果使用两个独立表项则浪费了有限的表项资源，可以将这俩表项合并起来，形式为图5B所示。
基于地址换算的特点在前述实施例中，上述N为2的M次方，M大于或等于1；
上述计算上述虚拟地址的大页号以及上述虚拟地址的偏移量，包括：
上述虚拟地址的大页号通过上述虚拟地址的虚拟页号右移M位得到；和/或，上述虚拟地址的偏移量通过截取上述虚拟地址的虚拟页号的后M位得到。
以图5A为例，N为4，M为2，因此虚拟大页号可以是虚拟页号截取除最后2位外的其他位；偏移量则为最后2位；如果同时应用到计算虚拟页号，假定页地址空间为2的J次方，那么大页号是截取除最后J+2外的其他位，偏移量为大页号后的2位。其他取值原理相同，本实施例不作赘述。
本发明实施例还提供了一种处理芯片，如图10所示，上述处理芯片包括：页表缓存1001和缓存控制单元1002；缓存控制单元1002还可以有输入和输出接口，输入的部分可以输入虚拟地址、页表移动的结果等；输出可以有预测页(对应预测地址)、物理页(对应物理地址)等；
请一并参阅图9所示，本实施例是TLB内的表项中正好有一个组合表项，即：用一个组合表项表示多个虚拟页到物理页的映射关系的情况；在这种情况下发生TLB Hit的场景，具体如下：
上述页表缓存1001中存储有页表，上述页表的表项包括至少一个组合表项，上述组合表项包括虚拟大页号，位向量字段以及物理大页号，其中，上述虚拟大页号为N个连续的虚拟页的标识，上述位向量字段包含N个比特，上述N个比特和上述N个连续的虚拟页一一对应，且上述N个比特分别用来标识上述N个连续的虚拟页的页表存在状态，上述物理大页号为上述N个连续的虚拟页所对应的N个连续的物理页的标识；
上述缓存控制单元1002包括第一输入端、第一输出端、第二输入端、第二输出端；上述第一输入端用于接收虚拟地址；上述第二输入端用于连接上述页表缓存1001，上述第二输入端用于连接上述页表缓存1001，上述第二输出端用于输出表项访问的结果；
上述缓存控制单元1002，用于通过上述第一输入端接收上述虚拟地址，计算上述虚拟地址的虚拟大页号以及上述虚拟地址所属虚拟页在上述虚拟大页内的偏移量；上述虚拟地址的虚拟大页号由上述虚拟地址所属的虚拟页号除以N取整得到；上述虚拟地址所属虚拟页在上述虚拟大页内的偏移量由上述虚拟地址所属的虚拟页号除以N取余得到；上述N为大于1的整数；通过上述第一输出端访问上述组合页表并通过上述第二输入端接收访问结果，依据上述访问结果确定上述虚拟地址的虚拟大页号与上述TLB包括的组合表项中的虚拟大页号是否相同，并确定上述组合表项中的位向量字段中与上述虚拟地址所属虚拟页对应的比特是否为预定值；若上述两个确定结果均为是，则确定上述虚拟地址对应的物理页号为：上述组合表项中的物理大页号与上述N的乘积，再与上述虚拟地址所属虚拟页在上述虚拟大页内的偏移量的和，通过上述 第二输出端输出上述虚拟地址对应的物理页号。
仍然参考图9所示，还有一种情况是有一个独立表项只表示一个虚拟页到物理页的映射关系，独立表项的结构，可参考图5A，在这种情况下产生TLB Hit的情况，具体如下：进一步地，上述页表缓存1001中存储的页表的表项包括至少一个独立表项，上述独立表项包括虚拟大页号，虚拟大页内偏移量，物理大页号以及物理大页内偏移量，其中，上述虚拟大页由N个连续的虚拟页构成，上述虚拟大页号为上述N个连续的虚拟页的标识，上述虚拟大页内偏移量为相对于上述独立表项的虚拟大页号的第一个虚拟页号的偏移量，上述物理大页由上述N个连续的虚拟页所对应的N个连续的物理页构成，上述物理大页号为上述N个连续的虚拟页所对应的N个连续的物理页的标识，上述物理大页内偏移量为相对于上述独立表项的物理大页号的第一个物理页号的偏移量；
上述缓存控制单元1002，还用于依据上述访问结果确定上述虚拟地址的虚拟大页号与上述TLB包括的独立表项中的虚拟大页号是否相同，并确定上述独立表项中的虚拟大页内偏移量与上述虚拟地址所属虚拟页在上述虚拟大页内的偏移量是否相同；若上述两个确定结果均为相同，则确定上述虚拟地址对应的物理页号为：上述独立表项的物理大页号与上述N的乘积，再与上述独立表项的物理大页内偏移量的和。
在本发明实施例中，组合表项可能可以用于预测物理页号，因此TLB Miss的情况下，有一种在组合表中虚拟大页号Hit的情况，这种情况下如果组合表项标识为可以进行地址预测，那么具体如下：进一步地，上述缓存控制单元1002，还用于在确定上述组合表项中的位向量字段中与上述虚拟地址所属虚拟页对应的比特为非预定值，并且，上述独立表项中的虚拟大页内偏移量与上述虚拟地址所属虚拟页在上述虚拟大页内的偏移量不相同，上述组合表项还还包括用于表示上述组合表项是否可用于地址预测的标识位之后，若确定上述虚拟地址的虚拟大页号与上述组合表项中的虚拟大页相同，且上述组合表项中包含用于表示上述组合表项可用于地址预测的标识位，则确定预测页号以上述预测页进行访存，并执行页表移动；上述预测页号为：上述组合表项中的物理大页 号与上述N的乘积，再与上述虚拟地址所属虚拟页在上述虚拟大页内的偏移量的和。
基于地址预测的结果正确性，如果地址预测正确，本发明实施例还提供了表项修改的方案，具体如下：进一步地，上述缓存控制单元1002还包括第三输入端，上述第三输入端用于接收页表移动的结果；
上述缓存控制单元1002，还用于若上述页表移动的结果表明上述预测页正确，通过上述第一输出端将上述组合表项中的位向量字段中与上述虚拟地址所属虚拟页在上述虚拟大页内的偏移量对应的比特修改为上述预定值。
本实施例新增了一个虚拟页与物理页之间的映射关系到TLB中，但是并没有新增表项，可以节省TLB中表项开销。
基于地址预测的结果正确性，如果地址预测错误，本发明实施例还提供了表项的修改方案，具体如下：进一步地，上述缓存控制单元1002，还用于在上述执行页表移动之后，若上述页表移动的结果表明上述预测页号错误，通过上述第一输出单元在上述页表缓存1001中的上述组合表项中设置用于表示上述组合表项不可用于地址预测的标识位。
本实施例将发生错误地址预测的组合表项标识为不可用于地址预测，这样可以避免再次出现地址预测错误的情况。
基于地址预测的正确性，如果地址预测错误，本发明实施例还提供了新增独立表项的实现方案，具体如下：进一步地，上述缓存控制单元1002，还用于在确定上述页表移动的结果表明上述预测页号错误之后，通过上述第一输出单元在上述页表缓存1001中新增新独立表项，上述新独立表项包含：虚拟大页号，虚拟大页内偏移量，物理大页号以及物理大页内偏移量；
其中，上述新独立表项的虚拟大页由N个连续的虚拟页构成，上述新独立表项的虚拟大页号由上述虚拟地址上述的虚拟页号除以N取整得到，上述新独立表项的虚拟大页内偏移量由上述虚拟地址所属的虚拟页号除以N取余得到；上述页表移动的结果为上述虚拟地址对应的真实物理页号；上述新独立表项的物理大页号由上述真实物理页号除以N取整得到，上述新独立表项的物理大页内偏移量由上述真实物理页号除以N取余得到。
本发明实施例还提供了在发生TLB Miss的情况下，未进行地址预测，需要新增表项的情况下，可能节省表项的一种情况，具体如下：进一步地，上述缓存控制单元1002，还用于若未通过上述TLB成功确定上述虚拟地址对应的物理页号，执行页表移动确定上述虚拟地址对应的真实物理页号；确定需要新增的目标表项，上述目标表项包含：虚拟大页号，虚拟大页内偏移量，物理大页号以及物理大页内偏移量；其中，上述目标表项的虚拟大页由N个连续的虚拟页构成，上述目标表项的虚拟大页号由上述虚拟地址上述的虚拟页号除以N取整得到，上述目标表项的虚拟大页内偏移量由上述虚拟地址所属的虚拟页号除以N取余得到；上述页表移动的结果为上述虚拟地址对应的真实物理页号；上述目标表项的物理大页号由上述真实物理页号除以N取整得到，上述目标表项的物理大页内偏移量由上述真实物理页号除以N取余得到；
若上述独立表项的虚拟大页号与上述目标表项的虚拟大页号相同，且上述独立表项的物理大页号与上述目标表项的物理大页号相同，且上述独立表项的虚拟大页内偏移量与上述目标表项的虚拟大页内偏移量的差值等于上述独立表项的物理大页内偏移量与上述目标表项的物理大页内偏移量的差值，则通过上述第一输出单元合并上述页表缓存1001中的上述独立表项和上述目标表项为目标组合表项，在上述目标组合表项中包含：虚拟大页号，位向量字段以及物理大页号；上述目标组合表项的虚拟大页号等于上述独立表项的虚拟大页号，上述目标组合表项的物理大页号等于上述独立表项的物理大页号，上述目标组合表项中的位向量字段中与上述虚拟地址所属虚拟页对应的比特为上述预定值，上述目标组合表项中的位向量字段中与上述独立表项的虚拟页对应的比特为上述预定值；上述独立表项的虚拟页的页号为上述独立表项的物理大页号与上述N的乘积，再与上述独立表项的物理大页内偏移量的和；
否则，通过上述第一输出单元在上述页表缓存1001中新增上述目标表项为新的独立表项。
在本实施例中，未通过上述TLB成功确定上述虚拟地址对应的物理页号，是指TLB中没有存储虚拟地址所需要的虚拟页号到物理页号的对应关系，具体可以是没有发生虚拟大页号Hit的情况。
为了进一步提高处理芯片的运算效率，上述缓存控制单元1002，用于若上述N为2的M次方，M大于或等于1；则通过上述虚拟地址的虚拟页号右移M位得到上述虚拟地址的大页号；和/或，通过截取上述虚拟地址的虚拟页号的后M位得到上述虚拟地址的偏移量。
移位运算可以采用移位寄存器实现、判断是否相同可以通过逻辑门电路实现、以上步骤中的各功能都可以通过逻辑电路实现，具体的逻辑电路布局种类繁多，本发明实施例对此不作唯一性说明，作为一个具体的举例本发明实施例还提供了另一种处理芯片，处理芯片中包含的TLB及其控制结构，如图11所示，主要包含：匹配逻辑(Match Logic)和控制逻辑(Control Logic)；这两个部分可以对应到图10所示结构中的缓存控制单元1002；
输入的内容主要有：页表移动结果(Page Table Walk Result)和虚拟地址(Virtual Address)；这两者并不是必须存在的，后续流程有说明。
在图11中，Item0～ItemN表示该TLB内的各个表项。该部分可以对应到图10所示结构中的缓存。
Virtual Address为该TLB的输入信号，表示需要进行转换的虚拟地址。
每个TLB的表项均有一个匹配逻辑(Match Logic)，该Match Logic根据输入的虚拟地址和该TLB的表项的内容，使用前文方法部分的方法，计算虚拟地址与该TLB的表项是否匹配、如果不匹配是否可以进行预测等信息，如果匹配则输出该表项的PFN信息(Info)，如果不匹配但可以预测则输出预测的PFN信息等等。
TLB内具有一个Control Logic，它根据各个TLB表项的输出结果，输出TLB_Match_Flag(用于表示物理地址是否有效)、TLB_Phy_Addr(物理地址)、TLB_Pred_Flag(用于表示预测地址是否有效)、以及Pred_Phy_Addr(预测物理地址)这四个信号。如果TLB Hit那么可以只有前面两个，如果预测地址则可以只有后面两个。
如果TLB_Match_Flag有效，则表明TLB Hit，此时TLB_Phy_Addr表示与输入的虚拟地址相对应的物理地址。如果TLB_Match_Flag无效但TLB_Pred_Flag有效，则Pred_Phy_Addr表示预测出来的物理地址。
当TLB Miss时，Control Logic根据Page Table Walk的结果以及当前各个表项的内容，使用前文方法部分的算法，对TLB中的表项进行更新。
在本实施例中，物理地址可以是物理页号，也可以是进一步根据物理页号和物理页内偏移量计算得到的更为精确的物理地址，依不同的地址访问管理的系统设定对应地设置，本发明实施例对此不作唯一性限定。以上处理芯片实施例中的技术内容可以一并参考方法实施例中的说明，在此不再赘述。
值得注意的是，上述装置只是按照功能逻辑进行划分的，但并不局限于上述的划分，只要能够实现相应的功能即可；另外，各功能单元的具体名称也只是为了便于相互区分，并不用于限制本发明的保护范围。
另外，本领域普通技术人员可以理解实现上述各方法实施例中的全部或部分步骤是可以通过程序来指令相关的硬件完成，相应的程序可以存储于一种计算机可读存储介质中，上述提到的存储介质可以是只读存储器，磁盘或光盘等。
以上仅为本发明较佳的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明实施例揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应该以权利要求的保护范围为准。

Claims (16)

  1. 一种页表缓存TLB中表项的访问方法，其特征在于，所述表项包括至少一个组合表项，所述组合表项包括虚拟大页号，位向量字段以及物理大页号，其中，所述虚拟大页号为N个连续的虚拟页的标识，所述位向量字段包含N个比特，所述N个比特和所述N个连续的虚拟页一一对应，且所述N个比特分别用来标识所述N个连续的虚拟页的页表存在状态，所述物理大页号为所述N个连续的虚拟页所对应的N个连续的物理页的标识，所述方法包括：
    接收虚拟地址，计算所述虚拟地址的虚拟大页号以及所述虚拟地址所属虚拟页在所述虚拟大页内的偏移量；所述虚拟地址的虚拟大页号由所述虚拟地址所属的虚拟页号除以N取整得到；所述虚拟地址所属虚拟页在所述虚拟大页内的偏移量由所述虚拟地址所属的虚拟页号除以N取余得到；所述N为大于1的整数；
    确定所述虚拟地址的虚拟大页号与所述TLB包括的组合表项中的虚拟大页号是否相同，并确定所述组合表项中的位向量字段中与所述虚拟地址所属虚拟页对应的比特是否为预定值；
    若所述两个确定结果均为是，则确定所述虚拟地址对应的物理页号为：所述组合表项中的物理大页号与所述N的乘积，再与所述虚拟地址所属虚拟页在所述虚拟大页内的偏移量的和。
  2. 根据权利要求1所述方法，其特征在于，所述表项包括至少一个独立表项，所述独立表项包括虚拟大页号，虚拟大页内偏移量，物理大页号以及物理大页内偏移量，其中，所述虚拟大页由N个连续的虚拟页构成，所述虚拟大页号为所述N个连续的虚拟页的标识，所述虚拟大页内偏移量为相对于所述独立表项的虚拟大页号的第一个虚拟页号的偏移量，所述物理大页由所述N个连续的虚拟页所对应的N个连续的物理页构成，所述物理大页号为所述N个连续的虚拟页所对应的N个连续的物理页的标识，所述物理大页内偏移量为相对于所述独立表项的物理大页号的第一个物理页号的偏移量，所述方法还包括：
    确定所述虚拟地址的虚拟大页号与所述TLB包括的独立表项中的虚拟大页号是否相同，并确定所述独立表项中的虚拟大页内偏移量与所述虚拟地址所 属虚拟页在所述虚拟大页内的偏移量是否相同；
    若所述两个确定结果均为相同，则确定所述虚拟地址对应的物理页号为：所述独立表项的物理大页号与所述N的乘积，再与所述独立表项的物理大页内偏移量的和。
  3. 根据权利要求1或2所述方法，其特征在于，若所述组合表项中的位向量字段中与所述虚拟地址所属虚拟页对应的比特为非预定值，并且，所述独立表项中的虚拟大页内偏移量与所述虚拟地址所属虚拟页在所述虚拟大页内的偏移量不相同，所述组合表项还还包括用于表示所述组合表项是否可用于地址预测的标识位，所述方法还包括：
    若所述虚拟地址的虚拟大页号与所述组合表项中的虚拟大页相同，且所述组合表项中包含用于表示所述组合表项可用于地址预测的标识位，则确定预测页号以所述预测页进行访存，并执行页表移动；所述预测页号为：所述组合表项中的物理大页号与所述N的乘积，再与所述虚拟地址所属虚拟页在所述虚拟大页内的偏移量的和。
  4. 根据权利要求3所述方法，其特征在于，在所述执行页表移动之后，所述方法还包括：
    若所述页表移动的结果表明所述预测页号正确，将所述组合表项中的位向量字段中与所述虚拟地址所属虚拟页在所述虚拟大页内的偏移量对应的比特修改为所述预定值。
  5. 根据权利要求3所述方法，其特征在于，在所述执行页表移动之后，所述方法还包括：
    若所述页表移动的结果表明所述预测页号错误，在所述组合表项中设置用于表示所述组合表项不可用于地址预测的标识位。
  6. 根据权利要求5所述方法，其特征在于，在确定所述页表移动的结果表明所述预测页号错误之后，所述方法还包括：
    新增新独立表项，所述新独立表项包含：虚拟大页号，虚拟大页内偏移量，物理大页号以及物理大页内偏移量；
    其中，所述新独立表项的虚拟大页由N个连续的虚拟页构成，所述新独立表项的虚拟大页号由所述虚拟地址所述的虚拟页号除以N取整得到，所述 新独立表项的虚拟大页内偏移量由所述虚拟地址所属的虚拟页号除以N取余得到；所述页表移动的结果为所述虚拟地址对应的真实物理页号；所述新独立表项的物理大页号由所述真实物理页号除以N取整得到，所述新独立表项的物理大页内偏移量由所述真实物理页号除以N取余得到。
  7. 根据权利要求2所述方法，其特征在于，若未通过所述TLB成功确定所述虚拟地址对应的物理页号，所述方法还包括：
    执行页表移动确定所述虚拟地址对应的真实物理页号；
    确定需要新增的目标表项，所述目标表项包含：虚拟大页号，虚拟大页内偏移量，物理大页号以及物理大页内偏移量；其中，所述目标表项的虚拟大页由N个连续的虚拟页构成，所述目标表项的虚拟大页号由所述虚拟地址所述的虚拟页号除以N取整得到，所述目标表项的虚拟大页内偏移量由所述虚拟地址所属的虚拟页号除以N取余得到；所述页表移动的结果为所述虚拟地址对应的真实物理页号；所述目标表项的物理大页号由所述真实物理页号除以N取整得到，所述目标表项的物理大页内偏移量由所述真实物理页号除以N取余得到；
    若所述独立表项的虚拟大页号与所述目标表项的虚拟大页号相同，且所述独立表项的物理大页号与所述目标表项的物理大页号相同，且所述独立表项的虚拟大页内偏移量与所述目标表项的虚拟大页内偏移量的差值等于所述独立表项的物理大页内偏移量与所述目标表项的物理大页内偏移量的差值，则合并所述独立表项和所述目标表项为目标组合表项，在所述目标组合表项中包含：虚拟大页号，位向量字段以及物理大页号；所述目标组合表项的虚拟大页号等于所述独立表项的虚拟大页号，所述目标组合表项的物理大页号等于所述独立表项的物理大页号，所述目标组合表项中的位向量字段中与所述虚拟地址所属虚拟页对应的比特为所述预定值，所述目标组合表项中的位向量字段中与所述独立表项的虚拟页对应的比特为所述预定值；所述独立表项的虚拟页的页号为所述独立表项的物理大页号与所述N的乘积，再与所述独立表项的物理大页内偏移量的和；
    否则，新增所述目标表项为新的独立表项。
  8. 根据权利要求1至7任意一项所述方法，其特征在于，所述N为2的 M次方，M大于或等于1；
    所述虚拟地址的大页号通过所述虚拟地址的虚拟页号右移M位得到；和/或，所述虚拟地址的偏移量通过截取所述虚拟地址的虚拟页号的后M位得到。
  9. 一种处理芯片，所述处理芯片包括：页表缓存TLB和缓存控制单元，其特征在于，
    所述页表缓存中存储有页表，所述页表的表项包括至少一个组合表项，所述组合表项包括虚拟大页号，位向量字段以及物理大页号，其中，所述虚拟大页号为N个连续的虚拟页的标识，所述位向量字段包含N个比特，所述N个比特和所述N个连续的虚拟页一一对应，且所述N个比特分别用来标识所述N个连续的虚拟页的页表存在状态，所述物理大页号为所述N个连续的虚拟页所对应的N个连续的物理页的标识；
    所述缓存控制单元包括第一输入端、第一输出端、第二输入端、第二输出端；所述第一输入端用于接收虚拟地址；所述第二输入端用于连接所述页表缓存，所述第二输入端用于连接所述页表缓存，所述第二输出端用于输出表项访问的结果；
    所述缓存控制单元，用于通过所述第一输入端接收所述虚拟地址，计算所述虚拟地址的虚拟大页号以及所述虚拟地址所属虚拟页在所述虚拟大页内的偏移量；所述虚拟地址的虚拟大页号由所述虚拟地址所属的虚拟页号除以N取整得到；所述虚拟地址所属虚拟页在所述虚拟大页内的偏移量由所述虚拟地址所属的虚拟页号除以N取余得到；所述N为大于1的整数；通过所述第一输出端访问所述组合页表并通过所述第二输入端接收访问结果，依据所述访问结果确定所述虚拟地址的虚拟大页号与所述TLB包括的组合表项中的虚拟大页号是否相同，并确定所述组合表项中的位向量字段中与所述虚拟地址所属虚拟页对应的比特是否为预定值；若所述两个确定结果均为是，则确定所述虚拟地址对应的物理页号为：所述组合表项中的物理大页号与所述N的乘积，再与所述虚拟地址所属虚拟页在所述虚拟大页内的偏移量的和，通过所述第二输出端输出所述虚拟地址对应的物理页号。
  10. 根据权利要求9所述处理芯片，其特征在于，
    所述页表缓存中存储的页表的表项包括至少一个独立表项，所述独立表项 包括虚拟大页号，虚拟大页内偏移量，物理大页号以及物理大页内偏移量，其中，所述虚拟大页由N个连续的虚拟页构成，所述虚拟大页号为所述N个连续的虚拟页的标识，所述虚拟大页内偏移量为相对于所述独立表项的虚拟大页号的第一个虚拟页号的偏移量，所述物理大页由所述N个连续的虚拟页所对应的N个连续的物理页构成，所述物理大页号为所述N个连续的虚拟页所对应的N个连续的物理页的标识，所述物理大页内偏移量为相对于所述独立表项的物理大页号的第一个物理页号的偏移量；
    所述缓存控制单元，还用于依据所述访问结果确定所述虚拟地址的虚拟大页号与所述TLB包括的独立表项中的虚拟大页号是否相同，并确定所述独立表项中的虚拟大页内偏移量与所述虚拟地址所属虚拟页在所述虚拟大页内的偏移量是否相同；若所述两个确定结果均为相同，则确定所述虚拟地址对应的物理页号为：所述独立表项的物理大页号与所述N的乘积，再与所述独立表项的物理大页内偏移量的和。
  11. 根据权利要求9或10所述处理芯片，其特征在于，
    所述缓存控制单元，还用于在确定所述组合表项中的位向量字段中与所述虚拟地址所属虚拟页对应的比特为非预定值，并且，所述独立表项中的虚拟大页内偏移量与所述虚拟地址所属虚拟页在所述虚拟大页内的偏移量不相同，所述组合表项还还包括用于表示所述组合表项是否可用于地址预测的标识位之后，若确定所述虚拟地址的虚拟大页号与所述组合表项中的虚拟大页相同，且所述组合表项中包含用于表示所述组合表项可用于地址预测的标识位，则确定预测页号以所述预测页进行访存，并执行页表移动；所述预测页号为：所述组合表项中的物理大页号与所述N的乘积，再与所述虚拟地址所属虚拟页在所述虚拟大页内的偏移量的和。
  12. 根据权利要求11所述处理芯片，其特征在于，
    所述缓存控制单元还包括第三输入端，所述第三输入端用于接收页表移动的结果；
    所述缓存控制单元，还用于若所述页表移动的结果表明所述预测页正确，通过所述第一输出端将所述组合表项中的位向量字段中与所述虚拟地址所属虚拟页在所述虚拟大页内的偏移量对应的比特修改为所述预定值。
  13. 根据权利要求11所述处理芯片，其特征在于，
    所述缓存控制单元，还用于在所述执行页表移动之后，若所述页表移动的结果表明所述预测页号错误，通过所述第一输出单元在所述页表缓存中的所述组合表项中设置用于表示所述组合表项不可用于地址预测的标识位。
  14. 根据权利要求12所述处理芯片，其特征在于，
    所述缓存控制单元，还用于在确定所述页表移动的结果表明所述预测页号错误之后，通过所述第一输出单元在所述页表缓存中新增新独立表项，所述新独立表项包含：虚拟大页号，虚拟大页内偏移量，物理大页号以及物理大页内偏移量；
    其中，所述新独立表项的虚拟大页由N个连续的虚拟页构成，所述新独立表项的虚拟大页号由所述虚拟地址所述的虚拟页号除以N取整得到，所述新独立表项的虚拟大页内偏移量由所述虚拟地址所属的虚拟页号除以N取余得到；所述页表移动的结果为所述虚拟地址对应的真实物理页号；所述新独立表项的物理大页号由所述真实物理页号除以N取整得到，所述新独立表项的物理大页内偏移量由所述真实物理页号除以N取余得到。
  15. 根据权利要求10所述处理芯片，其特征在于，
    所述缓存控制单元，还用于若未通过所述TLB成功确定所述虚拟地址对应的物理页号，执行页表移动确定所述虚拟地址对应的真实物理页号；确定需要新增的目标表项，所述目标表项包含：虚拟大页号，虚拟大页内偏移量，物理大页号以及物理大页内偏移量；其中，所述目标表项的虚拟大页由N个连续的虚拟页构成，所述目标表项的虚拟大页号由所述虚拟地址所述的虚拟页号除以N取整得到，所述目标表项的虚拟大页内偏移量由所述虚拟地址所属的虚拟页号除以N取余得到；所述页表移动的结果为所述虚拟地址对应的真实物理页号；所述目标表项的物理大页号由所述真实物理页号除以N取整得到，所述目标表项的物理大页内偏移量由所述真实物理页号除以N取余得到；
    若所述独立表项的虚拟大页号与所述目标表项的虚拟大页号相同，且所述独立表项的物理大页号与所述目标表项的物理大页号相同，且所述独立表项的虚拟大页内偏移量与所述目标表项的虚拟大页内偏移量的差值等于所述独立表项的物理大页内偏移量与所述目标表项的物理大页内偏移量的差值，则通过 所述第一输出单元合并所述页表缓存中的所述独立表项和所述目标表项为目标组合表项，在所述目标组合表项中包含：虚拟大页号，位向量字段以及物理大页号；所述目标组合表项的虚拟大页号等于所述独立表项的虚拟大页号，所述目标组合表项的物理大页号等于所述独立表项的物理大页号，所述目标组合表项中的位向量字段中与所述虚拟地址所属虚拟页对应的比特为所述预定值，所述目标组合表项中的位向量字段中与所述独立表项的虚拟页对应的比特为所述预定值；所述独立表项的虚拟页的页号为所述独立表项的物理大页号与所述N的乘积，再与所述独立表项的物理大页内偏移量的和；
    否则，通过所述第一输出单元在所述页表缓存中新增所述目标表项为新的独立表项。
  16. 根据权利要求9～15任意一项所述处理芯片，其特征在于，
    所述缓存控制单元，用于若所述N为2的M次方，M大于或等于1；则通过所述虚拟地址的虚拟页号右移M位得到所述虚拟地址的大页号；和/或，通过截取所述虚拟地址的虚拟页号的后M位得到所述虚拟地址的偏移量。
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